TWI818268B - Vcsel with carrier recycling - Google Patents

Abstract

Provided is a semiconductor laser diode. Although the materials used in the conventional technology can reduce the strain, the selections of materials are relatively limited and the carrier confinement ability is not good. To solve the above-mentioned problems, a phosphorus-containing semiconductor layer is provided in a laser diode. As such, it can effectively reduce the strain of the active region or the total strain of the laser diode, and improve the carrier confinement capability of the active region. Therefore, it can effectively reduce the total strain or significantly improve carrier confinement under appropriate conditions of laser diode. In some cases, it has the aforesaid effects. The phosphorus-containing semiconductor layer is suitable for an active region with one or more active layers. The active layer has a quantum well structure or a quantum dot structure. Especially after the phosphorus-containing semiconductor layer is provided in the active region with multiple active layers, high temperature performance are significantly improved or enhanced.

Description

Vertical resonant cavity surface emitting laser diode with carrier reuse mechanism

A vertical resonant cavity surface emitting laser diode, in particular, a vertical resonant cavity surface emitting laser diode with a carrier reuse mechanism.

Semiconductor laser diodes such as Vertical Cavity Surface Emitting Laser Diode (VCSEL) or Edge Emitting Laser Diode (EEL) can be used as 3D One of the light sources for sensing, LiDAR or optical communication.

VCSEL usually includes a pair of high-reflectivity film layers, commonly known as Distributed Bragg Reflector Layer (DBR Layer). There will be a resonant cavity between a pair of DBR layers. The resonant cavity usually includes a spacer layer and an active layer. The active layer usually includes a quantum well structure or a quantum dot structure. The quantum well structure is mainly composed of barrier walls. It is composed of Barrier Layer and Well Layer. The DBR layer is usually made of two or more materials with different refractive indexes that are repeatedly stacked and the thickness is accurately controlled to achieve high reflectivity. EEL is to coat a pair of film layers with different reflectivities on the opposite sides of the element to form a resonant cavity. The active layer usually contains a quantum well structure or a quantum dot structure. The quantum well structure of EEL, like VCSEL, is mainly composed of barrier layers. And the well layer is composed of an upper photoelectric control layer and a lower photoelectric control layer above and below the active layer.

If the active layer of a semiconductor laser diode has a quantum well structure, the well layer is usually made of a semiconductor material with a lower energy gap, and the barrier layer is composed of a material with a larger energy gap than the well layer. Therefore, the barrier layer And the energy band gap between well layers will form quantum wells. When the laser diode is forward biased, electrons and holes will be injected and confined in the quantum well structure, and the injected electrons, holes and other carriers will recombine in the quantum well and emit specific wavelengths The light generates constructive interference in the resonant cavity, and then emits laser light. According to the direction in which the laser light is emitted, the laser diode The body can be divided into surface-emitting laser diodes (VCSEL) and edge-emitting laser diodes (EEL), and surface-emitting laser diodes can also be further divided into front-emitting diodes according to the direction in which the laser light is emitted. Type laser diode (Top Emitting VCSEL) and back-emitting laser diode (Bottom Emitting VCSEL).

VCSEL has the following advantages: (1) narrow linewidth, conical laser beam is easy to couple with optical fiber; (2) can have fast modulation function at low current level, suitable for high-speed transmission applications; (3) can be used alone Mode output; (4) Low drive current (threshold current), low power consumption; (5) High output power; (6) Front or back light-emitting characteristics can be designed with 1D or 2D matrix; (7) The chip can be processed before packaging Testing can significantly reduce costs.

Epitaxial growth is performed on the substrate to form a laser diode structure. If the grown epitaxial layer material does not match the crystal lattice of the substrate, stress will be generated in the epitaxial layer and the accumulation of the epitaxial layer will be too large. The sum of stresses may cause defects or dislocations in the epitaxial layer in the laser diode structure, thereby affecting the reliability or power conversion efficiency (PCE) of the laser element. ). If the active layer of the laser diode has a quantum well structure, commonly used materials for the well layer include InGaAs or InAlGaAs. The main purpose of selecting the above materials is to improve the luminous efficiency (optical gain) of the laser diode and increase the operating frequency. Wide (frequency response) or used to emit a specific laser wavelength. However, the lattice mismatch between the InGaAs or InAlGaAs epitaxial layer material and the GaAs substrate is relatively large, which causes the active layer to generate large compressive stress and causes damage to the laser. The epitaxial layer of the polar body generates compressive stress accumulation.

When the material lattice of the well layer does not match the material lattice of the substrate, stress accumulation will occur in the active layer, and the sum of stresses in the epitaxial layer in the laser diode structure will rapidly accumulate, resulting in poor reliability. On the other hand, poor active layer carrier localization during high-temperature operation is also a problem that must be overcome.

When the phosphorus-containing semiconductor layer proposed in this specification is introduced into a semiconductor laser element, defects or dislocations in the multilayer structure can be reduced, or the carrier confinement capability of the active layer can be improved, or even both of the above effects can be achieved in some cases.

The first embodiment of this specification relates to a semiconductor laser diode. The semiconductor laser diode includes a GaAs substrate and a multi-layer structure on the GaAs substrate; the multi-layer structure includes an active region and an a first semiconductor layer; the active region includes one or a plurality of active layers, the or At least one of the active layers includes at least one well layer, the at least one well layer being selected from the group consisting of InGaAs, InAlGaAs, GaAsSb, GaAs, AlGaAs, AlGaAsSb, GaAsP and InGaAsP; the first semiconductor layer Disposed within or outside the active region, wherein the first semiconductor layer is selected from the group consisting of AlGaAsP, AlGaAsPN, AlGaAsPSb, AlGaAsPBi, InAlGaP, InAlGaPN, InAlGaPSb, InAlGaPBi, InGaAsP, InGaAsPN, InGaAsPSb, InGaAsPBi, InGaP, InGaPN, InGaPSb, The group consisting of InGaPBi and InAlGaAsP.

The second embodiment of this specification relates to a semiconductor laser diode. The semiconductor laser diode includes a GaAs substrate and a multi-layer structure on the GaAs substrate; the multi-layer structure includes an active region, a The second semiconductor layer and an intermediate layer; the active region includes one or a plurality of active layers, and at least one of the active layers includes at least one barrier layer and at least one well layer, and the at least one well layer is selected from InGaAs. , a group consisting of InAlGaAs, GaAsSb, GaAs, AlGaAs, AlGaAsSb, GaAsP and InGaAsP; the second semiconductor layer is disposed in the at least one barrier layer, wherein the second semiconductor layer is GaAsP; the intermediate layer is disposed in the at least one barrier layer Among at least one barrier layer and/or between the at least one barrier layer and the at least one well layer, the intermediate layer is selected from the group consisting of AlGaAsP, AlGaAsPN, AlGaAsPSb, AlGaAsPBi, InAlGaP, InAlGaPN, InAlGaPSb, InAlGaPBi, InGaAsP, InGaAsPN, InGaAsPSb, The group consisting of InGaAsPBi, InGaP, InGaPN, InGaPSb, InGaPBi, InAlGaAsP, GaAs and AlGaAs, wherein the energy gap of the at least one well layer is smaller than the energy gap of the at least one barrier layer and the energy gap of the intermediate layer.

The third embodiment of this specification relates to a semiconductor laser diode. The semiconductor laser diode includes a GaAs substrate and a multi-layer structure on the GaAs substrate; the multi-layer structure includes an epitaxial region, An active region, an upper epitaxial region and at least one carrier localization layer; the lower epitaxial region is located on the GaAs substrate, the active region is located on the lower epitaxial region, and the upper epitaxial region is located on the active region above; the at least one carrier confinement layer is located in the active region, the lower epitaxial region or the upper epitaxial region, and the at least one carrier confinement layer includes selected from the group consisting of AlGaAsP, AlGaAsPN, AlGaAsPSb, AlGaAsPBi, InAlGaP, The group consisting of InAlGaPN, InAlGaPSb, InAlGaPBi, InGaAsP, InGaAsPN, InGaAsPSb, InGaAsPBi, InGaP, InGaPN, InGaPSb, InGaPBi and InAlGaAsP.

The fourth embodiment of this specification relates to a semiconductor laser diode. The semiconductor laser diode includes a GaAs substrate and a multi-layer structure on the GaAs substrate; the multi-layer structure includes an active region, and the The active region includes one or a plurality of quantum dot structures, and at least one of the or the quantum dot structures includes a quantum dot, a wetting layer and a covering layer; wherein the quantum dot or the wetting layer is selected from the group consisting of InGaAs, InAlGaAs , GaAsSb, GaAs, AlGaAs, AlGaAsSb, GaAsP and InGaAsP; the covering layer is selected from the group consisting of AlGaAsP, AlGaAsPN, AlGaAsPSb, AlGaAsPBi, InAlGaP, InAlGaPN, InAlGaPSb, InAlGaPBi, InGaAsP, InGaAsPN, InGaAsPSb, InGaAsPBi, InGaP , InGaPN, InGaPSb, InGaPBi and InAlGaAsP.

The fifth embodiment of this specification relates to a semiconductor laser diode. The semiconductor laser diode includes an InP substrate and a multi-layer structure on the InP substrate; the multi-layer structure includes an epitaxial region, An active region, an upper epitaxial region and at least one carrier confinement layer; the lower epitaxial region is located on the InP substrate, and the active region is located on the lower epitaxial region, wherein the active region includes an active layer or A plurality of active layers, the upper epitaxial region is located above the active region; the at least one carrier confinement layer is located in the active region, the lower epitaxial region or the upper epitaxial region, and the at least one carrier confinement layer The system is selected from the group consisting of InGaP, InAlGaP, InP, InAlAsP, AlAsSb, AlAsBi, AlGaAsSb, AlGaAsBi, AlPSb, AlPBi, and InGaAsP.

1’:Semiconductor laser element

10’:Substrate

20’, 21’: active layer

30’: Lower epitaxial area

40’: Upper epitaxial area

100’:Multi-layer structure

A’: Active area

S1’: semiconductor layer

CF’: carrier confinement layer

J1: Side one

J2: Side two

J3: The third side

J4: The fourth side

CF’: carrier confinement layer

1:VCSEL

10: Substrate, GaAs substrate

100:Multi-layer structure

101:Buffer layer

102: Lower DBR layer

103: Lower compartment layer

20, 21: Active layer

104: Upper spacer layer

105: Go to DBR layer

106: Ohmic contact layer

201:Well layer

203: Barrier layer

205:Middle layer

24:Oxide layer

25: Tunnel junction layer

261, 262, 263: Spacer layer

S1: first semiconductor layer

S2: second semiconductor layer

CF: carrier confinement layer

3:EEL

300:Multi-layer structure

301: Lower covering layer

302: Lower photoelectric control layer

303: Upper photoelectric control layer

304:Coating layer

305: Ohmic contact layer

CF1, CF2: carrier confinement layer

1a to 1c are simple schematic diagrams showing some representative embodiments in which a phosphorus-containing semiconductor layer is disposed in an active region.

1d to 1g are simple schematic diagrams showing some representative embodiments in which the phosphorus-containing semiconductor layer is disposed outside the active region.

Figure 2 is a schematic diagram showing a conventional VCSEL.

FIG. 3a is a schematic diagram showing an embodiment in which the active layer in FIG. 2 is a quantum well structure.

Figure 3b is a schematic diagram showing the energy band relationship between the barrier layer and the well layer in Figure 3a.

FIG. 4a is a schematic diagram showing that a part of the barrier layer or the entire barrier layer is a first semiconductor layer.

FIG. 4b is a schematic diagram showing an embodiment in which each barrier layer forms a first semiconductor layer.

Figure 5a is a schematic diagram showing an embodiment of an intermediate layer between the barrier layer and the well layer.

Figure 5b is a schematic diagram showing the energy band relationship between the barrier layer, the intermediate layer and the well layer in Figure 5a.

Figure 6a is a schematic diagram showing an embodiment of inserting a GaAsP intermediate layer into the barrier layer.

Figure 6b is a schematic diagram showing the energy band relationship between the barrier layer, the intermediate layer and the well layer in Figure 6a.

Figure 7a is a schematic diagram showing an embodiment of inserting an AlGaAsP intermediate layer into the barrier layer.

Figure 7b is a schematic diagram showing the energy band relationship between the barrier layer, the intermediate layer and the well layer in Figure 7a.

FIG. 8a is a schematic diagram showing an embodiment in which the second semiconductor layer is used as a barrier layer and the intermediate layer is located between the second semiconductor layer and the well layer.

FIG. 8b is a schematic diagram showing an embodiment in which the second semiconductor layer is used as the barrier layer and the intermediate layer is inserted into the barrier layer.

FIG. 9 is a schematic diagram showing an embodiment of a VCSEL with an active region having multiple active layers.

FIG. 10a is a schematic diagram showing an embodiment in which the first semiconductor layer is formed above and below the active layer at the same time.

FIG. 10b shows a schematic diagram of an embodiment in which the first semiconductor layer is formed between the active layer and the lower spacer layer.

FIG. 11a is a schematic diagram showing an embodiment of the carrier confinement layer in the active region.

Figure 11b is a schematic diagram showing another embodiment of the carrier confinement layer in the active region.

FIG. 11c is a schematic diagram showing an embodiment of the carrier confinement layer outside the active region.

Figure 11d is a schematic diagram showing another embodiment of the carrier confinement layer outside the active region.

FIG. 12a is a schematic diagram showing an embodiment in which the carrier confinement layer is disposed on a portion of the lower spacer layer.

FIG. 12b is a schematic diagram showing an embodiment in which the carrier confinement layer is entirely disposed on the upper spacer layer.

FIG. 12c is a schematic diagram showing that each barrier layer of the active layer is provided with a carrier confinement layer.

FIG. 13 is a schematic diagram showing an embodiment in which a carrier confinement layer is disposed below and above the active layer.

Figures 14a to 14c are simple schematic diagrams showing some representative embodiments in which the active region includes two active layers and the carrier confinement layer is disposed between the two active layers.

FIG. 14d is a simple schematic diagram showing an embodiment when the active region includes two active layers and two carrier localization layers are disposed in the epitaxial region between the two active layers.

Figures 14e to 14h are simple schematic diagrams showing some representative embodiments in which the active area includes two active layers and the carrier localization layer is disposed outside the active area.

FIG. 15 is a schematic diagram showing a preferred embodiment in which a carrier confinement layer is disposed between two active layers.

FIG. 16 is a schematic diagram showing another preferred embodiment in which a carrier confinement layer is disposed between two active layers.

FIG. 17a is a schematic diagram showing an embodiment in which two carrier confinement layers are disposed between two active layers.

FIG. 17b is a schematic diagram showing an embodiment in which a carrier confinement layer is disposed above and below the active region.

FIG. 17c is a schematic diagram showing an embodiment in which a carrier confinement layer is disposed above and below each active layer.

Figure 18 is a schematic diagram showing a multi-layer structure of a conventional EEL.

FIG. 19a is a schematic diagram showing an embodiment of an EEL with a first semiconductor layer both above and below the active layer.

Figure 19b is a schematic diagram showing an embodiment of an EEL with carrier confinement layers both above and below the active layer.

Figure 20a is a schematic diagram of XRT imaging of Comparative Example 1.

Figure 20b is a schematic diagram of XRT imaging in Example 20.

Figure 20c is a schematic diagram of XRT imaging in Example 21.

Figure 21 is a comparison diagram of the maximum power conversion efficiency at different temperatures between Examples 21 and 22 and Comparative Example 2.

Figure 22 is a comparison diagram of the maximum power conversion efficiency at different temperatures between Example 23 and Comparative Example 3.

Figure 23 is a L-I-V curve graph measured at room temperature in Example 24 and Comparative Example 4.

Figure 24 is a L-I-V curve graph measured at high temperature in Example 24 and Comparative Example 4.

The embodiments of the present invention are described in more detail below with reference to drawings and component symbols, so that those skilled in the art can implement them after reading this specification. The thickness ratio between the film layers in the diagram is not the actual ratio, and the thickness of each film layer should be adjusted according to actual needs.

Examples of specific elements and their arrangements are described below to simplify the present invention. Of course these are only examples and should not limit the scope of the invention. For example, when a description refers to one layer being on top of another, it may include embodiments in which the layer is in direct contact with the other layer, or may include other components or epitaxial layers formed between the two without direct contact. Embodiments. In addition, repeated reference numbers and/or symbols may be used in different embodiments. These repetitions are only for the purpose of describing some embodiments simply and clearly, and do not represent a specific relationship between the different embodiments and/or structures discussed.

In addition, words related to space may be used, such as "below", "below", "lower", "above", "higher" and similar words. These relationships The word system is used to describe the diagram easily. The relationship between one element or feature in the formula and another element or feature. These spatial relative terms include the various orientations of a device in use or operation, as well as the orientation depicted in the diagrams.

The specification of the present invention provides different examples to illustrate the technical features of different implementations. For example, reference throughout this specification to "some embodiments" means that a particular feature, structure, or characteristic described in the embodiments is included in at least one embodiment. Therefore, the phrase "in some embodiments" appearing in different places throughout this specification does not necessarily refer to the same embodiment.

Additionally, specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Furthermore, for the terms "include", "have", "have", "wherein" or changes in the foregoing used herein, these semantics are similar to the term "comprising" to include corresponding features.

In addition, a "layer" may be a single layer or include multiple layers; and a "part" of an epitaxial layer may be one layer of the epitaxial layer or a plurality of adjacent layers.

In the prior art, a laser diode can be selectively provided with a buffer layer according to actual needs, and in some examples, the material of the buffer layer and the substrate can be the same. In addition, whether the buffer layer is provided or not has nothing to do with the technical features and effects to be described in the following embodiments. Therefore, for the sake of brief illustration, the following embodiments only use a laser diode with a buffer layer. For the sake of illustration, the laser diode without a buffer layer will not be described in detail. That is, the following embodiments can also be applied to replace the laser diode without a buffer layer.

Semiconductor laser components mainly include a substrate and a multi-layer structure. The multi-layer structure is formed on the substrate. It is well known that semiconductor laser components with different application purposes or working principles will use different multi-layer structures and even substrate materials; When the phosphorus-containing semiconductor layer proposed in this specification is applied to a semiconductor laser element, it can reduce defects and dislocations in the multilayer structure or improve carrier confinement capabilities, and even achieve both of the above effects in some cases. The semiconductor laser components in this specification refer to other suitable laser components such as VCSEL or EEL, but exclude laser diodes whose emission wavelength does not reach 700nm.

Referring to Figure 1a, the semiconductor laser element 1' of this specification mainly includes a substrate 10' and a multi-layer structure 100'. The multi-layer structure 100' is formed on the substrate 10'. The multi-layer structure 100' includes an active region A' and a phosphorus-containing region. Semiconductor layer S1'. Referring to Figures 1a and 1b~1c, the phosphorus-containing semiconductor layer S1' can be located at different positions within the active area A'; or, as shown in Figures 1d~1e, the semiconductor layer S1' is located above the active area. or below, and the semiconductor layer S1' is in direct contact with the active region A'; or, as shown in Figure 1f~1g, the semiconductor layer S1' is also located above or below the active region A', but the semiconductor layer S1' is indirectly catch In contact with the active region A', that is, there is an epitaxial layer between the semiconductor layer S1' and the active region A'; the specific implementation is described below.

[Example 1]

Referring to Figures 2 to 4a to 4b, Figure 2 is a schematic diagram showing an existing VCSEL. Figure 3a is a schematic diagram showing an embodiment in which the active layer in Figure 2 is a quantum well structure; Figure 3b is a schematic diagram showing the energy band levels of the barrier layer and the well layer in Figure 3a; Figure 4a is a diagram showing a part of the barrier layer or The entire barrier layer is a schematic diagram of the first semiconductor layer, and FIG. 4b is a schematic diagram showing an embodiment in which each barrier layer forms the first semiconductor layer.

The phosphorus-containing semiconductor layer S1' of Figures 1a to 1b is referred to as the first semiconductor layer S1 in Embodiment 1. Figures 2 to 3a and 3b are about the structure of the existing VCESL, and the active layer is a quantum well structure. For specific embodiments of the first semiconductor layer applied to VCSEL, please refer to Figure 4a, 4b and related content.

The semiconductor laser element shown in Figure 2 is VCSEL1. As shown in Figure 2, VCSEL1 includes a GaAs substrate 10 and a multi-layer structure 100. The active area A of the multi-layer structure 100 includes an active layer 20 (for the embodiment of multiple active layers, please refer to the following text). ), the multi-layer structure 100 sequentially includes a buffer layer 101, a lower DBR layer 102, a lower spacer layer 103, an active layer 20, an upper spacer layer 104, an upper DBR layer 105 and an ohmic contact layer 106 from bottom to top. The active layer 20 is located between the lower spacer layer 103 and the upper spacer layer 104 .

Buffer layer 101, lower DBR layer 102, lower spacer layer 103, upper spacer layer 104, upper DBR layer 105 and ohmic contact layer 106. The materials of these epitaxial layers can be commonly used semiconductor materials; according to actual needs, the lower DBR One or more epitaxial layers, such as an oxide layer, an ohmic contact layer, a spacer layer or other appropriate epitaxial layers, can be selectively provided in the layer 102 and/or the upper DBR layer 105 .

As shown in Figure 3a, one embodiment of the active layer 20 includes two well layers 201 and three barrier layer 203. The two well layers 201 and the three barrier layers 203 are staggered and stacked with each other, but their structure is not limited to this. That is, the active layer 20 may include n well layers 201 and n+1 barrier layers 203. If the active layer 20 is configured in this way, the uppermost layer and the lowermost layer of the active layer 20 are both barrier layers 203. In some embodiments, the barrier layer 20 at the uppermost layer and the lowermost layer of the active layer 20 may serve as the lower spacer layer 103 or the upper spacer layer 104 .

In an embodiment not shown, the active layer 20 may also include n well layers 201 and n-1 barrier layers 203. If the active layer 20 is configured in this way, the uppermost layer or the lowermost layer of the active layer 20 One of them is the well layer 201, or the uppermost layer and the lowermost layer of the active layer 20 are both the well layer 201. better Specifically, n is an integer from 1 to 5 (that is, the active layer 20 includes at least one well layer). More preferably, n is an integer from 2 to 5, which can improve the luminous efficiency (optical gain) or high temperature characteristics (high temperature) of the VCSEL. performance).

When the uppermost layer or the lowermost layer of the active layer 20 is the well layer 201, the lower spacer layer 103 or the upper spacer layer 104 adjacent to the well layer 201 acts as a barrier layer. When the uppermost layer and the lowermost layer of the active layer 20 are both well layers 201, the lower spacer layer 103 and the upper spacer layer 104 adjacent to the well layers 201 both serve as barrier layers.

In addition, as shown in the energy band diagram of Figure 3b, the barrier layer 203 is a semiconductor material with a higher conductive band energy level (E _c ), and the well layer 201 is a semiconductor material with a lower conductive band energy level, resulting in a conductive band insufficiency. Continuously (ΔE _c ) to form a so-called quantum well. Similarly, valence band discontinuity (ΔE _v ) will also occur at the valence band energy level (E _v ). When VCSEL1 is forward biased, electrons and holes will be injected and confined in the quantum well, and the injected electrons, holes and other carriers will recombine in the quantum well and emit light.

In most embodiments of this article, the preferred material of the well layer 201 is InGaAs, InAlGaAs, GaAsSb, GaAs, AlGaAs, AlGaAsSb, GaAsP, InGaAsP or a combination of the above materials. The VCSEL1 can be adjusted by changing the composition or thickness of the well layer 201 Laser wavelength, so the laser wavelength of semiconductor laser components can easily reach 700nm or above 800nm.

However, the lattice of some materials used as the well layer 201 does not match the GaAs substrate 10. In particular, the lattice constants of InGaAs, InAlGaAs, GaAsSb, AlGaAs, and AlGaAsSb are larger than those of the GaAs substrate. Therefore, after the epitaxial growth of the well layer, The layer generates compressive stress (Compressive Strain), and even if the composition of these materials is changed, the lattice constant will still be larger than the GaAs substrate; while the lattice constant is smaller than the GaAs substrate, there will be GaAsP, so after the epitaxial growth of the well layer, the well layer will The layer generates tensile stress. Similarly, even by changing the material composition of GaAsP, the lattice constant of GaAsP will still be smaller than the GaAs substrate; if some well layers or each well layer in the active layer generates compressive stress or tensile stress, then The accumulated stress in the active layer 20 or VCSEL 1 will become larger. Once the accumulated stress in the VCSEL is too large, it will cause defects or misalignment in the epitaxial layer of the VCSEL.

Therefore, a first semiconductor layer S1 containing phosphorus is provided in a multilayer structure. There are 17 preferred materials for the first semiconductor layer as shown in Table 1. The preferred materials for the first semiconductor layer S1 include the 17 materials in Table 1. At least one material or a combination of at least two materials.

【Table 1】

The lattice constant of the materials listed above can be changed. For example, by adjusting the amount of ingredients in the material, the lattice constant must match, be smaller than, or be larger than the GaAs substrate. Therefore, the first semiconductor layer can be determined according to the stress of the well layer. Tensile stress, compressive stress, or even no obvious stress is generated, so that the stress in the well layer can be effectively compensated by the first semiconductor layer, so that the accumulated stress in the active layer becomes smaller, thereby reducing defects or defects in the epitaxial layer of the VCSEL. The probability of differential dislocation occurs, thus improving the reliability of VCSEL.

The calculation method of the stress sum is: first multiply the stress value of each layer by its thickness to obtain the product value, and then subtract the product value of all compressive stresses from the product value of all tensile stresses to obtain the stress sum (as an absolute value).

If only the stress of the active layer itself is considered, in principle, as long as the sum of the stresses of the active layer itself becomes smaller; generally speaking, when the sum of the stresses of the active layer itself becomes smaller, the sum of the stresses of the VCSEL will also reduce; however, if the Lei outside the active layer The crystal layer will provide considerable stress. By appropriately selecting the materials of the well layer and/or the first semiconductor layer, the proportion of material components, the number of layers, and their thickness, the active layer can generate appropriate stress and stress magnitude. In this way, the active layer can also Moderately compensates the stress of the epitaxial layer outside the active layer.

Taking InGaP in Table 1 as an example, assuming that the molar ratio is In:Ga=51:49, InGaP will just lattice match the GaAs substrate; if you want to make the lattice constant of InGaP larger than the GaAs substrate, you must If the In content is further increased (Ga content becomes less), the first semiconductor layer can generate compressive stress; if the lattice constant of InGaP is smaller than the GaAs substrate, the Ga content must be increased (In content becomes less), In this way, the first semiconductor layer can generate tensile stress.

In principle, part or all of the barrier layer 203 is provided with the first semiconductor layer S1. For example, Figure 4a shows two ways of arranging the first semiconductor layer S1 in the barrier layer. One is to form the first semiconductor layer S1 in a part of the barrier layer 203, such as adjacent to the upper spacer layer 104 in Figure 4a. Barrier layer 203; the other is to form the first semiconductor layer S1 on the entire barrier layer 203, as shown in Figure 4a The barrier layer 203 is close to the lower spacer layer 103; the above-mentioned method of partially forming or entirely forming the first semiconductor layer in the barrier layer can be applied to one barrier layer or multiple barrier layers. For example, some barrier layers are A part of the first semiconductor layer is formed, and the other barrier layers are formed as a whole as the first semiconductor layer; as shown in Figure 4b, the first semiconductor layer can also be provided on each barrier layer; it should be noted that the first semiconductor layer The number, manner and location of the layers depend on the location and magnitude of stress in the well layer, and are not limited to the number and location described in this embodiment.

In this embodiment, by inserting the first semiconductor layer S1 containing phosphorus into the barrier layer 203, the barrier layer 203 can perform stress compensation on the well layer 201. For example, when the well layer 201 generates compressive stress, the barrier layer 203 The first semiconductor S1 in the layer generates tensile stress (Tensile Strain), so that the total stress accumulated in the active layer 20 becomes smaller; in addition, the barrier layer 203 can further expand the impact on the well layer due to the insertion of the phosphorus-containing first semiconductor layer S1. The energy band gap increases the carrier confinement (Carrier Confinement) of the active layer. When operating at high temperature, it can also confine carriers with higher energy in the quantum well. Therefore, when operating at high temperature, the luminous efficiency of VCSEL becomes Better.

It should be noted that whether the well layer will produce compressive stress or tensile stress is determined by the well layer material, the well material composition or the material of the substrate. That is, if the well layer produces tensile stress, the first semiconductor layer should produce Compressive stress; similarly, if the well layer generates compressive stress, the first semiconductor layer must provide tensile stress; if the energy gap of the first semiconductor layer is larger, it can also improve the carrier confinement capability of the VCSEL.

In some embodiments, the thickness of the well layer may be 1 nm ~ 30 nm, preferably 2 nm ~ 15 nm or 3 nm ~ 10 nm, wherein the thickness of the well layer may be determined according to the well layer material, the well layer material composition or the required wavelength of the well layer. adjust.

As mentioned above, the barrier layer 203 can not only perform stress compensation on the well layer 201, but the degree of stress compensation of the barrier layer 203 on the well layer 201 can also be adjusted. Specifically, when the material, material composition or thickness of the barrier layer 203 When being changed, the degree of stress compensation of the well layer 201 by the barrier layer 203 will also change; the thickness of the barrier layer 203 can be 1nm~30nm, preferably 2nm~15nm or 3nm~10nm, to reduce or eliminate the active layer 20 stress.

[Example 2]

Figure 5a is a schematic diagram showing an embodiment of having an intermediate layer between the barrier layer and the well layer; Figure 5b is a schematic diagram showing the energy band relationship between the barrier layer, the intermediate layer and the well layer in Figure 5a; Figure 6a is a diagram showing the insertion in the barrier layer A schematic diagram of an embodiment of the GaAsP interlayer. Figure 6b shows the barrier layer of Figure 6a. Schematic diagram of the energy band relationship between the intermediate layer and the well layer; Figure 7a is a schematic diagram showing an embodiment of inserting an AlGaAsP intermediate layer into the barrier layer; Figure 7b is a schematic diagram showing the energy band relationship between the barrier layer, the intermediate layer and the well layer in Figure 7a.

Compared with Fig. 3a, in Fig. 5a, an intermediate layer 205 is inserted between the well layer 201 and the barrier layer 203. The barrier layer 203 will not be in direct contact with the well layer 201. Or as shown in Figure 6a, an intermediate layer 205 is provided in the barrier layer 203 of the active layer 20. In other words, a layered structure of the barrier layer 203, the intermediate layer 205 and the barrier layer 203 is formed in sequence; wherein, the preferred material of the intermediate layer 205 Refer to Table 2 for a total of 20 materials. The material used as the middle layer is at least one material listed in Table 2 or an appropriate combination of two or more materials. Preferably, Embodiment 2 can be used in combination with Embodiment 1, that is, the middle layer includes at least one material in Table 2, and the barrier layer is at least one material in Table 1.

The lattice constants of the materials listed in Table 2 can be changed to be less than, greater than or equal to the lattice constant of GaAs, so the intermediate layer can be determined to produce tensile stress, compressive stress or even no stress.

In some embodiments, the materials of the barrier layer 203 and the intermediate layer 205 may be the same or different. The materials of the barrier layer 203 and the intermediate layer 205 are preferably different. Even if the materials of the barrier layer 203 and the intermediate layer 205 are the same, the composition ratios of the two materials are also different. For example, when the materials of the barrier layer 203 and the intermediate layer 205 are AlGaAsP, the proportions of aluminum, gallium, arsenic or phosphorus will be different. Ingredient ratios vary.

Although FIG. 5 a shows an embodiment in which the uppermost layer and the lowermost layer of the active layer 20 are barrier layers 203 , the uppermost layer and/or the lowermost layer of the active layer 20 can also be the well layer 201 ; the uppermost layer or the lowermost layer of the active layer 20 When it is the well layer 201, the well layer 201 can be in substantial contact with the lower spacer layer 103 or the upper spacer layer 104; when the uppermost layer and the lowermost layer of the active layer 20 are both the well layer 201, the well layer 201 can be in substantial contact with the lower spacer. layer 103 and upper spacer layer 104.

In one embodiment, as shown in FIG. 5 b , when the intermediate layer 205 is made of GaAsP, the conductive band energy level of the intermediate layer 205 is located between the conductive band energy levels of the well layer 201 and the barrier layer 203 . The middle layer is not Because it contains aluminum, it is not easily oxidized and can compensate for the stress in the well layer; for example, when the well layer has compressive stress, the middle layer has tensile stress to reduce the total stress in the active layer.

In some embodiments, as shown in Figures 6a and 7a, when the material of the intermediate layer 205 is GaAsP or AlGaAsP respectively, the energy band diagrams corresponding to Figures 6a and 7a are shown in Figures 6b and 7b respectively; the intermediate layer 205 is not limited to materials that provide tensile stress. Materials that provide compressive stress or no obvious stress can also be used based on the energy band gap of the quantum well and the degree of stress compensation.

The thickness of the middle layer 205 can be 1nm~30nm, preferably 2nm~15nm or 3nm~10nm, and the total thickness of the middle layer 205 and the barrier layer 203 between two adjacent well layers 51 can be between 1nm~ 30nm, preferably between 2nm~15nm or between 3nm~10nm.

In principle, the sum of the stresses of the well layer, barrier layer and intermediate layer of the active layer after stress compensation will be lower than the sum of uncompensated stress. Therefore, the intermediate layer can be determined based on the type and magnitude of stress in the well layer and barrier layer. Generate compressive stress or tensile stress or no stress. The total stress can change according to the materials, material composition ratio, number of layers or thickness of the barrier layer, intermediate layer, well layer, etc., so there is no limit here.

Although Embodiment 2 takes the middle layer being arranged in a single active layer (VCSEL) as an example, in the embodiment of multiple active layers (VCSEL), Embodiment 2 can also be used in one or some active layers in multiple active layers. Or in each active layer.

[Example 3]

Refer to FIG. 8a. FIG. 8a is a schematic diagram showing an embodiment in which the second semiconductor layer is used as the barrier layer and the intermediate layer is located between the second semiconductor layer and the well layer. Refer to FIG. 8b. FIG. 8b is a schematic diagram showing that the second semiconductor layer is used as the barrier layer. Barrier layer, a schematic diagram of an embodiment in which the intermediate layer is inserted into the barrier layer.

In Embodiment 3, a VCSEL is taken as an example. In terms of structure, Embodiment 3 can be compared with Embodiments 1 to 2 in terms of the quantum well structure of the multilayer structure 100 and the active layer 20 .

In terms of materials, the second semiconductor layer S2 and the intermediate layer 205 of Embodiment 3 are different from the first semiconductor layer S1 and the intermediate layer of Embodiment 1; specifically, the phosphorus-containing material of the second semiconductor layer S2 is limited to One kind of GaAsP, the second semiconductor layer S2 is at least part or all of the barrier layer 203; the material of the intermediate layer 205 is at least one of the 19 materials listed in Table 3 or a combination of two or more materials. The preferred material of the well layer 201 is the same as that of Embodiment 1. The preferred material of the well layer 201 is InGaAs, InAlGaAs, GaAsSb, GaAs, AlGaAs, AlGaAsSb, GaAsP, InGaAsP or a combination of the above materials.

Among the materials listed in Table 3 above, except for AlGaAs which can only produce compressive stress and GaAs which does not produce stress, the lattice constants of the other materials can be changed to be less than, greater than or even equal to the lattice constant of the GaAs substrate, so the middle Layers can be determined to produce tensile stress, compressive stress or even no stress.

In some embodiments, when the well layer 201 is made of InGaAs or InAlGaAs, the luminous efficiency or bandwidth of the VCSEL can be further improved. And by inserting a GaAsP layer (second semiconductor layer) in the barrier layer 203, and the substrate is a GaAs substrate, the GaAsP layer with a lattice constant smaller than the GaAs substrate will generate tensile stress, thereby compensating the stress of the well layer 201, thereby reducing Or the total stress in the active layer 20 can be eliminated to improve the reliability of the laser diode.

In one embodiment, when the conductive band energy level of the intermediate layer 205 is higher than the conductive band energy level of the barrier layer 203 made of GaAsP, the energy band gap between the intermediate layer 205 and the well layer 201 will be greater than the energy band gap between the GaAsP barrier layer 203 and the well layer. The energy band gap between the layers 201 can improve the ability of the quantum well to confine carriers and improve the high-temperature characteristics or reliability of the semiconductor laser diode.

Although Embodiment 3 takes the well layer, barrier layer and intermediate layer in a single active layer as an example, in the embodiment of multiple active layers, Embodiment 3 can also be used in one active layer, some active layers in multiple active layers. layer or active layer.

[Example 4]

The well layer, intermediate layer and barrier layer are InGaAs, AlGaAs and GaAsP, and the AlGaAs intermediate layer is set in the GaAsP barrier layer; GaAsP can provide tensile stress, reduce the total stress in the active layer and semiconductor laser, and reduce the semiconductor laser Hit dislocations or defects in the epitaxial layer. AlGaAs can increase the energy band gap between the quantum well and the well layer, thereby improving the ability of the quantum well to confine carriers to improve the high-temperature characteristics of the semiconductor laser diode.

[Example 5]

The well layer and barrier layer are InGaAs and AlGaAsP (no intermediate layer is provided); the AlGaAsP barrier layer can provide tensile stress and reduce the total stress in the active layer or semiconductor laser diode. It can reduce defects or misalignment in the epitaxial layer in semiconductor laser diodes. The AlGaAsP barrier layer can increase the energy band gap with the InGaAs well layer, thereby improving the ability of the quantum well to confine carriers to improve the high-temperature characteristics of the semiconductor laser diode. Alternatively, when there is no need to increase the energy band gap between the quantum well and the quantum well, the aluminum content in the AlGaAsP barrier layer can be appropriately reduced, and the probability of the active layer of the semiconductor laser diode being oxidized will also be reduced. , thereby improving the reliability of semiconductor laser diodes.

[Example 6]

Referring to FIG. 9 , FIG. 9 is a schematic diagram showing an embodiment of a VCSEL (multi-junction VCSEL) with an active region having multiple active layers.

As shown in FIG. 9 , the active area A includes active layers 20 and 21 , wherein each active layer 20 and/or 21 itself can apply the various embodiments of Embodiment 1 regarding the first semiconductor layer S1 and the methods of Embodiment 2 regarding the intermediate layer. For each embodiment of the layer and at least one of the embodiments of the second semiconductor layer S2 in Embodiment 3, please refer to the above description for relevant content; it should be noted that in the implementation of multiple active layers (multiple junctions) In this example, as shown in Table 4, the material of the first semiconductor layer includes GaAsP in addition to the 17 materials listed in Table 1.

The number of multi-active layers is not limited to two, but can also be three, four or five layers, where there is an epitaxial region between two adjacent active layers or between every two adjacent active layers; in some implementations In this example, at least a tunnel junction layer 25 is provided in the epitaxial region; multiple active layers help to improve the luminous power and power conversion efficiency (power conversion efficiency), but the more active layers are provided, the easier it is for stress to accumulate. By appropriately determining the materials, material composition ratios, number of layers, or thicknesses of the well layer, the first semiconductor layer S1 or the second semiconductor layer S2, the total stress of the active layer or VCSEL can be reduced.

Although FIG. 9 also shows that the oxide layer 24 and the spacer layers 261 ~ 263 are further provided in the epitaxial region, the oxide layer 24 or the spacer layers 261 ~ 263 are selectively configured according to actual needs. For example, the spacer layers 261 ~ 263 are usually Used to adjust the optical phase of light or as a confinement layer of light or a confinement layer of carriers; Figure 9 shows a preferred embodiment of the oxide layer 24 and the spacer layers 261~263, where the spacer Layers 261, 262, and 263 can be respectively inserted between the active layer 20 and the oxide layer 24, between the oxide layer 24 and the tunnel junction layer 25, and between the tunnel junction layer 25 and the active layer 21. In the case of three or more active layers, an oxide layer and/or a spacer layer can also be selectively or further formed between any two adjacent active layers. In addition to the specific implementation of the oxide layer and/or spacer layer, please refer to the above. , and can also be changed according to actual needs.

In some embodiments, the first semiconductor layer is provided in the spacer layers 261 and 263 adjacent to the active layer 20 and/or the active layer 21; or the first semiconductor layer is also provided in the active layer. The specific details of the first semiconductor layer The implementation mode is described with reference to Embodiment 1, 2 or 3.

In the prior art, commonly used materials for barrier layers are AlGaAs, GaAsP, and GaAs. Compared with GaAsP and GaAs, because the energy band gap between AlGaAs and the well layer is large, it can increase carrier confinement (Carrier Confinement). Therefore, during high-temperature operation, the AlGaAs barrier layer is also better at confining carriers in the quantum well. , thereby making the optical characteristics of VCSEL better. However, when the barrier layer is AlGaAs, it will have compressive stress. If the well layer also has compressive stress, excessive compressive stress will accumulate in the active layer, causing the epitaxial layer of the VCSEL to easily produce defects or dislocations, thus affecting the reliability of the VCSEL. Deterioration. When there are too many defects or dislocations, the optical characteristics of VCSEL will deteriorate. Although increasing the aluminum content in the barrier layer can further expand the energy band gap to improve the carrier confinement of the quantum well, as the aluminum content increases, the probability of the active layer being oxidized also increases. The oxidation of aluminum in the active layer will cause defects in the active layer, which will easily reduce the optical characteristics or reliability of the VCSEL.

When the barrier layer is AlGaAsP (a material listed in Table 1), compared to the barrier layer being AlGaAs, when the aluminum content of the AlGaAsP barrier layer and the AlGaAs barrier layer are the same, and the well layer materials are also the same, the barrier layer of AlGaAsP is The energy band gap of the well layer will be larger, and the carrier limitation will also increase.

When the barrier layer is AlGaAs, the energy band gap to the well layer can only be widened by increasing the aluminum content of AlGaAs. However, the higher the aluminum content, the easier it is for the barrier layer to be oxidized; and a first layer containing phosphorus is provided in the barrier layer. After the semiconductor layer S1, under the same aluminum content, the oxidation rate of the barrier layer containing phosphorus will be slower than that of the barrier layer without phosphorus; in addition, under the same aluminum content, the energy band gap of AlGaAsP to the well layer is smaller than that of the barrier layer without phosphorus. The energy band gap between AlGaAs and the well layer is even larger, so the aluminum content of AlGaAsP does not need to be as much as that of AlGaAs. In addition, AlGaAsP can also expand the energy band gap of the well layer by increasing the phosphorus content, which can Further reducing the aluminum content can further reduce the probability of the active layer 20 of the VCSEL 1 being oxidized and reduce the occurrence of defects in the active layer or VCSEL. The efficiency and reducing the defects of VCSEL in the epitaxial layer will help improve the reliability of VCSEL1. The usage amounts of phosphorus and aluminum can be adjusted based on considerations such as the energy band gap of the quantum well and the degree of stress compensation, so there is no limit here.

Similarly, when the first semiconductor layer formed in the barrier layer 203 is made of any other phosphorus-containing material listed in Table 1, it also has the effect of increasing the reliability of the VCSEL 1 .

[Example 7]

FIG. 10a is a schematic diagram showing an embodiment in which the first semiconductor layer is formed above and below the active layer at the same time. FIG. 10b shows a schematic diagram of an embodiment in which the first semiconductor layer is formed between the active layer and the lower spacer layer.

Figures 10a and 10b take VCSEL as an example. As shown in Figure 10a, a first semiconductor layer S1 is disposed above and below the active region; the material of the first semiconductor layer above and/or below the active region is at least one of the 20 materials listed in Table 5. One material or a combination of at least two or more materials; the 20 materials listed in Table 5 include the 17 materials in Table 1 as well as GaAsP, AlGaAs and GaAs.

In some embodiments, as shown in Figure 10a, the entire upper spacer layer 104 is the first semiconductor layer S1, and one side of the first semiconductor layer S1 is substantially in contact with the active layer 20; or, a part of the lower spacer layer 103 is The first semiconductor layer S1 may be in non-substantial contact with the active layer 20 , that is, a part of the lower spacer layer 103 is between the first semiconductor layer S1 and the active layer 20 . Whether the lower spacer layer 103 or the upper spacer layer 104 is in direct or indirect contact with the active layer 20 depends on implementation requirements. When the first semiconductor layer S1 is in the lower spacer layer 103 or the upper spacer layer 104, whether the first semiconductor layer S1 is in direct or indirect contact with the active layer 20 depends on implementation requirements.

In some embodiments, the materials of the "upper spacer layer and the first semiconductor layer" or the "lower spacer layer and the first semiconductor layer" can be the same or different; even if the "upper spacer layer and the first semiconductor layer" or the "lower spacer When the materials of the "layer and the first semiconductor layer" are the same, the composition ratios of the two materials may also be different.

In some embodiments, as shown in FIG. 10b , the first semiconductor layer S1 is formed between the lower spacer layer 103 and the active layer 20 , but is not limited thereto. The first semiconductor layer S1 can also be formed on the upper spacer layer 104 and active layer 20 (not shown).

In the case where the first semiconductor layer S1 is in indirect contact with the active layer; although in principle, the closer the first semiconductor layer S1 is to the active layer 20, the more obvious the effect of improving the carrier confinement capability or stress compensation of the active layer 20 will be. It is not limited that the first semiconductor layer S1 must be disposed in the epitaxial layer that is in contact with or adjacent to the active layer, such as the above-mentioned upper spacer layer or lower spacer layer. Because if the upper spacer layer or the lower spacer layer is thin or the first semiconductor layer can provide sufficient stress, even if there is an epitaxial layer between the first semiconductor layer and the active layer, the first semiconductor layer can still provide a certain amount of stress to the active layer. The carrier confinement capability or the stress summation that reduces the active layer or VCSEL.

It is worth noting that when the first semiconductor layer S1 is disposed outside the active layer 20, the barrier layer or the intermediate layer of the active layer can use conventional materials, or another first semiconductor layer can be disposed in the active layer. For a specific implementation of the first semiconductor layer, refer to the first semiconductor layer in Embodiments 1 to 3.

When the well layer or the epitaxial layer of the laser element will generate considerable stress, by applying any of the above embodiments or a combination of some embodiments in the laser element, the total stress of the active layer or the laser element is controlled to Within a certain range; in the above-mentioned embodiments, for example, some materials in Table 1 will have obvious carrier confinement effects under appropriate conditions. Although some content about carrier confinement has been mentioned in the previous article, it is scattered in different places in the previous article. Therefore, some preferred embodiments of carrier confinement will be described in detail below.

[Example 8]

Figure 11a is a schematic diagram showing a carrier confinement layer within the active area. Figure 11b is a schematic diagram showing another embodiment of the carrier confinement layer within the active area. Figure 11c is a schematic diagram showing the carrier confinement layer outside the active area. A schematic diagram of an embodiment. FIG. 11d is a schematic diagram of another embodiment showing the carrier confinement layer outside the active region.

Figures 11a to 11d are roughly the same as Figures 1b to 1e. The phosphorus-containing semiconductor layer S1' is uniformly called the carrier confinement layer CF' in Embodiment 8 and Figures 11a to 11d, and the active region A in Figures 11a to 11d ' contains an active layer; for embodiments of multiple active layers, please refer to Embodiments 12 to 15 below.

As shown in Figures 11a to 11d, the multilayer structure includes an active region A', a lower epitaxial region 30' and an upper epitaxial region 40'. The lower epitaxial region 30' and the upper epitaxial region 40' are located under the active region A'. and above; active area A' The side facing the lower epitaxial region 30' is defined as the first side J1, and the side of the active region A' facing the upper epitaxial region 40' is defined as the second side J2. In the following text, it is referred to as "the side of the active layer" alone. ”, it represents the first side and/or the second side; in the embodiment with multiple active layers, it also includes the third side, the fourth side to the Nth side, then the “side of the active layer” also represents the One, two or more from one side to the Nth side.

When the carrier confinement layer CF' is disposed in the active region A', in this arrangement, whether the carrier confinement layer CF' is actually in contact with or close to the lower epitaxial region 30", the carrier confinement layer CF' will There is a carrier confinement effect; in some embodiments, the carrier confinement layer CF' can even be disposed in each or some barrier layers of the active layer.

When the carrier confinement layer CF' is disposed in the lower epitaxial region 30' or the upper epitaxial region 40', in this arrangement, in principle, the closer the carrier confinement layer CF' is to the active region A', the higher the carrier confinement The effect is more obvious. In some embodiments, one side of the carrier confinement layer can be regarded as the first side J1 or the second side J2, that is, the carrier confinement layer is formed as the uppermost part of the lower epitaxial region or is formed as the upper epitaxial region. The lowermost part; alternatively, the carrier confinement layer is the lowermost or uppermost part of the active region. In other words, the carrier confinement layer is disposed between the lower epitaxial region and the active region or between the active region and the upper between epitaxial regions.

In some embodiments, there is also a part of an epitaxial layer, an epitaxial layer or some epitaxial layers between the carrier confinement layer and the first surface J1 or between the carrier confinement layer and the second surface J2; preferably , the carrier confinement layer CF' is at least one material or a combination of two or more materials among the 17 materials in Table 6.

[Example 9]

Figures 11a to 11d are schematic diagrams of principle embodiments, and for specific embodiments applied to VCSEL, please refer to Figures 12a to 12c. Figure 12a is a schematic diagram showing an embodiment in which the carrier confinement layer is disposed on a part of the lower spacer layer. Figure 12b is a schematic diagram showing an embodiment in which the carrier confinement layer is disposed entirely in the upper spacer layer. Figure 12c is a schematic diagram showing an active A schematic diagram showing that each barrier layer is provided with a carrier confinement layer.

Referring to Figure 12a and please cooperate with Figure 11d, the lower spacer layer 103 of Figure 12a can be regarded as being in the lower epitaxial region 30' of Figure 11d; as shown in Figure 12a, the carrier confinement layer CF is formed in the lower spacer layer 103 A part of the carrier confinement layer CF and the first surface J1 must be in an effective distance that can confine the carriers in the active layer, and therefore do not necessarily need to form substantial contact; in some embodiments, the upper spacer layer 104 The carrier confinement layer CF is entirely formed, as shown in FIG. 12b; and although FIG. 12c shows that the carrier confinement layer CF is disposed in a part of each barrier layer 203, it is not limited to this, and the carrier confinement layer CF can also be disposed in some parts of the barrier layer 203. All of the barrier layers or all of each barrier layer.

To sum up, Embodiment 9 forms a carrier confinement layer near one side of the active layer, and when the carrier confinement layer is at least one of the materials in Table 6, the conductive band of the carrier confinement layer to the active layer is discontinuous. Or the valence band becomes discontinuous, so when holes or electrons are injected into the active layer, especially when operating at high temperatures, the holes or electrons will be confined by the carrier confinement layer. The optical characteristics of the VCSEL will improve as the carrier confinement ability becomes better. It will also get better.

[Example 10]

In Embodiment 10, a carrier confinement layer CF is formed near one side of the active layer. The carrier confinement layer CF can be selected from at least one material or a combination of at least two materials listed in Table 7 or Table 8, wherein the ones in Table 7 The material has a large barrier height to the holes, so it has a good hole confinement effect, which is hereinafter referred to as the carrier confinement layer (hole confinement layer). The materials in Table 8 have a large barrier height for electrons, so they have a good confinement effect on electrons. They are hereinafter referred to as carrier confinement layers (electron confinement layers).

Taking Figure 12a as an example, in the case where holes are injected into the active layer 20 through the upper DBR layer 105 and the second surface J2, when the carrier confinement layer CF close to the first surface J1 uses any material in Table 7, Since the carrier confinement layer (hole confinement layer) CF has a large potential barrier to the holes, when the holes continue to move toward the GaAs substrate, the holes will be confined by the carrier confinement layer (hole confinement layer) CF. thus promoted Hole limitation of the active layer; it is worth mentioning that in the above case, when the carrier confinement layer close to the first surface J1 is selected from InGaP or AlGaInP in Table 7, and the epitaxial layer adjacent to the carrier confinement layer AlGaAs or other appropriate materials are used. Since the electron barrier at the interface between InGaP and AlGaAs or between AlGaInP and AlGaAs is relatively small or almost non-existent, electrons can be injected into the active layer without hindrance. Therefore, in laser components The resistance is not easy to increase. In this case, the upper DBR layer 105 is mainly P-type and the lower DBR layer 102 is mainly N-type.

Also taking Figure 12a as an example, in the case where electrons are injected into the active layer 20 through the upper DBR layer 105 and the second surface J2, when the carrier confinement layer CF close to the first surface J1 uses any material in Table 8 , since the carrier confinement layer CF has a large barrier to electrons (electron confinement layer), when electrons continue to move toward the GaAs substrate, the electrons will be confined by the carrier confinement layer (electron confinement layer) CF, thus improving the active layer Electronic limitations. It is worth mentioning that in the above situation, when the carrier confinement layer close to the first surface J1 is made of AlGaAsP in Table 8, and the epitaxial layer adjacent to the carrier confinement layer is made of AlGaAs or other appropriate materials, the electrical In terms of holes, since the hole barrier at the interface between AlGaAsP and AlGaAs is relatively small, holes can be injected into the active layer without hindrance, so the resistance in the laser element is not easy to increase. In this case, the upper DBR layer 105 is mainly N-type and the lower DBR layer 102 is mainly P-type.

[Example 11]

As shown in FIG. 13 , Embodiment 11 includes two carrier confinement layers CF1 and CF2. The two carrier confinement layers CF1 and CF2 are respectively formed near the first surface J1 and the second surface J2 of the active layer 20 . In the case where holes and electrons are injected into the active layer from the second surface J2 and the first surface J1 respectively, when the carrier confinement layer (hole confinement layer) CF1 and the carrier confinement layer (electron confinement layer) CF2 are selected, the table 7 and at least one material in Table 8, so that the potential barrier to the electron hole of the carrier confinement layer (hole confinement layer) CF1 and the potential barrier to electrons of the carrier confinement layer (electron confinement layer) CF2 can be improved, then the hole and electronic limitations are improved, thereby improving the characteristics of laser components.

In the same way, when holes and electrons are injected into the active layer from the first surface J1 and the second surface J2 respectively, when the carrier confinement layer (electron confinement layer) CF1 and the carrier confinement layer (hole confinement layer) CF2 are Select at least one material from Table 8 and Table 7, so that the carrier confinement layer (electron confinement layer) CF1 has a barrier height for electrons and the carrier confinement layer (hole confinement layer) CF2 has a barrier height for holes. (barrier height) can be increased, the limitations of holes and electrons will be improved, and the characteristics of laser components can be improved.

In a preferred embodiment, when InGaP or AlGaInP is selected in Table 7 and AlGaAsP is selected in Table 8, and the epitaxial layer adjacent to the carrier confinement layer CF1 and CF2 is selected from AlGaAs or other appropriate materials, not only holes and electrons In addition to significantly improving the limitations, holes and electrons can be injected into the active layer without any hindrance.

Selecting at least one of the materials listed in Table 6, Table 7 or Table 8 as the carrier confinement layer, and placing the carrier confinement layer at an appropriate position can exhibit the carrier confinement effect, especially during high temperature operations. Carrier localization effect. In this case, the barrier layer in the active layer can be made of a material that does not generate stress, or the first semiconductor layer can be applied above, below or in the active layer to generate appropriate stress for stress compensation. For specific implementation details, please refer to the related embodiments of the first semiconductor layer.

[Example 12]

Figures 14a to 14c are simple schematic diagrams showing some representative embodiments in which the active region includes two active layers and the carrier confinement layer is disposed between the two active layers. As shown in Figure 14a, the active area A' includes two active layers 20' and 21'. When the carrier confinement layer CF' is located in the active area A', the carrier confinement layer CF' can be located on the second surface J2 and the second surface. Between the three surfaces J3, the carrier confinement layer CF' can be separated from the second surface J2 or the third surface J3 by an effective distance that can confine the carriers in the active layer; in the case of three or more active layers, it can be only One or two carrier confinement layers are disposed between two adjacent active layers, or one or two carrier confinement layers can be disposed between any two adjacent active layers. In some other embodiments, as shown in Figures 14b and 14c, the carrier confinement layer CF' is directly in contact with the second surface J2 or the third surface J3.

It must be noted again that although Figures 14a, 14b, and 14c show that the carrier confinement layer CF' is between the two active layers 20' and 21', it is not limited thereto; in alternative embodiments, the carrier confinement layer CF' can be provided In the active layer, as shown in Figure 14a, the carrier confinement layer CF' is close to the second surface J2 or the third surface J3.

If there are more than three active layers, the carrier confinement layer can be formed between every two adjacent active layers, or the carrier confinement layer can be set separately in one active layer or some active layers, or it can be applied as appropriate. The above two are in an active zone with multiple active layers.

When a semiconductor laser element is provided with a carrier confinement layer in two active layers, in principle, the carrier confinement layer uses at least one material listed in Table 6.

[Example 13]

FIG. 14d is a simple schematic diagram showing an embodiment when the active region includes two active layers and two carrier localization layers are disposed in the epitaxial region between the two active layers. In Example 13, one of the two carrier confinement layers is selected from at least one material selected from Table 7 and the other is selected from at least one material selected from Table 8.

[Example 14]

Figures 14e to 14h are simple schematic diagrams showing some representative embodiments in which the active area includes two active layers and the carrier localization layer is disposed outside the active area. Embodiment 14 is based on Embodiment 9, so for the implementation of Embodiment 14, please refer to the relevant embodiments of Embodiment 9; in addition, carrier confinement layers can be respectively provided above and below the active region A'. One of the carrier confinement layers is at least one material selected from Table 7 and the other is at least one material selected from Table 8.

[Example 15]

Figure 14a is a schematic diagram of a principle embodiment, and for specific embodiments applied to VCSEL, please refer to Figure 15. Figure 15 is a schematic diagram showing a preferred embodiment in which a carrier confinement layer is disposed between two active layers. As shown in Figure 15, the VCSEL includes two active layers 20 and 21. There is an epitaxial region between the two active layers 20 and 21. The epitaxial region is between the second surface J2 and the third surface J3; the two active layers 20 A preferred structure of the epitaxial region between 21 and 21 is shown in Figure 9, which includes a tunnel junction layer, an oxide layer and a spacer layer; wherein the carrier confinement layer CF is provided in a part of the spacer layer 263 and is connected to the third spacer layer 263. A spacer layer 263 is also provided between the three surfaces J3, but it is not limited to this. For example, one side of the carrier confinement layer CF can also be used as the side in contact with the active layer 21. FIG. 16 shows that the carrier confinement layer CF can also be disposed in the spacer layer 261 near the second surface J2, and the carrier confinement layer CF is in the middle part of the spacer layer 261.

For a possible embodiment of Figure 14d, please refer to Figure 17a. Carrier confinement layers CF1 and CF2 are provided between the two active layers 20 and 21. Although Figure 17a shows that the carrier confinement layers CF1 and CF2 only occupy the spacer layer 261 and the spacer layer. 263, but it can also be all of the spacer layer 261 and the spacer layer 263; in one embodiment, as shown in Figure 17b, carrier confinement layers CF1 and CF2 are respectively provided above and below the active area A, although Figure 17b is It is shown that the carrier confinement layers CF1 and CF2 only occupy a part of the lower spacer layer 103 and the upper spacer layer 104 , but they can also be the entire lower spacer layer 103 and the upper spacer layer 104 . In some embodiments, carrier confinement layers and carrier confinement layers can also be formed above and/or below any active layer.

In some embodiments, as shown in Figure 17c, carrier confinement layers CF2 and CF3 are disposed between two adjacent active layers 20 and 21, and carrier confinement layers CF1 and CF3 are disposed above and below the active region A. CF4; when holes are injected into the fourth surface J4 through the upper spacer layer 104 and electrons are injected into the active layer 20 from the first surface J1, then the carrier confinement layer (hole confinement layer) CF1 and the carrier confinement layer (electronic hole confinement layer) hole localization layer) CF3 is at least one material in Table 7, and the carrier confinement layer (electron confinement layer) CF2 and the carrier confinement layer (electron confinement layer) CF4 are at least one material selected from Table 8.

If electrons are injected into the fourth surface J4 through the upper spacer layer 104 and holes are injected into the active layer 20 from the first surface J1, then the carrier confinement layer (electron confinement layer) CF1 and the carrier confinement layer (electron confinement layer) ) CF3 is selected from at least one material in Table 8, then the carrier confinement layer CF2 (hole confinement layer) and carrier confinement layer (hole confinement layer) CF4 are at least one material selected from Table 7 and.

[Example 16]

Referring to Figure 18, Figure 18 is a schematic diagram showing a multi-layer structure of a conventional EEL. Referring to Figure 19a, Figure 19a is a schematic diagram showing an embodiment of an EEL with a first semiconductor layer both above and below the active layer. Refer to Figure 19b. FIG. 19b is a schematic diagram showing an embodiment in which carrier confinement layers are provided above and below the active layer of the EEL. The semiconductor laser element shown in Figure 18 is EEL3. As shown in Figure 18, EEL3 includes a GaAs substrate 10 and a multilayer structure 300; the multilayer structure 300 further includes a lower cladding layer 301, The lower photoelectric confinement layer 302 (lower Separated Confinement Hetero-Structure), the active layer 20, the upper photoelectric confinement layer 303 (upper Separated Confinement Hetero-Structure), the upper cladding layer (upper cladding layer) 304 and the ohmic contact layer 305, among which the active layer Layer 20 is between the lower optoelectronic confinement layer 302 and the upper optoelectronic confinement layer 303 .

When the active layers of EEL3 and VCSEL1 have quantum well structures, since the quantum well structures of the two are the same, the first semiconductor layer implemented in each embodiment of VCSEL can also be directly implemented in EEL3; for example, the barrier layer of EEL3 Part or all of the first semiconductor layer is provided. In addition, the preferred material of the well layer is also the same. The principle of setting the first semiconductor layer and some exemplary embodiments are described in detail in Embodiment 1, please refer to; or, the barrier layer of EEL3 Part or all of the second semiconductor layer is provided, and the preferred materials of the well layer and the intermediate layer are also the same as those of the well layer and the intermediate layer in Embodiment 3. The arrangement principles and some exemplary embodiments of the second semiconductor layer are in Embodiment 3. For a detailed description, please refer to it; or, the active layer of EEL3 is further provided with an intermediate layer. The setting principles of the intermediate layer and some exemplary embodiments are detailed in Embodiment 2, please refer to it; or, the adjacent layer of EEL3 The first (second) semiconductor layer is arranged between the two active layers. The principle and exemplary embodiments of the arrangement of the first (second) semiconductor layer in the multiple active layers are described in detail in Embodiment 6; or, in the case of having multiple active layers, For the EEL of the active layer, in addition to setting a tunnel junction layer between the two active layers, a spacer layer can also be further formed. The preferred embodiment of the epitaxial region between the two active layers is described in detail in Embodiment 6. , please refer to. Some of the embodiments in Embodiments 1 to 6 can also be applied to the active layer of EEL. Although the main purpose of Embodiments 1 to 6 is stress compensation, it may also have a carrier confinement effect. Like VCSEL, the laser wavelength of EEL is above 700nm or 800nm.

If stress compensation is the main consideration and the first semiconductor layer is arranged outside the active layer; in terms of VCSEL, the first semiconductor layer is preferably arranged on the lower spacer layer or upper spacer layer of the VCSEL, or the lower spacer layer and The upper spacer layer is provided with the first semiconductor layer; in terms of EEL, the first semiconductor layer is preferably provided in the lower photoelectric confinement layer or the upper photoelectric confinement layer of the EEL, or both the lower photoelectric confinement layer and the upper photoelectric confinement layer are provided with the third semiconductor layer. A semiconductor layer is shown in Figure 19a; the first semiconductor layer can directly or indirectly contact the active layer. Depending on the type of stress and the degree of compensation, the preferred material of the first semiconductor layer can be selected from one of the materials in Table 1 or Table 4. If the energy gap of the selected material is large and the first semiconductor layer is formed in an appropriate position, there may also be Obvious carrier localization effect.

In the part outside the active layer, if carrier confinement is the main consideration, and the carrier confinement layer is arranged outside the active layer; in terms of VCSEL, the carrier confinement layer is preferably arranged at the lower interval of the VCSEL The carrier confinement layer or the upper spacer layer, or both the lower spacer layer and the upper spacer layer are provided with a carrier confinement layer; in terms of EEL, the carrier confinement layer is preferably provided in the lower photoelectric confinement layer or the upper photoelectric confinement layer of the EEL, or Both the lower photoelectric confinement layer and the upper photoelectric confinement layer are provided with carrier confinement layers, as shown in Figure 19b. The carrier confinement layer can directly or indirectly contact the active layer. The preferred material of the carrier confinement layer is selected from at least one material in Table 6. If the lattice constant of the selected material can be changed, it can even provide appropriate stress compensation for the active layer or the epitaxial layer of the VCSEL. Alternatively, in an EEL with multiple active layers, one or two carrier localization layers can be set outside the active area, between two active layers, or between any two active layers. For specific implementations, please refer to Embodiments 11 to 15. .

In some embodiments, if the thickness of the lower optoelectronic confinement layer or the upper optoelectronic confinement layer is thin enough, the carrier confinement layer can also be disposed on the lower cladding layer or the upper cladding layer.

In some embodiments, as shown in Figure 19b, the EEL includes two carrier confinement layers CF1 and CF2. A part of the lower optoelectronic confinement layer 302 is provided with a carrier confinement layer CF1, and a part of the upper optoelectronic confinement layer 303 is provided with a carrier confinement layer. Layer CF2; although two carrier confinement layers are shown in Figure 19b, one carrier confinement layer can also be provided only on part or all of the lower photoelectric confinement layer or the upper photoelectric confinement layer, and the carrier confinement layer can also be in direct contact with the active layer.

[Example 17]

In addition to the quantum well structure, the active regions of VCSEL and EEL also have quantum dot structures (not shown). One embodiment of the quantum dot structure mainly includes quantum dots (Quantum dots), Wetting layer and cap layer; in the quantum dot structure, the preferred material for the quantum dot or wetting layer is InGaAs, InAlGaAs, GaAsSb, GaAs, AlGaAs, AlGaAsSb, GaAsP, InGaAsP or any combination of the above materials.

In the case of VCSEL, in some embodiments, a spacer layer is provided above or below the quantum dot structure of the VCSEL, and in the embodiment of a plurality of quantum dot structures, a spacer layer can also be provided between two quantum dot structures; wherein the first A semiconductor layer (i.e., one of the 17 materials in Table 1) or a carrier confinement layer (i.e., one of the 17 materials in Table 6) can be formed on the covering layer, the spacer layer, or both; the covering layer, the spacer layer, or the above Part or all of them are provided with a first semiconductor layer or a carrier confinement layer.

In some embodiments, a spacer layer is disposed above or below the quantum dot structure of the VCSEL.

For EELs, in some embodiments, an optoelectronic confinement layer is provided under the quantum dot structure of the EEL, or an optoelectronic confinement layer is provided above the quantum dot structure of the EEL. In embodiments of a plurality of quantum dot structures, A lower optoelectronic confinement layer and/or an upper optoelectronic confinement layer is disposed between the two quantum dot structures, and part or all of the covering layer, the lower optoelectronic confinement layer or the upper optoelectronic confinement layer is disposed with a first semiconductor layer or a carrier confinement layer.

In some embodiments, a lower optoelectronic confinement layer and an upper optoelectronic confinement layer are disposed under and above the quantum dot structure of the EEL; or, the covering layer, the lower optoelectronic confinement layer, and the upper optoelectronic confinement layer are all disposed in the first semiconductor layer or carrier confinement layer.

[Example 18]

The substrate material of semiconductor laser elements such as VCSEL and EEL can also be InP. Compared with the GaAs substrate, when the substrate of the semiconductor laser element is an InP substrate, there are more material choices for each epitaxial layer on the substrate, such as Well The layer can be made of aluminum-containing or aluminum-free materials, but the energy gaps of materials suitable as epitaxial layers are relatively small, so the high-temperature characteristics must be further improved.

For example, in the active layer (region), a carrier confinement layer may be provided in a barrier layer, some barrier layers or each barrier layer of the active layer, or one or more carrier confinement layers may be provided in the upper epitaxial region and/or the lower epitaxial region. A carrier confinement layer. The arrangement principles and preferred embodiments of the carrier confinement layer are described in detail in Embodiments 11 to 15. Please refer to them. It is important to note that since the material of the substrate is InP, the preferred material for the carrier localization layer can be InGaP, InAlGaP, InP, InAlAsP, AlAsSb, AlAsBi, AlGaAsSb, AlGaAsBi, AlPSb, AlPBi, InGaAsP or any combination of the above materials. The PL peak wavelength of InGaAsP does not exceed 900nm.

Among the above materials, InGaP, InAlGaP, InP, and InGaAsP (hole confinement layers) have a good hole confinement effect; while InAlAsP, AlAsSb, AlAsBi, AlGaAsSb, AlGaAsBi, AlPSb, and AlPBi (electron confinement layers) have a good electron confinement effect. good.

The distance between the carrier confinement layer and the active layer usually does not exceed 120m, and the thickness of the carrier confinement layer is greater than 2nm.

[Examples 19, 20]

In this specification, the defects or misalignment in the VCSEL epitaxial layer are represented by XRT imaging (X-ray topography) of Comparative Example 1, Embodiment 19, and 20, respectively, to show the improvement of misalignment. Among them, Comparative Example 1, Examples 19 and 20 all use the central area of the VCSEL epiwafer for XRT imaging.

The materials and thicknesses used for each layer in the active layer are shown in Table 9 to compare the embodiments of this specification with the prior art (Comparative Example 1). In Comparative Example 1, there is an InGaAs well layer and a 6 nm AlGaAs barrier layer. In Example 19, a 4 nm AlGaAs intermediate layer is disposed in a GaAsP barrier layer with a thickness of 2 nm. Therefore, the thickness of the two GaAsP barrier layers on both sides of the AlGaAs intermediate layer and adjacent to the well layer is 1 nm ( Total is 2nm). The Al content of AlGaAs and AlGaAsP in Comparative Example 1, Example 19 and Example 20 is all 20%.

Figures 20a to 20c show XRT imaging according to Comparative Example 1 and Examples 19 and 20 of this specification. Figure 20a is the XRT imaging diagram of Comparative Example 1, and Figures 20b and 20c are the XRT imaging diagrams of Example 19 and Example 20 respectively. Through the XRT imaging of Comparative Example 1, it can be observed that Comparative Example 1 has multiple obvious dark lines, that is, obvious dislocations. In contrast, according to the XRT imaging of Example 19, although some dark lines can appear vaguely in Example 19, they are not obvious compared to Comparative Example 1. According to the XRT imaging of Example 20, almost no dark lines can be observed in Example 20 ( dislocation), therefore compared to Comparative Example 1, Examples 19 and 20 can reduce the dislocation of the epitaxial layer of the VCSEL.

Comparative Example 1 uses InGaAs and AlGaAs as the well layer and barrier layer. When the substrate is GaAs, both InGaAs and AlGaAs will generate compressive stress. Excessive compressive stress will cause more dislocations or defects in the epitaxial layer of the VCSEL. As shown in the XRT imaging of Figure 20a, multiple dark lines are clearly visible. In Embodiment 19, a phosphorus-containing material such as GaAsP is used as the barrier layer and AlGaAs is used as the intermediate layer to provide tensile stress in the barrier layer and reduce the stress sum of the active layer, thus reducing the misalignment or misalignment of the epitaxial layer of the VCSEL. defects and can improve carrier confinement capabilities. Example 20 also uses a phosphorus-containing material such as AlGaAsP as the barrier layer to provide tensile stress in the barrier layer. Therefore, compared with Comparative Example 1, defects or dislocations in the epitaxial layer of the VCSEL can be reduced.

The XRT imaging of Examples 19 and 20 shows that using phosphorus-containing materials (one of the 17 materials in Table 1) in semiconductor laser diodes can indeed effectively reduce the dislocation or dislocation of semiconductor laser diodes. defect.

[Examples 21, 22 and Comparative Example 2]

Figure 21 is a comparison diagram of the maximum power conversion efficiency (PCE MAX) of Embodiments 21 and 22 and Comparative Example 2 at different temperatures. In the VCSEL of Comparative Example 2, there is no active layer between the two active layers. A carrier confinement layer that confines holes; the VCSEL of Embodiment 21 is provided with an n-type AlGaInP hole confinement layer between two active layers to confine holes, while the VCSEL of Embodiment 22 is provided with an n-type AlGaInP hole confinement layer between the two active layers. An n-type InGaP hole confinement layer is disposed in between to confine holes. Please refer to Figure 15 for the location of the hole confinement layer. According to Embodiments 21 and 22, holes are injected into the active layer 21 through the fourth surface J4. The electrons are injected into the active layer 20 through the first surface J1; as shown in Figure 21, at room temperature, there is no obvious difference between the maximum power conversion efficiency of Comparative Example 2 and Embodiments 21 and 22, but at high temperatures, the The maximum power conversion efficiency of 21 and 22 is significantly higher than that of Comparative Example 2, and the higher the temperature, the maximum power conversion efficiency can be further improved.

[Example 23 and Comparative Example 3]

Figure 22 is a comparison chart of the maximum power conversion efficiency at different temperatures between Example 23 and Comparative Example 3. The VCSEL of Comparative Example 3 includes five active layers and is not provided with a carrier confinement layer for confining holes, while Example 23 The VCSEL also includes five active layers, and an n-type InGaP hole confinement layer is set between every two adjacent active layers to confine holes; according to Embodiments 21 and 22, holes are injected through the fourth surface J4 In the active layer 21, electrons are injected into the active layer 20 through the first surface J1; as shown in Figure 22, at room temperature, there is no significant difference in the maximum power conversion efficiency between Comparative Example 3 and Embodiment 23. distance, but at high temperature, the maximum power conversion efficiency of Example 23 is significantly higher than that of Comparative Example 2, and the higher the temperature, the maximum power conversion efficiency can be further improved.

It can be seen from this that providing carrier confinement layers in three, four or more active layers also has the effect of improving high-temperature characteristics. Generally speaking, compared with electrons, holes are relatively inactive. In the case of a VCSEL with only one active layer, the light output power density of a single active layer will not significantly increase the active area temperature or junction temperature, so holes are relatively inactive. It is easier to be localized in the active layer, and there is less need to limit the holes; however, in a VCSEL with multiple active layers, the light output power density of the VCSEL will increase significantly, so the active area temperature or junction temperature will also increase significantly. If it is high, the electric holes will become more active, so the electric holes must be limited. If the electric holes cannot be limited to the active layer, the optical characteristics of the VCSEL will be easily limited or difficult to further improve. In addition, VCSELs with multiple active layers achieve high optical output power or high power conversion efficiency through the carrier recycling (CARRIER RECYCLING) mechanism (VCSELs with a single active layer have no carrier recycling). Utilization mechanism), when the ability to confine holes between the two active layers is poor (holes can easily move to the tunnel junction layer), the carrier reuse effect will become worse. The characteristics of VCSEL with multiple active layers Easily degraded at relatively high temperatures. Since the InGaP hole confinement layer is provided in Embodiment 22 and 23 for confining holes, at high temperatures, the maximum power conversion efficiency of the VCSEL with two active layers and the VCSEL with five active layers is indeed significantly improved; similarly In Embodiment 21, the AlInGaP hole confinement layer for confining holes is also provided. Therefore, at high temperatures, the maximum power conversion efficiency of the VCSEL with two active layers is significantly improved.

[Example 24 and Comparative Example 4]

Figure 23 is the L-I-V curve measured at room temperature in Example 24 and Comparative Example 4. Figure 24 is the L-I-V curve measured at high temperature in Example 24 and Comparative Example 4. The room temperature is about 25°C, and the high temperature It is about 65°C; Example 24 is an EEL that includes a hole confinement layer for confining holes, while Comparative Example 4 is an EEL that does not include a carrier confinement layer for confining holes. Example 24 and Comparative Example 4 all use InP substrates; the material of the hole confinement layer used to confine holes is n-type InP (hereinafter referred to as InP carrier confinement layer), and the n-type InP hole confinement layer is provided between the active layer and the lower optoelectronic confinement layer. space, and one side of the n-type InP hole confinement layer is actually in contact with the active layer, that is, the active layer is directly formed on the InP hole confinement layer, where the active layer is made of aluminum-containing material, and the underlying photoelectric confinement layer The side that is in contact with the InP hole confinement layer is also made of aluminum; as shown in Figures 23 and 24, compared with Comparative Example 4 which does not have a carrier confinement layer to confine holes, Example 24 is at room temperature. Both have the same effect due to carrier limitation at high temperatures. has been improved, so the optical power and slope efficiency (SE) have also been improved, where slope efficiency SE is the slope of optical power and current (W/A). In Example 24, the emission wavelength of the laser diode is 1310 nm.

Continuing from the above section, when aluminum-containing materials are used as the barrier layer and well layer in the active layer, the conductive band discontinuity is relatively high and the valence band discontinuity is relatively small. Therefore, the electronic barrier height of the active layer of aluminum-containing materials is usually is higher, but the hole barrier height is lower, so the hole localization in the active layer is usually poor. By placing a phosphorus-containing carrier confinement layer above or below the active layer, the phosphorus-containing carrier confinement layer and the aluminum-containing active layer can form a large valence band discontinuity, so the hole barrier height can be improved to improve the hole localization of the active layer; Embodiment 24 is to provide an n-type InP hole localization layer between the aluminum-containing active layer and the aluminum-containing lower photoelectric localization layer, so that the originally lower price can be reduced. The electrical band discontinuity is significantly increased to increase the hole barrier height, so that the hole localization of the active layer is enhanced. At the same time, the phosphorus-containing carrier confinement layer and the aluminum-containing active layer and the aluminum-containing lower photoelectric confinement layer are The formed conductive band is discontinuous and not too large, so electrons can be injected into the active layer from the lower photoelectric localization layer without any hindrance, so the resistance is not easy to increase, which helps to improve the characteristics of the semiconductor laser diode.

The above are only used to explain the preferred embodiments of the present invention, and are not intended to limit the present invention in any form. Therefore, any modifications or changes related to the present invention are made under the same spirit of the invention. , should still be included in the scope of protection intended by the present invention.

1’:Semiconductor laser element

10’:Substrate

100’:Multi-layer structure

A’: Active area

S1’: semiconductor layer

Claims (40)

A vertical resonant cavity surface emitting laser diode includes: a GaAs substrate; and a multi-layer structure located on the GaAs substrate. The multi-layer structure includes: an active region including; a plurality of active layers including at least two Active layers, the two active layers include an upper active layer and a lower active layer. The upper active layer includes one or more quantum well layers or one or more quantum point structures. The lower active layer includes one or multiple quantum well layers or includes One or a plurality of quantum dot structures, there is an epitaxial region between the upper active layer and the lower active layer, the epitaxial region further includes: a tunnel junction layer; and a hole localization layer located on the upper active layer between the lower active layer and the tunnel junction layer or between the lower active layer and the tunnel junction layer. A vertical resonant cavity surface emitting laser diode as claimed in claim 1, wherein the hole localization layer is selected from the group consisting of InAlGaP, InAlGaPN, InAlGaPSb, InAlGaPBi, InGaAsP, InGaAsPN, InGaAsPSb, InGaAsPBi, InGaP, InGaPN, At least one of the group consisting of InGaPSb, InGaPBi and InAlGaAsP. A vertical resonant cavity surface emitting laser diode as claimed in claim 1, wherein the active region further includes an electron confinement layer, and when the hole confinement layer is located between the upper active layer and the tunnel junction layer time, the electron confinement layer is located between the lower active layer and the tunnel junction layer. A vertical resonant cavity surface emitting laser diode as claimed in claim 1, wherein the active region further includes an electron confinement layer, and when the hole confinement layer is located between the lower active layer and the tunnel junction layer time, the electron confinement layer is located between the upper active layer and the tunnel junction layer. A vertical resonant cavity surface emitting laser diode as claimed in claim 3 or 4, wherein the electron localization layer is selected from the group consisting of AlGaAsP, AlGaAsPN, AlGaAsPSb, AlGaAsPBi, InAlGaP, InAlGaPN, InAlGaPSb, InAlGaPBi and InAlGaAsP At least one type of group. A vertical resonant cavity surface emitting laser diode as claimed in claim 1, wherein one or a plurality of spacer layers are further included between the two active layers, and the tunnel junction layer is provided with the spacer layer. A vertical resonant cavity surface emitting laser diode as claimed in claim 6, wherein the hole confinement layer is disposed in the spacer layer. A vertical resonant cavity surface emitting laser diode as claimed in claim 3 or 4, wherein one or a plurality of spacer layers are further included between the two active layers, above and/or below the tunnel junction layer The spacer layer is provided, and the electron confinement layer is provided in the spacer layer. A vertical resonant cavity surface emitting laser diode as claimed in claim 6 or 7, wherein an oxide layer is further included between the two active layers; between the tunnel junction layer and the oxide layer, The spacer layer is disposed between the tunnel junction layer and the active layer adjacent to the tunnel junction layer or between the oxide layer and the active layer adjacent to the oxide layer. A vertical resonant cavity surface emitting laser diode as claimed in claim 1, wherein an oxide layer is further included between the two active layers, and when the hole localization layer is located at the interface between the upper active layer and the tunnel When between layers, the oxide layer is located between the lower active layer and the tunnel junction layer. A vertical resonant cavity surface emitting laser diode as claimed in claim 1, wherein an oxide layer is further included between the two active layers, and when the hole localization layer is located at the interface between the lower active layer and the tunnel When between layers, the oxide layer is located between the upper active layer and the tunnel junction layer. A vertical resonant cavity surface emitting laser diode includes: a GaAs substrate; and a multilayer structure. On the GaAs substrate, the multilayer structure includes: an active region, including; a plurality of active layers, including at least two active layers. The two active layers include an upper active layer and a lower active layer. The upper active layer includes one or more quantum well layers or one or multiple quantum point structures. The lower active layer includes one or more quantum well layers or includes one Or a plurality of quantum dot structures, with an epitaxial region between the upper active layer and the lower active layer, and the epitaxial region further includes: a tunnel junction layer; and an electron confinement layer located between the upper active layer and the tunnel junction layer or between the lower active layer and the tunnel junction layer. A vertical resonant cavity surface emitting laser diode as claimed in claim 12, wherein the electron localization layer is selected from the group consisting of AlGaAsP, AlGaAsPN, AlGaAsPSb, AlGaAsPBi, InAlGaP, InAlGaPN, InAlGaPSb, InAlGaPBi and InAlGaAsP At least one of. A vertical resonant cavity surface emitting laser diode as claimed in claim 12, wherein the active region further includes a hole confinement layer, and when the electron confinement layer is located between the upper active layer and the tunnel junction layer time, the hole localization layer is located between the lower active layer and the tunnel junction layer. A vertical resonant cavity surface emitting laser diode as claimed in claim 12, wherein the active region further includes a hole confinement layer, and when the electron confinement layer is located between the lower active layer and the tunnel junction layer time, the hole localization layer is located between the upper active layer and the tunnel junction layer. A vertical resonant cavity surface emitting laser diode as claimed in claim 14 or 15, wherein the hole localization layer is selected from the group consisting of InAlGaP, InAlGaPN, InAlGaPSb, InAlGaPBi, InGaAsP, InGaAsPN, InGaAsPSb, InGaAsPBi, InGaP, At least one of the group consisting of InGaPN, InGaPSb, InGaPBi and InAlGaAsP. A vertical resonant cavity surface emitting laser diode as claimed in claim 12, wherein one or a plurality of spacer layers are further included between the two active layers, and the tunnel junction layer is provided with the spacer layer. A vertical resonant cavity surface emitting laser diode as claimed in claim 17, wherein the electron confinement layer is disposed in the spacer layer. A vertical resonant cavity surface emitting laser diode as claimed in claim 14 or 15, wherein one or a plurality of spacer layers are further included between the two active layers, above and/or below the tunnel junction layer The spacer layer is provided, and the hole confinement layer is provided in the spacer layer. A vertical resonant cavity surface emitting laser diode as claimed in claim 17 or 18, wherein an oxide layer is further included between the two active layers; between the tunnel junction layer and the oxide layer, The spacer layer is disposed between the tunnel junction layer and an active layer adjacent to the tunnel junction layer or between the oxide layer and an active layer adjacent to the oxide layer. A vertical resonant cavity surface emitting laser diode includes: an InP substrate; and a multi-layer structure. On the InP substrate, the multi-layer structure includes: an active area including: a plurality of active layers, including at least two active layers. The two active layers include an upper active layer and a lower active layer. The upper active layer includes one or more quantum well layers or one or multiple quantum point structures. The lower active layer includes one or more quantum well layers or includes one Or a plurality of quantum dot structures, with an epitaxial region between the upper active layer and the lower active layer, and the epitaxial region further includes: a tunnel junction layer; and a hole localization layer located on the upper active layer between the tunnel junction layer or between the lower active layer and the tunnel junction layer. The semiconductor laser diode according to claim 21, wherein the hole localization layer is selected from at least one of the group consisting of InGaP, InAlGaP, InP and InGaAsP, wherein the PL peak wavelength of InGaAsP does not exceed 900 nm. . A vertical resonant cavity surface emitting laser diode as claimed in claim 21, wherein the active region further includes an electron confinement layer, and when the hole confinement layer is located between the upper active layer and the tunnel junction layer time, the electron confinement layer is located between the lower active layer and the tunnel junction layer. A vertical resonant cavity surface emitting laser diode as claimed in claim 21, wherein the active region further includes an electron confinement layer, and when the hole confinement layer is located between the lower active layer and the tunnel junction layer time, the electron confinement layer is located between the upper active layer and the tunnel junction layer. A vertical resonant cavity surface emitting laser diode as claimed in claim 23 or 24, wherein the electron confinement layer is selected from the group consisting of InAlAsP, AlAsSb, AlAsBi, AlGaAsSb, AlGaAsBi, AlPSb and AlPBi At least one. The vertical resonant cavity surface emitting laser diode as claimed in claim 21, wherein one or a plurality of spacer layers are further included between the two active layers, and the spacers are provided above and/or below the tunnel junction layer. layer. A vertical resonant cavity surface emitting laser diode as claimed in claim 26, wherein the hole confinement layer is disposed in the spacer layer. A vertical resonant cavity surface emitting laser diode as claimed in claim 23 or 24, wherein one or a plurality of spacer layers are further included between the two active layers, above and/or below the tunnel junction layer The spacer layer is provided, and the electron confinement layer is provided in the spacer layer. A semiconductor laser diode as claimed in claim 26 or 27, wherein an oxide layer is further included between the two active layers; between the tunnel junction layer and the oxide layer, the tunnel junction The spacer layer is disposed between the surface layer and the active layer adjacent to the tunnel junction layer or between the oxide layer and the active layer adjacent to the oxide layer. A vertical resonant cavity surface emitting laser diode as claimed in claim 21, wherein an oxide layer is further included between the two active layers, and when the hole localization layer is located at the interface between the upper active layer and the tunnel When between layers, the oxide layer is located between the lower active layer and the tunnel junction layer. A vertical resonant cavity surface emitting laser diode as claimed in claim 21, wherein an oxide layer is further included between the two active layers, and when the hole localization layer is located at the interface between the lower active layer and the tunnel When between layers, the oxide layer is located between the upper active layer and the tunnel junction layer. A vertical resonant cavity surface emitting laser diode includes: an InP substrate; and a multi-layer structure. On the InP substrate, the multi-layer structure includes: an active area including: a plurality of active layers, including at least two active layers. The two active layers include an upper active layer and a lower active layer. The upper active layer includes one or more quantum well layers or one or multiple quantum point structures. The lower active layer includes one or more quantum well layers or includes one Or a plurality of quantum dot structures, with an epitaxial region between the upper active layer and the lower active layer, and the epitaxial region further includes: a tunnel junction layer; and an electron confinement layer located between the upper active layer and the tunnel junction layer or between the lower active layer and the tunnel junction layer. A vertical resonant cavity surface emitting laser diode as claimed in claim 32, wherein the electron confinement layer is at least one selected from the group consisting of InAlAsP, AlAsSb, AlAsBi, AlGaAsSb, AlGaAsBi, AlPSb and AlPBi . A vertical resonant cavity surface emitting laser diode as claimed in claim 32, wherein the active region further includes a hole confinement layer, and when the electron confinement layer is located between the upper active layer and the tunnel junction layer time, the hole localization layer is located between the lower active layer and the tunnel junction layer. A vertical resonant cavity surface emitting laser diode as claimed in claim 32, wherein the active region further includes a hole confinement layer, and when the electron confinement layer is located between the lower active layer and the tunnel junction layer time, the hole localization layer is located between the upper active layer and the tunnel junction layer. A vertical resonant cavity surface emitting laser diode as claimed in claim 34 or 35, wherein the hole localization layer is selected from at least one of the group consisting of InGaP, InAlGaP, InP and InGaAsP, wherein InGaAsP The PL peak wavelength does not exceed 900nm. A vertical resonant cavity surface emitting laser diode as claimed in claim 32, wherein one or a plurality of spacer layers are further included between the two active layers, and the tunnel junction layer is provided with the spacer layer. A vertical resonant cavity surface emitting laser diode as claimed in claim 37, wherein the electron confinement layer is disposed in the spacer layer. A vertical resonant cavity surface emitting laser diode as claimed in claim 34 or 35, wherein one or a plurality of spacer layers are further included between the two active layers, above and/or below the tunnel junction layer The spacer layer is provided, and the hole confinement layer is provided in the spacer layer. A vertical resonant cavity surface emitting laser diode as claimed in claim 37 or 38, wherein an oxide layer is further included between the two active layers; between the tunnel junction layer and the oxide layer, The spacer layer is disposed between the tunnel junction layer and the active layer adjacent to the tunnel junction layer or between the oxide layer and the active layer adjacent to the oxide layer.

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