TWI817834B - Memory architecture and data processing method - Google Patents

Abstract

The present disclosure provides a memory architecture and data processing method. The memory architecture arranges a scheduler according to a transmission data by a time-division multiplexing. The memory architecture has a first processing module. The processing module provides a schedule information of a time-division multiplexing to execute the schedule and obtain an addressing package information. The first processing module transmits the transmission data to a specified chip address according to the schedule information of the time-division multiplexing and the addressing package information. Thereby, the resources of each chip may be integrated to meet the demands of different users. The purpose of rising a flexible usage for the chips may be achieved.

Description

Memory architecture and data processing methods

The invention relates to a chip structure, and in particular to a memory structure and a data processing method thereof.

A wafer stack structure is currently formed through a Wafer On Wafer (WOW) process. The wafer stack structure includes a substrate, a logic circuit layer and a memory crystal layer. The substrate, the logic circuit layer and The memory crystal layer has a plurality of accommodating cavities between each other. The accommodating cavities respectively form a plurality of chips corresponding to the substrate, the logic circuit layer and the memory crystal layer, and through the accommodating cavities A metal layer is provided on the body so that the substrate, the logic circuit layer and the memory crystal layer are electrically connected to each other, and through the wafer stacking process, the chips (Integrated Circuit, IC) can be manufactured at the same time, Then, the wafers are divided from each other to form a wafer.

In order to accurately separate the wafers, a sealing ring is provided on the logic circuit layer and the memory crystal layer. Through the sealing ring, the accommodation cavities are independent and not connected to each other, so that they can be separated along the The sealing ring separates the wafers into wafers.

However, in the existing technology, each accommodation cavity is independently disconnected through the sealing ring, so that electrical signals cannot be transmitted between the chips. As a result, after the chips are subsequently divided, only each chip can be used. The logic circuit layer and the memory crystal layer formed by the chip cannot be integrated and used according to the user's needs, which limits the user's use.

Therefore, it is necessary to further provide better improvement solutions in the existing technology.

In view of the above-mentioned shortcomings of the prior art, the main purpose of the present invention is to provide a memory architecture and a data processing method thereof, using time-division multiplexing (TDM) technology in the memory architecture to enable the processing of each chip. Data can be transferred between chips, which can improve the flexibility of use between chips.

To achieve the above objectives, the main technical means adopted by the present invention are mainly to apply the data processing method of the aforementioned memory architecture to the memory architecture with a first processing module, and the first processing module performs the following steps : Provide a time-sharing multiplexing scheduling information; obtain a timing information based on the time-sharing multiplexing scheduling information; based on the timing information, correspondingly preset the address of a chip; obtain a certain address packet information; and based on the timing information The timing information corresponds to the preset address of the chip and the addressing packet information, and transmits a transmission data to the specified address of the chip.

Through the above method, the first processing module can send the transmission data to the designated destination based on the time-sharing scheduling information and the addressing packet information. The address of the chip; thereby integrating the resources of each chip to respond to different user needs and achieve the purpose of improving the flexibility of use between each chip.

Another main technical means adopted by the present invention to achieve the above object is to make the aforementioned memory architecture include: a first chip; a second chip; and a first processing module that provides time-sharing multiplexing scheduling information, obtains timing information based on the time-sharing multiplexing scheduling information, and obtains a certain address Packet information; wherein the first processing module correspondingly presets an address of a first chip and an address of a second chip according to the timing information and the addressing packet information, and sends a transmission data to the designated first The address of the wafer or the second wafer.

Through the above structure, the first processing module can transmit the transmission data between the first chip or the second chip according to the time-sharing scheduling information and the addressing packet information, especially by The first chip specifies that the transmission data is sent to the address of the second chip, or the second chip specifies that the transmission data is sent to the address of the first chip; thereby the structure can integrate the resources of each chip, In order to respond to different user needs and achieve the purpose of improving the flexibility of use between various chips.

10:Memory architecture

11:First chip

12:Second chip

13:First processing module

13’: Second processing module

14:First memory

140:First cluster address

141:Second cluster address

14’: Second memory

15:First input/output interface address

15’: Second input/output interface address

30:Send chip address

31: Send cluster address

32:Receive chip address

33:Receive cluster address

34: Payload

Figure 1 is a system block diagram of a memory architecture according to a preferred embodiment of the present invention; Figure 2 is a system block diagram of a memory architecture according to a preferred embodiment of the present invention; Figure 3 is a system block diagram of a memory architecture according to a preferred embodiment of the present invention; Block diagram; Figure 4A is a schematic diagram of the transmission schedule of the addressed packet information in the preferred embodiment of the present invention; Figure 4B is a schematic diagram of the transmission path in the preferred embodiment of the present invention; Figure 5 is a schematic diagram of the addressed packet information in the preferred embodiment of the present invention. A schematic diagram of the addressed packet transmission format; Figure 6 is a flow chart of the data processing method of the memory architecture of the present invention; Figure 7 is a flow chart of another data processing method of the memory architecture of the present invention; Figure 8 is the memory architecture of the present invention. Another data processing method flow chart; FIG. 9 is another data processing flow chart of the memory architecture of the present invention; and FIG. 10 is another data processing flow chart of the memory architecture of the present invention.

Regarding the preferred embodiment of the memory architecture 10 of the present invention, the time-division multiplexing (TDM) technology is mainly applied inside the memory architecture 10 to schedule a transmission data, as shown in Figure 1 and As shown in Figure 2, the memory architecture 10 includes a first chip 11 and a second chip 12. The first chip 11 includes a first processing module 13 and a first memory 14, and the second chip 11 includes a first processing module 13 and a first memory 14. 12 includes a second processing module 13' and a second memory 14'.

Specifically, the first processing module 13 transmits the transmission data to a designated first chip or the second chip according to a time division multiplexing (TDM) schedule information and certain address packet information. The address of the chip, so that the first chip 11 and the second chip 12 can transmit data to each other, so that the first chip 11 and the second chip 12 can be used at the same time to achieve integration of the first chip 11 and The purpose of the second wafer 12. In this embodiment, the data processing method performed by the second processing module 13' is substantially the same as that of the first processing module 13, and will not be described again.

In this embodiment, the time-sharing multiplexing scheduling information includes timing information, and the timing information corresponds to preset addresses of the first chip and the second chip.

In this embodiment, as shown in FIG. 3 , the first memory 14 has a first cluster address 140 and a first input/output interface address 15. The first processing module 13 performs the processing according to the timing information. A first timing sequence and a second timing sequence correspond to the preset first cluster address 140 and the first input/output interface address 15. The second memory 14' has a second cluster address 141 and a The second input/output interface address 15', the first processing module 13 correspondingly presets the second cluster address 141 and the second input/output according to a third timing and a fourth timing in the timing information. Interface address 15'.

In this embodiment, as shown in FIG. 4A and FIG. 4B , the time-sharing multiplexing scheduling information includes a first column recording the timing information, and the timing information has the first timing, the second timing, A third timing sequence and a fourth timing sequence, and the time-sharing multiplexing schedule information includes a second to fifth column that record the address of the chip. Taking the second column as an example, the first processing module 13 According to the time-sharing scheduling information and the addressed packet transmission format, for convenience of explanation, please refer to the arrow direction in Figure 4A. The arrow direction indicates the transmission direction of the transmission data. The first The transmission data in the cluster address 140 is transmitted to the first input/output interface address 15, and the transmission data in the first input/output interface address 15 is transmitted to the second input/output interface address 15' , the transmission data in the second input/output interface address 15' is sent to the second cluster address 141, and the transmission data in the first cluster address 140 is received from the second cluster address 141 of the transmission data.

Further, taking the third example as an example, the first processing module 13 sequentially processes the transmission in the first input/output interface address 15 according to the time-sharing scheduling information and the addressed packet transmission format. The data is transmitted to the second input/output interface address 15', the transmission data in the second input/output interface address 15' is transmitted to the second cluster address 141, and the transmission data in the second cluster address 141 The transmission data is transmitted to the first cluster address 140, and the transmission data in the first input/output interface address 15 is to receive the transmission data in the first cluster address 140. As a result, a cyclic transmission is formed between the first cluster address 140, the second cluster address 141, the first input/output interface address 15, and the second input/output interface address 15'.

In this embodiment, as shown in Figure 5, an addressed packet transmission format is generated based on the addressed packet information and the transmission data. The addressed packet transmission format has a sending chip address 30, a sending cluster address 31, and a receiving The chip address 32, a receiving cluster address 33 and a payload (Payload) 34 are used to carry the transmission data.

In this embodiment, the first processing module 13 sets the sending chip address and the sending cluster address corresponding to the preset first cluster address 140 according to the first timing, and sets the sending chip address and the sending cluster address according to the second timing. Corresponding to the default first input/output interface address 15, set the receiving chip address and the receiving cluster address, and transmit the transmission data to the receiving chip address and the receiving cluster address according to the sending chip address, the sending cluster address, the receiving chip address and the receiving cluster address.

In this embodiment, the first processing module 13 sets the sending chip address and the sending cluster address corresponding to the preset first input/output interface address 15 according to the second timing, and sets the sending chip address and the sending cluster address according to the second timing sequence. Three timings correspond to the preset second input/output interface address 15', set the receiving chip address and the receiving cluster address, and according to the sending chip address, the sending cluster address, the receiving chip address and the receiving cluster address, transmitting the transmission data to the receiving chip address and the receiving cluster address.

In this embodiment, the first processing module 13 sets the sending chip address and the sending cluster address according to the preset second input/output interface address 15' corresponding to the third timing, and according to the The fourth timing corresponds to the preset second cluster address 141, sets the receiving chip address and the receiving cluster address, and based on the sending chip address, the sending cluster address, the receiving chip address and the receiving Cluster address, transmit the transmission data to the receiving chip address and the receiving cluster address.

In the above embodiment, the first memory 14 further includes a third cluster address (not shown), and the second memory 14' may further include a fourth cluster address (not shown). ), and the timing information will also be increased to adjust the time-sharing multiplexing schedule information, so that the first processing module 13 can process the third time-sharing multiplexing schedule according to the adjusted time-sharing multiplexing schedule information. The transmission data in a cluster address 140 is transmitted to the third cluster address, and then the transmission data in the third cluster address is transmitted to the first input/output interface address 15, and further, The transmission data in the first input/output interface address 15 is sent to the second input/output interface address 15', and then the transmission data in the second input/output interface address 15' is sent to The second cluster address 141, and finally, the transmission data in the second cluster address 141 is transmitted to the fourth cluster address.

As for the data processing method of another memory architecture of the present invention, as shown in Figure 6, the memory architecture has a first processing module, and the first processing module performs the following steps: Provide a time-sharing multiplexing schedule information (S10); obtain a certain address packet information (S20); and transmit a transmission data to a designated chip based on the time-sharing multiplexing schedule information and the address packet information address (S30).

In this embodiment, as shown in Figure 7, when the above method is executed to the step of "providing a time-sharing multiplexing schedule information (S10)", the following sub-steps are further performed: according to the time-sharing multiplexing schedule information, obtain timing information (S11); and correspondingly preset the address of the chip based on the timing information (S12).

In this embodiment, as shown in Figure 8, when the above method is executed to the step of "according to the timing information, correspondingly preset the address of the chip (S12)", it further includes the following sub-steps: Obtaining a first address of the chip A cluster address and a first input/output interface address (S120); and correspondingly presetting the first cluster address and the first input according to a first timing and a second timing in the timing information /Output interface address (S121).

In this embodiment, as shown in Figure 9, when the above method is executed to the step of "obtaining certain-addressed packet information (S20)", it includes the following sub-steps: generating certain-addressed packet transmission according to the certain-addressed packet information and the transmission data. Format (S21); and wherein, the addressed packet transmission format has a transmitting chip address, a transmitting cluster address, a receiving chip address, a receiving cluster address and the transmission data.

In this embodiment, as shown in Figure 10, when the above method is executed to "according to the time-division multiplexing scheduling information and the addressing packet information, a transmission data is sent to the address of a designated chip (S30) ” steps, including the following sub-steps: Obtain the first timing and the second timing, corresponding to the preset first cluster address and the first input/output interface address (S31); correspond to the preset first cluster bit according to the first timing address, set the sending chip address and the sending cluster address (S32); set the receiving chip address and the receiving cluster address corresponding to the preset first input/output interface address according to the second timing (S32) S33); and transmit the transmission data to the receiving chip address and the receiving cluster address according to the sending chip address, the sending cluster address, the receiving chip address and the receiving cluster address (S34).

To sum up, the first processing module can transmit the transmission data to the designated address of the chip based on the time-sharing scheduling information and the addressing packet information. In this way, each chip can be integrated resources to respond to different user needs and improve the flexibility of use between chips.

10:Memory architecture

11:First chip

12:Second chip

Claims (11)

A data processing method for a memory architecture. The memory architecture has a first processing module, and the first processing module performs the following steps: providing time-sharing multiplexing scheduling information; according to the time-sharing The multiplexing schedule information is used to obtain timing information; according to the timing information, the address of a chip is correspondingly preset; a certain address packet information is obtained; and according to the timing information, the address of the chip and the address packet information are correspondingly preset. , transmit a transmission data to the specified address of the chip. The data processing method of the memory architecture as described in claim 1, wherein when the above method is executed to the step of "according to the timing information, correspondingly preset the address of the chip", it further includes the following sub-steps: Obtaining the address of the chip a first cluster address and a first input/output interface address; and correspondingly presetting the first cluster address and the first input/output interface according to a first timing and a second timing in the timing information. Output interface address. The data processing method of memory architecture as described in claim 2, wherein when the above method is executed to the step of "obtaining a certain address packet information", it includes the following sub-steps: generating a certain address based on the address packet information and the transmission data. Packet transmission format; wherein, the addressed packet transmission format has a sending chip address, a sending cluster address, a receiving chip address, a receiving cluster address and the transmission data. The data processing method of memory architecture as described in claim 3, wherein when the above method is executed to "transmit a transmission data to a designated chip based on the time-sharing scheduling information and the addressing packet information, Address" step, including the following sub-steps: The first timing and the second timing are obtained, corresponding to the preset first cluster address and the first input/output interface address; according to the first timing corresponding to the preset first cluster address, set the sending chip address and the sending cluster address; setting the receiving chip address and the receiving cluster address according to the second timing corresponding to the preset first input/output interface address; and according to the sending chip bit address, the transmitting cluster address, the receiving chip address and the receiving cluster address, and transmit the transmission data to the receiving chip address and the receiving cluster address. A memory architecture, which includes: a first chip; a second chip; and a first processing module that provides time-sharing multiplexing scheduling information and obtains time-sharing multiplexing scheduling information based on the time-sharing multiplexing scheduling information A timing information, and obtain certain addressed packet information; wherein, the first processing module correspondingly presets an address of a first chip and an address of a second chip according to the timing information and the addressed packet information, and transmits a transmission The data is transmitted to the specified address of the first chip or the second chip. The memory architecture of claim 5, wherein the first chip includes: a first memory having a first cluster address and a first input/output interface address; wherein the first processing The module correspondingly presets the first cluster address and the first input/output interface address according to a first timing and a second timing in the timing information. The memory architecture of claim 6, wherein the second chip includes: a second memory having a second cluster address and a second input/output interface address; wherein the first processing A third timing and a fourth timing in the timing information of the module correspond to the preset second cluster address and the second input/output interface address. The memory architecture of claim 7, wherein the first processing module generates an addressed packet transmission format based on the addressed packet information and the transmission data. The addressed packet transmission format has a transmitting chip address and a transmitting cluster. address, a receiving chip address, a receiving cluster address and the transmission data. The memory architecture of claim 8, wherein the first processing module sets the sending chip address and the sending cluster address corresponding to the preset first cluster address according to the first timing, and According to the second timing corresponding to the preset first input/output interface address, the receiving chip address and the receiving cluster address are set, and according to the sending chip address, the sending cluster address, the receiving chip bit address and the receiving cluster address, and transmit the transmission data to the receiving chip address and the receiving cluster address. The memory architecture of claim 9, wherein the first processing module sets the sending chip address and the sending cluster address corresponding to the preset first input/output interface address according to the second timing. , and set the receiving chip address and the receiving cluster address according to the preset second input/output interface address corresponding to the third timing, and according to the sending chip address, the sending cluster address, the receiving The chip address and the receiving cluster address are used to transmit the transmission data to the receiving chip address and the receiving cluster address. The memory architecture of claim 10, wherein the first processing module sets the sending chip address and the sending cluster address corresponding to the preset second input/output interface address according to the third timing. , and set the receiving chip address and the receiving cluster address according to the preset second cluster address corresponding to the fourth timing, and according to the sending chip address, the sending cluster address, the receiving chip address and the receiving cluster address, transmitting the transmission data to the receiving chip address and the receiving cluster address.

Images