TWI817300B - Integrated system and method for quality management of mosfet - Google Patents

Abstract

An integrated system and a method for quality management of MOSFET, wherein a design server receives a chip probing data transmitted from a manufacturing server and a final test data transmitted from a package server and then extracts the required chip probing data and the final test data which are in different formats. Further, the above-mentioned data are stored in the design server to facilitate the IC designer to quickly and accurately determine the problem of process errors.

Description

Integrated system and method for quality management of MOSFETs

The present invention relates to an integrated system and method for quality management of metal oxide semi-field effect transistors, in particular to a metal oxide semi-field effect transistor that integrates relevant data of the design, manufacturing and packaging processes to improve the quality of metal oxide semi-field effect transistors. Quality management integrated systems and methods.

Most of today's Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) quality management technologies use a single process for correction, such as CN106298582B: During electrical testing, based on the abnormal data of the current batch of back-end tests , query the correspondence table to find the suspected process abnormal step of the current batch; TW200949476A: Based on the error code of the abnormal signal of the test machine, determine the type of the reported signal, and notify the person in charge of the machine to perform maintenance, etc.

However, although integrated circuit (IC) design factories can predict the quality of ICs through design verification, they usually cannot obtain the actual errors in wafer manufacturing and packaging testing in real time, and have to spend a long time waiting for wafer manufacturing. In addition, the data provided by different manufacturers have different data formats, so engineers at IC design factories need to spend a lot of time and energy sorting out massive amounts of data to find problem points that may cause process errors. .

Accordingly, how to integrate relevant data from the design, manufacturing, and packaging processes of MOSFET products to improve the quality of MOSFET products is a problem that needs to be solved.

In view of the above problems, the inventor of the present invention has improved the integrated system and method for quality management of metal oxide semi-field effect transistors based on many years of experience in related industries. Therefore, the main purpose of the present invention is to provide an integrated metal oxide semi-field effect transistor. Data related to the design, manufacturing, and packaging processes of MOSFET products to develop an integrated system and method for MOSFET quality management to improve the quality of MOSFET products.

In order to achieve the above purpose, the present invention mainly receives a bare die probing data sent by a manufacturing server and a final test data sent by a packaging server through a design server, and uses a semantic analysis module to analyze the data according to the complex number. A set of data fields is used to identify a bare die probing word structure and a final test word structure in the die probing data and the final test data respectively, and then a data analysis module is used according to the die probing word structure. structure and final test word structure, respectively extract the corresponding die test data and final test data, and store them in the design server; in this way, engineers at the IC design factory can grab the gold from the design server. Relevant data on the design, manufacturing, and packaging processes of oxygen-semi-field effect transistor products to quickly identify the problem points of process errors.

In order to enable you, the review committee, to clearly understand the purpose, technical features and effectiveness of the present invention, the following description is provided with illustrations, please refer to it.

Please refer to "Figure 1", which is a system architecture diagram (1) of the present invention. As shown in the figure, the MOSFET quality management integrated system of the present invention mainly includes a design server 1, which is connected with a manufacturing server. The server 2 and a packaged server 3 are connected for information. The server 1 is designed to have a processing unit 11, and a storage unit 12 and a communication unit 13 are connected for information to the processing unit 11.

The processing unit 11 may include a semantic analysis module 111 and a data analysis module 112. The semantic analysis module 111 may execute a natural language processing (NLP) to perform word segmentation analysis and grammar analysis on the input data. analysis, text classification, information extraction, etc., and then automatically extract specific information for database access. The data analysis module 112 can extract corresponding data for data analysis based on the specific information; in addition, the processing unit 11 can It is a microcontroller unit (MCU), which may include at least one processor and at least one memory, and the memory and the processor are electrically connected so that the processor can access specific instruction codes from the memory, and Execute the application program defined by the specific instruction code. The aforementioned application program mainly includes: an application program that allows the processing unit 11 to convert data formats (natural language processing), an application program that allows the processing unit 11 to analyze data, and a program that allows the processing unit 11 to track regularly. and applications that collect data, applications that enable the communication unit 13 to communicate with other devices, etc.

The storage unit 12 can be used to store electronic data, and can be a solid state disk (Solid State Disk or Solid State Drive, SSD), a hard disk (Hard Disk Drive, HDD), or a static memory (Static Random Access Memory, SRAM). ), a random access memory (Random Access Memory, DRAM), or a cloud drive (Cloud Drive), or any combination thereof.

The communication unit 13 can be used to receive/transmit data through the network, the manufacturing server 2, and the packaging server 3. The aforementioned network can be a local area network, a wide area network, a 4G network, a 5G network, A Wi-Fi network, a Bluetooth network, or a combination thereof.

Please refer to "Figure 2", which is a flow chart of the method of the present invention. As shown in the figure, the integrated method for quality management of metal oxide semiconductor field effect transistors of the present invention has the following steps:

Manufacturing control S1: Please refer to "Figure 3", which is a schematic diagram (1) of the implementation of the present invention. As shown in the figure, the design server 1 uses the communication unit 13 to store an integrated circuit in the storage unit 12 The design data D1 is sent to the manufacturing server 2 for the operator of the manufacturing server 2 to perform wafer manufacturing based on the integrated circuit design data D1. When the wafer manufacturing is completed, the operator of the manufacturing server 2 returns a die pin Test data (Chip Probing, CP) D2 to the design server 1; among them, the integrated circuit design data D1 may include an integrated circuit design drawing, a corresponding design verification data, etc., and the bare chip probing data D2 may include The production yield judgment standard is one of a threshold voltage, a source-drain breakdown voltage, a gate-source leakage current, and a sink-source leakage current, or a combination thereof.

Identify the bare die probing word structure S2: Since different brands and different types of instruments will produce different formats of bare die probing data D2, the bare die probing data D2 is subjected to a natural language processing (Natural Language Processing) in advance. , NLP), please refer to "Figure 4", which is a schematic diagram (2) of the implementation of the present invention. As shown in the figure, after receiving one or more pieces of die probing data D2, the semantic analysis module 111 according to the storage unit The plurality of data field sets in 12 identify one or a plurality of die pin test word structures D3 in the die pin test data D2, wherein the die pin test word structure D3 can include a plurality of die pin test words. A first keyword T1 and a second keyword T2 in the measurement data D2. The aforementioned keywords may be related words for metal oxide semiconductor field effect transistor bare chip needle testing, and in other embodiments, the keywords It is not limited to the first keyword T1 and the second keyword T2, and may further include a plurality of keywords; the data field set may include the corresponding collocation relationship between the first keyword T1 and the second keyword T2, and the aforementioned collocation relationship may be a key One or a combination of the collocation attributes of word order, the collocation attributes of keyword word boundaries, the collocation attributes of keyword language, the collocation attributes of keyword proper nouns, and the collocation attributes of keyword parts of speech, but not in this way is limited to; for example, different die measurement data D2 have different names for "gate source leakage current". After comparison and analysis by the semantic analysis module 111 according to the matching attributes in the data field set, all can be Identify the keywords belonging to different permutations or data fields in different die probe data D2, such as "leakage current", "I _GS ", "IGSS", "gate source", "GS", etc. A single keyword or combination should belong to the word structure D3 of the bare chip pin test of "gate source leakage current".

Continuing with the above, for further details, please refer to "Figure 5", which is a schematic diagram (3) of the implementation of the present invention. As shown in the figure, the data field collection can be based on the collocation attributes and keyword boundaries of the keyword order. One or a combination of the collocation attributes, the collocation attributes of the keyword language, the collocation attributes of the keyword proper nouns, and the collocation attributes of the keyword part of speech, etc., form a semantic structure of a tree structure.

Extract the corresponding die pin measurement value S3: the data analysis module 112 extracts the corresponding die pin measurement data D2 according to the die pin pin measurement word structure D3, and stores it in the storage unit 12; for example , please continue to refer to "Figure 4". As shown in the figure, the IGSS, gate source leakage current, and leakage current (GS) in different die pin test data D2 all belong to the die pin test words of "gate source leakage current". Structure D3.

Determine the wafer production yield rate S4: If the wafer production yield rate reaches more than 95%, perform packaging control S5; if the wafer production yield rate is lower than 95% (excluding 95%), perform bare chip pin test Analysis S9.

Packaging control S5: Please refer to "Figure 6", which is a schematic diagram (4) of the implementation of the present invention. As shown in the figure, the design server 1 uses the communication unit 13 to store the integrated circuit design in the storage unit 12 The data D1 is sent to the packaging server 3 for the operator of the packaging server 3 to perform integrated circuit packaging based on the integrated circuit design data D1. When the integrated circuit packaging is completed, the operator of the packaging server 3 returns a final test Data (Final Testing, FT) D4 is sent to the design server 1. The final test data D4 can include a drain-source impedance, a threshold voltage, a source-drain breakdown voltage, a gate-source leakage current, and a drain-source leakage current. , and an avalanche energy, etc., or the packaging yield judgment criteria of one or a combination thereof.

Identify the final test word structure S6: This step is similar to identifying the die test word structure S2. The difference is that natural language processing is performed on the final test data D4. After receiving one or multiple pieces of the final test data D4, the semantic meaning The analysis module 111 identifies one or a plurality of final test word structures D5 in the final test data D4 according to the plurality of data field sets in the storage unit 12, wherein the final test word structure D4 may include a plurality of final tests. A third keyword and a fourth keyword in the data D4. The aforementioned keywords may be related words for final testing of MOSFETs, and in other embodiments, the keywords are not limited to the third keyword. The word and the fourth keyword can further include a plurality of keywords; the data field set can include the corresponding collocation relationship between the third keyword and the fourth keyword, and the aforementioned collocation relationship can be the collocation attributes and keywords in the sequence of the keywords. One or a combination of, but not limited to, the collocation attributes of word boundaries, the collocation attributes of keyword language, the collocation attributes of keyword proper nouns, and the collocation attributes of keyword parts of speech.

Extract the corresponding final test value S7: Please refer to "Figure 7", which is a schematic diagram (5) of the implementation of the present invention. As shown in the figure, the data analysis module 112 extracts the corresponding final test value S7 based on the final test word structure D5. The final test data D4 is stored in the storage unit 12 .

Determine the integrated circuit packaging yield rate S8: If the integrated circuit packaging yield rate reaches more than 92%, the process ends; if the integrated circuit packaging yield rate is lower than 92% (excluding 92%), the final test analysis is performed S10 .

Bare chip pin test analysis S9: Please refer to "Figure 8", which is a schematic diagram of the metal oxide semi-field effect transistor bare chip pin test data of the present invention. As shown in the figure, the data analysis module 112 extracts the product in the storage unit 12 Analyze the integrated circuit design data D1 and the bare chip needle test data D2, compare whether the value of the bare chip needle test data D2 is consistent with the allowable value of the integrated circuit design data D1, and based on the non-matching bare chip needle test error value E1 executes the wafer design change S11, and corrects the photosensitive agent coating, exposure, development, etching and other processing methods and parameters of the wafer production based on the bare die needle measurement error value E1.

Final test analysis S10: The data analysis module 112 analyzes the integrated circuit design data D1 and the final test data D4 in the storage unit 12, and compares whether the value of the final test data D4 is consistent with the allowable value of the integrated circuit design data D1. , a final test error value, and further execute S12 to determine whether the error value is related to the package. If so, execute the package design change S13, and correct the cutting, wiring, adhesion, and sealing of the packaging production based on the inconsistent final test error value. Wait for the manufacturing method and parameters; if not, perform wafer design change S11.

In one embodiment, please refer to "Fig. 9", which is the system architecture diagram (2) of the present invention. As shown in the figure, the processing unit 11 may further include a tracking module 113, and the tracking module 113 can be used for timing The manufacturing server 2 and the packaging server 3 are required to send back a feedback information F so that the operator of the design server 1 is aware of the situation of wafer manufacturing and integrated circuit packaging. The feedback information F may include manufacturing or packaging progress, manufacturing Or one or a combination of encapsulated errata, estimated completion time of each project, etc.

It can be seen from the above that the MOSFET quality management integrated system and method of the present invention mainly receives the bare die probing data transmitted by the manufacturing server through the design server, and then determines whether the wafer manufacturing yield has been implemented. Needle test analysis to make design changes based on error points; secondly, the design server receives the final test data sent by the packaging server, determines whether the packaging yield is the final test analysis, and then determines whether the error point is related to the packaging, and then targets the error point Make design changes; furthermore, the present invention can extract the required bare chip probing data and final test data from data in different formats, and the relevant data of each design, manufacturing, and packaging link will be stored in the design server In order to facilitate the engineers of the IC design factory to quickly and accurately determine the problem of process errors; it can be seen from the above that after the present invention is implemented, it can indeed provide an integrated metal oxide semi-field effect transistor product design, manufacturing, and packaging processes. The relevant data is for the purpose of improving the quality of metal oxide semiconductor field effect transistor products and the integrated system and method of metal oxide semiconductor field effect transistor quality management.

However, the above are only preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Anyone skilled in the art can make equal changes and modifications without departing from the spirit and scope of the present invention. , should all be covered by the patent scope of the present invention.

To sum up, the invention has the patent requirements of "industrial applicability", "novelty" and "progressivity"; the applicant has filed an invention patent application with the Jun Bureau in accordance with the provisions of the Patent Law.

1 Design server 11 Processing unit 111 Semantic analysis module 112 Data analysis module 113 Tracking Module 12 storage units 13 Communication unit 2 Manufacturing Servers 3 Packaging Servers S1 Manufacturing Control S2 Distinguish the word structure of bare chip needle test S3 Extract the corresponding bare die needle measurement value S4 Determine wafer production yield S5 packaging control S6 Identify the final test word structure S7 Extract the corresponding final test value S8 Determine integrated circuit packaging yield S9 bare die pin test analysis S10 final test analysis S11 Wafer design changes S12 Determine whether the error value is related to packaging S13 Package design changes D1 Integrated circuit design data D2 Bare chip probing data D3 Bare chip needle test word structure D4 Final test data D5 final test word structure T1 The first keyword T2 The second keyword E1 Bare chip pin measurement error value

Figure 1 is a system architecture diagram (1) of the present invention. Figure 2 is a flow chart of the method of the present invention. Figure 3 is a schematic diagram (1) of the implementation of the present invention. Figure 4 is a schematic diagram (2) of the implementation of the present invention. Figure 5 is a schematic diagram (3) of the implementation of the present invention. Figure 6 is a schematic diagram (4) of the implementation of the present invention. Figure 7 is a schematic diagram (5) of the implementation of the present invention. Figure 8 is a schematic diagram of the needle test data of the metal oxide semi-field effect transistor bare chip of the present invention. Figure 9 is a system architecture diagram (2) of the present invention.

S1 Manufacturing Control S2 Distinguish the word structure of bare chip needle test S3 Extract the corresponding bare die needle measurement value S4 Determine wafer production yield S5 packaging control S6 Identify the final test word structure S7 Extract the corresponding final test value S8 Determine integrated circuit packaging yield S9 bare die pin test analysis S10 final test analysis S11 Wafer design changes S12 Determine whether the error value is related to packaging S13 Package design changes

Claims (8)

An integrated method for quality management of MOSFETs, which integrates multiple pieces of data at various development stages of a MOSFET product, including: a bare die probing data received by a design server from a manufacturing server ; A semantic analysis module of the design server performs natural language processing on the die probing data, and identifies a die probing word structure based on a plurality of data field sets, and a die probing word structure of the design server The data analysis module extracts the corresponding die probing data according to the word structure of the die probing and stores it in a storage unit of the design server; when the data analysis module extracts a The integrated circuit design data and the bare chip probing data are analyzed, and the bare chip probing data is compared with an allowable value of the integrated circuit design data. If not, a bare chip detection analysis is performed, and Perform a wafer design change to correct a wafer production parameter based on inconsistent probe error values of a die; the design server receives a final test data from a packaging server; the semantic analysis module targets The final test data performs the natural language processing, and a final test word structure is identified based on the plurality of data field sets. The data analysis module extracts the corresponding final test data based on the final test word structure and Store in the storage unit; and When the data analysis module analyzes the integrated circuit design data and the final test data in the storage unit, and compares whether the final test data is consistent with the allowable value of the integrated circuit design data, if not, then Perform a final test analysis to obtain a final test error value, and further determine whether the final test error value is related to the package. If so, perform a package design change and correct a package parameter based on the final test error value. If not, Then execute the wafer design change. The integrated method for quality management of MOSFETs as described in claim 1, wherein the bare die probing word structure has a first keyword and a second keyword in the die probing data. The integrated method for quality management of MOSFETs as described in claim 2, wherein the data field set includes a matching attribute of a keyword sequence corresponding to the first keyword and the second keyword, One or a combination of the collocation attributes of a keyword's word boundary, the collocation attributes of a keyword's language, the collocation attributes of a keyword's proper nouns, or the collocation attributes of a keyword's part of speech. The integrated method for quality management of MOSFETs as described in claim 1, wherein the final test word structure has a third keyword and a fourth keyword in the final test data. The integrated method for quality management of MOSFETs as described in claim 4, wherein the data field set includes a matching attribute of a keyword sequence corresponding to the third keyword and the fourth keyword, One or a combination of the collocation attributes of a keyword's word boundary, the collocation attributes of a keyword's language, the collocation attributes of a keyword's proper nouns, or the collocation attributes of a keyword's part of speech. An integrated system for quality management of metal oxide semiconductor field effect transistors, which integrates multiple pieces of data at various development stages of a metal oxide semiconductor field effect transistor product, including: a manufacturing server for transmitting bare die probing data; and a package A server for transmitting final test data; a design server that is informationally connected to the manufacturing server and the packaging server and has a semantic analysis module, a data analysis module, and a storage unit; The semantic analysis module is configured to perform natural language processing and identify a bare chip needle test word structure or a final test word structure based on a plurality of data field sets in the storage unit; the data analysis module is configured to According to the bare die probing word structure or the final test word structure, the corresponding bare die probing data and the final test data are respectively extracted; when the data analysis module extracts an integrated circuit in the storage unit Analyze the design data and the bare die probing data, and compare whether the bare die probing data is consistent with an allowable value of the integrated circuit design data. If not, perform a Die detection and analysis, and perform a wafer design change based on an inconsistent die detection error value to correct a wafer production parameter; and when the data analysis module converts the product in the storage unit Analyze the integrated circuit design data and the final test data to compare whether the final test data is consistent with the allowable value of the integrated circuit design data. If not, perform a final test analysis to obtain a final test error value, and It is further performed to determine whether the final test error value is related to the package. If so, a package design change is performed, and a package parameter is corrected according to the final test error value. If not, the wafer design change is performed. The integrated system for quality management of MOSFETs as described in claim 6, wherein the data field set includes a first keyword, a second keyword, a keyword sequence collocation attribute, and a keyword boundary collocation One of the attributes, the collocation attribute of a keyword's language, the collocation attribute of a keyword's proper noun, or the collocation attribute of a keyword's part of speech, or a combination thereof. The integrated system for quality management of MOSFETs as described in claim 6, wherein the design server has a tracking module for regularly requesting the manufacturing server and the packaging server to send feedback information, and the feedback The information includes one or a combination of a manufacturing or packaging progress, a manufacturing or packaging errata, an estimated completion time of a work item.

Images