TWI816348B - Data driver and control method - Google Patents

Abstract

The disclosure provides a data driver. The data driver includes a shift register, a logic circuit and a data latch. The shift register is configured to output a first output signal. The logic circuit is configured to output a second output signal according to the first output signal and a reset control signal. A switch of the logic circuit is configured to transmit a data signal to an inner node in the logic circuit. During a data setting period, when the logic circuit outputs the second output signal with a first logic level according to the first output signal with an enable level, the switch is turn on. During a reset period, the logic circuit outputs the second output signal with the first logic level, according to the reset control signal with the enable level, the switch is turn on, to transmit the data signal to the inner node.

Description

Data drivers and control methods

The content of this case relates to a data driver, especially a data driver and its control method.

In today's display technology, if the reset operation of the data driver fails during the reset operation of the monitor on/off, it will cause the problem of uneven gray scale in the display screen. Therefore, how to improve the reset operation of the data drive is an important issue in this field.

This disclosure document provides a data driver. The data driver includes a shift register, a first logic circuit and a data latch. The shift register is used to output the first output signal. The first logic circuit is used to output a second output signal according to the first output signal and the reset control signal output by the shift register, wherein when one of the first output signal and the reset control signal has an enable level, The first logic circuit outputs a second output signal having a first logic level. Data latches contain switches. The switch is used to transmit the data signal to the internal node according to the second output signal. During the data setting period, when the first logic circuit outputs the second output signal with the first logic level according to the first output signal with the enable level, the switch is turned on. During the reset period, the first logic circuit outputs a second output signal with a first logic level according to the reset control signal with an enable level, so that the switch is turned on to transmit the data signal to the internal node.

This disclosure document provides a method of control. The control method consists of the following steps. The first output signal is output from the shift register. The first logic circuit outputs a second output signal according to the first output signal and the reset control signal output from the shift register, wherein when one of the first output signal and the reset control signal has an enable level, The first logic circuit outputs a second output signal having a first logic level. During the reset period, the first logic circuit outputs a second output signal having a first logic level based on the reset control signal having an enable level. During the reset period, the circuit path between the internal node of the data latch and the output terminal of the register is turned on according to the second output signal having the first logic level, so as to transmit the output of the register to the internal node of the data latch. .

In summary, this disclosure uses a logic circuit to generate a second output signal based on the reset control signal and the first output signal, and during the reset period, the internal node of the data latch and the output of the register are turned on based on the second output signal. The circuit path between the terminals is used to transmit the reset data signal of the register to the internal node of the data latch.

The following is a detailed description with examples and accompanying drawings to better understand the aspects of this case. However, the examples provided are not intended to limit the scope of this case, and the description of structural operations is not intended to limit its scope. The order of execution and any structure reassembled from components to produce a device with equal functions are all within the scope of this case. In addition, in accordance with industry standards and common practices, the drawings are for illustrative purposes only and are not drawn to original dimensions. In fact, the dimensions of various features may be arbitrarily increased or decreased to facilitate explanation. In the following description, the same components will be labeled with the same symbols to facilitate understanding.

The indexes 1~n in the component numbers and signal numbers used in the description and drawings of this case are only for the convenience of referring to individual components and signals, and are not intended to limit the number of the aforementioned components and signals to a specific number. In the description and drawings of this case, if a certain component number or signal number is used without specifying the index of the component number or signal number, it means that the component number or signal number refers to an unspecified component group or signal group to which it belongs. any component or signal.

In addition, the words "including", "including", "having", "containing", etc. used in this article are all open terms, which mean "including but not limited to". In addition, "and/or" used in this article includes any one or more of the relevant listed items and all combinations thereof.

In this article, when a component is referred to as "connected" or "coupled," it may mean "electrically connected" or "electrically coupled." "Connection" or "coupling" can also be used to indicate the coordinated operation or interaction between two or more components. In addition, although terms such as "first", "second", ... are used to describe different components in this document, these terms are only used to distinguish components or operations described with the same technical terms.

Please refer to Figure 1 , which is a schematic diagram of a display device 100 according to an embodiment of the present disclosure. As shown in FIG. 1 , the display device 100 includes a gate driver 110 , a data driver 120 and a pixel array 130 .

In some embodiments, the gate driver 110 includes decoders GDEC[1]~GDEC[z]. Each of the decoders GDEC[1]~GDEC[z] is electrically coupled to the pixel PIX of the same pixel line (pixel line) of the pixel array 130, and is used to control the data setting path of the pixel PIX of the pixel line. Whether it is turned on so that the corresponding pixel data is transmitted to the corresponding pixel PIX in the pixel column through the aforementioned path. In some embodiments, the pixel PIX can be implemented by a pixel embedded memory (Memory In Pixel), and during the power-on/off period of the display device 100, the gate driver 110 can conduct all pixels to the corresponding data lines DY. [1] to DT[y] path to reset all pixel PIX. In this case, if the potential of the data line fails to be reset, the pixel's embedded memory will retain its original potential and the gray scale of the display will be uneven.

Therefore, in order to improve the uniformity of the display screen when the display screen performs a reset operation during power on/off, this disclosure document uses the data driver 120 to reset the potential of the data lines DY[1]~DY[y], so that the pixel array Each pixel in 130 can complete the reset operation through the data lines DY[1]~DY[y], thereby improving the grayscale uniformity of the display screen during the reset. How to control the data driver 120 to perform the reset operation will be described in detail in subsequent embodiments.

The data driver 120 includes a shift buffer circuit 122, a data latch circuit 124 and logic circuits 126[1]~126[x]. The bit shift register circuit 122 includes shift registers HSR[1]˜HSR[x], where “x” can be any positive integer. In some embodiments, "x" may be implemented by 26. However, in other embodiments, "x" may be implemented by 48, 52, or other positive integers. Therefore, this case is not limited to this.

The shift registers HSR[1]~HSR[x] are electrically coupled to the logic circuits 126[1]~126[x] respectively, and generate and transmit the first output signals OUT[1]~OUT[x] to the logic circuits 126[1]~126[x]. Circuits 126[1]~126[x], so that the logic circuits 126[1]~126[x] generate second output signals HSR_out[1]~HSR_out[ according to the first output signals OUT[1]~OUT[x] x] and the third output signal .

The logic circuits 126[1]~126[x] are electrically coupled to the data latch circuit 124 to transmit the second output signals HSR_out[1]~HSR_out[x] to the data latch circuit 124. The data latch circuit 124 includes data latches 128[1]~128[y].

The data latches 128[1]~128[y] are respectively connected to the data lines DY[1]~DY[y-1] to respectively pass the data lines DY[1] according to the pixel rows scanned by the gate driver 110. ~DY[y-1] provides pixel data to the corresponding pixel PIX in the pixel column, where "y" can be any positive integer. In some embodiments, "y" may be implemented by 208, however, in other embodiments, "y" may be implemented by 312, 416, or other positive integers. Therefore, this case is not limited to this.

It should be noted that the number of a group of data latches (for example, data latches 128[1]~128[a], of which data latch 128[a] is not shown in the figure) and The product of the number of shift registers is equal to the total number of data latches. In other words, the aforementioned number of data latches "a" multiplied by the total number of shift registers "x" is equal to the total number of data latches "y". For example, the data latches 128[1]~128[a] of the same group are used to receive the second output signal HSR_out[1] and the third output signal , to simultaneously provide pixel voltages to the data lines DY[1]~DY[a]. In some embodiments, "a" may be implemented by 8. However, in other embodiments, "a" may be implemented by 4, 16, or 24, or other positive integers. Therefore, this case is not limited to this.

Similarly, another group of data latches 128[a+1]~128[2a] are used to receive the second output signal HSR_out[2] and the third output signal , to simultaneously provide pixel voltages to the data lines DY[a+1]~DY[2a].

Please refer to Figure 2. Figure 2 is a schematic diagram of the data latch 228[n] according to an embodiment of the present disclosure. Each of the data latches 128[1]~128[y] shown in Figure 1 can be implemented by the data latch 228[n] shown in Figure 2, where n can be any positive integer. Correspondingly, the data line [n] connected to the data latch 228[n] corresponds to one of the data lines DY[1]~DY[y] shown in Figure 1.

As shown in FIG. 2 , the data latch 228[n] includes a switch 230 and a feedback circuit 240 . The switch 230 in this disclosure is implemented as a transmission gate. In other embodiments, those skilled in the art can replace the transmission gate in the present disclosure with a P-type metal oxide field effect transistor switch or an N-type metal oxide field effect transistor switch and correspond to the control signal By adjusting accordingly, the same function as the embodiment of the present disclosure can be achieved.

Specifically, switch 230 includes transistor 232 and transistor 234 . The first terminals of the transistor 232 and the transistor 234 are used to receive the data signal SI_D[p], and the gate terminals of the transistor 232 and the transistor 234 are respectively used to receive the third output signal. and the second output signal HSR_out[m]. third output signal It is the reverse signal of the second output signal HSR_out[m].

The transistor 232 is implemented as a P-type transistor, and the transistor 234 is implemented as an N-type transistor. The transistor 232 and the transistor 234 are based on the third output signal. And the logic level of the second output signal HSR_out[m] is turned on or off at the same time.

In this way, when the second output signal HSR_out[m] has a high logic level, the switch 230 is turned on to transmit the data signal SI_D[p] to the internal node N1 via the transistors 232 and 234 .

In the embodiment of FIG. 2 , the feedback circuit 240 is implemented by a clocked-CMOS logic gate. Feedback circuit 240 includes transistors 242, 244, 246, and 248.

Architecturally, the transistors 242, 244, 246 and 248 are electrically connected in series between the system high voltage terminal VDD and the ground terminal. Specifically, the transistors 242 and 244 are electrically connected in series between the system high voltage terminal VDD and the internal node N1. The first terminal of the transistor 242 is electrically coupled to the system high voltage terminal VDD, the second terminal of the transistor 242 is electrically coupled to the first terminal of the transistor 244, and the gate terminal of the transistor 242 is used to receive the second output signal HSR_out. [m]. Also, transistors 242 and 244 may be implemented as P-type transistors.

Transistors 246 and 248 are electrically connected in series between the ground terminal and the internal node N1. The second terminal of the transistor 248 is grounded, the first terminal of the transistor 248 is electrically coupled to the second terminal of the transistor 246, and the gate terminal of the transistor 248 is used to receive the third output signal. . Also, transistors 246 and 248 may be implemented as N-type transistors.

Since the transistor 242 can be implemented by a P-type transistor and the transistor 248 can be implemented by an N-type transistor, when the second output signal HSR_out[m] has a low logic level, the transistor 242 conducts the system high voltage terminal VDD to the terminal of the transistor 244 The circuit path of the first end, and the third output signal that is inverse to the second output signal HSR_out[m] With a high logic level, transistor 248 will conduct a circuit path from ground to the second terminal of transistor 246 .

The second terminal of transistor 244 and the first terminal of transistor 246 are both electrically coupled to internal node N1, and the gate terminals of transistors 244 and 246 are both electrically coupled to node N2. If the second output signal HSR_out[m] has a low logic level, the switch 230 will be turned off and the transistors 242 and 248 will be turned on. At this time, the level of the node N2 will turn on one of the transistors 244 and 246, and turn off the other of the transistor 244 and the transistor 246, thereby changing the potential of the system high voltage VDD according to the level of the node N2. It is transmitted to the internal node N1 through the transistors 242 and 244 or the potential of the ground terminal is transmitted to the internal node N1 through the transistors 246 and 248.

In this way, when the second output signal HSR_out[m] has a low logic level, the feedback circuit 240 is used to latch the potential of the internal node N1.

Please refer to Figure 3. Figure 3 is a schematic diagram of the register RES[p] used to generate the data signal SI_D[p] according to an embodiment of the present disclosure. The register RES[p] includes pins "D", "C" and "R", which are used to receive the input data Input, the clock signal CLK and the reset signal inverse to the enable signal SCS respectively. , to generate the data signal SI_D[p] based on the aforementioned signal. In some embodiments, the inverter INV is electrically coupled to the pin "R" of the register RES[p] to convert the enable signal SCS into a reset signal. , and input the reset signal To the pin "R" of the register RES[p].

Please refer to Figure 4. Figure 4 is a schematic diagram of a logic circuit 426[m] according to an embodiment of the present disclosure. As shown in FIG. 4 , logic circuit 426[m] includes logic circuits 428 and 434 . Each of the logic circuits 126[1]~126[x] shown in Figure 1 can be implemented by the logic circuit 426[m] shown in Figure 4, where "m" can be any positive integer.

Functionally, the logic circuits 428 and 434 are used to receive and output the second output signal HSR_out[m] and the third output signal respectively according to the first output signal OUT[m] and the reset control signal ALLCLEAR. . Among them, the first output signal OUT[m] corresponds to one of the first output signals OUT[1]~OUT[x] in Figure 1.

Specifically, the logic circuit 428 includes an NOR gate 430 and an inverter 432 . The NOR gate 430 is used to receive the first output signal OUT[m] and the reset control signal ALLCLEAR. If at least one of the first output signal OUT[m] and the reset control signal ALLCLEAR has an enable level (for example, a high logic level), the output of the inverter gate 430 will be at a low logic level, and the inverter The inverter INV electrically coupled to the output terminal of the OR gate 430 generates a second output signal HSR_out[m] with a high logic level. On the other hand, if at least one of the first output signal OUT[m] and the reset control signal ALLCLEAR has a low logic level, the output of the inverter 430 will be at a high logic level, and the inverter INV will generate The second output signal HSR_out[m] has a low logic level.

Logic circuit 434 includes an inverse-OR gate 436 . The NOR gate 436 is used to receive the first output signal OUT[m] and the reset control signal ALLCLEAR, and if at least one of the first output signal OUT[m] and the reset control signal ALLCLEAR has a high logic level, the NOR gate 436 OR gate 436 generates a third output signal with a low logic level . On the other hand, if the first output signal OUT[m] has a low logic level, the NOR gate 436 will generate a third output signal with a high logic level. .

Please also refer to Figures 1 to 5. FIG. 5 is a schematic diagram of the timing of control signals according to an embodiment of the present disclosure. As shown in FIG. 5 , an operation cycle of the display device 100 from power on to power off is roughly divided into four periods, which are the initialization period T1 , the maintenance period T2 , the data setting period T3 , the reservation period T4 and the reset period. Setup period T5. It should be noted that the length of the periods in Figure 5 is only used as an example and is not intended to limit this disclosure document.

During the initialization period T1, the enable signal SCS has a second logic level (for example, a low logic level), so that the enable signal SCS Having a first logic level (for example, a high logic level) to perform a reset operation on the register RES[p].

During the sustain period T2, the enable signal SCS has a high logic level, so that the enable signal Has a low logic level to stop the reset operation of register RES[p].

During the data setting period T3, the register RES[p] generates and outputs the data signal SI_D[p] to the data latch 128[n] according to the input data Input and the clock signal CLK. At this time, if the third output signal HRS_out[m] has a high logic level, the switch 230 of the data latch 128[n] will be turned on and the data signal SI_D[p] will be transmitted to the data latch 128[n] Internal node N1. On the other hand, if the third output signal HRS_out[m] has a low logic level, the switch 230 of the data latch 128[n] will be closed, and the feedback circuit 240 of the data latch 128[n] will operate accordingly. , thereby latching the potential of internal node N1.

For example, during the period when the data signal SI_D[p] has the data voltage D(1), when the first output signal OUT[m] generated by the shift register HSR[1] has a high logic level, the logic circuit 426[m] The second output signal HSR_out[m] generated according to the first output signal OUT[m] will have a high logic level. Correspondingly, the third output signal which is inverse to the second output signal HSR_out[m] Has a low logic level.

At this time, the second output signal HSR_out[m] with a high logic level and the third output signal with a low logic level The transistors 232 and 234 in the switch 230 of the data latch 128[n] will be turned on respectively, thereby transmitting the data voltage D(1) of the data signal SI_D[p] to the internal node of the data latch 128[n]. N1, and converts the data voltage D(1) into the data voltage DV(1) transmitted to the data line DY[n] via the inverting amplifiers 252, 254, 256 and 258 electrically connected in series with the internal node N1.

After the potential of the internal node N1 of the data latch 128[n] is set to the data voltage D(1), the first output signal OUT[m] generated by the shift register HSR[m] will be pulled down to low logic level, the logic circuit 426[m] accordingly generates a second output signal HSR_out[m] with a low logic level and a third output signal with a high logic level. , so that the data latch 128[n] depends on the second output signal HSR_out[m] and the third output signal , latch data voltage D(1). The operation method of the feedback circuit 240 has been described in the previous embodiment, so it will not be described again here.

To give another example, during the data setting period T3, if the data signal SI_D[p] has the data voltage D(q), and when the first output signal OUT[m] generated by the shift register HSR[1] has When the logic level is high, the second output signal HSR_out[m] generated by the logic circuit 426[m] according to the first output signal OUT[m] has a high logic level. Correspondingly, the third output signal which is inverse to the second output signal HSR_out[m] Has a low logic level.

At this time, the second output signal HSR_out[m] with a high logic level and the third output signal with a low logic level The transistors 232 and 234 in the switch 230 of the data latch 128[n] will be turned on respectively, thereby transmitting the data voltage D(q) of the data signal SI_D[p] to the internal node of the data latch 128[n]. N1, and converts the data voltage D(q) into the data voltage DV(q) transmitted to the data line DY[n] via the inverting amplifiers 252, 254, 256 and 258 electrically connected in series with the internal node N1.

After the potential of the internal node N1 of the data latch 128[n] is set to the data voltage D(q), the first output signal OUT[m] generated by the shift register HSR[m] will be pulled down to low logic level, the logic circuit 426[m] accordingly generates a second output signal HSR_out[m] with a low logic level and a third output signal with a high logic level. , so that the data latch 128[n] depends on the second output signal HSR_out[m] and the third output signal , the latch data voltage D(q). The operation method of the feedback circuit 240 has been described in the previous embodiment, so it will not be described again here.

During the reservation period T4, since both the first output signal OUT[m] and the reset control signal ALLCLEAR have a low logic level, the logic circuit 426[m] generates a second output signal HSR_out[m] with a low logic level. The latch operation will be maintained so that the data line DY[n] still has the data voltage DV(q). On the other hand, during the reserved period T4, since the enable signal SCS has a low logic level, the register RES[p] will be reset according to the inverse signal of the enable signal SCS. Reset is performed to output the data signal SI_D[p] with a low logic level.

During the reset period T5, since the enable signal SCS still maintains a low logic level, the data signal SI_D[p] has a low logic level. Moreover, since the reset control signal ALLCLEAR has a high logic level, the logic circuit 426[m] will generate a second output signal HSR_out[m] with a high logic level to turn on the data latch 228[n]. The switch 230 transmits the data signal SI_D[p] with a low logic level to the internal node N1, thereby resetting the potential of the internal node N1 and the data line DY[n].

In other words, during the reset period T5, the switch 230 is turned on according to the second output signal HSR_out[m] with a high logic level to connect the internal node N1 of the data latch 228[n] and the output terminal of the register RES[p]. circuit path between them, and transmits the data signal SI_D[p] with a low logic level after the register RES[p] is reset to the internal node N1 of the data latch 228[n], thereby resetting the data line DY [n] to a low logic level.

At this time, since the third output signal With a low logic level, transistor 248 in feedback circuit 240 turns off, thereby closing the circuit path from ground to the second terminal of transistor 246 . In this way, at the beginning of the reset period T5, no matter whether the transistor 246 is turned on or not, the potential of the ground terminal will not be transmitted to the internal node N1 through the transistor 248.

Moreover, since the second output signal HSR_out[m] has a high logic level, the transistor 242 in the feedback circuit 240 will be turned off, thereby turning off the circuit path from the system high voltage terminal VDD to the first terminal of the transistor 244. In this way, at the beginning of the reset period T5, no matter whether the transistor 244 is turned on or not, the potential of the system high voltage terminal VDD will not be transmitted to the internal node N1 through the transistor 242, causing the reset operation to fail.

In some embodiments, the gate driver 110 will conduct circuit paths of all pixels PIX to the corresponding data lines DY[1]~DY[n] during the reset period T5. The data lines DY[1]~DY[n ] At the same time, the potential of the low logic level is transmitted to all the pixels PIX as the data voltage, thereby resetting all the pixels PIX of the display device 100 during the reset period T5, thereby improving the uniformity of the picture of the display device 100.

Please refer to Figure 6, which is a schematic diagram of the data latch 628[n] according to an embodiment of the present disclosure. As shown in FIG. 6 , the data latch 628[n] includes a switch 630 and a feedback circuit 640 . Each of the data latches 128[1]~128[y] shown in Figure 1 can be implemented by the data latch 628[n] shown in Figure 6, where n can be any positive integer.

Switch 630 includes transistor 232 and transistor 234 . The connection relationship and operating mode of the switch 630 shown in FIG. 6 are similar to the switch 230 in FIG. 2, so they will not be described again here.

In the embodiment of FIG. 6, the feedback circuit 640 is implemented by a transmission gate. Specifically, the feedback circuit 640 includes a transistor 642 and a transistor 644 . Transistor 642 is implemented as a P-type transistor, and transistor 644 is implemented as an N-type transistor. Architecturally, transistors 642 and 644 are connected in parallel between internal nodes N1 and N2.

Functionally, the gate terminal of the transistor 642 is used to receive the second output signal HSR_out[m], and the gate terminal of the transistor 644 is used to receive the third output signal in the opposite direction. , so that the transistors 642 and 644 are simultaneously turned on or off according to the logic level of the second output signal HSR_out[m].

Specifically, if the second output signal HSR_out[m] has a high logic level, the switch 630 will be turned on and the feedback circuit 640 will be turned off. On the other hand, if the second output signal HSR_out[m] has a low logic level, the switch 630 will be turned off, and the feedback circuit 640 will be turned on to latch the potential of the internal node N1 and pass the potential of the internal node N1 through Inversion amplifiers 622 and 624 are transmitted to the data line DY[n].

The remaining operating modes and functions of the data latch 628[n] are generally similar to the data latch 228[n], so they will not be described again here.

To sum up, this disclosure uses the logic circuit 426[m] to generate the second output signal HSR_out[m] according to the reset control signal ALL and the first output signal OUT[m], and during the reset period T5, according to the second The output signal HSR_out[m] conducts the circuit path between the internal node N1 of the data latch 228[n] and the output terminal of the register RES[p], thereby converting the reset data signal SI_D[ of the register RES[p] p] is transmitted to the internal node N1 of the data latch 228[n], thereby resetting the data latch 228[n]. In this way, the potential of the data line DY[n] can be reset.

Although this case has been disclosed in the form of implementation, it does not limit this case. Anyone familiar with this technology can make various changes and modifications without departing from the spirit and scope of this case. Therefore, the scope of protection of this case shall be regarded as appended hereto. The scope of the patent application shall prevail.

In order to make the above and other objects, features, advantages and embodiments of the present disclosure more obvious and understandable, the accompanying symbols are explained as follows: 100:Display device 110: Gate driver 120:Data drive

122: Shift temporary storage circuit

124: Data latch circuit

126[1]~126[x],426[m]: logic circuit

128[1]~128[y],228[n],628[n]: data latch

130:Pixel array

230,630: switch

232,234,242,244,246,248,632,634,642,644: transistor

240,640: Feedback circuit

252,254,256,258,652,654: reverse amplifier

430,436: reverse OR gate

432:Reverser

N1: internal node

N2: node

OUT[1]~OUT[x],OUT[m]: first output signal

HSR_out[1]~HSR_out[x],HSR_out[m]: second output signal

~

,

:第三輸出訊號

~

,

:Third output signal

ALLCLEAR: reset control signal

HSR[1]~HSR[x]: shift register

DY[1]~DY[y]: data line

D(1)~D(q),DV(1)~DV(q): data voltage

GDEC[1]~GDEC[z]: decoder

RES[p]: register

SI_D[p]: data signal Input: input signal CLK: clock signal SCS: enable signal : Reset signal INV: Inverter T1: Initialization period T2: Sustainment period T3: Data setting period T4: Reserve period T5: Reset period

In order to make the above and other objects, features, advantages and embodiments of the present disclosure more obvious and understandable, the accompanying drawings are described as follows: Figure 1 is a schematic diagram of a display device according to an embodiment of the present disclosure. Figure 2 is a schematic diagram of a data latch according to an embodiment of the present disclosure. FIG. 3 is a schematic diagram of a register used to generate data signals according to an embodiment of the present disclosure. FIG. 4 is a schematic diagram of a logic circuit according to an embodiment of the present disclosure. FIG. 5 is a schematic diagram of the timing of control signals according to an embodiment of the present disclosure. FIG. 6 is a schematic diagram of a data latch according to an embodiment of the present disclosure.

Domestic storage information (please note in order of storage institution, date and number) without Overseas storage information (please note in order of storage country, institution, date, and number) without

100:Display device

110: Gate driver

120:Data drive

122: Shift temporary storage circuit

124: Data latch circuit

126[1]~126[x]: Logic circuit

128[1]~128[y]: Data latch

130:Pixel array

PIX: pixel

HSR[1]~HSR[x]: shift register

DY[1]~DY[y]: data line

GDEC[1]~GDEC[z]: register

OUT[1]~OUT[x]: first output signal

HSR_out[1]~HSR_out[x]: second output signal

~

:第三輸出訊號

~

:Third output signal

Claims (10)

A data driver includes: a shift register for outputting a first output signal; a first logic circuit for outputting the first output signal and a reset control signal based on the shift register , outputting a second output signal, wherein when one of the first output signal and the reset control signal has a consistent enable level, the first logic circuit generates a first logic level according to the enable level. the second output signal; and a data latch, including: a switch for transmitting a data signal to an internal node according to the second output signal, wherein: during a data setting period, when the first logic circuit When the first output signal with the enable level outputs the second output signal with the first logic level, the switch is turned on; and during a reset period, the first logic circuit is based on having the enable level. The reset control signal with the first logic level outputs the second output signal with the first logic level, turning on the switch to transmit the data signal to the internal node. The data driver as described in claim 1, including: a register for generating the data signal based on an input data, a clock signal and a reset signal, wherein during the reset period, a flip-flop has the The reset signal of the energy level outputs the data signal having a second logic level, and the switch of the data latch is based on the The second output signal is turned on to transmit the data signal with the second logic level to the internal node. The data driver as claimed in claim 1, wherein the data latch further includes: a feedback circuit for latching the potential of the internal node according to the second output signal, wherein: during the reset period, the third A logic circuit outputs the second output signal with the first logic level according to the reset control signal with the enable level to turn off the feedback circuit. The data driver as claimed in claim 3, wherein during the data setting period: when the first logic circuit outputs the second output having the first logic level based on the first output signal having the enable level signal, the feedback circuit is turned off; and when the first logic circuit outputs the second output with a second logic level based on the first output signal with a disable level and the reset control signal. signal, the feedback circuit is turned on. The data driver of claim 3, wherein the feedback circuit is electrically coupled between the internal node of the data latch and an output terminal. The data driver as claimed in claim 3, wherein the feedback circuit is implemented by a transmission gate or a timing control-complementary metal oxide semiconductor logic circuit. The data driver of claim 1, wherein the switch relationship is implemented by a transmission gate. The data driver as claimed in claim 1, further comprising: a second logic circuit for outputting a third output signal according to the first output signal and the reset control signal output by the shift register, and When one of the first output signal and the reset control signal has the enable level, the second logic circuit outputs the third output signal with a second logic level. The data driver as described in claim 8, wherein the switch is used to transmit the data signal to the internal node according to the third output signal, wherein: during the data setting period, when the second logic circuit has the enable bit When the first output signal with the second logic level is correct, the switch is turned on; and during the reset period, the second logic circuit is based on the reset with the enable level. The control signal is set, and the third output signal with the second logic level is output to turn on the switch. A control method includes: a shift register outputting a first output signal; a first logic circuit outputting a first output signal based on the first output signal and a reset control signal output by the shift register. A second output signal, wherein when one of the first output signal and the reset control signal has a consistent enable level, the first logic circuit generates the first logic level with a first logic level according to the enable level. Two output signals; during a reset period, the first logic circuit outputs the second output signal with the first logic level according to the reset control signal with the enable level; and during the reset During this period, the second output signal having the first logic level conducts a circuit path between an internal node of a data latch and an output terminal of a register to transmit the output of the register to the data latch. of this internal node.