TWI816348B - Data driver and control method - Google Patents
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Abstract
Description
本案內容係關於一種資料驅動器,特別是關於一種資料驅動器及其控制方法。The content of this case relates to a data driver, especially a data driver and its control method.
在現今顯示技術中,若顯示器在開機/關機的重置操作期間,資料驅動器的重置操作失敗,會造成顯示畫面灰階不均等問題。因此,如何改善資料驅動器的重置運作,為本領域中重要的議題。In today's display technology, if the reset operation of the data driver fails during the reset operation of the monitor on/off, it will cause the problem of uneven gray scale in the display screen. Therefore, how to improve the reset operation of the data drive is an important issue in this field.
本揭示文件提供一種資料驅動器。資料驅動器包含移位暫存器、第一邏輯電路以及數據鎖存器。移位暫存器用以輸出第一輸出訊號。第一邏輯電路用以依據移位暫存器輸出的第一輸出訊號以及重置控制訊號,輸出第二輸出訊號,其中當第一輸出訊號以及重置控制訊號其中一者具有致能位準,第一邏輯電路輸出具有第一邏輯位準的第二輸出訊號。數據鎖存器包含開關。開關用以依據第二輸出訊號傳送資料訊號至內部節點。在資料設定期間,當第一邏輯電路輸依據具有致能位準的第一輸出訊號,輸出具有第一邏輯位準的第二輸出訊號時,開關導通。在重置期間,第一邏輯電路輸依據具有致能位準的重置控制訊號,輸出具有第一邏輯位準的第二輸出訊號,使開關導通,以將資料訊號傳送至內部節點。This disclosure document provides a data driver. The data driver includes a shift register, a first logic circuit and a data latch. The shift register is used to output the first output signal. The first logic circuit is used to output a second output signal according to the first output signal and the reset control signal output by the shift register, wherein when one of the first output signal and the reset control signal has an enable level, The first logic circuit outputs a second output signal having a first logic level. Data latches contain switches. The switch is used to transmit the data signal to the internal node according to the second output signal. During the data setting period, when the first logic circuit outputs the second output signal with the first logic level according to the first output signal with the enable level, the switch is turned on. During the reset period, the first logic circuit outputs a second output signal with a first logic level according to the reset control signal with an enable level, so that the switch is turned on to transmit the data signal to the internal node.
本揭示文件提供一種控制方法。控制方法包含下列步驟。由移位暫存器,輸出第一輸出訊號。由第一邏輯電路,依據移位暫存器輸出的第一輸出訊號以及重置控制訊號,輸出第二輸出訊號,其中當第一輸出訊號以及重置控制訊號其中一者具有致能位準,第一邏輯電路輸出具有第一邏輯位準的第二輸出訊號。在重置期間,由第一邏輯電路輸依據具有致能位準的重置控制訊號,輸出具有第一邏輯位準的第二輸出訊號。在重置期間,依據具有第一邏輯位準第二輸出訊號導通數據鎖存器的內部節點與寄存器的輸出端之間的電路路徑,以將寄存器的輸出傳送至該數據鎖存器的內部節點。This disclosure document provides a method of control. The control method consists of the following steps. The first output signal is output from the shift register. The first logic circuit outputs a second output signal according to the first output signal and the reset control signal output from the shift register, wherein when one of the first output signal and the reset control signal has an enable level, The first logic circuit outputs a second output signal having a first logic level. During the reset period, the first logic circuit outputs a second output signal having a first logic level based on the reset control signal having an enable level. During the reset period, the circuit path between the internal node of the data latch and the output terminal of the register is turned on according to the second output signal having the first logic level, so as to transmit the output of the register to the internal node of the data latch. .
綜上所述,本揭示文件利用邏輯電路依據重置控制訊號以及第一輸出訊號產生第二輸出訊號,並且在重置期間,依據第二輸出訊號導通數據鎖存器的內部節點與寄存器的輸出端之間的電路路徑,從而將寄存器經重置後的資料訊號傳送至數據鎖存器的內部節點。In summary, this disclosure uses a logic circuit to generate a second output signal based on the reset control signal and the first output signal, and during the reset period, the internal node of the data latch and the output of the register are turned on based on the second output signal. The circuit path between the terminals is used to transmit the reset data signal of the register to the internal node of the data latch.
下文係舉實施例配合所附圖式作詳細說明,以更好地理解本案的態樣,但所提供之實施例並非用以限制本案所涵蓋的範圍,而結構操作之描述非用以限制其執行之順序,任何由元件重新組合之結構,所產生具有均等功效的裝置,皆為本案所涵蓋的範圍。此外,根據業界的標準及慣常做法,圖式僅以輔助說明為目的,並未依照原尺寸作圖,實際上各種特徵的尺寸可任意地增加或減少以便於說明。下述說明中相同元件將以相同之符號標示來進行說明以便於理解。The following is a detailed description with examples and accompanying drawings to better understand the aspects of this case. However, the examples provided are not intended to limit the scope of this case, and the description of structural operations is not intended to limit its scope. The order of execution and any structure reassembled from components to produce a device with equal functions are all within the scope of this case. In addition, in accordance with industry standards and common practices, the drawings are for illustrative purposes only and are not drawn to original dimensions. In fact, the dimensions of various features may be arbitrarily increased or decreased to facilitate explanation. In the following description, the same components will be labeled with the same symbols to facilitate understanding.
本案說明書和圖式中使用的元件編號和訊號編號中的索引1~n,只是為了方便指稱個別的元件和訊號,並非有意將前述元件和訊號的數量侷限在特定數目。在本案說明書和圖式中,若使用某一元件編號或訊號編號時沒有指明該元件編號或訊號編號的索引,則代表該元件編號或訊號編號是指稱所屬元件群組或訊號群組中不特定的任一元件或訊號。The indexes 1~n in the component numbers and signal numbers used in the description and drawings of this case are only for the convenience of referring to individual components and signals, and are not intended to limit the number of the aforementioned components and signals to a specific number. In the description and drawings of this case, if a certain component number or signal number is used without specifying the index of the component number or signal number, it means that the component number or signal number refers to an unspecified component group or signal group to which it belongs. any component or signal.
此外,在本文中所使用的用詞『包含』、『包括』、『具有』、『含有』等等,均為開放性的用語,即意指『包含但不限於』。此外,本文中所使用之『及/或』,包含相關列舉項目中一或多個項目的任意一個以及其所有組合。In addition, the words "including", "including", "having", "containing", etc. used in this article are all open terms, which mean "including but not limited to". In addition, "and/or" used in this article includes any one or more of the relevant listed items and all combinations thereof.
於本文中,當一元件被稱為『連接』或『耦接』時,可指『電性連接』或『電性耦接』。『連接』或『耦接』亦可用以表示二或多個元件間相互搭配操作或互動。此外,雖然本文中使用『第一』、『第二』、…等用語描述不同元件,該用語僅是用以區別以相同技術用語描述的元件或操作。In this article, when a component is referred to as "connected" or "coupled," it may mean "electrically connected" or "electrically coupled." "Connection" or "coupling" can also be used to indicate the coordinated operation or interaction between two or more components. In addition, although terms such as "first", "second", ... are used to describe different components in this document, these terms are only used to distinguish components or operations described with the same technical terms.
請參閱第1圖,第1圖為本揭露一實施例之顯示裝置100的示意圖。如第1圖所示,顯示裝置100包含閘極驅動器110、資料驅動器120以及畫素陣列130。Please refer to Figure 1 , which is a schematic diagram of a display device 100 according to an embodiment of the present disclosure. As shown in FIG. 1 , the display device 100 includes a gate driver 110 , a data driver 120 and a pixel array 130 .
在一些實施例中,閘極驅動器110包含解碼器GDEC[1]~GDEC[z]。解碼器GDEC[1]~GDEC[z]每一者電性耦接畫素陣列130同一畫素列(pixel line)的畫素PIX,用以控制該畫素列的畫素PIX的資料設定路徑是否導通,以使相應的畫素資料經由前述路徑傳送至該畫素列中之對應的畫素PIX。在一些實施例中,畫素PIX可以由畫素內嵌記憶體(Memory In Pixel)實施,並且顯示裝置100在開/關機期間,閘極驅動器110可導通所有畫素的至相應的資料線DY[1]至DT[y]的路徑,來重置所有的畫素PIX。在此情形中,若資料線的電位重置失敗,會造成畫素內嵌記憶體保留原本的電位而使顯示畫面灰階不均。In some embodiments, the gate driver 110 includes decoders GDEC[1]~GDEC[z]. Each of the decoders GDEC[1]~GDEC[z] is electrically coupled to the pixel PIX of the same pixel line (pixel line) of the pixel array 130, and is used to control the data setting path of the pixel PIX of the pixel line. Whether it is turned on so that the corresponding pixel data is transmitted to the corresponding pixel PIX in the pixel column through the aforementioned path. In some embodiments, the pixel PIX can be implemented by a pixel embedded memory (Memory In Pixel), and during the power-on/off period of the display device 100, the gate driver 110 can conduct all pixels to the corresponding data lines DY. [1] to DT[y] path to reset all pixel PIX. In this case, if the potential of the data line fails to be reset, the pixel's embedded memory will retain its original potential and the gray scale of the display will be uneven.
因此,為了改善顯示畫面在開/關機期間執行重置操作時顯示畫面的均勻性,本揭示文件利用資料驅動器120重置資料線DY[1]~DY[y]的電位,而使畫素陣列130中的每一個畫素能夠經由資料線DY[1]~DY[y]完成重置操作,藉此在重置期間改善顯示畫面的灰階均勻性。如何控制資料驅動器120進行重置操作,會在後續實施例中詳細說明。Therefore, in order to improve the uniformity of the display screen when the display screen performs a reset operation during power on/off, this disclosure document uses the data driver 120 to reset the potential of the data lines DY[1]~DY[y], so that the pixel array Each pixel in 130 can complete the reset operation through the data lines DY[1]~DY[y], thereby improving the grayscale uniformity of the display screen during the reset. How to control the data driver 120 to perform the reset operation will be described in detail in subsequent embodiments.
資料驅動器120包含移位暫存電路122、數據鎖存電路124以及邏輯電路126[1]~126[x]。位移位暫存電路122包含移位暫存器HSR[1]~HSR[x],其中所述「x」可以係任何正整數。在一些實施例中,所述「x」可以由26實施。然而,在其他實施例中,「x」可以由48、52、或其他正整數實施。因此,本案不以此為限。The data driver 120 includes a shift buffer circuit 122, a data latch circuit 124 and logic circuits 126[1]~126[x]. The bit shift register circuit 122 includes shift registers HSR[1]˜HSR[x], where “x” can be any positive integer. In some embodiments, "x" may be implemented by 26. However, in other embodiments, "x" may be implemented by 48, 52, or other positive integers. Therefore, this case is not limited to this.
移位暫存器HSR[1]~HSR[x]分別電性耦接邏輯電路126[1]~126[x],並且產生及傳送第一輸出訊號OUT[1]~OUT[x]至邏輯電路126[1]~126[x],以使邏輯電路126[1]~126[x]依據第一輸出訊號OUT[1]~OUT[x]產生第二輸出訊號HSR_out[1]~HSR_out[x]以及第三輸出訊號 。 The shift registers HSR[1]~HSR[x] are electrically coupled to the logic circuits 126[1]~126[x] respectively, and generate and transmit the first output signals OUT[1]~OUT[x] to the logic circuits 126[1]~126[x]. Circuits 126[1]~126[x], so that the logic circuits 126[1]~126[x] generate second output signals HSR_out[1]~HSR_out[ according to the first output signals OUT[1]~OUT[x] x] and the third output signal .
邏輯電路126[1]~126[x]電性耦接數據鎖存電路124,以將第二輸出訊號HSR_out[1]~HSR_out[x]傳送至數據鎖存電路124。數據鎖存電路124包含數據鎖存器128[1]~128[y]。The logic circuits 126[1]~126[x] are electrically coupled to the data latch circuit 124 to transmit the second output signals HSR_out[1]~HSR_out[x] to the data latch circuit 124. The data latch circuit 124 includes data latches 128[1]~128[y].
數據鎖存器128[1]~128[y]分別連接至資料線DY[1]~DY[y-1],以依據閘極驅動器110掃描的畫素列,分別經由資料線DY[1]~DY[y-1]提供畫素資料至該畫素列中相應的畫素PIX,其中所述「y」可以係任何正整數。在一些實施例中,所述「y」可以由208實施,然而,在其他實施例中,「y」可以由312、416、或其他正整數實施。因此,本案不以此為限。The data latches 128[1]~128[y] are respectively connected to the data lines DY[1]~DY[y-1] to respectively pass the data lines DY[1] according to the pixel rows scanned by the gate driver 110. ~DY[y-1] provides pixel data to the corresponding pixel PIX in the pixel column, where "y" can be any positive integer. In some embodiments, "y" may be implemented by 208, however, in other embodiments, "y" may be implemented by 312, 416, or other positive integers. Therefore, this case is not limited to this.
需要注意的是,一組數據鎖存器的數量(例如,數據鎖存器128[1]~128[a],其中的數據鎖存器128[a]未繪示於圖式之中)與移位暫存器的數量的乘積等同於數據鎖存器的總數量。換言之,前述的一組數據鎖存器的數量「a」乘以移位暫存器的總數量「x」等於數據鎖存器的總數量「y」。舉例而言,同一組的數據鎖存器128[1]~128[a]皆係用以接收第二輸出訊號HSR_out[1]以及第三輸出訊號 ,以同時提供畫素電壓至資料線DY[1]~DY[a]。在一些實施例中,「a」可以由8實施。然而,在其他實施例中,「a」可以由4、16或24或其他正整數實施。因此,本案不以此為限。 It should be noted that the number of a group of data latches (for example, data latches 128[1]~128[a], of which data latch 128[a] is not shown in the figure) and The product of the number of shift registers is equal to the total number of data latches. In other words, the aforementioned number of data latches "a" multiplied by the total number of shift registers "x" is equal to the total number of data latches "y". For example, the data latches 128[1]~128[a] of the same group are used to receive the second output signal HSR_out[1] and the third output signal , to simultaneously provide pixel voltages to the data lines DY[1]~DY[a]. In some embodiments, "a" may be implemented by 8. However, in other embodiments, "a" may be implemented by 4, 16, or 24, or other positive integers. Therefore, this case is not limited to this.
類似地,另一組的數據鎖存器128[a+1]~128[2a] 皆係用以接收第二輸出訊號HSR_out[2]以及第三輸出訊號 ,以同時提供畫素電壓至資料線DY[a+1]~DY[2a]。 Similarly, another group of data latches 128[a+1]~128[2a] are used to receive the second output signal HSR_out[2] and the third output signal , to simultaneously provide pixel voltages to the data lines DY[a+1]~DY[2a].
請參閱第2圖,第2圖為本揭露一實施例之數據鎖存器228[n]的示意圖。第1圖所示的數據鎖存器128[1]~128[y]每一者皆可由第2圖所示的數據鎖存器228[n]實施,其中n可為任意正整數。相應地,數據鎖存器228[n]連接的資料線[n]對應於第1圖所示的資料線DY[1]~DY[y]其中一者。Please refer to Figure 2. Figure 2 is a schematic diagram of the data latch 228[n] according to an embodiment of the present disclosure. Each of the data latches 128[1]~128[y] shown in Figure 1 can be implemented by the data latch 228[n] shown in Figure 2, where n can be any positive integer. Correspondingly, the data line [n] connected to the data latch 228[n] corresponds to one of the data lines DY[1]~DY[y] shown in Figure 1.
如第2圖所示,數據鎖存器228[n]包含開關230以及迴授電路240。本揭示文件中的開關230是以傳輸閘實施。於另一些實施例中,本領域習知技藝人士可將本揭示中的傳輸閘由P型金屬氧化物場效電晶體開關或N型金屬氧化物場效電晶體開關替換並對控制訊號相對應地調整,也可以達到與本揭示實施例相同的功能。As shown in FIG. 2 , the data latch 228[n] includes a switch 230 and a feedback circuit 240 . The switch 230 in this disclosure is implemented as a transmission gate. In other embodiments, those skilled in the art can replace the transmission gate in the present disclosure with a P-type metal oxide field effect transistor switch or an N-type metal oxide field effect transistor switch and correspond to the control signal By adjusting accordingly, the same function as the embodiment of the present disclosure can be achieved.
具體而言,開關230包含電晶體232以及電晶體234。電晶體232以及電晶體234的第一端用以接收資料訊號SI_D[p],並且電晶體232以及電晶體234的閘極端分別用以接收第三輸出訊號 以及第二輸出訊號HSR_out[m]。第三輸出訊號 係第二輸出訊號HSR_out[m]的反向訊號。 Specifically, switch 230 includes transistor 232 and transistor 234 . The first terminals of the transistor 232 and the transistor 234 are used to receive the data signal SI_D[p], and the gate terminals of the transistor 232 and the transistor 234 are respectively used to receive the third output signal. and the second output signal HSR_out[m]. third output signal It is the reverse signal of the second output signal HSR_out[m].
電晶體232係以P型電晶體實施,電晶體234係以N型電晶體實施,電晶體232以及電晶體234依據第三輸出訊號 以及第二輸出訊號HSR_out[m]的邏輯位準同時導通或關斷。 The transistor 232 is implemented as a P-type transistor, and the transistor 234 is implemented as an N-type transistor. The transistor 232 and the transistor 234 are based on the third output signal. And the logic level of the second output signal HSR_out[m] is turned on or off at the same time.
如此,當第二輸出訊號HSR_out[m]具有高邏輯位準時,開關230會導通從而將資料訊號SI_D[p]經由電晶體232以及234傳送至內部節點N1。In this way, when the second output signal HSR_out[m] has a high logic level, the switch 230 is turned on to transmit the data signal SI_D[p] to the internal node N1 via the transistors 232 and 234 .
在第2圖的實施例中,迴授電路240係由時序控制-互補式金屬氧化物半導體邏輯閘(Clocked-CMOS Logic Gate)實施。迴授電路240包含電晶體242、244、246以及248。In the embodiment of FIG. 2 , the feedback circuit 240 is implemented by a clocked-CMOS logic gate. Feedback circuit 240 includes transistors 242, 244, 246, and 248.
在架構上,電晶體242、244、246以及248電性串連在系統高電壓端VDD以及接地端之間。具體而言,電晶體242以及244電性串聯在系統高電壓端VDD以及內部節點N1之間。電晶體242的第一端電性耦接系統高電壓端VDD,電晶體242的第二端電性耦接電晶體244的第一端,電晶體242的閘極端用以接收第二輸出訊號HSR_out[m]。並且,電晶體242以及244可由P型電晶體實施。Architecturally, the transistors 242, 244, 246 and 248 are electrically connected in series between the system high voltage terminal VDD and the ground terminal. Specifically, the transistors 242 and 244 are electrically connected in series between the system high voltage terminal VDD and the internal node N1. The first terminal of the transistor 242 is electrically coupled to the system high voltage terminal VDD, the second terminal of the transistor 242 is electrically coupled to the first terminal of the transistor 244, and the gate terminal of the transistor 242 is used to receive the second output signal HSR_out. [m]. Also, transistors 242 and 244 may be implemented as P-type transistors.
電晶體246以及248電性串聯在接地端以及內部節點N1之間。電晶體248的第二端接地,電晶體248的第一端電性耦接電晶體246的第二端,電晶體248的閘極端用以接收第三輸出訊號 。並且,電晶體246以及248可由N型電晶體實施。 Transistors 246 and 248 are electrically connected in series between the ground terminal and the internal node N1. The second terminal of the transistor 248 is grounded, the first terminal of the transistor 248 is electrically coupled to the second terminal of the transistor 246, and the gate terminal of the transistor 248 is used to receive the third output signal. . Also, transistors 246 and 248 may be implemented as N-type transistors.
由於電晶體242可由P型電晶體實施且電晶體248可由N型電晶體實施,在第二輸出訊號HSR_out[m]具有低邏輯位準時,電晶體242導通系統高電壓端VDD至電晶體244的第一端的電路路徑,且與第二輸出訊號HSR_out[m]呈反向的第三輸出訊號 具有高邏輯位準,電晶體248會導通接地端至電晶體246的第二端的電路路經。 Since the transistor 242 can be implemented by a P-type transistor and the transistor 248 can be implemented by an N-type transistor, when the second output signal HSR_out[m] has a low logic level, the transistor 242 conducts the system high voltage terminal VDD to the terminal of the transistor 244 The circuit path of the first end, and the third output signal that is inverse to the second output signal HSR_out[m] With a high logic level, transistor 248 will conduct a circuit path from ground to the second terminal of transistor 246 .
電晶體244的第二端以及電晶體246的第一端皆電性耦接內部節點N1,電晶體244以及246的閘極端皆電性耦接節點N2。若第二輸出訊號HSR_out[m]具有低邏輯位準時,開關230會關斷並且電晶體242以及248會導通。此時,節點N2的位準會導通電晶體244以及電晶體246其中一者,並關斷電晶體244以及電晶體246中的另一者,從而依據節點N2的位準將系統高電壓VDD的電位經由電晶體242以及244傳送至內部節點N1或者是將接地端的電位經由電晶體246以及248傳送至內部節點N1。The second terminal of transistor 244 and the first terminal of transistor 246 are both electrically coupled to internal node N1, and the gate terminals of transistors 244 and 246 are both electrically coupled to node N2. If the second output signal HSR_out[m] has a low logic level, the switch 230 will be turned off and the transistors 242 and 248 will be turned on. At this time, the level of the node N2 will turn on one of the transistors 244 and 246, and turn off the other of the transistor 244 and the transistor 246, thereby changing the potential of the system high voltage VDD according to the level of the node N2. It is transmitted to the internal node N1 through the transistors 242 and 244 or the potential of the ground terminal is transmitted to the internal node N1 through the transistors 246 and 248.
如此,在第二輸出訊號HSR_out[m]具有低邏輯位準時,迴授電路240用以鎖存內部節點N1的電位。In this way, when the second output signal HSR_out[m] has a low logic level, the feedback circuit 240 is used to latch the potential of the internal node N1.
請參閱第3圖,第3圖為本揭露一實施例之用於產生資料訊號SI_D[p]的寄存器RES[p]的示意圖。寄存器RES[p]包含接腳「D」、「C」以及「R」,分別用以接收輸入資料Input、時脈訊號CLK以及與致能訊號SCS呈反向的重置訊號 ,以依據前述訊號產生資料訊號SI_D[p]。在一些實施例中,反向器INV電性耦接寄存器RES[p]的接腳「R」,以將致能訊號SCS轉換為重置訊號 ,並輸入重置訊號 至寄存器RES[p]的接腳「R」。 Please refer to Figure 3. Figure 3 is a schematic diagram of the register RES[p] used to generate the data signal SI_D[p] according to an embodiment of the present disclosure. The register RES[p] includes pins "D", "C" and "R", which are used to receive the input data Input, the clock signal CLK and the reset signal inverse to the enable signal SCS respectively. , to generate the data signal SI_D[p] based on the aforementioned signal. In some embodiments, the inverter INV is electrically coupled to the pin "R" of the register RES[p] to convert the enable signal SCS into a reset signal. , and input the reset signal To the pin "R" of the register RES[p].
請參閱第4圖,第4圖為本揭露一實施例之邏輯電路426[m]的示意圖。如第4圖所示,邏輯電路426[m]包含邏輯電路428以及434。第1圖所示的邏輯電路126[1]~126[x] 每一者皆可由第4圖所示的邏輯電路426[m]實施,其中「m」可以為任意正整數。Please refer to Figure 4. Figure 4 is a schematic diagram of a logic circuit 426[m] according to an embodiment of the present disclosure. As shown in FIG. 4 , logic circuit 426[m] includes logic circuits 428 and 434 . Each of the logic circuits 126[1]~126[x] shown in Figure 1 can be implemented by the logic circuit 426[m] shown in Figure 4, where "m" can be any positive integer.
在功能上,邏輯電路428以及434皆用以接收並依據第一輸出訊號OUT[m]以及重置控制訊號ALLCLEAR,分別輸出第二輸出訊號HSR_out[m]以及第三輸出訊號 。其中,第一輸出訊號OUT[m]對應於第1圖中第一輸出訊號OUT[1]~OUT[x]中之一者。 Functionally, the logic circuits 428 and 434 are used to receive and output the second output signal HSR_out[m] and the third output signal respectively according to the first output signal OUT[m] and the reset control signal ALLCLEAR. . Among them, the first output signal OUT[m] corresponds to one of the first output signals OUT[1]~OUT[x] in Figure 1.
具體而言,邏輯電路428包含反或閘430以及反向器432。反或閘430用以接收第一輸出訊號OUT[m]以及重置控制訊號ALLCLEAR。若第一輸出訊號OUT[m]以及重置控制訊號ALLCLEAR中之至少一者具有致能位準(例如,高邏輯位準)時,反或閘430的輸出會在低邏輯位準,與反或閘430的輸出端電性耦接的反向器INV會產生具有高邏輯位準的第二輸出訊號HSR_out[m]。另一方面,若第一輸出訊號OUT[m]以及重置控制訊號ALLCLEAR中之至少一者皆具有低邏輯位準時,反或閘430的輸出會在高邏輯位準,反向器INV會產生具有低邏輯位準的第二輸出訊號HSR_out[m]。Specifically, the logic circuit 428 includes an NOR gate 430 and an inverter 432 . The NOR gate 430 is used to receive the first output signal OUT[m] and the reset control signal ALLCLEAR. If at least one of the first output signal OUT[m] and the reset control signal ALLCLEAR has an enable level (for example, a high logic level), the output of the inverter gate 430 will be at a low logic level, and the inverter The inverter INV electrically coupled to the output terminal of the OR gate 430 generates a second output signal HSR_out[m] with a high logic level. On the other hand, if at least one of the first output signal OUT[m] and the reset control signal ALLCLEAR has a low logic level, the output of the inverter 430 will be at a high logic level, and the inverter INV will generate The second output signal HSR_out[m] has a low logic level.
邏輯電路434包含反或閘436。反或閘436用以接收第一輸出訊號OUT[m]以及重置控制訊號ALLCLEAR,且若第一輸出訊號OUT[m]以及重置控制訊號ALLCLEAR中之至少一者具有高邏輯位準時,反或閘436會產生具有低邏輯位準的第三輸出訊號 。另一方面,若第一輸出訊號OUT[m]具有低邏輯位準時,反或閘436會產生具有高邏輯位準的第三輸出訊號 。 Logic circuit 434 includes an inverse-OR gate 436 . The NOR gate 436 is used to receive the first output signal OUT[m] and the reset control signal ALLCLEAR, and if at least one of the first output signal OUT[m] and the reset control signal ALLCLEAR has a high logic level, the NOR gate 436 OR gate 436 generates a third output signal with a low logic level . On the other hand, if the first output signal OUT[m] has a low logic level, the NOR gate 436 will generate a third output signal with a high logic level. .
請一併參閱第1至第5圖。第5圖為本揭露一實施例之控制訊號的時序的示意圖。如第5圖所示,在顯示裝置100自開機至關機的一次操作週期大致上經區分為四個期間,其分別為初始化期間T1、維持期間T2、資料設定期間T3、預留期間T4以及重置期間T5。需特別說明的是,第5圖中的該些期間的時間長度僅用以示例,並非用以限制本揭露文件。Please also refer to Figures 1 to 5. FIG. 5 is a schematic diagram of the timing of control signals according to an embodiment of the present disclosure. As shown in FIG. 5 , an operation cycle of the display device 100 from power on to power off is roughly divided into four periods, which are the initialization period T1 , the maintenance period T2 , the data setting period T3 , the reservation period T4 and the reset period. Setup period T5. It should be noted that the length of the periods in Figure 5 is only used as an example and is not intended to limit this disclosure document.
於初始化期間T1,致能訊號SCS具有第二邏輯位準(例如,低邏輯位準),以使致能訊號 具有第一邏輯位準(例如,高邏輯位準),藉以對寄存器RES[p]進行重置操作。 During the initialization period T1, the enable signal SCS has a second logic level (for example, a low logic level), so that the enable signal SCS Having a first logic level (for example, a high logic level) to perform a reset operation on the register RES[p].
於維持期間T2,致能訊號SCS具有高邏輯位準,以使致能訊號 具有低邏輯位準,藉以停止對寄存器RES[p]進行重置操作。 During the sustain period T2, the enable signal SCS has a high logic level, so that the enable signal Has a low logic level to stop the reset operation of register RES[p].
於資料設定期間T3,寄存器RES[p]依據輸入資料Input以及時脈訊號CLK,產生並輸出資料訊號SI_D[p]至數據鎖存器128[n]。此時,若第三輸出訊號HRS_out[m]具有高邏輯位準,數據鎖存器128[n]的開關230會導通,並將資料訊號SI_D[p]傳送至數據鎖存器128[n]的內部節點N1。另一方面,若第三輸出訊號HRS_out[m]具有低邏輯位準,數據鎖存器128[n]的開關230會關閉,並且數據鎖存器128[n]的迴授電路240會相應作動,從而鎖存內部節點N1的電位。During the data setting period T3, the register RES[p] generates and outputs the data signal SI_D[p] to the data latch 128[n] according to the input data Input and the clock signal CLK. At this time, if the third output signal HRS_out[m] has a high logic level, the switch 230 of the data latch 128[n] will be turned on and the data signal SI_D[p] will be transmitted to the data latch 128[n] Internal node N1. On the other hand, if the third output signal HRS_out[m] has a low logic level, the switch 230 of the data latch 128[n] will be closed, and the feedback circuit 240 of the data latch 128[n] will operate accordingly. , thereby latching the potential of internal node N1.
舉例而言,在資料訊號SI_D[p]具有資料電壓D(1)的期間,當移位暫存器HSR[1]所產生的第一輸出訊號OUT[m]具有高邏輯位準,邏輯電路426[m]依據第一輸出訊號OUT[m]所產生的第二輸出訊號HSR_out[m]會具有高邏輯位準。相應地,與第二輸出訊號HSR_out[m]呈反向的第三輸出訊號 具有低邏輯位準。 For example, during the period when the data signal SI_D[p] has the data voltage D(1), when the first output signal OUT[m] generated by the shift register HSR[1] has a high logic level, the logic circuit 426[m] The second output signal HSR_out[m] generated according to the first output signal OUT[m] will have a high logic level. Correspondingly, the third output signal which is inverse to the second output signal HSR_out[m] Has a low logic level.
此時,具有高邏輯位準的第二輸出訊號HSR_out[m]以及具有低邏輯位準的第三輸出訊號 會分別導通數據鎖存器128[n]的開關230中的電晶體232以及234,從而將資料訊號SI_D[p]的資料電壓D(1)傳送至數據鎖存器128[n]的內部節點N1,並且經由與內部節點N1電性串聯的反向放大器252、254、256以及258將資料電壓D(1)轉換為傳送至資料線DY[n]的資料電壓DV(1)。 At this time, the second output signal HSR_out[m] with a high logic level and the third output signal with a low logic level The transistors 232 and 234 in the switch 230 of the data latch 128[n] will be turned on respectively, thereby transmitting the data voltage D(1) of the data signal SI_D[p] to the internal node of the data latch 128[n]. N1, and converts the data voltage D(1) into the data voltage DV(1) transmitted to the data line DY[n] via the inverting amplifiers 252, 254, 256 and 258 electrically connected in series with the internal node N1.
在數據鎖存器128[n]的內部節點N1的電位經設定於資料電壓D(1)之後,移位暫存器HSR[m]所產生的第一輸出訊號OUT[m]會被下拉至低邏輯位準,邏輯電路426[m]相應產生具有低邏輯位準的第二輸出訊號HSR_out[m]以及具有高邏輯位準的第三輸出訊號 ,以使數據鎖存器128[n]依據第二輸出訊號HSR_out[m]以及第三輸出訊號 ,鎖存資料電壓D(1)。迴授電路240的作動方式已於前述實施例說明,故在此不再贅述。 After the potential of the internal node N1 of the data latch 128[n] is set to the data voltage D(1), the first output signal OUT[m] generated by the shift register HSR[m] will be pulled down to low logic level, the logic circuit 426[m] accordingly generates a second output signal HSR_out[m] with a low logic level and a third output signal with a high logic level. , so that the data latch 128[n] depends on the second output signal HSR_out[m] and the third output signal , latch data voltage D(1). The operation method of the feedback circuit 240 has been described in the previous embodiment, so it will not be described again here.
再舉一個例子,在資料設定期間T3中,若資料訊號SI_D[p]具有資料電壓D(q),且當移位暫存器HSR[1]所產生的第一輸出訊號OUT[m]具有高邏輯位準時,邏輯電路426[m]依據第一輸出訊號OUT[m]產生的第二輸出訊號HSR_out[m]具有高邏輯位準。相應地,與第二輸出訊號HSR_out[m]呈反向的第三輸出訊號 具有低邏輯位準。 To give another example, during the data setting period T3, if the data signal SI_D[p] has the data voltage D(q), and when the first output signal OUT[m] generated by the shift register HSR[1] has When the logic level is high, the second output signal HSR_out[m] generated by the logic circuit 426[m] according to the first output signal OUT[m] has a high logic level. Correspondingly, the third output signal which is inverse to the second output signal HSR_out[m] Has a low logic level.
此時,具有高邏輯位準的第二輸出訊號HSR_out[m]以及具有低邏輯位準的第三輸出訊號 會分別導通數據鎖存器128[n]的開關230中的電晶體232以及234,從而將資料訊號SI_D[p]的資料電壓D(q)傳送至數據鎖存器128[n]的內部節點N1,並且經由與內部節點N1電性串聯的反向放大器252、254、256以及258將資料電壓D(q)轉換為傳送至資料線DY[n]的資料電壓DV(q)。 At this time, the second output signal HSR_out[m] with a high logic level and the third output signal with a low logic level The transistors 232 and 234 in the switch 230 of the data latch 128[n] will be turned on respectively, thereby transmitting the data voltage D(q) of the data signal SI_D[p] to the internal node of the data latch 128[n]. N1, and converts the data voltage D(q) into the data voltage DV(q) transmitted to the data line DY[n] via the inverting amplifiers 252, 254, 256 and 258 electrically connected in series with the internal node N1.
在數據鎖存器128[n]的內部節點N1的電位經設定於資料電壓D(q)之後,移位暫存器HSR[m]所產生的第一輸出訊號OUT[m]會被下拉至低邏輯位準,邏輯電路426[m]相應產生具有低邏輯位準的第二輸出訊號HSR_out[m]以及具有高邏輯位準的第三輸出訊號 ,以使數據鎖存器128[n]依據第二輸出訊號HSR_out[m]以及第三輸出訊號 ,鎖存資料電壓D(q)。迴授電路240的作動方式已於前述實施例說明,故在此不再贅述。 After the potential of the internal node N1 of the data latch 128[n] is set to the data voltage D(q), the first output signal OUT[m] generated by the shift register HSR[m] will be pulled down to low logic level, the logic circuit 426[m] accordingly generates a second output signal HSR_out[m] with a low logic level and a third output signal with a high logic level. , so that the data latch 128[n] depends on the second output signal HSR_out[m] and the third output signal , the latch data voltage D(q). The operation method of the feedback circuit 240 has been described in the previous embodiment, so it will not be described again here.
於預留期間T4,由於第一輸出訊號OUT[m]以及重置控制訊號ALLCLEAR皆具有低邏輯位準,邏輯電路426[m]產生具有低邏輯位準的第二輸出訊號HSR_out[m],會維持鎖存操作,使資料線DY[n]仍具有資料電壓DV(q)。另一方面,預留期間T4,由於致能訊號SCS具有低邏輯位準,寄存器RES[p]會依據與致能訊號SCS呈反向的重置訊號 進行重置,以輸出具有低邏輯位準的資料訊號SI_D[p]。 During the reservation period T4, since both the first output signal OUT[m] and the reset control signal ALLCLEAR have a low logic level, the logic circuit 426[m] generates a second output signal HSR_out[m] with a low logic level. The latch operation will be maintained so that the data line DY[n] still has the data voltage DV(q). On the other hand, during the reserved period T4, since the enable signal SCS has a low logic level, the register RES[p] will be reset according to the inverse signal of the enable signal SCS. Reset is performed to output the data signal SI_D[p] with a low logic level.
於重置期間T5,由於致能訊號SCS仍然維持於低邏輯位準,資料訊號SI_D[p]具有低邏輯位準。並且,由於重置控制訊號ALLCLEAR具有高邏輯位準,邏輯電路426[m]會產生具有高邏輯位準的第二輸出訊號HSR_out[m],以導通數據鎖存器228[n]之中的開關230,從而將具有低邏輯位準的資料訊號SI_D[p]傳送至內部節點N1,藉此重置內部節點N1以及資料線DY[n]的電位。During the reset period T5, since the enable signal SCS still maintains a low logic level, the data signal SI_D[p] has a low logic level. Moreover, since the reset control signal ALLCLEAR has a high logic level, the logic circuit 426[m] will generate a second output signal HSR_out[m] with a high logic level to turn on the data latch 228[n]. The switch 230 transmits the data signal SI_D[p] with a low logic level to the internal node N1, thereby resetting the potential of the internal node N1 and the data line DY[n].
換言之,於重置期間T5,開關230依據具有高邏輯位準的第二輸出訊號HSR_out[m]導通,以導通數據鎖存器228[n]的內部節點N1與寄存器RES[p]的輸出端之間的電路路徑,並將寄存器RES[p]重置後且具有低邏輯位準的資料訊號SI_D[p]傳送至數據鎖存器228[n]的內部節點N1,進而重置資料線DY[n]的電位至低邏輯位準。In other words, during the reset period T5, the switch 230 is turned on according to the second output signal HSR_out[m] with a high logic level to connect the internal node N1 of the data latch 228[n] and the output terminal of the register RES[p]. circuit path between them, and transmits the data signal SI_D[p] with a low logic level after the register RES[p] is reset to the internal node N1 of the data latch 228[n], thereby resetting the data line DY [n] to a low logic level.
此時,由於第三輸出訊號 具有低邏輯位準,迴授電路240中的電晶體248會關斷,從而關斷接地端至電晶體246的第二端的電路路徑。如此,於重置期間T5初始時,無論電晶體246是否導通,接地端的電位不會經由電晶體248經傳送至內部節點N1。 At this time, since the third output signal With a low logic level, transistor 248 in feedback circuit 240 turns off, thereby closing the circuit path from ground to the second terminal of transistor 246 . In this way, at the beginning of the reset period T5, no matter whether the transistor 246 is turned on or not, the potential of the ground terminal will not be transmitted to the internal node N1 through the transistor 248.
並且,由於第二輸出訊號HSR_out[m]具有高邏輯位準,迴授電路240中的電晶體242會關斷,從而關斷系統高電壓端VDD至電晶體244的第一端的電路路徑。如此,於重置期間T5初始時,無論電晶體244是否導通,系統高電壓端VDD的電位不會經由電晶體242經傳送至內部節點N1,而導致重置操作失敗。Moreover, since the second output signal HSR_out[m] has a high logic level, the transistor 242 in the feedback circuit 240 will be turned off, thereby turning off the circuit path from the system high voltage terminal VDD to the first terminal of the transistor 244. In this way, at the beginning of the reset period T5, no matter whether the transistor 244 is turned on or not, the potential of the system high voltage terminal VDD will not be transmitted to the internal node N1 through the transistor 242, causing the reset operation to fail.
在一些實施例中,閘極驅動器110於重置期間T5會導通所有畫素PIX至相應的資料線DY[1]~DY[n]的電路路經,資料線DY[1]~DY[n] 同時將低邏輯位準的電位作為資料電壓傳送至所有的畫素PIX,藉此在重置期間T5重置顯示裝置100的所有畫素PIX,從而改善顯示裝置100的畫面的均勻性。In some embodiments, the gate driver 110 will conduct circuit paths of all pixels PIX to the corresponding data lines DY[1]~DY[n] during the reset period T5. The data lines DY[1]~DY[n ] At the same time, the potential of the low logic level is transmitted to all the pixels PIX as the data voltage, thereby resetting all the pixels PIX of the display device 100 during the reset period T5, thereby improving the uniformity of the picture of the display device 100.
請參閱第6圖,第6圖為本揭露一實施例之數據鎖存器628[n]的示意圖。如第6圖所示,數據鎖存器628[n]包含開關630以及迴授電路640。第1圖所示的數據鎖存器128[1]~128[y]每一者皆可由第6圖所示的數據鎖存器628[n]實施,其中n可為任意正整數。Please refer to Figure 6, which is a schematic diagram of the data latch 628[n] according to an embodiment of the present disclosure. As shown in FIG. 6 , the data latch 628[n] includes a switch 630 and a feedback circuit 640 . Each of the data latches 128[1]~128[y] shown in Figure 1 can be implemented by the data latch 628[n] shown in Figure 6, where n can be any positive integer.
開關630包含電晶體232以及電晶體234。第6圖所示的開關630的連接關係以及作動方式相似於第2圖中的開關230,故在此不再贅述。Switch 630 includes transistor 232 and transistor 234 . The connection relationship and operating mode of the switch 630 shown in FIG. 6 are similar to the switch 230 in FIG. 2, so they will not be described again here.
在第6圖的實施例中,迴授電路640是由傳輸閘(Transmission gate)實施。具體而言,迴授電路640包含電晶體642以及電晶體644。電晶體642係由P型電晶體實施,並且電晶體644是由N型電晶體實施。在架構上,電晶體642以及644並聯於內部節點N1以及節點N2之間。In the embodiment of FIG. 6, the feedback circuit 640 is implemented by a transmission gate. Specifically, the feedback circuit 640 includes a transistor 642 and a transistor 644 . Transistor 642 is implemented as a P-type transistor, and transistor 644 is implemented as an N-type transistor. Architecturally, transistors 642 and 644 are connected in parallel between internal nodes N1 and N2.
在功能上,電晶體642的閘極端用以接收第二輸出訊號HSR_out[m],電晶體644的閘極端用以接收與呈反向的第三輸出訊號 ,以使電晶體642以及644依據第二輸出訊號HSR_out[m]的邏輯位準同時導通或關斷。 Functionally, the gate terminal of the transistor 642 is used to receive the second output signal HSR_out[m], and the gate terminal of the transistor 644 is used to receive the third output signal in the opposite direction. , so that the transistors 642 and 644 are simultaneously turned on or off according to the logic level of the second output signal HSR_out[m].
具體而言,若第二輸出訊號HSR_out[m]具有高邏輯位準,開關630會導通,並且迴授電路640會關斷。另一方面,若第二輸出訊號HSR_out[m]具有低邏輯位準,開關630會關斷,並且迴授電路640會導通,以鎖存內部節點N1的電位,並將內部節點N1的電位經由反向放大器622以及624傳送至資料線DY[n]。Specifically, if the second output signal HSR_out[m] has a high logic level, the switch 630 will be turned on and the feedback circuit 640 will be turned off. On the other hand, if the second output signal HSR_out[m] has a low logic level, the switch 630 will be turned off, and the feedback circuit 640 will be turned on to latch the potential of the internal node N1 and pass the potential of the internal node N1 through Inversion amplifiers 622 and 624 are transmitted to the data line DY[n].
數據鎖存器628[n]的其餘作動方式及功能大致相似於數據鎖存器228[n],故在此不再贅述。The remaining operating modes and functions of the data latch 628[n] are generally similar to the data latch 228[n], so they will not be described again here.
綜上所述,本揭示文件利用邏輯電路426[m]依據重置控制訊號ALL以及第一輸出訊號OUT[m]產生第二輸出訊號HSR_out[m],並且在重置期間T5,依據第二輸出訊號HSR_out[m]導通數據鎖存器228[n]的內部節點N1與寄存器RES[p]的輸出端之間的電路路徑,從而將寄存器RES[p]經重置後的資料訊號SI_D[p]傳送至數據鎖存器228[n]的內部節點N1,進而對數據鎖存器228[n]進行重置。如此,得以重置資料線DY[n]的電位。To sum up, this disclosure uses the logic circuit 426[m] to generate the second output signal HSR_out[m] according to the reset control signal ALL and the first output signal OUT[m], and during the reset period T5, according to the second The output signal HSR_out[m] conducts the circuit path between the internal node N1 of the data latch 228[n] and the output terminal of the register RES[p], thereby converting the reset data signal SI_D[ of the register RES[p] p] is transmitted to the internal node N1 of the data latch 228[n], thereby resetting the data latch 228[n]. In this way, the potential of the data line DY[n] can be reset.
雖然本案已以實施方式揭露如上,然其並非限定本案,任何熟習此技藝者,在不脫離本案之精神和範圍內,當可作各種之更動與潤飾,因此本案之保護範圍當視後附之申請專利範圍所界定者為準。Although this case has been disclosed in the form of implementation, it does not limit this case. Anyone familiar with this technology can make various changes and modifications without departing from the spirit and scope of this case. Therefore, the scope of protection of this case shall be regarded as appended hereto. The scope of the patent application shall prevail.
為使本揭露之上述和其他目的、特徵、優點與實施例能更明顯易懂,所附符號之說明如下: 100:顯示裝置 110:閘極驅動器 120:資料驅動器In order to make the above and other objects, features, advantages and embodiments of the present disclosure more obvious and understandable, the accompanying symbols are explained as follows: 100:Display device 110: Gate driver 120:Data drive
122:移位暫存電路 122: Shift temporary storage circuit
124:數據鎖存電路 124: Data latch circuit
126[1]~126[x],426[m]:邏輯電路 126[1]~126[x],426[m]: logic circuit
128[1]~128[y],228[n],628[n]:數據鎖存器 128[1]~128[y],228[n],628[n]: data latch
130:畫素陣列 130:Pixel array
230,630:開關 230,630: switch
232,234,242,244,246,248,632,634,642,644:電晶體 232,234,242,244,246,248,632,634,642,644: transistor
240,640:迴授電路 240,640: Feedback circuit
252,254,256,258,652,654:反向放大器 252,254,256,258,652,654: reverse amplifier
430,436:反或閘 430,436: reverse OR gate
432:反向器 432:Reverser
N1:內部節點 N1: internal node
N2:節點 N2: node
OUT[1]~OUT[x],OUT[m]:第一輸出訊號 OUT[1]~OUT[x],OUT[m]: first output signal
HSR_out[1]~HSR_out[x],HSR_out[m]:第二輸出訊號 HSR_out[1]~HSR_out[x],HSR_out[m]: second output signal
~,:第三輸出訊號 ~ , :Third output signal
ALLCLEAR:重置控制訊號 ALLCLEAR: reset control signal
HSR[1]~HSR[x]:移位暫存器 HSR[1]~HSR[x]: shift register
DY[1]~DY[y]:資料線 DY[1]~DY[y]: data line
D(1)~D(q),DV(1)~DV(q):資料電壓 D(1)~D(q),DV(1)~DV(q): data voltage
GDEC[1]~GDEC[z]:解碼器 GDEC[1]~GDEC[z]: decoder
RES[p]:寄存器 RES[p]: register
SI_D[p]:資料訊號 Input:輸入訊號 CLK:時脈訊號 SCS:致能訊號 :重置訊號 INV:反向器 T1:初始化期間 T2:維持期間 T3:資料設定期間 T4:預留期間 T5:重置期間 SI_D[p]: data signal Input: input signal CLK: clock signal SCS: enable signal : Reset signal INV: Inverter T1: Initialization period T2: Sustainment period T3: Data setting period T4: Reserve period T5: Reset period
為使本揭露之上述和其他目的、特徵、優點與實施例能更明顯易懂,所附圖式之說明如下: 第1圖為本揭露一實施例之顯示裝置的示意圖。 第2圖為本揭露一實施例之數據鎖存器的示意圖。 第3圖為本揭露一實施例之用於產生資料訊號的寄存器的示意圖。 第4圖為本揭露一實施例之邏輯電路的示意圖。 第5圖為本揭露一實施例之控制訊號的時序的示意圖。 第6圖為本揭露一實施例之數據鎖存器的示意圖。 In order to make the above and other objects, features, advantages and embodiments of the present disclosure more obvious and understandable, the accompanying drawings are described as follows: Figure 1 is a schematic diagram of a display device according to an embodiment of the present disclosure. Figure 2 is a schematic diagram of a data latch according to an embodiment of the present disclosure. FIG. 3 is a schematic diagram of a register used to generate data signals according to an embodiment of the present disclosure. FIG. 4 is a schematic diagram of a logic circuit according to an embodiment of the present disclosure. FIG. 5 is a schematic diagram of the timing of control signals according to an embodiment of the present disclosure. FIG. 6 is a schematic diagram of a data latch according to an embodiment of the present disclosure.
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無 Domestic storage information (please note in order of storage institution, date and number) without Overseas storage information (please note in order of storage country, institution, date, and number) without
100:顯示裝置 100:Display device
110:閘極驅動器 110: Gate driver
120:資料驅動器 120:Data drive
122:移位暫存電路 122: Shift temporary storage circuit
124:數據鎖存電路 124: Data latch circuit
126[1]~126[x]:邏輯電路 126[1]~126[x]: Logic circuit
128[1]~128[y]:數據鎖存器 128[1]~128[y]: Data latch
130:畫素陣列 130:Pixel array
PIX:畫素 PIX: pixel
HSR[1]~HSR[x]:移位暫存器 HSR[1]~HSR[x]: shift register
DY[1]~DY[y]:資料線 DY[1]~DY[y]: data line
GDEC[1]~GDEC[z]:寄存器 GDEC[1]~GDEC[z]: register
OUT[1]~OUT[x]:第一輸出訊號 OUT[1]~OUT[x]: first output signal
HSR_out[1]~HSR_out[x]:第二輸出訊號 HSR_out[1]~HSR_out[x]: second output signal
~:第三輸出訊號 ~ :Third output signal
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW508549B (en) * | 2000-04-04 | 2002-11-01 | Sharp Kk | Static clock pulse generator and display |
US20070146354A1 (en) * | 2000-05-09 | 2007-06-28 | Sharp Kabushiki Kaisha | Data signal line drive circuit, drive circuit, image display device incorporating the same, and electronic apparatus using the same |
US20090195281A1 (en) * | 1997-06-12 | 2009-08-06 | Fujitsu Limited | Timing Signal Generating Circuit, Semiconductor Integrated Circuit Device and Semiconductor Integrated Circuit System to which the Timing Signal Generating Circuit is Applied, and Signal Transmission System |
TW201138308A (en) * | 2009-12-23 | 2011-11-01 | Semiconductor Energy Lab | Semiconductor device |
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- 2022-03-31 TW TW111112616A patent/TWI816348B/en active
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US20090195281A1 (en) * | 1997-06-12 | 2009-08-06 | Fujitsu Limited | Timing Signal Generating Circuit, Semiconductor Integrated Circuit Device and Semiconductor Integrated Circuit System to which the Timing Signal Generating Circuit is Applied, and Signal Transmission System |
TW508549B (en) * | 2000-04-04 | 2002-11-01 | Sharp Kk | Static clock pulse generator and display |
US20070146354A1 (en) * | 2000-05-09 | 2007-06-28 | Sharp Kabushiki Kaisha | Data signal line drive circuit, drive circuit, image display device incorporating the same, and electronic apparatus using the same |
TW201138308A (en) * | 2009-12-23 | 2011-11-01 | Semiconductor Energy Lab | Semiconductor device |
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