TWI815407B - 用於促進一計算環境內之處理的電腦程式產品、電腦系統及電腦實施方法 - Google Patents
用於促進一計算環境內之處理的電腦程式產品、電腦系統及電腦實施方法 Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
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- G06—COMPUTING OR CALCULATING; COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
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- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
- G06F9/3013—Organisation of register space, e.g. banked or distributed register file according to data content, e.g. floating-point registers, address registers
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- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
- G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
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- G06—COMPUTING OR CALCULATING; COUNTING
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- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/04—Architecture, e.g. interconnection topology
- G06N3/044—Recurrent networks, e.g. Hopfield networks
- G06N3/0442—Recurrent networks, e.g. Hopfield networks characterised by memory or gating, e.g. long short-term memory [LSTM] or gated recurrent units [GRU]
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- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/04—Architecture, e.g. interconnection topology
- G06N3/0464—Convolutional networks [CNN, ConvNet]
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- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/08—Learning methods
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- G06—COMPUTING OR CALCULATING; COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/04—Architecture, e.g. interconnection topology
- G06N3/048—Activation functions
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- Computational Linguistics (AREA)
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- Testing And Monitoring For Control Systems (AREA)
- Particle Accelerators (AREA)
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Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17/350,365 | 2021-06-17 | ||
| US17/350,365 US11693692B2 (en) | 2021-06-17 | 2021-06-17 | Program event recording storage alteration processing for a neural network accelerator instruction |
Publications (2)
| Publication Number | Publication Date |
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| TW202301110A TW202301110A (zh) | 2023-01-01 |
| TWI815407B true TWI815407B (zh) | 2023-09-11 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
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| TW111115169A TWI815407B (zh) | 2021-06-17 | 2022-04-21 | 用於促進一計算環境內之處理的電腦程式產品、電腦系統及電腦實施方法 |
Country Status (7)
| Country | Link |
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| US (2) | US11693692B2 (enExample) |
| JP (1) | JP7750990B2 (enExample) |
| CN (1) | CN117441172A (enExample) |
| DE (1) | DE112022002300T5 (enExample) |
| GB (1) | GB2622349A (enExample) |
| TW (1) | TWI815407B (enExample) |
| WO (1) | WO2022263997A1 (enExample) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US11693692B2 (en) | 2021-06-17 | 2023-07-04 | International Business Machines Corporation | Program event recording storage alteration processing for a neural network accelerator instruction |
| US12495005B1 (en) * | 2024-03-22 | 2025-12-09 | Chelsio Communications, Inc. | Programmable processing of network protocol packets |
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| CN111353595A (zh) * | 2018-12-20 | 2020-06-30 | 上海寒武纪信息科技有限公司 | 运算方法、装置及相关产品 |
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2021
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2022
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- 2023-04-28 US US18/308,793 patent/US12008395B2/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20170103304A1 (en) * | 2015-10-08 | 2017-04-13 | Via Alliance Semiconductor Co., Ltd. | Neural network unit with plurality of selectable output functions |
| CN111353595A (zh) * | 2018-12-20 | 2020-06-30 | 上海寒武纪信息科技有限公司 | 运算方法、装置及相关产品 |
| CN111126583A (zh) * | 2019-12-23 | 2020-05-08 | 中国电子科技集团公司第五十八研究所 | 一种通用神经网络加速器 |
Also Published As
| Publication number | Publication date |
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| CN117441172A (zh) | 2024-01-23 |
| GB202400226D0 (en) | 2024-02-21 |
| DE112022002300T5 (de) | 2024-02-22 |
| US12008395B2 (en) | 2024-06-11 |
| US11693692B2 (en) | 2023-07-04 |
| WO2022263997A1 (en) | 2022-12-22 |
| JP7750990B2 (ja) | 2025-10-07 |
| TW202301110A (zh) | 2023-01-01 |
| JP2024523790A (ja) | 2024-07-02 |
| US20230273810A1 (en) | 2023-08-31 |
| US20220405120A1 (en) | 2022-12-22 |
| GB2622349A (en) | 2024-03-13 |
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