TWI813139B - Semiconductor package element capable of improving side solderability and manufacturing method thereof - Google Patents

Abstract

A semiconductor package component that can improve side solderability, including a chip, a plastic sealing layer covering the chip, and a conductive layer formed on the plastic sealing layer. The distribution position of the conductive layer is based on the pins of the chip. Designed in this position, the completed conductive layer is electrically connected to the signal contacts of the chip and constitutes the pins of the semiconductor package components. Each pin is exposed on the plastic encapsulation layer and forms a concave step surface. The step surface The shape of the surface is determined by the overlapping first photoresist layer and second photoresist layer during the manufacturing process. When the semiconductor package component is to be soldered to a circuit board, the stepped surface of each pin can be used for solder adsorption and filling. This improves the soldering quality between the semiconductor package component and the circuit board, and allows the optical inspection device to determine the soldering status of each pin.

Description

Semiconductor packaging components that can improve side solderability and manufacturing methods thereof

The present invention relates to a packaging component, and in particular, to a semiconductor packaging component that can improve side solderability and a manufacturing method thereof.

Figures 7A to 7G disclose a conventional manufacturing method of a packaged component. Figure 7A shows a lead frame substrate 100 used in manufacturing the packaged component. A plurality of connecting ribs 101 made of metal are formed on the lead frame substrate 100. The A plurality of connecting ribs 101 are connected to the pins 102 . In addition to the connection ribs 101, there are also electroplated connection strips 103 on the lead frame substrate 100.

As shown in FIGS. 7B and 7C , the chip 200 is placed at the preset die bonding position of the lead frame substrate 100 , and metal wires 201 are connected to the chip 200 and the corresponding pins 102 through wiring operations, such as in FIG. 7C An example is that a single chip 200 is connected to six independent pins 102 .

After the wiring work is completed, as shown in FIG. 7D , the lead frame substrate 100 and the chip 200 are molded, and the chip 200 is covered with the plastic molding material 300 . Next, the first cutting operation is performed as shown in FIG. 7E. The first cutting operation is performed along the X-axis direction of the lead frame substrate 100. The cutting position is as shown by the dotted line, that is, along the connecting rib 101 therein. Make the cut. After the cutting is completed, the cut cross section of each pin 102 will be revealed.

After completing the first cutting operation in the X-axis direction, the electroplating operation is carried out. As shown in FIG. 7F , since there is a connected electroplated connection strip 103 on the lead frame substrate 100, the electroplated connection strip 103 can be energized, and an electroplating layer can be formed on the cut section of each pin 102. After the electroplating is completed, a second cutting operation is performed. The second cutting operation is performed along the Y-axis direction of the lead frame substrate 100, as shown in Figure The dashed line position shown on 7F. The package component after cutting is shown in FIG. 7G. On the cutting surface in the Y-axis direction, the cutting cross section with the connecting rib 101 can be seen exposed, so the copper 400 is exposed.

As mentioned above, although the existing production method can complete tin plating on the side of the pin on the package component, the intermediate process requires two cutting operations, namely the first cutting along the X-axis direction and the first cutting along the Y-axis direction. The second cutting is required, so the process is relatively complex and the cost is high; the packaged components will also have exposed copper problems after the second cutting.

The main purpose of the present invention is to provide a "semiconductor packaging component that can improve side solderability and a manufacturing method thereof", and to provide a semiconductor packaging component without the need for secondary cutting. The semiconductor packaging component has exposed contacts on the side. Feet can facilitate welding operations.

According to a preferred embodiment, the "semiconductor package component that can improve side solderability" proposed by the present invention includes: a chip with at least one signal contact on the front and back respectively, wherein the signal contact on the back is a contact On the first side of a conductive substrate; a plastic encapsulation layer covers the chip, and a first opening and a second opening are formed in the plastic encapsulation layer; a conductive layer fills each of the first opening and the second opening; The inside of the second opening serves as the pin of the semiconductor package component, wherein the conductive layer in the first opening is electrically connected to the signal contact on the back side of the chip through the conductive substrate. The conductive layer is electrically connected to the signal contacts on the front side of the chip; an insulating protective layer covers the second side of the conductive substrate and the front side of the plastic sealing layer; a first surface of each pin is exposed on the On the side of the plastic layer, a second surface of each pin is exposed on the insulating protective layer. The first surface and the second surface of each pin are vertically adjacent. On the first surface and the second surface of the pin Has an antioxidant layer.

The present invention proposes a manufacturing method to manufacture the above-mentioned semiconductor packaging component. The method includes: bonding a chip to the first side of a conductive substrate, wherein the front and back sides of the chip are respectively provided with at least one signal contact; encapsulating it with a plastic Cover the chip with a layer of plastic; form a first opening and a second opening in the plastic layer; fill a conductive layer inside the first opening and the second opening to serve as a pin, wherein the first opening The conductive layer in the hole is electrically connected to the signal contact on the back of the chip through the conductive substrate, and the conductive layer in the second opening is electrically connected to the signal contact on the front of the chip; an insulating protective layer is formed on The second side of the conductive substrate and the front side of the plastic encapsulation layer are cut at predetermined cutting lines on the insulating protective layer to form independent semiconductor packaging components, wherein a first pin of each semiconductor packaging component is One surface is exposed on the side of the plastic layer, a second surface of each pin is exposed on the insulating protective layer, and the first surface and the second surface of each pin are vertically adjacent; forming an anti-oxidation layer to Covering the first surface and the second surface of each pin.

According to another preferred embodiment, the "semiconductor package component that can improve side solderability" proposed by the present invention includes: a chip with at least one signal contact on the front and back respectively, wherein the back of the chip is provided with On the first side of a conductive substrate; a plastic sealing layer covers the chip, and first openings and second openings are formed in the plastic sealing layer; a conductive layer fills each of the first openings and the first opening; The inside of the second opening serves as the pin of the semiconductor package component, wherein the conductive layer in the first opening is electrically connected to the signal contact on the back side of the chip through the conductive substrate. The conductive layer is electrically connected to the signal contact on the front side of the chip; An insulating protective layer covers the second surface of the conductive substrate and the front surface of the plastic sealing layer; wherein, the portion of each pin exposed on the plastic sealing layer forms a stepped surface, and the stepped surface includes a sequence of adjacent A first arc surface, a second arc surface and a vertical surface.

The present invention also proposes a manufacturing method to manufacture the above-mentioned semiconductor packaging component. The method includes: bonding a chip to the first side of a conductive substrate, wherein the front and back sides of the chip are respectively provided with at least one signal contact; The plastic sealing layer covers the wafer; a first opening and a second opening are formed in the plastic sealing layer. The first opening is located on the side of the wafer and penetrates the plastic sealing layer. The second opening extends to the front side of the wafer. signal contacts; forming a first photoresist layer, wherein the first photoresist layer exposes the first opening and the second opening after exposure and development; forming a second photoresist layer and overlapping the first photoresist layer On the resist layer, the second photoresist layer exposes the first opening and the second opening after exposure and development, wherein the coverage of at least a part of the second photoresist layer is larger than that of the first photoresist layer below it; A conductive layer is filled inside the first opening and the second opening, wherein the conductive layer in the first opening is electrically connected to the signal contact on the back side of the chip through the conductive substrate, and the second opening is The conductive layer in the opening is electrically connected to the signal contact on the front side of the chip; the first photoresist layer and the second optical layer are removed so that the conductive layer forms a pin; an insulating protective layer is formed on the conductive layer The second side of the substrate and the front side of the plastic sealing layer are cut on the predetermined cutting lines on the insulating protective layer to form independent semiconductor packaging components, wherein each pin of the semiconductor packaging component is exposed on the plastic sealing layer. A step surface is partially formed, and the step surface includes a first arc surface, a second arc surface and a vertical surface that are adjacent in sequence; an anti-oxidation layer is formed to cover the step surface of each pin.

The semiconductor packaging component and its manufacturing method proposed by the present invention do not require pre-preparation of a lead frame with a specific design as in the prior art, and do not need to perform two cuts during the manufacturing process, thereby avoiding the problem of copper exposure after the final cutting. In the semiconductor package component of the present invention, each pin on the side surface can be used for solder adsorption contact, thereby improving the soldering quality when the component is connected to the circuit board.

10: Conductive substrate

11: Side 1

12:Second side

20:wafer

21: Signal contact

30:Plastic sealing layer

31a: First opening

31b: Second opening

40: Pre-plated layer

42:Conductive layer

42a, 42b: Pin

421: First surface

422: Second surface

43:Step surface

431: First arc surface

432:Second arc surface

433:Vertical plane

44: Insulating protective layer

46:Antioxidant layer

50: Photoresist layer

51: First photoresist layer

52: Second photoresist layer

P:circuit board

M1, M2: metal contacts

S:Solder

100: Lead frame substrate

101: Connect the ribs

102: Pin

103:Electroplating connecting strip

200:wafer

201:Wire

300:Plastic sealing material

400:Exposed copper

1A to 1K: schematic diagram of the manufacturing process according to the first embodiment of the present invention.

Figure 2: Application diagram of the first embodiment of the present invention.

FIG. 3A is a schematic diagram of the appearance of a package component manufactured according to the manufacturing method of the first embodiment of the present invention.

Figure 3B: A schematic diagram of the appearance of another package component manufactured according to the manufacturing method of the first embodiment of the present invention.

FIG. 3C is a schematic diagram of the appearance of another package component manufactured according to the manufacturing method of the first embodiment of the present invention.

4A to 4M: schematic diagram of the manufacturing process of the second embodiment of the present invention.

Figure 5: Application diagram of the second embodiment of the present invention.

Figure 6: A schematic diagram of the appearance of a package component produced according to the second embodiment of the present invention.

Figure 7A~Figure 7G: Schematic diagram of the manufacturing process of existing packaging components.

1A to 1K are process schematic diagrams of the first preferred implementation. In FIG. 1A , a plurality of wafers 20 are bonded to the first surface 11 of a conductive substrate 10 through a die bonding process. The conductive substrate 10 can be A copper substrate. The back side of each chip 20 has at least one signal contact (back-side metal) 21 for bonding to the first surface 11 of the conductive substrate 10. The signal contact 21 is formed on the back side by, for example, metal sputtering. , there is also at least one signal contact (not shown in the figure) on the front side of the chip 20 .

Referring to FIG. 1B , a plastic sealing layer 30 is formed on the conductive substrate 10 to cover each chip 20 . The material of the plastic sealing layer 30 can be dielectric materials such as PP and EMC. After the plastic sealing layer 30 is formed, the planarization step shown in FIG. 1C is performed if necessary, and grinding or cleaning operations are performed on the surface of the plastic sealing layer 30 to make the surface of the entire plastic sealing layer 30 a smooth surface.

Referring to FIG. 1D, first openings (vias) 31a and second openings 31b are formed at preset pin positions of the plastic sealing layer 30. The positions and numbers of the first openings 31a and the second openings 31b are determined by Depending on the required pin positions of the product, for example, the first openings 31a are located on the same side of the chip 20; or there are a plurality of first openings 31a on opposite sides of the chip 20; or there are a plurality of first openings 31a. An opening 31 a is distributed around the wafer 20 . The first opening 31a around the chip 20 completely penetrates the plastic layer 30 to expose the first surface 11 of the conductive substrate 10, so that the bottom end of the first opening 31a is flush with the third surface of the conductive substrate 10. On one side 11 , the second opening 31 b extends from the surface of the plastic sealing layer 30 to the signal contact on the front surface of the chip 20 . The first opening 31a and the second opening 31b can be made by methods such as laser drilling (Laser drilling), ultrasonic drilling (Ultrasonic drilling), Micro Electrical Discharge Machining (μ-EDM), Technologies such as Micro powder blasting or Inductively Coupled Plasma Reactive Ion Etching (ICP-RIE) are not particularly limited in their forming methods. The first opening and the second opening described in this specification refer to the openings at different positions, thereby distinguishing the types of different openings, rather than referring to the number of the first opening and the second opening.

Referring to FIG. 1E, a pre-plated layer 40 is formed on the wall of each first opening 31a, the second opening 31b and the surface of the plastic layer 30. The pre-plated layer 40 serves as a seed layer for subsequent production of a conductive layer. layer), the pre-plating layer 40 can be made by electro-less plating, sputtering and other technologies; preferably, the material of the pre-plating layer 40 is titanium/copper (Ti/Cu ).

Please refer to FIGS. 1F to 1G. A photoresist layer 50 is formed on the surface of the pre-plated layer 40. After patterning, the photoresist layer 50 is positioned at positions corresponding to the first openings 31a and the second openings 31b. form The window is opened to expose the pre-plated layer 40 . A conductive layer 42 is filled inside each of the first opening 31a and the second opening 31b. The preferred material of the conductive layer 42 is copper.

Referring to FIG. 1H , after the conductive layer 42 is formed, the photoresist layer 50 and the pre-plating layer 40 below are removed, and the conductive layer 42 forms a plurality of pins. In a preferred embodiment, the conductive layer 42 in each first opening 31a and second opening 31b forms an independent pin 42a, 42b; in another preferred embodiment, according to the pins of the chip 20 By design, the conductive layers 42 in the plurality of first openings 31a and/or the second openings 31b can also be electrically connected to each other to form a common contact (not shown in the figure).

Referring to FIG. 1I , an insulating protective layer 44 (solder mask) is formed on the second surface 12 of the conductive substrate 10 and the front surface of the plastic sealing layer 30 . The insulating protective layer 44 has the functions of waterproofing and preventing oxidation. Among them, because the insulating protective layer 44 on the front side is distributed between the adjacent pins 42a and 42b, the insulating protective layer 44 can be used as a solder resist layer to prevent the adjacent pins 42a and 42b from short circuiting.

Referring to FIGS. 1J to 1K , sawing is performed at a predetermined cutting position on the insulating protective layer 44 , so that each chip 20 and its plastic packaging layer 30 become independent packaging components. An anti-oxidation layer 46 is formed on the exposed surface of each pin 42a, 42b. The anti-oxidation layer 46 can be an organic solderability preservative (OSP), electroless tin plating (E'less Tin), or electroless electroplating. Nickel immersion gold (ENIG), lead-free tin spray (HASL), etc. The area covered by the anti-oxidation layer 46 includes the first surface 421 of each pin 42a and 42b exposed due to cutting and the second surface 422 of each pin 42a and 42b that is not covered by the insulating protective layer 44. Viewed from a cross-section, each The first surface 421 and the second surface 422 of the pins 42 a and 42 b are vertically adjacent in an L shape, and the first surface 421 is flush with the side of the plastic layer 30 .

Please refer to FIG. 2 , which is an application schematic diagram of the first embodiment of the present invention. The signal contact 21 of the chip 20 is electrically connected to the pin 42 a through the conductive substrate 10 . Taking the direction shown in FIG. 2 as an illustration, the pins 42 a and 42 b The bottom surfaces are all on the same plane for soldering to a circuit board P. These pins 42a and 42b are electrically connected to the metal contacts M1 and M2 on the circuit board P through solder S. The solder S can be adsorbed on the side and bottom of each pin 42a and 42b to increase the contact area. Ensure welding reliability. Other than that In addition, automatic optical inspection (AOI) equipment can also directly photograph the joint situation between the packaged component and the circuit board P to judge the soldering quality of the packaged component.

One of the package components produced according to the above process has an appearance as shown in Figure 3A. The package component has a pin 42a, 42b on two opposite sides, and the first surface 421 of each pin 42a, 42b is exposed at the same time. On the side of the package component, the second surface 422 will be exposed on the soldering bottom surface of the package component, and the anti-oxidation layer 46 is plated on the exposed first surface 421 and second surface 422 of each pin 42a, 42b; please refer again. As shown in FIG. 3B , according to the pin position design of the package component, a plurality of pins 42 a can also be concentrated on the same side of the package component. Figure 3C is also another package component produced according to the above process. There are a plurality of pins 42a and 42b distributed on each side. The package component has the shape of a QFN component.

Please also refer to FIGS. 4A to 4M , which are schematic diagrams of the manufacturing process of the second preferred embodiment of the present invention. In the second preferred embodiment, the same component symbols are used as in the first embodiment, because the manufacturing method of FIGS. 4A to 4E The manufacturing method is the same as that in Figures 1A to 1E and will not be described again here.

Please refer to FIG. 4F. A first photoresist layer 51 is formed on the surface of the pre-plated layer 40. After patterning, the first photoresist layer 51 is formed at positions corresponding to the first openings 31a and the second openings 31b. Windows are respectively formed to expose the pre-plating layer 40 .

Please refer to FIG. 4G. After the first photoresist layer 51 is formed, a second photoresist layer 52 is formed on the surface of the first photoresist layer 51, so that the second photoresist layer 52 overlaps the first photoresist layer. 51, the overall thickness of the second photoresist layer 52 after stacking the first photoresist layer 51 may be equal to the thickness of the single photoresist layer 50 in the first embodiment. Similarly, after the second photoresist layer 52 is patterned, openings are also formed at positions corresponding to the first openings 31a and the second openings 31b, and are exposed in the openings of the second photoresist layer 52. The pre-plated layer 40. Comparing Figure 4F and Figure 4G, when patterning the second photoresist layer 52, the mask pattern of the second photoresist layer 52 is specially designed. For the photoresist layer expected to form the side pins of the package component, this The invention specifically designs that the extension width W2 of the second photoresist layer 52 is greater than the extension of the first photoresist layer 51 below it. Width W1 (W2>W1). For example, if the second photoresist layer 52 is a negative photoresist, the photosensitive portion will be retained after development. Therefore, the mask opening width of the second photoresist layer 52 can be designed to be slightly larger than that of the first photoresist layer. With a width W1 of 51, the coverage area of the second photoresist layer 52 after development can be slightly larger than that of the first photoresist layer 51. The sides of the second photoresist layer 52 are naturally slightly bent downward, so that the edges of the photoresist layer after the second photoresist layer 52 and the first photoresist layer 51 are superimposed form side edges that are wider at the top and narrower at the bottom.

Referring to FIG. 4H, a conductive layer 42 is further formed in the openings not covered by the second photoresist layer 52 and the first photoresist layer 51. The conductive layer 42 fills each first opening 31a and the second opening. Inside the hole 31b, the preferred material of the conductive layer 42 is copper.

As shown in FIG. 4I , after the conductive layer 42 is formed, the first photoresist layer 51 and the second photoresist layer 52 are removed, so that the conductive layer 42 is formed into a plurality of pins. Because the overlapped edges of the first photoresist layer 51 and the second photoresist layer 52 have a shape that is wide at the top and narrow at the bottom, the first photoresist layer 51 and the second photoresist layer 52 can be completely etched without leaving any residue. In a preferred embodiment, the conductive layer 42 in each first opening 31a and second opening 31b forms an independent pin 42a, 42b; in another preferred embodiment, according to the pin position of the chip 20 By design, the conductive layers 42 in the plurality of first openings 31a and/or the second openings 31b can also be electrically connected to each other to form a common contact (not shown in the figure). After removing the photoresist, a stepped surface 43 is formed on the side of each pin 42a, 42b. The stepped surface 43 is composed of a first arc surface 431, a second arc surface 432 and a vertical surface 433 connected in sequence. The first arc surface 431 and the second arc surface 432 are arc-shaped convex surfaces; the vertical surface 433 is a flat surface, flush with the side surface of the packaging component.

As shown in FIG. 4J , the pre-plated layer 40 originally covered by the first photoresist layer 51 and the second photoresist layer 52 is etched to expose the plastic sealing layer 30 under the pre-plated layer 40 .

As shown in FIG. 4K , an insulating protective layer 44 (solder mask) is formed of an insulating material on the bottom surface of the conductive substrate 10 and the front surface of the plastic sealing layer 30 . The insulating protective layer 44 on the front side of the plastic sealing layer 30 is distributed between the adjacent pins 42a and 42b and can be used as a solder resist layer to prevent the adjacent pins 42a and 42b from being short-circuited.

Please refer to FIG. 4L , cutting (sawing) is performed at a predetermined cutting position, so that each chip 20 and its plastic packaging layer 30 form an independent package component. The side surfaces of the pins 42a and 42b of each package component are exposed as they are cut, so a surface protection treatment as shown in FIG. 4K is further performed to form an anti-oxidation layer 46 on the exposed surfaces of the pins 42a and 42b. The oxide layer 46 may be organic solderability preservative (OSP), electroless tin plating (E'less Tin), electroless nickel immersion gold plating (ENIG), lead-free spray tin plating (HASL), etc. The range covered by the anti-oxidation layer 46 includes the stepped surface 43 of each pin 42a and 42b exposed due to cutting and the surface of each pin 42a and 42b that is not covered by the insulating protective layer 44.

Please refer to Figure 5, which is a schematic diagram of the application of the packaged component according to the second embodiment of the present invention. The difference from the first embodiment is that the side surfaces of the pins 42a and 42b have stepped surfaces 43. When the packaged component is welded to the circuit board P, The stepped surface 43 can accommodate more solder S, thereby increasing the welding area and ensuring the reliability of welding.

Please refer to FIG. 6 , which shows the appearance of a package component produced according to the process of the second embodiment. A plurality of pins 42a and 42b are formed on opposite sides of the package component, and each pin 42a and 42b has the step surface 43 . The shape of the package component is not limited to the shape of Figure 6, and can also be any of the embodiments shown in Figures 3A to 3C.

Through the description of the above specific embodiments, the packaging component and its manufacturing method of the present invention have the following characteristics:

1. According to at least one embodiment of the present invention, each exposed pin distributed on the side of the package component can be fully covered with solder, thereby increasing the area in contact with the solder and ensuring welding quality.

2. According to at least one embodiment of the present invention, the present invention uses two continuously superimposed photomasks to define the pin shape of the package component, so that the pins form a stepped surface that can accommodate more solder. The stepped surface can increase the number of solders and solder. contact area.

3. During the production process of the present invention, there is no need to perform continuous operations such as first cutting, electroplating, and second cutting as in the previous technology, which can reduce cutting steps and avoid the problem of exposed copper after the final cutting.

4. The present invention does not require the use of traditional lead frames and wire bonding during the manufacturing process.

5. In the present invention, the conductive material (such as copper) filled inside the first opening and the second opening constitutes the pin of the package component. The pin has a large contact area with the chip, which can improve the heat conduction of the package component. , producing better heat dissipation effect.

20:wafer 21: Signal contact 30:Plastic sealing layer 40: Pre-plated layer 42a, 42b: Pin 431: First arc surface 432:Second arc surface 433:Vertical plane 44: Insulating protective layer 46:Antioxidant layer P:circuit board M1, M2: metal contacts S:Solder

Claims (14)

A semiconductor package component that can improve side solderability, including: a chip, the front and back of which are respectively provided with at least one signal contact, wherein the signal contact on the back is in contact with the first side of a conductive substrate; a plastic package A layer that covers the wafer, and a first opening and a second opening are formed in the plastic layer, and the bottom end of the first opening is flush with the first surface of the conductive substrate; a conductive layer , filled inside each of the first opening and the second opening to serve as a pin of a semiconductor package component, wherein the conductive layer in the first opening electrically contacts the first surface of the conductive substrate to The signal contact on the back side of the chip is electrically connected, the conductive layer in the second opening is electrically connected on the signal contact on the front side of the chip; an insulating protective layer covers the second side of the conductive substrate and The front side of the plastic sealing layer; wherein, a first surface of each pin is exposed on the side of the plastic sealing layer, a second surface of each pin is exposed on the insulating protective layer, and the first surface of each pin Vertically adjacent to the second surface, there is an anti-oxidation layer on the first surface and the second surface of the pin. For the semiconductor package component that can improve side solderability as described in claim 1, the first surface of each pin is flush with the side of the plastic layer, and the anti-oxidation layer on the second surface is insulated from the The protective layer is flush. In the semiconductor package component that can improve side solderability as described in claim 1, the first surface and the second surface of each pin are both flat surfaces. A method for manufacturing semiconductor packaging components that can improve side solderability, including: bonding a chip to the first side of a conductive substrate, wherein at least one signal contact is provided on the front and back of the chip; covering it with a plastic encapsulation layer The wafer; forming a first opening and a second opening in the plastic layer; Filling a conductive layer inside the first opening and the second opening to serve as a pin, wherein the conductive layer in the first opening is electrically connected to the signal contact on the back of the chip through the conductive substrate , the conductive layer in the second opening is electrically connected to the signal contact on the front side of the chip; an insulating protective layer is formed on the second side of the conductive substrate and the front side of the plastic layer; on the insulating protective layer Predetermined cutting lines are used to cut to form independent semiconductor package components, wherein a first surface of each pin of each semiconductor package component is exposed on the side of the plastic sealing layer, and a second surface of each pin is exposed In the insulating protective layer, the first surface and the second surface of each pin are vertically adjacent; an anti-oxidation layer is formed to cover the first surface and the second surface of each pin. As claimed in claim 4, the manufacturing method of semiconductor packaging components that can improve side solderability, in the step of filling a conductive layer in the first opening and the second opening, further includes: on the surface of the plastic sealing layer, A pre-plating layer is preformed inside the first opening and the second opening; a single photoresist layer is coated on the pre-plating layer, and the photoresist layer is patterned to form a plurality of openings, wherein the plurality of openings are The first opening and the second opening are opened correspondingly to expose the first opening and the second opening; through the opening on the photoresist layer, the conductive layer is filled in the first opening and the second opening; and the photoresist layer is removed. As described in claim 5, the method for manufacturing a semiconductor packaging component that can improve side solderability is: after removing the photoresist layer, the insulating protective layer is filled in the original position of the photoresist layer to cover the front side of the plastic encapsulation layer. The manufacturing method of semiconductor packaging components that can improve side solderability as described in claim 4, wherein: in the step of covering the chip with a plastic sealing layer, the surface of the plastic sealing layer is further ground; In the step of forming the first opening and the second opening in the plastic sealing layer, the first opening is located around the chip and penetrates the plastic sealing layer, and the second opening corresponds to the signal contact extending to the front surface of the chip. The first opening and the second opening are formed using a laser drilling process. A semiconductor packaging component that can improve side solderability, including: a chip, the front and back of which are respectively provided with at least one signal contact, wherein the signal contact on the back is in contact with the first side of a conductive substrate; a plastic sealing layer , the wafer is covered, and first openings and second openings are formed in the plastic layer; a conductive layer is filled inside each of the first opening and the second opening to serve as a semiconductor packaging element pins, wherein the conductive layer in the first opening is electrically connected to the signal contact on the back side of the chip through the conductive substrate, and the conductive layer in the second opening is electrically connected to the front side of the chip Signal contact; an insulating protective layer covers the second surface of the conductive substrate and the front surface of the plastic sealing layer; wherein, the portion of each pin exposed to the plastic sealing layer forms a step surface, and the step surface includes sequential phases. A first arc surface, a second arc surface and a vertical surface are adjacent. The semiconductor package component that can improve side solderability as described in claim 8, wherein the first arc surface and the second arc surface of each pin are an arc-shaped convex surface, and the vertical surface is a flat surface. flush with the side of the plastic sealing layer. A method for manufacturing semiconductor packaging components that can improve side solderability, including: bonding a chip to the first side of a conductive substrate, wherein at least one signal contact is provided on the front and back of the chip; covering it with a plastic encapsulation layer The chip has a first opening and a second opening formed in the plastic layer. The first opening is located on the side of the chip and penetrates the plastic layer. The second opening extends to the signal contact on the front side of the chip. ; A first photoresist layer is formed, wherein the first photoresist layer exposes the first opening and the second opening after exposure and development; a second photoresist layer is formed and overlapped on the first photoresist layer, the The second photoresist layer exposes the first opening and the second opening after exposure and development, wherein the coverage area of at least a part of the second photoresist layer is larger than that of the first photoresist layer below it; a conductive layer is filled in Inside the first opening and the second opening, the conductive layer in the first opening is electrically connected to the signal contact on the back side of the chip through the conductive substrate, and the conductive layer in the second opening is The layer is electrically connected to the signal contacts on the front side of the chip; the first photoresist layer and the second optical layer are removed so that the conductive layer forms a pin; an insulating protective layer is formed on the second side of the conductive substrate And the front side of the plastic packaging layer; cut the predetermined cutting lines on the insulating protective layer to form an independent semiconductor packaging component, wherein the portion of each pin of the semiconductor packaging component exposed to the plastic packaging layer forms a stepped surface , the step surface includes a first arc surface, a second arc surface and a vertical surface that are adjacent in sequence; an anti-oxidation layer is formed to cover the step surface of each pin. The manufacturing method of semiconductor packaging components that can improve side solderability as described in claim 10, wherein: before forming the first photoresist layer, on the surface of the plastic layer and inside the first opening and the second opening A pre-plated layer is formed in advance; after removing the first photoresist layer and the second photoresist layer, the pre-plated layer that is not covered by the conductive layer is further removed to expose the surface of the plastic sealing layer. The manufacturing method of semiconductor packaging components that can improve side solderability as described in claim 10, wherein for the second photoresist layer whose coverage area is larger than that of the first photoresist layer, the edge of the second photoresist layer is naturally bent. The manufacturing method of semiconductor packaging components that can improve side solderability as described in claim 10, wherein the first arc surface and the second arc surface of each pin are an arc-shaped convex surface, and the vertical surface is a flat surface, and Flush with the side of the plastic sealing layer. The manufacturing method of semiconductor packaging components that can improve side solderability as described in claim 10, wherein: in the step of covering the chip with a plastic sealing layer, the surface of the plastic sealing layer is further ground; and a first opening is formed in the plastic sealing layer. In the step of opening holes and second openings, the first openings are located around the chip and penetrate the plastic sealing layer, and the second openings extend correspondingly to the signal contacts on the front side of the chip. The first openings and the second openings are The openings are formed using a laser drilling process.