TWI812221B - Memory device and operation method thereof - Google Patents

Abstract

A memory device and an operation method thereof are provided. The operation method includes: in a programming operation, programming a plurality of threshold voltages of a plurality of switches on a plurality of string select lines and a plurality of ground select lines as a first reference threshold voltage, and programming a plurality of threshold voltages of a plurality of dummy memory cells on a plurality of dummy word lines as being gradually increased along a first direction or a second direction, and the threshold voltages of the dummy memory cells being higher than the first reference threshold voltage; wherein the first direction being from the string select lines to a plurality of word lines and the second direction being from the ground select lines to the word lines.

Description

Memory device and method of operating the same

The present invention relates to a memory device and an operating method thereof.

In a memory device, when the memory device is read after being idle for a long time (hereinafter referred to as the first read), the read current will be high, and a low threshold voltage (Vt) will usually be induced, which is easy to A temporary read error occurred. However, temporary read errors usually do not occur on the next read (i.e., the second read) because the idle time between two consecutive reads is usually not too long.

Figure 1A shows the read waveforms for the first read and the second read. The idle time between the first read (100μs) and the second read (100μs) is approximately 10μs. As shown in Figure 1A, the read voltage Vread and the threshold voltage Vt are both 1.5V, the drain voltage Vd is 0.6V, and the pass voltage Vpass is 8V.

Figure 1B shows the read current (ID) versus read time graph for the first read and the second read. As shown in Figure 1B, the read current ID for the first read is higher than the read current ID for the second read. The timing T1 represents the sensing timing, that is, the read current is taken out at the sensing timing T1 to determine the critical voltage value of the memory cell. For the first reading, it will correspond to a lower critical voltage, which is prone to Temporary read errors; and, for the second read, will correspond to the normal threshold voltage, and there will be less temporary read errors.

Figure 1C (X-axis is "second read time") and Figure 1D (X-axis is "idle time") show the second read current and read time graphs under different idle times. As shown in Figure 1C and Figure 1D, when the idle time is longer (such as 1s), the second read current will be higher, which means that temporary read errors are more likely to occur; and, when the idle time is shorter, time (such as 10μs), the lower the second reading current will be, that is, the less likely temporary reading errors will occur.

Therefore, how to avoid temporary read errors of memory devices is one of the efforts.

According to an example of this case, an operating method of a memory device is proposed. The memory device includes a plurality of ground selection lines, a plurality of string selection lines, a plurality of character lines, and a plurality of redundant character lines. The redundant character lines A first portion of the character lines is close to the string select lines, a second portion of the redundant word lines is close to the ground select lines, and the word lines are between the redundant word lines. Between the first part and the second part of the redundant word lines, the operating method of the memory device includes: programming the string select lines and the ground select lines during programming operation A plurality of threshold voltages of a plurality of switches to have a first reference threshold voltage; and a plurality of threshold voltages of a plurality of redundant memory unit cells on the redundant word lines are programmed to be along a first direction or A second direction is gradually increasing and the critical voltages of the redundant memory unit cells are higher than the first reference critical voltage, wherein the first direction The second direction is from the string selection lines to the word lines, and the second direction is from the ground selection lines to the word lines.

According to another example of this case, a memory device is proposed, including: a plurality of bit lines; a plurality of ground selection lines; a plurality of first switches located at the intersections of the bit lines and the ground selection lines; a plurality of strings Selection lines, a plurality of second switches located at the intersections of the bit lines and the string selection lines; a plurality of word lines, and a plurality of memory unit cells located at the intersections of the bit lines and the word lines at; and a plurality of redundant word lines, a plurality of redundant memory unit cells located at the intersections of the bit lines and the redundant word lines; wherein one of the redundant word lines is the first A portion is close to the string select lines, a second portion of one of the redundant word lines is close to the ground select lines, and the word lines are between the first portion of the redundant word lines and Between the second portion of the redundant word lines, the plurality of threshold voltages of the first switches and the second switches on the string select lines and the ground select lines are programmed to have a first a reference threshold voltage, a plurality of threshold voltages of the redundant memory unit cells of the redundant word lines are programmed to gradually increase along a first direction or a second direction, and the redundant The threshold voltages of the memory cell are higher than the first reference threshold voltage, wherein the first direction is from the string selection lines to the word lines, and the second direction is from the ground selection lines to The character lines.

In order to have a better understanding of the above and other aspects of the present invention, examples are given below and are described in detail with reference to the accompanying drawings:

T1: Induction timing

200:Memory device

B0~BQ: memory block

CSL: common source line

WL0~WLN: character lines

BL0~BLP: bit lines

SW: switch

SSL0~SSL2: string selection line

DWLT0-DWLT2, DWLB0-DWLB2: redundant word lines

GSL0~GSL2: Ground selection line

SS: memory string

MC: memory unit

DMC: redundant memory unit

L31, L32: Channel voltage curve graph

510: Steps

Figure 1A shows the read waveforms for the first read and the second read.

Figure 1B shows the read current (ID) versus read time graph for the first read and the second read.

Figures 1C and 1D show second read current versus read time graphs at different idle times.

Figure 2 shows an equivalent circuit diagram of a memory device according to an embodiment of the present invention.

Figure 3 shows the channel voltage and signal line position diagram of an embodiment of the present invention and the conventional technology.

Figure 4A shows the reading waveform diagrams of the first reading and the second reading in an embodiment of the present invention.

Figure 4B shows the idle time at the first word line (between the first read and the second read) versus the second read current.

Figure 4C shows the idle time at the second word line (between the first read and the second read) versus the second read current.

Figure 5 shows a flow chart of a memory device operating method according to another embodiment of the present invention.

The technical terms in this specification refer to the idioms in the technical field. If there are explanations or definitions for some terms in this specification, the explanation or definition of this part of the terms shall prevail. Each embodiment of the present disclosure has one or more technical features. Under the premise that it is possible to implement, there are generally known people in this technical field. The skilled person may selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

Figure 2 shows an equivalent circuit diagram of the memory device 200 according to an embodiment of the present invention. The memory device 200 is, for example, but not limited to, a three-dimensional (3D) memory device. As shown in Figure 2, the memory device 200 includes a plurality of memory blocks B0~BQ (Q is a positive integer), a common source line CSL, and a plurality of word lines WL0~ WLN (N is a positive integer), a plurality of redundant word lines, a plurality of bit lines BL0~BLP (P is a positive integer), a plurality of string select lines and a plurality of ground select lines (GSL). In Figure 1, although three string selection lines SSL0~SSL2, three ground selection lines GSL0~GSL2 and six redundant word lines DWLT0~DWLT2 and DWLB0~DWLB2 are shown, this case is not limited thereto. , the string selection lines, the ground selection lines and the redundant word lines can have other numbers, which is also within the spirit of this case. In addition, the redundant word lines DWLT0 ~ DWLT2 close to the string select lines SSL0 ~ SSL2 can also be called a first part of the redundant word lines, and the redundant word lines DWLT0 ~ DWLT2 close to the ground select lines GSL0 ~ GSL2 The redundant word lines DWLB0~DWLB2 can also be called the second part of the redundant word lines. The word lines WL0 ~ WLN are between the first portion of the redundant word lines and the second portion of the redundant word lines.

Taking the memory device 200 as an example, the order from bottom to top is: ground selection lines GSL0~GSL2, redundant word lines DWLB0~DWLB2, word lines WL0~WLN, redundant word lines DWLT0~DWLT2 and string select line SSL0~SSL2. That is, the ground select line GSL0 is at the bottom and the string select line SSL2 is at the top.

Each of the memory blocks B0~BQ includes a plurality of switches SW and a plurality of memory strings SS. Each memory string SS includes a plurality of memory cells MC. The memory cells MC are located at the intersections of the word lines WL0 ~ WLN and the bit lines BL0 ~ BLP. In addition, each memory string SS includes a plurality of redundant memory cells DMC, and the redundant memory cells DMC are located at the intersections of the redundant word lines DWLB0~DWLB2 and the bit lines BL0~BLP, or Yes, the redundant memory cells DMC are located at the intersections of the redundant word lines DWLT0~DWLT2 and the bit lines BL0~BLP. In the same memory block, the memory cells MC and the redundant memory cells DMC coupled to the same bit line form a memory string SS. The memory cells MC and the redundant memory cells DMC are, for example, but not limited to, composed of MOSFET transistors, but it should be noted that this case is not limited thereto. The memory units MC and the redundant memory units DMC can be composed of other similar components, which is also within the spirit of this case.

The switches SW are respectively located at the intersections of the string selection lines SSL0~SSL2 and the bit lines BL0~BLP, or at the intersections of the ground selection lines GSL0~GSL2 and the bit lines BL0~BLP. When a relevant memory string SS is selected, the relevant switch SW will be turned on. The switches SW are, for example, but not limited to, composed of MOSFET transistors, but it should be noted that the present invention is not limited thereto. The switches SW can be composed of other similar components, which is also within the spirit of this case.

The plurality of unit cell currents flowing through the memory strings SS will flow through the common source line CSL to the relevant circuits at the back end to perform related operations.

In an embodiment of the present case, during programming, the redundant character lines on the string select lines SSL0~SSL2, the ground select lines GSL0~GSL2, the redundant word lines DWLB0~DWLB2, and the redundant word lines DWLT0~DWLT2 are The threshold voltage programming conditions of the remaining memory cell DMC and/or the switches SW are as follows, but it should be understood that this is only for illustration and the present case is not limited thereto.

The threshold voltages of the switches SW of the string selection lines SSL0 ~ SSL2 and the ground selection lines GSL0 ~ GSL2 are programmed to have a first reference threshold voltage. In one embodiment of the present case, the first reference threshold voltage is, for example but not limited to, 2V.

The threshold voltages of the redundant memory cells DMC on the redundant word lines DWLB0 and DWLT2 are programmed to have a second reference threshold voltage, and the second reference threshold voltage is higher than the first reference threshold voltage. In one embodiment of the present case, the second reference threshold voltage is, for example but not limited to, 3V.

The threshold voltages of the redundant memory cells DMC on the redundant word lines DWLB1 and DWLT1 are programmed to have a third reference threshold voltage, and the third reference threshold voltage is higher than the second reference threshold voltage. In one embodiment of the present case, the third reference threshold voltage is, for example but not limited to, 4V.

The threshold voltages of the redundant memory cells DMC on the redundant word lines DWLB2 and DWLT0 are programmed to have a fourth reference threshold voltage, and the fourth reference threshold voltage is higher than the third reference threshold voltage. In one embodiment of the present case, the fourth reference threshold voltage is, for example but not limited to, 5V.

That is to say, in an embodiment of the present case, the critical voltages of the redundant memory unit cells DMC on the redundant word lines DWLB0~DWLB2 and DWLT0~DWLT2 are programmed to be along the first direction or the second direction. Gradually increase, where the first direction is, for example, from the string selection lines SSL0 ~ SSL2 to the word lines WL0 - WLN; the second direction is, for example, from the ground selection lines GSL0 ~ GSL2 to the word lines WL0 -WLN direction.

In one embodiment of this case, after the first read is completed, the pass voltage applied to the unselected word lines will decrease to a logic low level, which is between the high threshold voltage redundant memory cell (located in the redundant The area between the remaining word lines DWLT0 and DWLB2 (that is, the memory cells MC of the word lines WL0 ~ WLN) will be able to be read between the first read and the second read. Establish a downward coupling environment during idle time.

For convenience of explanation, N=47 is used as an example here, but it should be noted that this case is not limited to this. For example, in the above example, the memory cells on the word lines at certain locations (here, word lines WL10 and WL30 are taken as examples, but it is understood that this case is not limited thereto) will have high critical voltages. The memory cells on the word lines at other positions (here, word lines WL20 and WL40 are taken as examples, but it is understood that this case is not limited thereto) will have low critical voltages.

In the conventional technology, after the first reading is completed, the pass voltage of the unselected word line drops to a logic low potential (for example, drops to the ground potential). As a result, the memory unit cell on the word line WL20 (with a low threshold voltage) will be in the downward coupling region formed by word lines WL10 and WL30, because the word lines The memory cells on WL20 (with low threshold voltage) are between the high threshold voltage memory cells (ie, the memory cells on word lines WL10 and WL30). However, the memory unit cell (having a low threshold voltage) on word line WL40 is not in the downward coupling interval formed by word lines WL10 and WL30. This is because in the conventional technology, the SSL side and the GSL side The switches usually have low threshold voltage. Therefore, in the conventional technology, the memory unit cell (having a low critical voltage) on the word line WL40 is not in the downward coupling range, and it is difficult to maintain the memory string in the strong inversion state, so it temporarily reads errors. The situation is more serious.

On the contrary, in one embodiment of the present case, after the first read is completed, the pass voltage of the unselected word line drops to a logic low potential (for example, drops to the ground potential). As a result, the pass voltage on the word line WL20 The memory cell (having a low threshold voltage) will be in the downward coupling region formed by word lines WL10 and WL30, and the memory cell (having a low threshold voltage) on word line WL40 will be in a The downward coupling section formed by word line WL30 and redundant word lines DWLT0-DWLT2. Therefore, in this embodiment, it is easier to maintain the memory string in the strong inversion state, so temporary read errors can be effectively suppressed.

In one embodiment of the present case, a high threshold voltage redundant memory cell (DMC) is used to establish down coupling conditions during the idle time between the first read and the second read. and environment.

In one embodiment of this case, downward coupling means that after the read operation is completed, if there are high critical voltage redundant memory cells around (such as above or below) the memory cell, then when the pass voltage Vpass down to 0V, the high Those memory cells in the range of critical voltage memory cells will enter downward coupling. When there is downward coupling, electrons in the memory string channel can be temporarily trapped, allowing the memory unit cell to remain in a strong inversion state for a long time. The advantage of this is to reduce the de-trapping behavior of the grain boundary trap in the poly channel of the memory unit cell, and try to keep the memory unit cell in the crystal The trapping status of the particle boundary trap. To reduce the risk of trap loss behavior is to reduce the critical voltage (Vt) change when reading again (next time). In the next reading operation, the correct value can be read. When reading the current, there will be no problem in interpreting the critical voltage (Vt), thus achieving the purpose of improving temporary reading errors.

In one embodiment of this case, during the idle time between the first read and the second read, a redundant memory with a higher threshold voltage (Vt=5V) on each of the GSL side and the SSL side is used. The bulk unit cell maintains the memory string in a strong inversion state through downward coupling, delaying the occurrence of trap loss behavior in grain boundary traps in the polycrystalline silicon channels of the memory unit cell.

In an embodiment of the present case, a gradually increasing critical voltage distribution of the redundant memory unit cells is established on a plurality of redundant memory unit cells on the GSL side and the SSL side. This can reduce the band-to-band leakage current near the high critical voltage (Vt=5V) redundant memory cell, and can also extend the maintenance time of the memory string in the strong inversion state. This further delays the occurrence of trap loss behavior in grain boundary traps in memory cell polycrystalline silicon channels.

In an embodiment of this case, without additional circuit area cost, it can be Effectively suppresses temporary read errors.

Figure 3 shows the channel voltage diagram of an embodiment of the present invention and the conventional technology. The horizontal axis in Figure 3 represents the position of the signal line, the leftmost position represents the ground selection line GSL0 at the bottom, and the rightmost position represents the string selection line SSL2 at the top. The vertical axis of Figure 3 represents the channel voltage. Curve L31 represents, in one embodiment of the present case, the channel voltage measured at each signal line position at the end of the first reading operation; curve L32 represents, in the conventional technology, at the end of the first reading operation , the channel voltage measured at each signal line position. In Figure 3, the memories on the ground select lines GSL0~GSL2, redundant word lines DWLB0~DWLB2, word lines WL0~WLN, redundant word lines DWLT0~DWLT2 and string select lines SSL0~SSL21 The critical voltage distribution of the unit cell MC and/or the redundant memory unit cell DMC is as described above.

Comparing the curves L31 and L32, it can be seen that in an embodiment of the present case, by establishing a gradually increasing critical voltage distribution of the redundant memory unit cells on the GSL side and the SSL side, the high critical voltage can be reduced. Voltage redundancy creates a channel voltage difference near the memory unit cell to reduce band leakage current and prolong the maintenance time of the memory series in the strong inversion state, thereby reducing the trap loss of grain boundary traps in the polycrystalline silicon channel of the memory unit cell. The behavior is further delayed, thereby reducing the critical voltage (Vt) change of the memory cell and improving temporary read errors.

Figure 4A shows the reading waveform diagrams of the first reading and the second reading in an embodiment of the present invention. The idle time between the first read and the second read can be 10μs or 100μs or 1ms or 10ms or 100ms or 1s or 10s or 100s or 1000s etc. As shown in Figure 4A, the read voltage Vread is related to the critical The voltages Vt are all 1.5V, the drain voltage Vd is 0.6V, and the pass voltage Vpass is 8V. It should be noted that this is just for illustration, and this case is not limited thereto.

Figure 4B shows a comparison of the idle time (between the first read and the second read) at the word line WL40 versus the second read current between an embodiment of the present invention and the conventional technology, and Figure 4C The figure shows a comparison of the idle time (between the first read and the second read) at the word line WL20 versus the second read current in an embodiment of the present invention and the conventional technology.

As shown in Figure 4B and Figure 4C, regardless of the idle time, the second reading current of the embodiment of the present case is significantly lower than the second reading current of the conventional technology 1 and the conventional technology 2. The higher The second read current will correspond to a lower threshold voltage (Vt), which is prone to temporary read errors. Therefore, an embodiment of the present case can effectively suppress temporary read errors. Here, in the prior art 1, during programming, the critical voltages of the redundant memory cells DMC of the redundant word lines DWLB0~DWLB2 and the redundant word lines DWLT0~DWLT2 are programmed to have, For example, it is 0V. In prior art 2, during programming, the critical voltages of the redundant memory cells DMC of the redundant word lines DWLB2 and DWLT0 are programmed to have, for example, 5V, and the redundant word lines DWLB0~ The critical voltages of the redundant memory cells DMC of DWLB1 and redundant word lines DWLT1 ~ DWLT2 are programmed to have, for example, 0V.

Figure 5 shows a flow chart of a memory device operating method according to another embodiment of the present invention. As shown in Figure 5, the memory device operation method includes: during the programming operation, programming a plurality of the string selection lines and the ground selection lines. A plurality of threshold voltages of switches to have a first reference threshold voltage; and a plurality of threshold voltages of a plurality of redundant memory unit cells on the redundant word lines are programmed to be along a first direction or a second The direction is gradually increasing and the critical voltages of the redundant memory unit cells are higher than the first reference critical voltage, wherein the first direction is from the string select lines to the word lines, and the third Two directions are from the ground select lines to the word lines (510).

An embodiment of the present invention can be applied to polycrystalline silicon channel three-dimensional memory devices, such as but not limited to 3D NAND memory devices, 3D NOR memory devices, etc., to improve temporary read errors.

In summary, although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the appended patent application scope.

510: Steps

Claims (10)

An operating method of a memory device. The memory device includes a plurality of ground selection lines, a plurality of string selection lines, a plurality of character lines, and a plurality of redundant character lines. One of the redundant character lines is the first A portion is close to the string select lines, a second portion of one of the redundant word lines is close to the ground select lines, and the word lines are between the first portion of the redundant word lines and Between the second portions of the redundant word lines, the operating method of the memory device includes: during programming operation, programming a plurality of switches on the string select lines and the ground select lines. The threshold voltage has a first reference threshold voltage; and the threshold voltages of the plurality of redundant memory unit cells on the redundant word lines are programmed to be gradually along a first direction or a second direction. increase and the threshold voltages of the redundant memory unit cells are higher than the first reference threshold voltage, wherein the first direction is from the string select lines to the word lines, and the second direction is from The ground select lines go to the character lines. The operating method of the memory device as claimed in claim 1, wherein in the first direction, the critical values of the redundant memory unit cells on the first part of the redundant word lines are The voltage is programmed to gradually increase along the first direction and is higher than the first reference threshold voltage. The operating method of the memory device according to claim 2, wherein, The first part of the redundant word lines includes at least a first redundant word line, a second redundant word line and a third redundant word line. The first redundant word line The threshold voltages of the redundant memory cells adjacent to the string select lines; the first redundant word line are programmed to a second reference threshold voltage, and the second reference threshold voltage is higher than The first reference threshold voltage; the threshold voltages of the redundant memory cells on the second redundant word line are programmed to a third reference threshold voltage, and the third reference threshold voltage is higher than the third reference threshold voltage. two reference threshold voltages; and the threshold voltages of the redundant memory cells on the third redundant word line are programmed to a fourth reference threshold voltage, the fourth reference threshold voltage being higher than the third Reference critical voltage. The operating method of the memory device as claimed in claim 3, wherein in the second direction, the critical values of the redundant memory unit cells on the second part of the redundant word lines are The voltage is programmed to gradually increase along the second direction and is higher than the first reference threshold voltage. The operating method of the memory device according to claim 4, wherein the second part of the redundant word lines includes at least a fourth redundant word line, a fifth redundant word line and a The sixth redundant word line, the fourth redundant word line is adjacent to the ground selection lines; the critical voltages of the redundant memory cells on the fourth redundant word line are programmed is the second reference critical voltage; The threshold voltages of the redundant memory cells on the fifth redundant word line are programmed to the third reference threshold voltage; and the redundant memory cells on the sixth redundant word line The critical voltages of the cells are programmed as the fourth reference critical voltage. A memory device includes: a plurality of bit lines; a plurality of ground selection lines; a plurality of first switches located at the intersections of the bit lines and the ground selection lines; a plurality of string selection lines; a plurality of second switches switches are located at the intersections of the bit lines and the string selection lines; a plurality of word lines, a plurality of memory unit cells are located at the intersections of the bit lines and the word lines; and a plurality of redundancy lines Word lines, a plurality of redundant memory unit cells are located at the intersections of the bit lines and the redundant word lines; wherein, a first part of the redundant word lines is close to the string selection lines, a second portion of one of the redundant word lines is close to the ground selection lines, and the word lines are between the first portion of the redundant word lines and the redundant word lines between the second part, the plurality of threshold voltages of the first switches and the second switches on the string selection lines and the ground selection lines are programmed to have a first reference threshold voltage, A plurality of threshold voltages of the redundant memory unit cells of the redundant word lines are programmed to gradually increase along a first direction or a second direction, and the threshold voltages of the redundant memory unit cells The threshold voltages are higher than the first reference threshold voltage, wherein the first direction is from the string selection lines to the word lines, and the second direction is from the ground selection lines to the word lines. . The memory device of claim 6, wherein in the first direction, the critical voltages of the redundant memory unit cells of the first portion of the redundant word lines are programmed is gradually increasing along the first direction and is higher than the first reference threshold voltage. The memory device of claim 7, wherein the first part of the redundant word lines includes at least a first redundant word line, a second redundant word line and a third redundant word line. The first redundant word line is adjacent to the string selection lines; the critical voltages of the redundant memory cells on the first redundant word line are programmed to a first Two reference threshold voltages, the second reference threshold voltage is higher than the first reference threshold voltage; the threshold voltages of the redundant memory unit cells on the second redundant word line are programmed to a third reference a threshold voltage, the third reference threshold voltage is higher than the second reference threshold voltage; and the threshold voltages of the redundant memory cells on the third redundant word line are programmed to a fourth reference threshold voltage, the fourth reference threshold voltage is higher than the third reference threshold voltage. The memory device of claim 8, wherein in the second direction, the critical voltages of the redundant memory unit cells on the second portion of the redundant word lines are programmed becomes gradually increasing along the second direction and is higher than the first reference threshold voltage. The memory device of claim 9, wherein the second part of the redundant word lines includes at least a fourth redundant word line, a fifth redundant word line and a sixth redundant word line. The fourth redundant word line is adjacent to the ground selection lines; the critical voltages of the redundant memory cells on the fourth redundant word line are programmed to be two reference threshold voltages; the threshold voltages of the redundant memory unit cells on the fifth redundant word line are programmed to the third reference threshold voltage; and the threshold voltages of the redundant memory cells on the sixth redundant word line The threshold voltages of the redundant memory cells are programmed to the fourth reference threshold voltage.

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