TWI517164B - Memory device, method for producing program bias pulse for the memory device and integrated circuit including the memory device - Google Patents

Description

Memory device, method for generating a programmed bias pulse in the memory device, and integrated circuit including the memory device

Embodiments of the present invention relate to flash memory technology, and more particularly to flash memory technology that is suitable for use in high density in blocks.

Flash memory is one of the non-volatile integrated circuit memory technologies. Traditional flash memory uses floating gate memory cells. Another type of flash memory cell is called a charge trapping memory cell, which uses a dielectric charge trapping layer instead of a floating gate.

A typical charge storage memory cell includes a field effect transistor (FET) structure including a source and a drain separated by a channel, and a gate separated from the channel by a charge storage structure, wherein the charge storage structure comprises A tunneling dielectric layer, a charge storage layer (floating gate or dielectric layer), and a barrier dielectric layer. Earlier conventional designs, such as SONOS devices, in which the source, drain and channel are formed on the germanium substrate (S), the tunneling dielectric layer is over the germanium oxide (O), and the charge storage layer is formed of tantalum nitride. (N), the barrier dielectric layer is formed of ruthenium oxide (O), and the gate is polycrystalline germanium (S).

The data stored in a flash memory device is made by controlling the amount of charge trapped in its charge trapping structure. The amount of charge stored is set to the threshold voltage of the memory cell in a flash memory device, which allows the data therein to be read.

How to accurately control the amount of charge stored in a target memory cell during stylization operations when the target threshold voltage specification in a low voltage application becomes more tight, and in applications where multiple bits are stored in each memory cell It becomes very difficult, and at the same time, it is necessary to prevent the charge stored in the memory cell from interfering with other memory cells during stylization and erasing operations.

Therefore, there is a need to provide a new flash memory technology that provides better control of the charge stored in the flash memory.

Embodiments of the present invention disclose an integrated circuit including a flash memory that is configured to generate a programmed bias pulse using a controller that biases the bit lines and strings in a first condition a column selection line; a word line coupled to a target memory cell to a first voltage level, wherein the bit line and the string selection line are in the first case; and thereafter, the stylized partial And biasing the bit lines and the string selection lines in a second case in the pulse pulse; and setting the word lines coupled to the target memory cells to a second voltage level, when the bit lines And the string selection line. In the second case, the second voltage level is higher than the first voltage level.

Embodiments of the present invention disclose a low voltage operation memory device configuration including a plurality of memory cell strings arranged in series in a semiconductor body, for example, a reverse gate series that can be applied in an anti-gate array. The plurality of word lines are coupled to the corresponding memory cells. a control circuit coupled to the plurality of word lines and the semiconductor body to program a selected target memory cell, comprising applying a stylized bias pulse having at least one cyclic step profile, including an initial stage of stylized voltage and The pass voltage is set to have an initial level, and a subsequent portion of the stylized voltage and selectively boosts the pass voltage to the second level. In the initial stage, the bit line voltage and the series select line voltage are used to turn on the serial selection switch, and the serial selection switch is turned off in the subsequent stage.

A memory device as described herein is configured to reduce the programmed voltage to a first size less than the programmed size before applying the suppression bit line voltage to turn off the series selection switch of the unselected series And after applying the suppression bit line voltage to turn off the string selection switch of the unselected string, the stylized voltage rises to the programmed size.

The objects according to the present invention are provided in the following description of the embodiments in conjunction with the drawings.

Descriptions of embodiments of the present invention are described in conjunction with Figures 1 through 18.

Figures 1A and 1B respectively show a cross-sectional view of a plurality of charge-trapping flash memory cells connected in series to form an anti-gate sequence, and a bias diagram for performing FN tunneling stylization, which is in the inverse gate flash memory. Typical operations in the architecture. FIG. 1A shows a bias diagram of a reverse gate sequence including a target memory cell on a selected bit line, and FIG. 1B shows a bias diagram of a reverse gate sequence on an unselected bit line. . A technique for implementing a backlash flash memory using an energy gap engineering SONOS charge trapping technique can be found in U.S. Patent No. 7,315,474, issued toU.S. The reverse gate series can be implemented using a number of different configurations, including fin field discharge crystal technology, shallow trench isolation technology, vertical reverse gate technology, and the like. For an example of certain vertical reversal gate structures, see European Patent No. EP 2048709 to Kim et al., entitled "Non-volatile memory device, method of operating same and method of fabricating the same."

Referring to FIG. 1A, the memory cell is formed in a semiconductor body 10. For n-channel memory cells, semiconductor body 10 can be an isolated p-well within a deeper n-well of a semiconductor wafer. Alternatively, the semiconductor body 10 can be isolated by an insulating layer or other similar means.

The plurality of flash memory cells can be arranged in a series of bit line directions that are orthogonal to the direction of the word line. The word lines 22-27 extend through a number of parallel anti-gate trains. Nodes 12-18 are n-type regions (for n-channel devices) in the semiconductor body and serve as source/drain regions for the memory cells. A first switch formed by a MOS transistor (e.g., a first switching transistor) has a gate in the ground select line GSL 21 coupled to the first word line 22 (WL0 in Figure 1C) The corresponding memory cell is formed between one of the contacts 11 formed by the n-type region in the semiconductor body 10. This contact 11 is connected to the common source line CS 30. A second switch formed by a MOS transistor (e.g., a second switching transistor) has a gate in the string select line SSL 28 coupled to the corresponding memory cell and semiconductor by the last word line 27. The n-type region in the body 10 is formed between one of the contacts 19. This contact 19 is connected to a sensing node such as bit line BL 31. This bit line BL 31 is an example of a "sensing node" of the noun used herein. The first and second switching switches in this exemplary embodiment are MOS transistors, in this example thyristor dielectric layers 7 and 8.

In this illustration, there are six memory cells in this series for the sake of simplicity. In a typical configuration, an inverse gate sequence can contain 16, 32 or more memory bank arrangements. The word lines 22-27 corresponding to these memory cells have a charge trapping structure 9 between the word lines and the channel regions in the semiconductor body 10. The charge trapping structure 9 in this memory cell can be a dielectric charge trapping structure, a floating gate charge trapping structure, or other suitable flash memory structure suitable for programming using the techniques described herein. In addition, no junctions have been developed in embodiments that are inverse gate flash structures in which nodes 13-17, and optionally nodes 12 and 18, may be omitted from this configuration.

Figure 1A shows a cross-sectional view of a conventional technique NAND architecture flash memory in which FN tunneling is induced to program bias the memory cells (target memory cells) corresponding to word lines 24. Schematic, which uses a typical incremental step pulse stylization (ISSP) operation. According to the bias voltage shown here, the ground select line GSL is biased to approximately 0V and the common source line is grounded such that the first switch corresponding to the ground select line GSL 21 is off and the tandem select line SSL bias To about V _CC and the selected bit line is also grounded, so that the second switch corresponding to the serial select line SSL 28 is turned on. Under these conditions, the semiconductor body in region 33 associated with the gate series is precharged to about 0V. The selected word line 24 is biased to a high voltage stylized class V-PGM, which in some embodiments can be on the order of 20-22 volts. Selecting such a high voltage is sufficient to cause hot electrons in the body 10 to tunnel into the charge trapping structure 9 of the selected memory cell. At the same time, the unselected word lines 22, 23, 25-27 are biased to a turn-on voltage V-PASS which is less than a V-PGM that is less than a stylized voltage that can suppress unselected cells in the series. As a result, electrons tunnel into the charge trapping structure of the selected memory cell during the stylized pulse.

FIG. 1B is a cross-sectional view showing a conventional flash memory (NAND) architecture flash memory, which shares the bias of the uncharacterized bit lines of the gate lines 22 to 27 and the gate series of the gate array. schematic diagram. As can be seen from the figure, all word lines, ground selection lines GSL and serial selection lines SSL are the same as those shown in FIG. 1A. Similarly, the common source line 30 is also grounded. However, the unselected bit lines are biased to a level of approximately V _CC . This will turn off the second switch, which corresponds to the string select line SSL, and decouples the semiconductor body in region 35 from the unselected bit line BL32. As a result, the semiconductor body in region 35 will self-pressurize by the capacitive coupling generated by the voltage applied to word lines 22-27, which can prevent the charge trapping structure in the memory cells of the unselected inverse gate series from being sufficiently disturbed. The electric field is formed.

Incremental step pulse programming (ISSP) operation is a commonly known technique, see Suh et al., "A 3.3V 32Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme", IEEE International Solid-state Circuits Conference, 1995, Pp 128-130. According to this basic technique, in order to program the target memory cell to achieve its threshold voltage within a range representing a particular data value, a series of stylization/verification steps are performed, each of the stylized pulses in the series being compared to the previous One pulse is incremented by a fixed value. Between each pulse, a verify potential is applied to the word line of the memory cell, and the data is sensed to determine if the threshold voltage of the memory cell exceeds the stylized verification level. This stylized verification class is set to the lower edge of the range that is suitable for sensing the value of this target memory cell data.

Figure 2 shows a dynamic diagram of an incremental step pulse stylization (ISSP) operation showing the threshold voltage distribution 50 of the initial pulse phase of the incremental step pulse programming (ISSP) series and the threshold voltage distribution 52 of the final stage. Among the traces 50 of the threshold voltage distribution, most of the memory cells are below the stylized verification threshold voltage PV, including a memory cell having a threshold voltage 51 which is very close to the stylized verification threshold voltage PV. As shown in the figure, the memory cells in the slashed area pass the verification but do not perform subsequent stylized pulses. However, these memory cells below the stylized verification threshold voltage PV will be applied one or more additional stylized pulses. The final distribution 52 of the threshold voltage is wide enough to include a threshold voltage at 55, which is corresponding to a subsequent stylized pulse and then increases by a threshold voltage that remains below the upper edge of the target range 52. As shown in the figure, the distribution 52 of the threshold voltage is relatively wide enough to accommodate the increase from point 51 to point 55.

The characteristics of a typical incremental step pulse programming (ISSP) technique are shown in Figure 3, which is a plot of threshold voltage versus programmed pulse height in the Incremental Step Pulse Stylized (ISSP) series. In general, the stylized potential added to subsequent pulses is set such that the slope of track 60 is approximately one, and that the number of offsets of the threshold voltage in each step is an equation of slope and initial threshold voltage. The slope of the incremental step pulse stylization (ISSP) is used to indicate the change in the threshold voltage at each step.

Figure 4 shows the limitations of an improved incremental step-pulse stylization (ISSP) technique, described in Park et al., "A 7MB/s 64Gb 3-Bit/Cell DDR NAND Flash Memory in 20 nm-Node Technology" IEEE International Solid-state Circuits Conference, 2011, pp 212-213. Figure 4 shows a trajectory 66 of a typical incremental step pulse stylized (ISSP) series showing the characteristics of a fixed slope. According to a paper by Park et al., when the memory cell is programmed over a temporary stylized verification class, the bit line bias is slightly increased when the next stylized pulse is applied to the target memory cell until the final stylized verification is reached. class. The tunneling is suppressed as such, and the slope of the incremental step pulse stylization (ISSP) in region 65 is reduced. See Figure 11.8.3 of the Park et al. paper, in which case this stylized distribution can be narrowed. Although the slope of region 65 is reduced, the effect of increasing the bit line bias occurs only in a few pulses, after which the slope is again increased. Such a small range of improved incremental step pulse stylization (ISSP) slopes limits the effectiveness of the paper by Park et al.

Figure 5 is a schematic cross-sectional view showing a reverse NAND string showing the bias voltages for sharing the unselected bit lines of the word lines 22 to 27 in the selected series, and wherein the target is The memory cell 500 is coupled to a word line adjacent to the ground selection switching transistor 501. This condition can lead to the gate induced threshold leakage current (GIDL) described by Lee et al. in the paper "A New Programming Disturbance Phenomenon In NAND Flash Memory by Source/Drain Hot Electrons Generated by GIDL Current". As described by Lee et al. in the paper, applying a stylized pulse V _Pgm close to the ground select line can create a relatively high electric field between the target memory cell 500 and the ground select switch transistor 501. The gate-induced drain leakage current at the gate of the switching transistor results in the formation of an electron-hole pair. Because of the high electric field, the energy obtained by the electrons is sufficient to cause thermal electron tunneling in the memory cells that receive the unselected lines of the stylized potential, thus interfering with the charge stored in the unselected memory cells.

Figure 6 shows the simulation results for the channel voltages in the unselected series. In the diagram of Fig. 6, the word line adjacent to the ground selection line is on the right side (as opposed to the arrangement in Fig. 5). It can be seen from the figure that because the channel potential of the region boost cannot be shared by adjacent memory cells, a very high partial region boosting situation is caused. This may be due to the fact that the source/drain junction 505 is completely depleted due to the high bias voltage; or because the adjacent memory cells are programmed to the high level state because the insufficient gate is overdriven.

Figure 7 shows a schematic diagram of a modified incremental stepping pulsed series of programmed voltages, pass voltages, series select line voltages, and bit line voltages. This improved incremental step pulse stylized series has a reduced slope. . These voltages are placed separately for clarity of illustration. At the beginning of each pulse (time t0), its voltage level is approximately ground in this example. Trace 100 is a stylized voltage (V-PGM) pulse applied to the selected memory cell word line. Trace 101 is a pass voltage (V-PASS) pulse applied to the unselected memory cell word line. Trace 102 is a voltage pulse (V-SSL) applied to the tandem selection line of the target string. Trace 103 is the voltage pulse (V-BL) applied to the bit line of the target string when this is a programmed pulse. In this example, the common source line and the ground selection line GSL are set to be grounded such that the switch corresponding to the ground selection line GSL 21 is turned off, and the selected and unselected series are decoupled from the common source line. . One of the improved incremental step pulse stylized series is given a programmed bias pulse, and at time t0, the tracks 100, 101, 102, 103 are all at ground level. At time t0, the voltage of the string select line SSL increases to V _SS11 , which typically reaches V _cc at approximately time t1. At time t1, both tracks 100, 101 are incremented to their respective first levels 111, 121, respectively. The level 111 is set to a voltage that is dependent on the number of cycles executed in the incremental step pulsed series, approximately between 15V and 22V. The level 121 is set to a voltage high enough to keep the unselected transistor on but low enough to suppress unprogrammed memory cells, typically between about 5V and 10V. The voltage at the string select line SSL is shown at track 102 remaining at _Vcc until time t2. Therefore, the serial selection switch is turned on between time t0 and t1 until at least time t2, the semiconductor body of the selected series remains connected to the ground bit line and remains at the ground potential. The condition of the initial portion of the programmed bias pulse INIT-PGM in Figure 7 is the basic condition imposed by the FN tunneling induced by the incremental step-pulse stylized series. Interposed in time between times t1 and t2 should be sufficient to V _PASS1 and V _pgm1 line voltage level in a stable character. In the initial portion of the pulse, the FN stylization of the selected memory cell is weaker because the voltage level matched to the pulse of the previously normal incremental step pulse is selected, and thereafter the previous pulse is applied. To increase the threshold voltage. The stylization of the initial portion of the bias pulse is less sufficient as a result of applying a previous pulse resulting in a higher threshold voltage.

At time t2, the voltage of the tandem select line SSL drops to an intermediate level at time t3. At approximately time t2, the voltage of the selected bit line increases, reaching the _Vb12 level at approximately t3. The series selection line SSL and the voltage change of the selected bit line cause the serial selection switch to be turned off or reduce its conductivity such that the current flow of the selected series is reduced or turned off at approximately t3. Other voltage levels can also be applied to the tandem select line SSL and the selected bit line to achieve the same result. The difference between V _SS12 and V _b12 can be set to be smaller than the threshold voltage of the tandem selection transistor (V _SS12 - V _b12 <Vt) to achieve such a result. At about time t3, the turn-on voltage applied to the unselected memory cells is increased by a ΔV _pass to the level 122. Moreover, at approximately time t3, the stylized voltage applied to the selected memory cell is increased by a ΔV _prog to a level 112 to begin the MODULATED-PGM phase of the stylized pulse. Because the ground selection switch and the series selection switch are both turned off or nearly turned off at time t3, the boosted turn-on voltage and the stylized voltage are electrically coupled to the channel due to ΔV _pass and ΔV _prog , followed by the stylized pulse. Partly boosts the equivalent channel voltage and slows down the FN tunneling current. This channel potential is boosted by β ₀ * ΔV _pass , where β ₀ is less than 1, and is thus determined by the electrical coupling of the memory cells. The voltage drop between the control gate and the channel is approximately (1-β ₀ ) ΔV _prog , if ΔV _pass = ΔV _prog . During this time interval, FN stylization continues, but becomes less efficient and changes the slope of the incremental step pulse stylized (ISSP) series.

At the end of this stylized bias pulse at time t4, both the trace 100 of the programmed voltage and the trace 101 of the turn-on voltage return to ground. Similarly, the voltage of the tandem select line SSL and the selected bit line also returns to ground at or about t4. In one experiment, the time between t0 and t2 was about 1 microsecond, the time between t2 and t4 was about 9 microseconds, and the pulse width of a standard incremental step pulse stylized (ISSP) series was about It is 10 microseconds. Of course, other time intervals can be used to suit a particular application circuit.

Therefore, the application of the programmed bias pulse using the controller in the integrated circuit shown in FIG. 17 is described as follows: biasing the bit line and the string selection line in a first case (for example, the conditions of time t1 to t2) Setting a word line coupled to a target memory cell to a first voltage level (eg, V _pgm1 ), and the bit line and the string selection line are in the first case; thereafter, in a second case a bias bit line and a string select line (eg, a condition of time t3 to t4); and setting a word line coupled to a target memory cell to a second voltage level (eg, V _pgm2 ), and the bit line And the string selection line. In the second case, the second voltage level is higher than the first voltage level.

In such an embodiment, the first case includes setting the bit line voltage V _bl1 to a selected bit line and the voltage V _ssl1 to a string selection line of the selected string to couple the bit line to the string selection line. And the second case includes setting the bit line voltage V _bl2 to a selected bit line and the voltage V _ssl2 to a string selection line of the selected string to decouple the bit line from the string selection line. An initial programmed level is set in the first case and a boost programming level is set in the second case.

In the example shown in Fig. 7, ΔV _pass = ΔV _prog . However, the relationship between the channel voltage change ΔV _ch and the initial channel voltage V _chini can be represented by the following equation (where N is the number of word lines in this series):

ΔV _ch ～V _chini +N-1/N*β*ΔV _pass +1/N*β*ΔV _prog

Therefore, the channel boost is mainly determined by ΔV _pass . If you want to increase the channel boost and thus further reduce the incremental step pulse programming (ISSP) series slope, you can increase the value of ΔV _pass . For example, ΔV _pass can be increased to twice the ΔV _prog .

Figure 8 shows a plot of the relationship between the threshold voltage and the number of stylized pulses achieved by applying a pulse similar to that of Figure 7, which is compared to a conventional incremental step pulsed programmed pulse. The characteristic of a conventional incremental step pulse stylized pulse is that it has a slope as shown by trace 130 in the illustration. Trace 131 is a slope that is achieved using a similarly stepped stylized bias pulse as in Figure 7, which is smaller than trace 130 to induce less threshold voltage increase. Trace 132 shows the slope achieved by the suppression bias applied to the unselected series. As shown, in a conventional incremental step-pulse stylized pulse train, the bit line voltage is maintained at approximately a fixed value. In the series of incrementally stepped programmable bias pulses according to Figure 7, the bit line voltage is grounded at the initial portion of this pulse, and then the subsequent portion of the pulse is slightly increased while the serial select line SSL voltage is simultaneously After V _{cc is} slightly reduced, the serial select line SSL switch is quickly turned off with a small voltage oscillation. When suppressing voltage application, the bit line voltage is set to a high voltage of approximately V _cc at the beginning, and is capacitively and unselected in series due to the effect of the on-voltage pulse and the full size of the programmed voltage. coupling.

Figure 9 shows an operational diagram of a modified two-stage incremental step pulse stylized series using the techniques described herein. In the first phase, a series of pulses are applied using a bias arrangement similar to the conventional incremental stepping pulsed series, in which the bit line is maintained at approximately ground potential, the string select line is driven by SSL to approximately V _cc , The word line of the selected memory cell is driven to pass the voltage level, and the word line of the selected memory cell is driven to pass the stylized potential. Figure 9 shows three stylized bias pulses in the first phase, including pulse 200, pulse 201, and pulse 202. After pulse 200, pulse 201, and pulse 202, a stylized verification loop represented by 200a, 201a, 202a is applied. Each of the verify potentials (levels 206, 208, 210) used in the stylized verify cycle after the three pulses is approximately equal to the pass voltage level V _PASS . The three pulsed stylized potentials are stepwise increased such that pulse 200 has a programmed potential level 205, pulse 201 has a programmed potential level 207, and pulse 202 has a programmed potential level 209. The slope of the incremental stepped stylized series is approximately constant as the programmed pulse applied in the first stage, as shown in the initial portion of trace 130 in FIG.

In the second phase of the stylization cycle, it is the start of the self-programming bias pulse 203, which is an adjusted stylized bias similar to that described in FIG. At pulse 203, the initial portion of the bit line voltage is grounded and then slightly increased in subsequent portions of this pulse. The initial portion of the pulse selects the line select line SSL voltage to be approximately V _cc and then a slight decrease in subsequent portions of this pulse. The initial portion of this pulse is increased by the voltage to the first level 220 and then boosted to the level 222 by subsequent portions of this pulse. The level 220 can be the same as the verify voltage level 210 used last in the first stage. Also. The programmed voltage at pulse 203 is increased to the first level 211 for the initial portion of this pulse, and then boosted to level 215 for subsequent portions of this pulse. In this example, the level 211 can be the same as the programmed voltage 209 used by the first stage last pulse 202 of the incremental step pulse stylized series. The voltage level from the initial voltage portion of the pulse to the subsequent portion is preferably aligned in time as shown. As described above, the first pulse of the second phase will follow the stylized verification loop 203a. If the memory cell does not pass this verification cycle, another pulse is applied.

Figure 9 also shows the second pulse 204 in the second phase of this stylized cycle. In pulse 204, the bit line voltage and the string select line SSL voltage are generally adjusted as described in FIG. The pass voltage of the unselected word line is boosted to the level 221 for the initial portion of this pulse, and then boosted to the level 223 for subsequent portions of this pulse. In this example, the level 221 can be the same as the level 220 of the previous pulse. However, the pass voltage of the stylized bias pulse is increased to 223 in the subsequent portion relative to the pulse 203 self-alignment 221, and the amount of voltage increase is determined by this algorithm. Moreover, in pulse 204, the programmed voltage is boosted to the first level 212 at the initial portion of the pulse, and then boosted to the level 216 by subsequent portions of the pulse 204, the programmed voltage increase is determined by This algorithm is decided. In this example, the level 212 can be the same as the programmed voltage level 209 of the last pulse 202 of the first stage of the incremental step pulsed series. The amount of stylized voltage increase from the level 212 to the level 216 is greater than the amount of voltage increase from the level 211 of the first pulse 203 to the level 215. The voltage level from the initial voltage portion of the pulse to the subsequent portion is preferably aligned in time as shown. As described above, the first pulse of the second phase will follow the stylized verification loop 204a. If the memory cell does not pass this verification cycle, another pulse is applied. This program will repeat until the verification passes or the maximum number of retries has been performed.

Figure 9A shows a dynamic schematic of a modified incremental step pulse stylization (ISSP) operation based on a procedure similar to that in Figure 7. Figure 9A shows the threshold voltage distribution 250 when a stylized verification level (PV1) is applied after the programmed bias pulse of the first stage of the Improved Incremental Step Pulse Stylization (ISSP) series. Among the traces 250 of the threshold voltage distribution, some of the memory cells have a higher than the stylized verification threshold voltage PV1, and pass the first stage verification condition, and some of the memory cells have a lower than the stylized verification threshold voltage PV1. In addition, Figure 9A also shows a narrower distribution 251, which can be used to improve the final range of threshold voltages that occur during the second phase of the incremental step pulse programming (ISSP) series. The second phase of the Improved Stepping Pulse Styling (ISSP) series is to apply a final or target stylized stylized verification level (PV2). A memory cell that remains at a threshold voltage lower than the temporary stylized verification level (PV1) in the distribution 250 can be programmed in the first stage, and then can be programmed as a normal incremental step pulse as in the first option in FIG. The (ISSP) slope (track 130) grounds the voltage V-BL. A memory cell above the stylized verification threshold voltage PV1 but below the stylized verification threshold voltage PV2, such as point 252 at the high end of the distribution 250, performs the second phase of the modified incremental step pulse programming (ISSP) series. The incremental step pulse stylization (ISSP) slope can be reduced as described above. The final threshold voltage distribution 251 shows that it is narrower than the distribution 52 in Figure 2. This effect can be achieved in the second phase of the Improved Incremental Step Pulse Styling (ISSP) series, which operates at a lower incremental step pulse stylized (ISSP) slope such that when there is a threshold voltage close to point 252 The memory cell is less likely to reach a point 253 that increases its threshold voltage beyond the distal end of the distribution 251 when a pulse is applied in the second phase.

Figure 9B shows a dynamic schematic of another two-stage modified incremental step pulse stylization (ISSP) operation using the techniques described herein. In the first phase, a series of pulses are applied using a series of bias arrangements including stepped V-PASS and stepped V-VPM pulses, which have V-SSL level pulses, while the bit lines are maintained at approximately Potential.

Figure 9B shows three stylized bias pulses in a first phase, including pulse 300, pulse 301, and pulse 302. After each pulse 300, pulse 301, pulse 302, a stylized verification loop represented by 300a, 301a, 302a is applied. Each verification potential in the stylized verification loop after the three pulses is set to the temporary verification level PV1. The stylized potentials of the three pulses are stepwise increased, including the initial portion being at a certain level and the subsequent portions being gradually increased, such that the pulse 300 has a stylized potential stepped from the initial level 305 to the level 305' The pulse 301 has a stylized potential stepped from the initial level 307 to the level 307'. The pulse 302 has a stylized potential that is stepped from the initial level 309 to the level 309'. The initial levels of the voltages of the stylized potentials 305, 307, 309 can be equal in the figure. Similarly, the pass voltage applied in the first stage pulses 300, 301, 302 is also stepped, including the initial portion being at a certain level and the subsequent portion being gradually increased, so that the pulse 300 has a pass potential from the initial level. Bit 306 is stepped to level 306', pulse 301 has a pass potential from initial level 308 to level 308', and pulse 302 has a pass potential from initial level 310 to level 310'. The initial levels 305, 307, 309 of the voltage through the potential can be equal in the figure. In the pulses 300, 301, 302, the bit line voltage V-BL is set to, for example, the reference level 340 of the ground, and the serial selection gate is set to a constant value of, for example, Vcc in the pulse, so that the series Select the transistor to remain on. In the first phase, the stylized verification level applied in the stylized verification loops 300a, 301a, 302a can be set to the temporary level PV1, which is slightly lower than the target stylized verification level.

In the second phase of the stylization cycle, it is to begin the self-programming bias pulse 303, which is an adjusted stylized bias similar to that described in FIG. At pulse 303, the bit line voltage V-BL at the level 318 of the initial portion of this pulse is grounded, and then the subsequent portion of this pulse is slightly increased to 318'. The string select line SSL voltage at the initial portion of this pulse at level 316 is approximately V _cc and is subsequently slightly reduced to the level 316' for subsequent portions of this pulse. The initial portion of this pulse is increased by the voltage to a first level 312, and then boosted to a level 312' for subsequent portions of this pulse. The first level 312 can be the same as the verify voltage levels 306, 308, 310 used last in the first stage. Also. The programmed voltage at pulse 303 is increased to the first level 311 at the initial portion of this pulse, and then boosted to the level 311' for subsequent portions of this pulse. In this example, the level 311 can be the same as the programmed voltage 309 used by the first stage last pulse 302 of the incremental step pulse stylized series. The voltage level from the initial voltage portion of the pulse to the subsequent portion is preferably aligned in time as shown. As described above, the first pulse of the second phase will follow the stylized verification loop 303a. If the memory cell does not pass this verification cycle, another pulse is applied. In the second phase, the stylized verification level applied at the stylized verification loops 303a, 304a can be set to the target standard bit PV2.

Figure 9B also shows the second pulse 304 in the second phase of this stylized cycle. In pulse 304, the bit line voltage and the string select line SSL voltage are generally adjusted as described in FIG. The pass voltage of the unselected word line is first boosted to the level 314 by the initial portion of this pulse, and then boosted to the level 314' for subsequent portions of this pulse. In this example, the level 314 can be the same as the level 312 of the previous pulse. However, the pass voltage of the stylized bias pulse is increased to 314' from the subsequent portion 314 relative to the pulse 303, and the amount of voltage increase is determined by this algorithm. Moreover, in pulse 304, the programmed voltage is boosted to a first level 313 for the initial portion of the pulse, and then boosted to a level 313' for subsequent portions of the pulse 304, the programmed voltage increase is This algorithm determines. In this example, the level 313 can be the same as the programmed voltage level 309 of the last pulse 302 of the first stage of the incremental step pulsed series. The amount of stylized voltage increase from the level 313 to the level 313' is greater than the amount of voltage increase from the level 311 of the first pulse 303 to the level 311'. The voltage level from the initial voltage portion of the pulse to the subsequent portion is preferably aligned in time as shown. As described above, the first pulse of the second phase will follow the stylized verification loop 304a. If the memory cell does not pass this verification cycle, another pulse is applied. This program will repeat until the verification passes or the maximum number of retries has been performed.

Figure 10 shows a schematic diagram of the circuit layout of the two reverse gate series 181, 182. The two reverse gate series 181, 182 respectively select the transistor and the ground selection transistor via the tandem column and the respective bit line BL-. 1 and BL-2 are coupled to a common source line CS line 185. The bias voltage is shown to adjust the programmed bias voltage applied to the word line WL(i) corresponding to the target memory cell 180 in the gate string 181. The first switching transistor 191 receives a ground potential GND via the ground selection line GSL to decouple the reverse gate sequence from the grounded common selection line 185. The second switching transistor 192 is biased by an adjusted V-SSL pulse on the tandem select line SSL. The selected bit line BL-1 similarly receives an adjusted V-BL voltage. The other word lines WL(0) through WL(i-1) and WL(i+1) through WL(N-1) in the series receive an adjusted V-PASS voltage. The unselected bit line (eg, BL-2) is coupled to V _cc such that the unselected string is protected by self-boost without stylized interference.

Figure 11 is a plot of threshold voltage versus number of stylized pulses to show additional programmable and applied stylized bias pulses to adjust the incremental stepped pulsed series of pulses. The trajectory of a conventional incremental stepping pulsed series of pulses is shown as line 130 which is similar to that shown in FIG. The trajectory of the series of incrementally stepped pulsed pulsed pulses as described in FIG. 8 is shown as line 131, wherein all of the unselected word lines receive the boosted pass voltage pulse V-PASS. This slope can be set to an intermediate value of the trajectory 150 as shown in Fig. 11 by controlling the stepping of the unselected word line in the series by the voltage V-PASS bias. For example, some unselected word lines can receive a step-through voltage V-PASS bias pulse, such as pulses 121 and 122 in Figure 7, while others can receive no boost in subsequent portions of the pulse. Passing voltage. This result reduces the capacitive coupling of the channel and the programmed current level is between lines 130 and 131.

Figure 12 is a plot of threshold voltage versus number of stylized pulses to show additional programmable and applied stylized bias pulses to modify the incremental stepped pulsed series of pulses. The trajectory of a conventional incremental stepping pulsed series of pulses is shown as line 130 which is similar to that shown in FIG. The trajectory of the series of incrementally stepped pulsed pulsed pulses as described in FIG. 8 is shown as line 131, wherein all of the unselected word lines receive the boosted pass voltage pulse V-PASS. This slope can be further reduced to the trajectory 160 as shown in the figure by adjustment of other programmed bias pulses. In this example, the number of voltage boosts ΔV _PASS can be set to be larger than ΔV _Pgm , including 2 times ΔV _Prog in this example. This result can increase the capacitive coupling of the channel and the programmed current level is lower than line 131.

Figure 13 is a schematic diagram showing the circuit layout of the two opposite gate series 181, 182 similar to those of Figure 10, wherein the two reverse gate series 181, 182 are respectively selected via a series selection transistor and a ground selection transistor and respective The bit lines BL-1 and BL-2 are coupled to the common source line 185. The bias voltage is shown to adjust the programmed bias voltage applied to the word line WL(i) corresponding to the target memory cell 180 in the gate string 181. However, in this adjustment bias, the adjustment V*-PASS* pass voltage is applied only to the word lines WL(i+1) to WL(N-1), and the standard unboosted pass voltage is applied only to the characters. Lines WL(0) through WL(i-1), and the adjusted stylized voltage is applied to the target word line WL(i) as explained in FIG. This arrangement can be changed by, for example, setting an intermediate value trajectory 150 between the slope of the sequence of incremental stepped pulsed programmed pulses described in Figure 8 and the slope of the conventional incremental stepped pulsed series of pulses. The slope of the incremental stepping pulsed series of pulses is described in Figure 8.

Figure 14 shows that the modified stylized bias pulse can suppress the self-boosting potential of the partial region and prevent gate-induced drain leakage current (GIDL) interference caused by the conditions in Figures 5 and 6. In Fig. 14, the initial line voltage (UNSELECTED V-BL) 510 of the stylized bias pulse on the unselected line and the serial select line voltage (V-SSL) 509 on the serial select line SSL are displayed. section. In addition, the initial portion of the pass voltage (V-PASS) 511 on the unselected word line and the stylized voltage (V-PGM) 512 on the selected word line is also displayed. In order to suppress self-boosting of some areas, the leading edges of these voltages are adjusted. At time t0, the string select line voltage (V-SSL) applied to the serial select transistor to a level such as _Vcc is turned on to turn the switch on. The common source line and ground selection switch are set to block current flow, for example setting both to approximately 0V or ground. At time t1, the stylized potential transitions to the level 520, which may be, for example, approximately equal to the pass potential, for example 8V or other deficiency to induce the tunneling current of the target memory cell to the target memory. In the cell. At this time, because the bit line potential in this example is still maintained at ground, the channel of the unselected line remains at approximately ground level and is not boosted. At time t2, the programmed potential reaches the level 520. At time t3, in some cases, it coincides with time t2. After t3 or after, the programmed voltage V-PGM is stabilized at the level 520, and the unselected bit line voltage is converted to a suppression level of about V _CC . , which causes the tandem selection transistor on the unselected line to be turned off. In this interval, the selected bit line voltage is maintained at or near ground potential, and the tandem selection switch in the selected string is strongly turned on. In this example, the time between t1 and t3 can be approximately 1 to 2 microseconds. This period of time is long enough for the programmed voltage V-PGM to stabilize at level 520. At time t4, when the series selection transistor is turned off, the unselected bit line voltage is stabilized at its target standard. At time t5, the pass voltage 511 is boosted to the pass potential (about 8 to 10 V) used to program the bias pulse, and is stable at about t6. Thereafter, at time t7, the stylized potential 512 is boosted to the programmed potential (about 20V) used to program the bias pulse, and is stable at about t8. At times t5 and t7, the unselected channels are floating, and capacitive boosting occurs according to the standard incremental step pulsed program pulse series to suppress stylized interference. In addition, the reference trace 521 as shown in FIG. 14 shows the programmed pulse timing of the standard incremental step pulsed program pulse series, where the programmed voltage transitions at time t5 when the serial floating is not selected.

As indicated in Figure 14, the stylized bias pulse includes a pre-stylation phase PRE-PGM in which the word line of the selected memory cell is precharged to an intermediate level _Vpgm0 , in which case it is not Will cause the channel in the selected or unselected string to be boosted, and a stylized phase PGM, wherein the word line of the selected memory cell is boosted to a level V _pgm , and the character of the memory cell is not selected The line is boosted to a pass voltage level, which in this case does not cause the channel in the unselected string to be boosted. However, the boost caused by the selected word line is greatly reduced, suppressing gate-induced drain leakage current (GIDL) interference as described above.

Therefore, the application of the programmed bias pulse using the controller in the integrated circuit shown in FIG. 17 is described as follows: biasing the bit line and the string selection line in a first case (for example, the conditions of time t1 to t3) Setting a word line coupled to a target memory cell to a first voltage level (eg, V _pgm0 ), and the bit line and the string selection line are in the first case; thereafter, in a second case a bias bit line and a string select line (eg, a condition of time t4 to t8); and setting a word line coupled to a target memory cell to a second voltage level (eg, V _pgm ), and the bit line And the string selection line. In the second case, the second voltage level is higher than the first voltage level.

In such an embodiment, the first case includes setting the bit line voltage SELECTED V-BL to a selected bit line and a UNSELECTED V-BL such as V _CC to an unselected bit line, and for example, V _CC The voltage V-SSL is coupled to a string selection line of the series to couple the selected string to the bit line and the unselected string to the unselected bit line. The second case includes setting a voltage V-SSL of, for example, V _CC to a serial selection line of a selected string, setting a bit line voltage of the selected bit line to ground, and coupling the selected string to the bit line. And setting, for example, UN SELECTED V-BL of V _CC to an unselected bit line to decouple the unselected bit line from the unselected string selection line. Therefore, in the first case, the voltage of the selected word line is raised to V _pgm0 without inducing channel boosting in the series, and then in the second case, the voltage of the selected word line is raised. The voltage pressed to a stylized level _Vpgm and the unselected word line is boosted to a pass level _Vpass , in which case channel boosting in the unselected series is not induced.

Figure 15 shows the efficacy of using a channel voltage having a stylized bias pulse similar to the initial portion of Figure 14 for the unselected series of channel voltages. In the absence of improvement, the channel voltage has a profile similar to trace 550 that has a highly boosted level adjacent the ground selection transistor. After the improvement, the boost of the channel voltage is relatively uniform, as shown by trace 551. Therefore, it can suppress the interference generated by the gate-induced drain leakage current.

As in the technique shown in Figure 14, the timing of the leading edge of the stylized bias pulse is adjusted, which can be combined with a pulse similar to that shown in Figure 5, wherein the level of the programmed pulse 512 corresponds to the adjustment pulse. The initial part. In Figure 16, an example of a stylized bias pulse including a pre-programmed, initial stylization phase, and an adjustment stylization phase is shown, combining the stylized bias effects in Figures 5 and 14.

Figure 16 shows a timing diagram of the improved stylized bias pulse, including the pre-stylized phase PRE-PGM, which suppresses the self-boosting potential of the partial region, with the initial stylization phase INTI-PGM and the tuning stylization phase MODULATE- The PGM controls the flow of this incremental stepping pulse to program the pulse train. Prior to t0, the voltage involved in the stylized bias pulse includes bit line voltage 1604 on the unselected bit line, bit line voltage 1603 on the selected bit line, voltage 1602 on the string select line SSL, V The -PASS voltage 1601 is on the unselected word line, and the V-PGM voltage 1600 is on the selected word line. All voltages are about 0V or ground. At time t0, the serial select line voltage (V-SSL) applied to the serial select transistor is boosted to a _Vssl1 level, such as _Vcc , for the beginning of the pre-programming phase. Subsequently, the V-PGM voltage on the selected word line is boosted to a middle (1611) level such as V _pgm0 , and then the bit line voltage V-BL on the unselected bit line is boosted to about V _cc . At time t1, the pre-stylization phase is completed, the V-PGM voltage on the selected word line is stabilized at V _pgm0 , and the serial selection switch of the unselected string is turned off. At the beginning of time t1, the initial stylization phase is started, in which the V-PASS voltage on the unselected word line is boosted to an initial pass voltage (1621) level such as _Vpass1 , and the V-PGM on the word line is selected. The voltage is boosted to, for example, the initial programmed voltage (1612) level of V _pgm1 . At time t2, the voltage on the tandem selection switch (V-SSL) is lowered to the _Vssl2 level, and the bit line voltage V-BL (SELECTED) on the selected bit line is boosted to about V _bl2 to reduce or Cut off the current in the selected string. In addition, the V-PASS voltage on the unselected word line is boosted to a second pass voltage (1622) level such as _Vpass2 , and the V-PGM voltage on the selected word line is boosted to, for example, _Vpgm2 . The second stylized voltage (1623) level causes the body in the selected series to be boosted by the number of ΔV _pass and ΔV _prog equations as previously described. At time t3, the stylized bias pulse is terminated.

Therefore, the application of the programmed bias pulse using the controller in the integrated circuit shown in FIG. 17 is described as follows: in a first case, the bias bit line and the tandem selection line (for example, the condition of time t0 to t1) ): setting a word line coupled to a target memory cell to a first voltage level (eg, V _pgm0 ), and the bit line and the string selection line are in the first case: after, in a second case a bias bit line and a string select line (eg, a condition of time t1 to t2); setting a word line coupled to a target memory cell to a second voltage level (eg, V _pgm1 ), and the bit line and The serial selection line is in the second case, the second voltage level is higher than the first voltage level; thereafter, in a third case, the bit line and the string selection line are biased (eg, the conditions of time t2 to t3) And setting a word line coupled to a target memory cell to a third voltage level (eg, V _pgm2 ), and the bit line and the string selection line are in the third case, the third voltage level is high At the second voltage level.

Figure 17 shows a simplified schematic diagram of an integrated circuit 975 including a flip-flop flash memory array 960 having the adjusted incremental stepping pulse program described herein, in accordance with an embodiment of the present invention. Logic. In some embodiments, this array 660 includes multi-level memory cells. A column of decoders 961 is coupled to a plurality of word lines 962 arranged along the direction of the column of memory array 960. In this example, the row decoder in block 966 is coupled to a set of page buffers 963 via data bus 967. The overall bit line 964 is coupled to the area bit line (not shown) and arranged along the row direction of the memory array 960. The address is provided via bus 965 to column decoder (block 961) and row decoder (block 966). The data from the other circuits 974 (including, for example, input/output ports) are provided via input line 973. Other circuits may be included in the general purpose processor or special purpose application circuit in the integrated circuit, or a combination of modules. A system single chip function supported by memory array 960 is provided. The data is supplied to the input/output ports on the integrated circuit 975 via the input/output line 973, or to other data terminals inside/outside the integrated circuit 975.

The controller used in this embodiment uses state mechanism 969 to provide a signal to control the generation of the bias adjustment supply voltage or via a voltage supply in block 968 to perform the various operations described herein. These operations include erasing and reading, as well as the adjustment of the incremental step pulse stylization operations described herein. The controller can be utilized with special purpose logic circuitry as is well known to those skilled in the art. In an alternate embodiment, the controller includes a general purpose processor that can be used in the same integrated circuit to execute a computer program to control the operation of the device. In yet another embodiment, the controller is a combination of special purpose logic circuitry and a general purpose processor.

The controller 969 can be configured to apply a stylized method comprising applying a stylized bias arrangement similar to that described in FIG. 7, comprising: applying a stylized voltage to the selected word line and passing a voltage to the complex The other word lines in the word line, the programmed voltage and the at least one pass voltage having a first size in an initial stage of the programmed bias pulse, and transitioning to a respective second in a subsequent stage a size; applying a bit line voltage to the sensing node corresponding to the selected string and a reference voltage to the reference node corresponding to the selected string; and applying a string selection voltage to the at least one string Selecting a line, the bit line voltage and the series select line voltage are used to turn on the serial select switch in the initial phase of the programmed bias pulse, and turn off the serial select switch in the subsequent phase switch.

The controller may also include causing the bit line voltage to be set to a programmed bias level VBL1 during the initialization phase, the series select bias being raised to VSSL1, wherein (VSSL1-VBL1) is greater than the series Selecting a threshold voltage of the switch, and then increasing the programmed voltage and the pass voltage to respective first sizes, and at the subsequent stage, the bit line voltage is increased and the series select bias is decreased (VSSL1- VBL1) is less than the threshold voltage of the series select switch, and then the programmed voltage and the pass voltage are increased to respective second sizes.

The controller can also implement the pulse shape shown in Figure 14 to suppress interference on unselected bit lines. The controller can also be used to apply the modified stylized bias pulse shown in Figure 14 regardless of the position of the target memory cell, or only when the target memory cell is connected to, for example, a ground select line or string. The column selection line is related when switching the transistor. In addition, the controller can also implement the pulse shape shown in Figure 16, in conjunction with the suppression region boost and the incremental stepping pulse stylized series described herein.

The controller may also include logic to implement a two-stage (or multi-stage) incremental step pulse programming (ISSP) stylized series to set the first stage of the programmed bias, including the stylized voltages V _Pgm , ΔV _Pgm Passing the voltage V _PASS , ΔV _PASS , selecting and unselecting the bit line voltage Vb1, the string selection line voltage Vssl, the ground selection line voltage Vgsl, and the pulse shape and voltage level of the common source line voltage Vcs, after which Programmatically adjust the bias voltage using the adjusted incremental stepping pulse described herein to set the programmed bias of the second stage such that the slope of the incremental step pulse stylization (ISSP) is less than the first stage in the second phase, such that A flash memory stylized operation with narrower boundaries.

Figure 18 shows a flow diagram of the logic executed by this controller in an example system using a two-stage incremental step pulse stylized series of the present invention as described, for example, in Figure 9B. At the beginning of this stylization operation, the peripheral support circuitry in the controller and the chip sets the programmed bias voltage of the first stage 700 of the incremental stepping pulse stylized series. The stylized bias voltage of the first stage includes the stylized voltage V _Pgm , ΔV _Pgm , the pass voltage V _PASS , ΔV _PASS , the selected and unselected series bit line voltage Vbl, the tandem select line voltage Vssl, the ground select line Pulse shape and voltage level of voltage Vgsl and common source line voltage Vcs. For example, in one embodiment, this first phase involves a standard incremental stepping pulsed series in which the pulses are set to, for example, "square wave" as shown in the first stage of Figure 9, or as shown in FIG. "Staircase wave" to suppress gate-induced drain leakage current (GIDL). Thereafter, a verify bias 702 is applied after the stylized bias pulse 701 is applied. Thereafter, this logic determines whether the target memory cell passes the temporary verify voltage level PV1 of this verify operation (703). If passed, the stylized operation of the target memory cell proceeds to the second phase 707. If the memory cell does not pass, then this logic determines whether the number of retries exceeds the upper limit of the number of retries in the first phase X 705. If the upper limit of the number of retries in the first stage is not exceeded, the first stage parameter values ΔV _PASS and ΔV _Pgm 706 are added to the programmed voltage and the pass voltage. In various embodiments, ΔV _PASS and ΔV _Pgm may be constant values or varied in the series. Moreover, in some or all of the series of pulses, ΔV _PASS may also be zero in some embodiments.

If at block 705, the upper limit of the number of retries is exceeded, or if the memory cell is determined to pass the temporary verification voltage level PV1 in block 703, then the logic sets the stylization of the second stage of the incremental stepping stylized series. Bias (707). The stylized bias voltage of the second stage includes the stylized voltage V _Pgm , ΔV _Pgm , the pass voltage V _PASS , ΔV _PASS , the selected and unselected bit line voltage Vbl, the serial select line voltage Vssl, the ground select line Pulse shape and voltage level of voltage Vgsl and common source line voltage Vcs. For example, in one embodiment, this second phase involves adjusting the incremental stepping pulsed series, wherein the pulses are set to, for example, a "stepped waveform" as shown in the second stage of Figure 9. Thereafter, a verify bias voltage PV 708 is applied after applying the programmed bias pulse 708 (709). If the memory cell is temporarily verified by the voltage level PV1, it is programmed using an adjustment incremental step pulse, such as that described in FIG. 7, such that a small increment of the threshold voltage of the trajectory 131 in FIG. 8, for example, can be induced. Thereafter, this logic determines if the target memory cell passes this verification operation 710. If passed, the stylized operation of the target memory cell ends and the stabilizing bias 711 is programmed for the remainder of the stylized cycle. If the memory cell does not pass, then this logic determines whether the number of retries exceeds the upper limit of the second phase retries Y 712. If the upper limit of the number of retries in the second phase is exceeded, it is determined that an error has occurred and the program fails 713. If the upper limit of the number of retries in the second phase is not exceeded, the programmed voltage and the pass voltage are increased by a second phase parameter value ΔV _PASS and ΔV _Pgm 714. In various embodiments, ΔV _PASS and ΔV _Pgm may be constant values or varied in the series. Moreover, in some or all of the series of pulses, ΔV _PASS may also be zero in some embodiments. As mentioned earlier, for a modified incremental stepping pulsed series using stepped pulses, ΔV _PASS and ΔV _Pgm may be the same or different to control the threshold voltage change caused by this pulse and its increment. Stepping pulse stylized series slope. In addition, using a stepped pulse to adjust the stylized pulsed arrangement of the step-pulse stylized series, this stepped V _PASS can be applied to all or some of the unselected word lines to control the criticality caused by this pulse. Voltage change and its incremental stepping pulse stylized series slope.

If, at block 705, the upper limit X of the number of retries is exceeded and the memory cell does not pass the temporary verification voltage level PV1, an alternative solution may be to apply stylized stylization and stylization of the voltage in the second stage. The bias line pulse maintains the bit line voltage at a predetermined value until the memory cell passes the temporary verify voltage level PV1. The trajectory 130 as shown in Fig. 8 can still be achieved by an incremental step pulse stylization typically having a slope of one. Thereafter, the program verification verification level can be increased to the target standard position PV2, and the Vbl step value of the pulse is increased to complete the stylization. This is done in a three-stage stylized cycle, with the first phase in Figure 9 plus the first phase in Figure 9B and the second phase in Figure 9B.

Figure 19 shows a flow diagram of the logic executed by this controller in an example system using a two-stage incremental step pulse stylized series of the present invention as described, for example, in Figure 9B. At the beginning of this stylization operation, the peripheral support circuits in the controller and the chip set the programmed bias voltage of the first stage 800 of the incremental stepping pulse stylized series. The stylized bias voltage of the first stage includes a stepped stylized voltage V _Pgm , ΔV _Pgm , a stepped pass voltage V _PASS , ΔV _PASS , a bit line voltage Vbl of the selected and unselected series, and a series select line voltage Vssl The ground selection line voltage Vgsl and the common source line voltage Vcs have a pulse shape and a voltage level. For example, in one embodiment, this first phase involves a series in which the stylization and pass voltage pulses are set to, for example, the "step wave" shown in the first stage of Figure 9B. In addition, the stylized and pass voltage pulses may also include the "step wave" shown in Figure 14 to suppress gate induced drain leakage current (GIDL). Thereafter, a verify bias 802 is applied after the stylized bias pulse 801 is applied. Thereafter, this logic determines whether the target memory cell passes the temporary verify voltage level PV1 of the verify operation (803). If passed, the stylized operation of the target memory cell proceeds to the second stage 807. If the memory cell does not pass, then this logic determines whether the number of retries exceeds the upper limit of the number of retries in the first phase X 805. If the upper limit of the number of retries in the first stage is not exceeded, the first stage parameter values ΔV _PASS and ΔV _Pgm 806 are added to the programmed voltage and the pass voltage. In various embodiments, ΔV _PASS and ΔV _Pgm may be constant values or varied in the series. Moreover, in some or all of the series of pulses, ΔV _PASS may also be zero in some embodiments.

If at block 805, the upper limit of the number of retries is exceeded or if the memory cell is determined to pass the temporary verify voltage level PV1 in block 803, then the logic sets the stylization of the second stage of the incremental stepping stylized series. Bias (807). The stylized bias voltage of the second stage includes the stylized voltage V _Pgm , ΔV _Pgm , the pass voltage V _PASS , ΔV _PASS , the selected and unselected bit line voltage Vbl, the serial select line voltage Vssl, the ground select line Pulse shape and voltage level of voltage Vgsl and common source line voltage Vcs. For example, in one embodiment, this second phase involves adjusting the incremental stepping pulsed series, wherein the pulses are set to, for example, a "stepped waveform" as shown in the second stage of Figure 9B. In this second phase, the stylized bias pulse includes stepped Vbl and Vssl on the selected bit line. Therefore, as shown in Fig. 9B, the Vssl level drops from Vssl1 to Vssl2 in this pulse, and the Vbl level in this pulse increases from Vbl1 to Vbl2. Vssl1 and Vbl1 are used to set the serial selection transistor to be turned on, and Vssl2 and Vbl2 are set to be smaller than the threshold voltage of the tandem selection transistor. Thereafter, a verify bias voltage 808 is applied after applying the programmed bias pulse 808 (809). Thereafter, this logic determines if the target memory cell passes this verification operation 810. If passed, the stylized operation of the target memory cell ends and the stylized suppression bias 811 is performed for the remainder of the stylized cycle. If the memory cell does not pass, then this logic determines whether the number of retries exceeds the upper limit of the number of retries in the second phase Y 812. If the upper limit of the number of retries in the second phase is exceeded, it is determined that an error has occurred and the program has failed 813. If the upper limit of the number of retries in the second phase is not exceeded, the programmed voltage and the pass voltage are increased by a second phase parameter value ΔV _PASS and ΔV _Pgm 814. In various embodiments, ΔV _PASS and ΔV _Pgm may be constant values or varied in the series. Moreover, in some or all of the series of pulses, ΔV _PASS may also be zero in some embodiments. As mentioned earlier, for a modified incremental stepping pulsed series using stepped pulses, ΔV _PASS and ΔV _Pgm may be the same or different to control the threshold voltage change caused by this pulse and its increment. Stepping pulse stylized series slope. In addition, using a stepped pulse to adjust the stylized pulsed arrangement of the step-pulse stylized series, this stepped V _PASS can be applied to all or some of the unselected word lines to control the criticality caused by this pulse. Voltage change and its incremental stepping pulse stylized series slope.

In some embodiments, the stylized pulse bias can be configured by logic and circuitry associated with the controller to suppress interference generated by the gate induced drain leakage current as depicted in FIG. In such an embodiment, the step of setting the programmed pulse bias includes the leading edge of the programmed bias pulse, and the target is made before the unselected bit line is set to the suppression level to turn off the serial select line switch. The word line is stepped closer to V _Pgm by a boost, after which the remainder of the boost V _Pgm level turns off the tandem select line switch. Such an adjustment of the leading edge of the stylized pulse bias can suppress the interference generated by the gate induced drain leakage current, which can be applied by applying an incremental stepping pulse stylized series, a standard incremental step pulse stylized series, or both. Achieved.

The stylized method described herein can be applied to a conventional anti-gate array using a common source architecture, an anti-gate array with a virtual ground-type architecture, or other target that can be changed during a programmed bias pulse. The memory architecture of the memory cell threshold voltage has the advantage of more accurately controlling or suppressing the interference generated by the gate induced drain leakage current.

Although the present invention has been described with reference to the embodiments, the present invention is not limited by the detailed description thereof. Alternatives and modifications are suggested in the foregoing description, and other alternatives and modifications will be apparent to those skilled in the art. In particular, all combinations of components that are substantially identical to the invention can achieve substantially the same results as the present invention without departing from the spirit of the invention. Therefore, all such alternatives and modifications are intended to be within the scope of the invention as defined by the appended claims and their equivalents.

7, 8. . . Gate dielectric layer

9. . . Charge trapping structure

10. . . Semiconductor body

11, 19. . . contact

12~18. . . node

twenty one. . . Ground selection line GSL

22~27. . . Word line

28. . . Serial selection line SSL

30. . . Common source line CS

31. . . Bit line

32. . . Unselected bit line

33. . . Precharged body area

35. . . Boost body area

181, 182. . . Reverse gate train

185. . . Common source line

180, 300, 500. . . Target memory cell

191, 192. . . Switching transistor

501. . . Ground selection switching transistor

975. . . Integrated circuit

960. . . Anti-gate flash memory

961. . . Column decoder

962. . . Word line

963. . . Page buffer

966. . . Row decoder

967. . . Overall bit line

964. . . Data bus

965. . . Busbar

969. . . State mechanism for adjusting incremental stepping, staging, erasing, and reading operations

968. . . Bias adjustment supply voltage

973. . . Data input line

974. . . Other circuit

The invention is defined by the scope of the patent application. These and other objects, features, and embodiments are described in the following sections of the accompanying drawings, in which:

Figures 1A and 1B respectively show a cross-sectional view of the reverse gate sequence and an unselected reverse gate sequence bias, which is based on a conventional FN tunneling stylization technique.

Figure 2 shows a dynamic schematic of an incremental step-pulse stylization (ISSP) operation of the prior art, showing the critical voltage distribution during the initial pulse phase of the incremental step pulse stylized (ISSP) series and the critical voltage distribution at the final stage.

Figure 3 shows the relationship between the threshold voltage and the stylized pulse height for a typical incremental step pulse stylized (ISSP) technique.

Figure 4 shows a plot of the threshold voltage of a modified incremental step pulse stylized (ISSP) technique versus the programmed pulse height.

Figure 5 shows a schematic cross-sectional view of a NAND string, showing a conventional FN tunneling biasing technique (similar to Figure 1B) in which the target memory cell is switched to an adjacent grounded selective transistor. The word lines are coupled and exposed to gate-induced drain leakage current (GIDL).

Figure 6 shows the simulation results for the channel voltages in the unselected series.

Figure 7 shows a schematic diagram of several signal voltages of an improved incremental step-pulse stylized series of flash memory cells using only the programmed pulse bias described herein.

Figure 8 shows a schematic of a modified two-stage incremental stepping pulsed series of programmed pulse series as described herein.

Figure 9 shows a plot of the threshold voltage versus a number of different stylized pulses for a two-stage incremental step-pulse stylized series of typical incremental step-pulse stylization (ISSP) and adjustments as described herein, and suppression of unselected strings. The column's memory cells are incremented by a stepped pulse stylized threshold voltage curve for comparison.

Figure 9A shows a dynamic schematic of a modified incremental step pulse stylization (ISSP) operation.

Figure 9B shows a dynamic schematic of another modified incremental step pulse stylization (ISSP) operation.

Figure 10 shows a schematic diagram of the circuit layout of the inverted gate memory array using the programmed bias operation described herein.

Figure 11 is a plot of the threshold voltage versus a number of different stylized pulses comparing a typical incremental step pulse stylization (ISSP) with the adjusted two-stage incremental step-pulse stylized series described herein to establish a first reduction. Incremental step pulse stylization (ISSP) slope, and an improved two-stage incremental step pulse stylized series to establish a second reduced incremental step pulse stylized (ISSP) slope, with a second reduced incremental step pulse program The (ISSP) slope is greater than the first decreasing incremental step pulse stylized (ISSP) slope.

Figure 12 shows a circuit layout diagram of an inverted gate memory array using the programmed bias operation described herein, with stepped pass voltage applied to certain word lines in the string rather than all word lines. .

Figure 13 shows a schematic diagram of the circuit layout similar to the two inverted gate series of Figure 10.

Figure 14 shows that the modified stylized bias pulse can suppress the self-boosting potential of the partial region and prevent gate-induced drain leakage current (GIDL) interference caused by the conditions in Figures 5 and 6.

Figure 15 shows the efficacy of using a channel voltage having a stylized bias pulse similar to the initial portion of Figure 14 for the unselected series of channel voltages.

Figure 16 shows a timing diagram of the improved stylized bias pulse, including the pre-stylized phase PRE-PGM, which suppresses the self-boosting potential of the partial region, with the initial stylization phase INTI-PGM and the tuning stylization phase MODULATE- The PGM controls the flow of this incremental stepping pulse to program the pulse train.

Figure 17 shows a simplified schematic diagram of an integrated circuit including a reverse gate flash memory array having the adjusted incremental step pulse stylization logic described herein, in accordance with an embodiment of the present invention.

Figure 18 is a flow chart showing the logic executed by this controller in an exemplary system using the two-stage or multi-stage incremental step-pulse stylized series of the present invention.

Figure 19 is a flow chart showing the logic executed by the controller in accordance with another exemplary system of the present invention using the two-stage or multi-stage incremental step pulse stylized series of the present invention.

Claims (23)

A memory device includes: a plurality of sensing nodes and a reference node; a plurality of memory cell strings, each of which is arranged between the corresponding sensing node and the reference node, and includes a serial selection switch Selectively connecting the string to the corresponding bit line; a plurality of word lines and at least one string selection line, the word line being coupled to the corresponding memory cell of the plurality of memory strings and the at least one string The column select line is coupled to the corresponding serial select switch; the logic AND circuit and the plurality of word line lines, the at least one string select line, the plurality of bit lines, and the reference node are coupled to program a Selecting a selected word line of a memory cell in the string to establish a stylized memory cell threshold voltage within a target threshold voltage, the logic and circuitry configured to apply a stylized bias pulse, including: applying a stylization And the voltage to the selected word line and the pass voltage to other word lines in the plurality of word lines, the programmed voltage and the at least one pass voltage having a first phase in the initial stage of the stylized bias pulse Small, and in a subsequent stage, transition to a respective second size; applying a bit line voltage to the sensing node corresponding to the selected string and a reference voltage to the reference node corresponding to the selected string And applying a string of select voltages to the at least one string select line, the bit line voltage and the string select line voltage being used to enable the series select switch in the initial phase of the programmed bias pulse Switching, and in the subsequent stage, turning off the serial selection switch or reducing the conductivity of the serial selection switch. The memory device of claim 1, wherein the logic and circuit are configured to perform a verification step, including determining whether the selected memory cell has a stylization The memory cell threshold voltage is within a target threshold voltage, and if the selected memory cell has a verification failure number that does not exceed an upper limit of the number of critical retries, increasing the programmed voltage and the second of the one or both of the pass voltages A corresponding stylized voltage increase and a voltage increase is applied to the size, and then a stylized bias pulse is reapplied. The memory device of claim 2, wherein the adding comprises increasing a stylized voltage increase of the second size of the stylized voltage, and increasing the second size of the pass voltage on at least one word line. Through the voltage increase, wherein the pass voltage increase is greater than the stylized voltage increase. The memory device of claim 1, wherein in the initial stage, the bit line voltage is set to a programmed bias level Vbl1, and the series selection bias is raised to Vssl1, where (Vssl1- Vbl1) is greater than a threshold voltage of the serial selection switch, and then the programmed voltage and the pass voltage are increased to respective first sizes, and the bit line voltage is increased at the subsequent stage and the series is selected The bias voltage is reduced such that (Vssl1-Vbl1) is less than the threshold voltage of the series select switch, and then the programmed voltage and the pass voltage are increased to respective second magnitudes. The memory device of claim 1, wherein the plurality of memory cells are arranged in a reverse sequence. A memory device includes: a plurality of sensing nodes and a reference node; a plurality of memory cell strings, each of which is arranged between the corresponding sensing node and the reference node, and includes a serial selection switch Selectively connecting the string to a corresponding bit line; a plurality of word line lines and at least one string selection line, wherein the word line is coupled to a corresponding memory cell of the plurality of memory cells and the at least one string selection line is coupled to the corresponding serial selection switch; The logic AND circuit and the plurality of word line lines, the at least one string selection line, the plurality of bit lines, and the reference node are coupled to program a selected word line of a memory cell in the series Establishing a stylized memory cell threshold voltage within a target threshold voltage, the logic and circuitry configured to perform a stylized operation comprising at least a first phase and a second phase; and executing a program in the first phase The first stage includes applying a first programmed bias pulse and a first stylized verifying step, the first stylized bias pulse comprising: applying a stylized voltage to the selected word line and Passing a voltage to other word lines in the plurality of word lines, the programmed voltage and the at least one pass voltage having a first size in an initial phase of the programmed bias pulse, and transitioning to a subsequent stage to a respective second size; applying a bit line voltage to the sensing node corresponding to the selected string and a reference voltage to the reference node corresponding to the selected string; and applying a series of select voltages to The at least one string selection line, the bit line voltage and the string selection line voltage are used to turn on the serial selection switch in the initial stage of the programmed bias pulse, and are turned off in the subsequent stage The serial selection switching switch includes: determining whether the selected memory cell has a stylized memory cell threshold voltage within a temporary target threshold voltage to identify whether the selected memory cell passes the temporary verification, and if The selected memory cell passes the temporary verification, and then enters the second stage. If the selected memory cell has a verification failure number less than a first retry number upper limit, the size of the stylized voltage is increased and the first stage stylization is reapplied. Biasing, and if the temporary verification of the selected memory cell fails beyond the upper limit of the first number of retries, then enters the second phase, and Performing a stylization/verification series in the second phase, the second phase includes applying a second stylized bias pulse and a second stylized verifying step, the second stylized bias pulse comprising: applying a stylization And the voltage to the selected word line and the pass voltage to other word lines in the plurality of word lines, the programmed voltage and the at least one pass voltage having a first size in an initial stage of the programmed bias pulse And transitioning to a respective second size in a subsequent stage; applying a bit line voltage to the sensing node corresponding to the selected string and a reference voltage to the reference node corresponding to the selected string; And applying a series of select voltages to the at least one string select line, the bit line voltage and the string select line voltage being used to turn on the serial select switch in the initial phase of the programmed bias pulse And closing the serial selection switch or reducing the conductivity of the serial selection switch in the subsequent stage; and the second stylized verification step includes determining whether the selected memory cell has a The programmed memory cell threshold voltage is within a target threshold voltage to identify whether the selected memory cell passes the verification, and if the selected memory cell passes the verification, the stylization operation is ended, if the selected memory cell has a verification failure number less than one The upper limit of the critical retries increases the respective second magnitudes of the stylized voltage and the pass voltage and reapplies the second stage stylized bias. The memory device of claim 6, wherein the increasing comprises increasing a stylized voltage increase of the second size of the stylized voltage, and increasing the second size of the pass voltage on at least one word line. Through the voltage increase, wherein the pass voltage increase is greater than the stylized voltage increase. The memory device of claim 6, wherein in the initial stage, the bit line voltage is set to a programmed bias level Vbl1, and the series selection bias is raised to Vssl1, where (Vssl1- Vbl1) is larger than the serial selection switch a threshold voltage, and then the stylized voltage and the pass voltage are increased to respective first magnitudes, and at the subsequent stage the bit line voltage is increased and the series select bias is decreased such that (Vssl1-Vbl1) is Less than the threshold voltage of the series selection switch, and then the stylized voltage and the pass voltage are increased to respective second sizes. The memory device of claim 6, wherein the plurality of memory cells are arranged in a reverse sequence. A memory device includes: a plurality of sensing nodes and a reference node; a plurality of memory cell strings, each of which is arranged between the corresponding sensing node and the reference node, and includes a serial selection switch Selectively connecting the string to the corresponding bit line; a plurality of word lines and at least one string selection line, the word line being coupled to the corresponding memory cell of the plurality of memory strings and the at least one string The column select line is coupled to the corresponding serial select switch; the logic AND circuit and the plurality of word line lines, the at least one string select line, the plurality of bit lines, and the reference node are coupled to program a Selecting a selected word line of a memory cell in the string to establish a stylized memory cell threshold voltage within a target threshold voltage, the logic and circuit configured to apply a stylized bias pulse to the selected memory cell, the program The biasing pulse includes: applying a stylized voltage having a programmed size to the selected word line and having a pass-through voltage to other word lines in the plurality of word lines; applying a bit Voltage to the series corresponding to the selected sense node and a reference voltage to the reference node corresponding to the selected series; and Applying a suppression bit line voltage to the sensing node corresponding to an unselected string and a reference voltage to the reference node corresponding to the unselected string; applying a string selection voltage to the at least one string selection line The bit line voltage and the string select line voltage are used to turn on the serial select switch in the initial phase of the programmed bias pulse; wherein the suppress bit line voltage is applied to turn off the unselected The serialized voltage is boosted to be less than the programmed size before the series of selects the switch, and after the series of select switch switches is applied to turn off the unselected series of switches The stylized voltage rises to the stylized size. The memory device of claim 10, comprising: raising the stylized voltage to a first voltage level in a first time interval, wherein the first voltage level is less than the programmed size; a second time interval after the first time interval, setting a gate voltage of a first series selection switch to a threshold higher than a bit line voltage of the selected series and lower than the bit selection string a magnitude of a threshold value of the suppression bit line voltage; and a third time interval after the second time interval, the pass voltage is changed to a pass voltage lower than the programmed size and the stylized voltage is raised To the stylized size. The memory device of claim 10, wherein the plurality of memory cells are arranged in a reverse sequence. A method for generating a programmed bias pulse in a charge storage memory device configured as a reverse gate array, comprising: a reverse gate sequence coupled to a bit line via a serial select switch and including a word line, The method includes: biasing the bit lines and the string selection lines in a first case; Setting a word line coupled to a target memory cell to a first voltage level, wherein the bit line and the string selection line are in the first case; thereafter, biasing the second line in the second case a bit line and a string selection line; and setting the word line coupled to the target memory cell to a second voltage level, wherein the bit line and the string selection line are in the second case, The second voltage level is higher than the first voltage level. The method of claim 13, wherein the first case comprises: setting a bit line voltage on a selected bit line and a voltage on a selected string selection line in a selected string, And coupling the selected string to the bit line; and the second case includes setting a bit line voltage on a selected bit line and a voltage on a selected string selection line in a selected string And decoupling the selected string from the bit line. The method of claim 13, wherein the first case comprises: setting a bit line voltage on a selected bit line in a selected string, and selecting an unselected bit line voltage to be unselected a bit line and a voltage on a selected string selection line to couple the selected string to the bit line and to couple an unselected string to the unselected bit line; and the second case Included in a selected string, setting a bit line voltage on a selected bit line, an unselected bit line voltage on an unselected bit line, and a voltage on a selected string selection line to The selection string is coupled to the bit line and the unselected string is decoupled from the unselected bit line. The method of claim 13, comprising: after setting the word line to the second voltage level to be coupled to the target memory cell, biasing the bit lines and strings in a third case. a column selection line and setting the character coupled to the target memory cell The line is connected to a third voltage level. When the bit lines and the string selection lines are in the third case, the third voltage level is higher than the second voltage level. The method of claim 16, wherein the first case comprises: setting a bit line voltage on a selected bit line in a selected string, and selecting an unselected bit line voltage to be unselected. a bit line and a voltage on a selected string selection line to couple the selected string to the bit line and to couple an unselected string to the unselected bit line; the second case includes Setting a bit line voltage in a selected string on a selected bit line, an unselected bit line voltage on an unselected bit line, and a voltage on a selected string selection line to select the line line The string is coupled to the bit line and decouples the unselected string from the unselected bit line; and the third case includes setting a bit line voltage to a selected bit line and a voltage A selected string selection line is used to uncouple the selected string from the bit line. An integrated circuit includes: a charge storage memory device configured as a reverse gate array, including a reverse gate sequence coupled to a bit line via a serial select switch and including a word line; and a controller Configuring to generate a stylized bias pulse: biasing the bit lines and the string selection lines in a first case; setting a word line coupled to a target memory cell to a first voltage level When the bit lines and the string selection lines are in the first case; thereafter, biasing the bit lines and the string selection lines in a second case in the stylized bias pulse to reduce Or cutting off the current entering the series via the series selection switch. The integrated circuit of claim 18, wherein the controller is configured to generate a stylized bias pulse to set the word line coupled to the target memory cell to a second voltage level. The bit line and the string selection line are in the second case, the second voltage level is higher than the first voltage level. The integrated circuit of claim 18, wherein the first case comprises: setting a bit line voltage in a selected string to a selected bit line and selecting a voltage in a selected string; a line connecting the selected string to the bit line; and the second case includes setting a bit line voltage on a selected bit line and a voltage in a selected string in a selected string A line is selected to decouple the selected string from the bit line. The integrated circuit of claim 18, wherein the first case comprises: setting a bit line voltage on a selected bit line in a selected string, and selecting an unselected bit line voltage in the Unselecting a bit line and a voltage on a selected string selection line to couple the selected string to the bit line and coupling an unselected string to the unselected bit line; and the The second case includes setting a bit line voltage on a selected bit line in a selected string, an unselected bit line voltage on an unselected bit line, and a voltage on a selected string selection line to The selected string is coupled to the bit line and the unselected string is decoupled from the unselected bit line. The integrated circuit of claim 19, comprising: after setting the word line to the second voltage level to be coupled to the target memory cell, biasing the bit lines in a third case And serially selecting the line, and setting the word line coupled to the target memory cell to a third voltage level, wherein the bit line and the string selection line are in the third case, the third voltage The level is higher than the second voltage level. The integrated circuit of claim 22, wherein the first case comprises: setting a bit line voltage on a selected bit line in a selected string, and selecting an unselected bit line voltage in the Unselecting a bit line and a voltage on a selected string selection line to couple the selected string to the bit line and coupling an unselected string to the unselected bit line; the second The situation includes setting a bit line voltage on a selected bit line in a selected string, an unselected bit line voltage on an unselected bit line, and a voltage on a selected string selection line to The selected string is coupled to the bit line and decouples the unselected string from the unselected bit line; and the third case includes setting a bit line voltage on a selected bit line and a The voltage is on a selected string selection line to decouple the selected string from the bit line.