TWI810062B - Semiconductor structure and method of forming the same - Google Patents

Abstract

A semiconductor structure includes a substrate, a gate insulating layer, a conductive layer, a gate, a first barrier layer, a second barrier layer, a first oxide layer, and a second oxide layer. The substrate has a trench. The gate insulating layer covers a surface of the trench, in which the gate insulating layer has a first portion and a second portion, and the second portion is on the first portion. The first portion of the gate insulating layer surrounds the conductive layer. The second portion of the gate insulating layer surrounds the gate. The first barrier layer is between the conductive layer and the gate insulating layer. The second barrier layer is between the conductive layer and the gate. The first oxide layer is on the second barrier layer and surrounds a bottom surface and sidewalls of the gate. The second oxide layer covers an upper surface of the gate.

Description

Semiconductor structures and methods of forming them

The present disclosure relates to a semiconductor structure and a method of forming the same.

The word line in the memory is connected to the gate of the transistor. By applying a voltage to the word line, the gate switch can be controlled and the signal can be read. Buried word line (Buried Word Line) sets the word line under the surface of the wafer to increase the integration density of device components and reduce the size of the device. However, in the buried word line structure, as a barrier layer to prevent impurities from diffusing to the gate, the bonding ability between its material (such as titanium nitride) and part of the gate material (such as polysilicon) is weak, making The gate is detached from the embedded word line structure, which affects the functional performance of the embedded word line structure, and the product yield rate is reduced.

The present disclosure relates to a semiconductor structure. In some embodiments, the semiconductor structure includes a substrate, a gate insulating layer, a conductive layer, a gate, a first barrier layer, a second barrier layer, a first oxide layer, and a second barrier layer. Dioxide layer. The substrate has grooves. The gate insulating layer covers the surface of the groove, wherein the gate insulating layer has a first part and a second part, and the second part is located on the first part. The first portion of the gate insulating layer surrounds the conductive layer. A second portion of the gate insulating layer surrounds the gate. The first barrier layer is located between the conductive layer and the gate insulating layer. The second barrier layer is located between the conductive layer and the gate. The first oxide layer is located on the second barrier layer and surrounds the lower surface and the sidewall of the gate. The second oxide layer covers the upper surface of the gate.

In some embodiments, the first oxide layer and the second oxide layer directly contact the gate.

In some embodiments, the second oxide layer further includes the first extension portion higher than the portion of the second oxide layer covering the upper surface of the gate, and the first extension portion covers the second portion of the gate insulating layer.

In some embodiments, the second oxide layer further includes a second extension portion located outside the groove and located on the substrate.

In some embodiments, the first oxide layer includes silicon dioxide, silicon oxynitride, silicon nitride or a combination thereof, the second oxide layer includes silicon dioxide, silicon oxynitride, silicon nitride or a combination thereof, and the gate Pole includes polysilicon.

In some embodiments, the semiconductor structure further includes a source region and a drain region located in the substrate and located on two sides of the gate.

The present disclosure also relates to a method of forming a semiconductor structure. In some embodiments, the method includes the following operations. Grooves are formed in the substrate. A gate insulating layer is formed to cover the surface of the groove, wherein the gate insulating layer has a first part and a second part, and the second part is located on the first part. A first barrier layer is formed on the first part. A conductive layer is formed on the first barrier layer, wherein the conductive layer is spatially separated from the gate insulating layer by the first barrier layer. A second barrier layer is formed to cover the upper surface of the conductive layer. A first oxide layer is formed on the second barrier layer and the second portion of the gate insulating layer. The gate is formed on the first oxide layer, wherein the first oxide layer surrounds the lower surface and the sidewall of the gate. A second oxide layer is formed covering the upper surface of the gate.

In some embodiments, forming the gate includes forming the gate in direct contact with the first oxide layer, and forming the second oxide layer includes forming the second oxide layer in direct contact with the gate.

In some implementations, when the second oxide layer is formed, the second oxide layer further includes a portion of the second oxide layer that covers the upper surface of the gate electrode with the first extension portion higher than that of the second oxide layer covering the gate electrode, and the first extension portion covers the gate electrode The second part of the insulating layer.

In some embodiments, when the second oxide layer is formed, the second oxide layer further includes a second extension portion outside the groove and on the substrate.

Different examples are provided below to illustrate different features of the present disclosure. To simplify the current disclosure, the components and configurations will be described below with specific examples. Of course, these are examples only and are not intended to be limiting. For example, the description below that the first feature is formed above the second feature may include an embodiment in which the first feature and the second feature are formed by direct contact, and may also include other features on the first feature and the second feature. An embodiment wherein the first feature and the second feature are formed without direct contact.

Additionally, spatially relative terms, such as above and below, are conveniently used herein to describe the relationship of one element or feature to another element or feature in the drawings. However, the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. Thus descriptions of spatially relative terms herein should be interpreted relatively when the device is otherwise oriented (rotated 90 degrees or otherwise). In the discussion herein, unless otherwise stated, the same reference numbers in different drawings refer to the same or similar elements formed from the same or similar materials by the same or similar methods.

The present disclosure provides a semiconductor structure, which includes a substrate, a gate insulating layer, a conductive layer, a gate, a first barrier layer, a second barrier layer, a first oxide layer, and a second oxide layer. The substrate has grooves. The gate insulating layer covers the surface of the groove, wherein the gate insulating layer has a first part and a second part, and the second part is located on the first part. The first portion of the gate insulating layer surrounds the conductive layer. A second portion of the gate insulating layer surrounds the gate. The first barrier layer is located between the conductive layer and the gate insulating layer. The second barrier layer is located between the conductive layer and the gate. The first oxide layer is located on the second barrier layer and surrounds the lower surface and the sidewall of the gate. The second oxide layer covers the upper surface of the gate. In the disclosure, there is a first oxide layer between the gate and the second barrier layer, and a second oxide layer, the second oxide layer and the first oxide layer surround the upper surface of the gate together, The lower surface and the side wall solve the problem that the gate electrode falls off from the semiconductor structure due to the weak binding ability between the gate electrode and the second barrier layer. The semiconductor structure disclosed in this disclosure makes the gate firmly located in the embedded word line, which is not easy to fall off, avoids the function of the word line being affected, and improves the yield rate. Having a sufficient number of word lines can read a large number of signals, and having a solidly stacked conductive layer, second barrier layer, and gate structure according to the present disclosure can reduce the resistance that is too large to cause current generation. Next, the semiconductor structure of the present disclosure will be described in detail according to the embodiments.

FIG. 1 is a cross-sectional view of a semiconductor structure formed according to some embodiments of the present disclosure. In FIG. 1, the semiconductor structure 100 includes a substrate 102, a gate insulating layer 104, a conductive layer 106, a gate 108, a first barrier layer 110, a second barrier layer 112, a first oxide layer 114 and a second oxide layer 116 . In some embodiments, the semiconductor structure 100 further includes a source region 118 and a drain region 120 located in the substrate 102 and located on two sides of the gate 108 . It should be noted that the positions of the source region 118 and the drain region 120 are only schematically shown in FIG. 1 , and the positions of the source region 118 and the drain region 120 can also be exchanged. In some embodiments, the semiconductor structure 100 further includes a first insulating layer 122 on the substrate 102 and between the substrate 102 and the second oxide layer 116 . In some embodiments, the first insulating layer 122 includes silicon nitride. In some embodiments, the semiconductor structure 100 further includes a second insulating layer 124 on the second oxide layer 116 . In some embodiments, the second insulating layer 124 includes silicon nitride.

The substrate 102 of the present disclosure is described in detail. The substrate 102 has a groove 103 . In addition to the groove 103 , the substrate 102 further includes an n-type region 102N and a p-type region 102P, wherein the n-type region 102N is located above the p-type region 102P. The groove 103 passes through the junction of the n-type region 102N and the p-type region 102P as shown in FIG. 1 , so that part of the groove 103 is located in the n-type region 102N and part of the groove 103 is located in the p-type region 102P. In some embodiments, the groove 103 has an arc bottom surface as shown in FIG. 1 , which is for illustration rather than limitation, and the bottom surface of any shape is within the scope of the present disclosure. In some embodiments, the n-type region 102N is a silicon substrate doped with boron atoms after ion implantation. In some embodiments, the p-type region 102P is a silicon substrate doped with phosphorus atoms after ion implantation. In other embodiments, the n-type region 102N can be replaced by a p-type region, and the p-type region 102P can be replaced by an n-type region.

The gate insulating layer 104 of the present disclosure will be described in detail. The gate insulating layer 104 covers the surface 103S of the groove 103 , and the gate insulating layer 104 has a first portion 104A and a second portion 104B, wherein the second portion 104B is located above the first portion 104A. In addition, the gate insulating layer 104 spatially separates the gate 108 from the source region 118 and the drain region 120 . In some embodiments, the gate insulating layer 104 directly contacts the surface 103S of the groove 103 . In some embodiments, the gate insulating layer 104 conformally covers the entire surface 103S of the groove 103 as shown in FIG. 1 . In some embodiments, the first portion 104A of the gate insulating layer 104 is located in the p-type region 102P of the substrate 102, and the second portion 104B of the gate insulating layer 104 is located in the n-type region 102N of the substrate 102, but not limited thereto. . In some embodiments, the gate insulating layer 104 includes silicon dioxide.

The conductive layer 106 of the present disclosure is described in detail. The conductive layer 106 is located above the gate insulating layer 104 and adjacent to the p-type region 102P of the substrate 102 , wherein the first portion 104A of the gate insulating layer 104 surrounds the conductive layer 106 as shown in FIG. 1 . In some embodiments, conductive layer 106 includes tungsten. In some embodiments, conductive layer 106 acts as a wire. In some embodiments, the conductive layer 106 (for example, tungsten) has a low resistivity, and the driving voltage can be used to promote the conduction of the circuit between the gates to turn on the word line.

The gate 108 of this disclosure is described in detail. The gate 108 is located above the conductive layer 106 and adjacent to the n-type region 102N of the substrate 102 , wherein the second portion 104B of the gate insulating layer 104 surrounds the gate 108 as shown in FIG. 1 . In some embodiments, the gate 108 includes polysilicon.

The first barrier layer 110 of the present disclosure is described in detail. The first barrier layer 110 is located between the conductive layer 106 and the first portion 104A of the gate insulating layer 104, that is, the first barrier layer 110 spatially separates the conductive layer 106 from the gate insulating layer 104 to prevent impurities from the substrate 102 Diffusion into the conductive layer 106 forms contamination. In some embodiments, the first barrier layer 110 is in direct contact with the conductive layer 106, and due to the gap between the material of the first barrier layer 110 (for example: titanium nitride) and the material of the conductive layer 106 (for example: tungsten) The bonding ability is good, preventing the conductive layer 106 from falling off from the first barrier layer 110, stabilizing the semiconductor structure 100, and improving the bonding tightness through the thermal annealing process. In some embodiments, the first barrier layer 110 includes titanium nitride, tungsten nitride, tantalum nitride or a combination thereof.

The second barrier layer 112 of this disclosure is described in detail. The second barrier layer 112 is located between the conductive layer 106 and the gate electrode 108, that is, the second barrier layer 112 separates the conductive layer 106 from the gate electrode 108 in space, preventing the impurity of the gate electrode 108 from diffusing into the conductive layer 106 to form pollute. In some embodiments, the second barrier layer 112 is in direct contact with the conductive layer 106, and due to the gap between the material of the second barrier layer 112 (for example: titanium nitride) and the material of the conductive layer 106 (for example: tungsten) The bonding ability is good, preventing the conductive layer 106 from falling off from the second barrier layer 112, and the thermal annealing process can improve the bonding tightness. In addition, the semiconductor structure 100 is further stabilized by the first barrier layer 110 and the second barrier layer 112 jointly surrounding the conductive layer 106 . In some embodiments, the material of the second barrier layer 112 is different from the material of the first barrier layer 110 . In some embodiments, the material of the second barrier layer 112 is the same as that of the first barrier layer 110 . In some embodiments, the second barrier layer 112 includes titanium nitride, tungsten nitride, tantalum nitride or a combination thereof.

The first oxide layer 114 of the present disclosure is described in detail. The first oxide layer 114 is located on the second barrier layer 112 , covers a part P of the second portion 104B of the gate insulating layer 104 , and surrounds the lower surface 108B and the sidewall 108S of the gate 108 as shown in FIG. 1 . In some embodiments, the first oxide layer 114 is in direct contact with the gate 108 , and due to the gap between the material of the first oxide layer 114 (eg, silicon dioxide) and the material of the gate 108 (eg, polysilicon) The bonding ability is good, preventing the gate electrode 108 from falling off from the first oxide layer 114 , and the thermal annealing process can be used to improve the bonding tightness and stabilize the semiconductor structure 100 . In some embodiments, the first oxide layer 114 includes silicon dioxide, silicon oxynitride, silicon nitride or a combination thereof.

The second oxide layer 116 of the present disclosure is described in detail. The second oxide layer 116 covers the upper surface 108U of the gate 108 . In some embodiments, the second oxide layer 116 further includes a first extension portion 116B as shown in FIG. portion 116A, and this first extension portion 116B covers the remaining portion RP of the second portion 104B of the gate insulating layer 104, so that the second oxide layer 116 and the first oxide layer 114 jointly cover the second portion RP of the gate insulating layer 104 Full coverage of the second part 104B. In some embodiments, the second oxide layer 116 further includes a second extension portion 116C as shown in FIG. above the substrate 102 and the first insulating layer 122 . In some embodiments, the second oxide layer 116 is in direct contact with the gate 108 , and due to the gap between the material of the second oxide layer 116 (eg, silicon dioxide) and the material of the gate 108 (eg, polysilicon) The combination ability is good, the gate electrode 108 is prevented from falling off from the second oxide layer 116, and the tightness of the combination can be improved by the thermal annealing process. In addition, the gate electrode 108 is surrounded by the first oxide layer 114 and the second oxide layer 116 together, so that the semiconductor structure 100 is further stabilized. In addition, in the embodiment where the second oxide layer 116 further includes the first extension portion 116B, the first extension portion 116B directly contacts the remaining portion RP of the second portion 104B of the gate insulating layer 104 as shown in FIG. 1 , and Since the material of the second oxide layer 116 (such as silicon dioxide) has good bonding ability with the material of the gate insulating layer 104 (such as silicon dioxide), the first extension portion of the second oxide layer 116 116B is firmly located on the gate insulating layer 104, and the gate 108 located under the second oxide layer 116 is also firmly located in the semiconductor structure 100, and does not fall off from the semiconductor structure 100, for example, from the groove 103 of the substrate 102 It falls off in the middle, and the tightness of the combination can be improved by the thermal annealing process. In addition, in the embodiment where the second oxide layer 116 further includes the second extension portion 116C, since the second extension portion 116C extends from the first extension portion 116B to the outside of the groove 103 , and is connected to the opening of the groove 103 The first extension portion 116B has an included angle A of, for example, 85° to 95°, so when the second extension portion 116C covers the substrate 102 outside the groove 103, the second extension portion 116C can provide additional structural support, so that the The gate 108 under the second oxide layer 116 is more firmly located in the semiconductor structure 100 , preventing the gate 108 from falling off from the semiconductor structure 100 , for example, from the groove 103 of the substrate 102 . In some embodiments, the material of the second oxide layer 116 is different from the material of the first oxide layer 114 . In some embodiments, the material of the second oxide layer 116 is the same as that of the first oxide layer 114 . In some embodiments, the second oxide layer 116 includes silicon dioxide, silicon oxynitride, silicon nitride or a combination thereof.

In the above-mentioned semiconductor structure 100, there is a first oxide layer 114 between the gate 108 and the second barrier layer 112, and a second oxide layer 116 is located on the gate 108, so as to solve the problem between the gate 108 and the second barrier layer 112. Due to the weak bonding ability between the layers 112 , the gate electrode 108 is detached from the semiconductor structure 100 and affects the function and operation of the word line. The semiconductor structure 100 described above enables the gate 108 to be more firmly located in the buried word line.

The present disclosure also provides a method of forming the above-mentioned semiconductor structure, and the method includes the following operations. Grooves are formed in the substrate. A gate insulating layer is formed to cover the surface of the groove, wherein the gate insulating layer has a first part and a second part, and the second part is located on the first part. A first barrier layer is formed on the first part. A conductive layer is formed on the first barrier layer, wherein the conductive layer is spatially separated from the gate insulating layer by the first barrier layer. A second barrier layer is formed to cover the upper surface of the conductive layer. A first oxide layer is formed on the second barrier layer and the second portion of the gate insulating layer. The gate is formed on the first oxide layer, wherein the first oxide layer surrounds the lower surface and the sidewall of the gate. A second oxide layer is formed covering the upper surface of the gate. The semiconductor structure formed by the above method has a first oxide layer between the gate electrode and the second barrier layer, and further has a second oxide layer, so that the second oxide layer and the first oxide layer jointly surround the gate electrode. The upper surface, the lower surface and the side wall of the electrode solve the problem that the gate electrode falls off from the semiconductor structure due to weak binding ability between the gate electrode and the second barrier layer. Moreover, the semiconductor structure formed by the above method makes the gate more firmly located in the embedded word line, which is not only difficult to fall off, but also prevents the function of the word line from being affected. In addition to improving the yield rate, it can also ensure that, for example, it is used in memory A sufficient number of word lines in the body can read a large number of signals. In addition, the semiconductor structure formed by the above method has a solidly stacked conductive layer, a second barrier layer and a gate electrode, which can reduce resistance and prevent current from being difficult to generate due to excessive resistance. Next, the method for forming a semiconductor structure in the present disclosure will be described in detail according to the embodiments.

FIG. 2 is a flowchart of a method of forming a semiconductor structure according to some embodiments of the present disclosure. 3-11 are cross-sectional views of intermediate processes in the formation of semiconductor structures according to some embodiments of the present disclosure. When reading the method flow chart in FIG. 2, please refer to the cross-sectional views of intermediate process structures in FIGS.

The operation 202 in the method 200 for forming the semiconductor structure 100 in FIG. 2 is described in detail, and correspondingly referring to FIG. 3 , the groove 103 is formed in the substrate 102 . First, the substrate 102 is provided or received. The substrate 102 includes an n-type region 102N and a p-type region 102P, and the n-type region 102N is located above the p-type region 102P. Next, the first insulating layer 122 is formed on the n-type region 102N of the substrate 102 . Then, a groove 103 is formed in the substrate 102 as shown in FIG. is located in the n-type region 102N and part of the groove 103 is located in the p-type region 102P. In some embodiments, the n-type region 102N is a silicon substrate doped with boron atoms after ion implantation. In some embodiments, the p-type region 102P is a silicon substrate doped with phosphorus atoms after ion implantation. In some embodiments, the groove 103 is formed in the substrate 102 by etching the substrate 102 . In some embodiments, the substrate 102 further includes a source region 118 and a drain region 120, located on both sides of the groove 103, and located on both sides of the gate 108 to be formed in a subsequent process (for example, refer to FIG. 10 ). It should be noted that the positions of the source region 118 and the drain region 120 are only schematically shown in the figure, and details are referred to above, and will not be repeated here.

Operation 204, operation 206, and operation 208 in the method 200 for forming the semiconductor structure 100 in FIG. 2 are described in detail, and reference is made to FIG. 4 to FIG. 5 correspondingly.

First, in operation 204, a gate insulating layer 104 is formed to cover the surface 103S of the groove 103, wherein the gate insulating layer 104 has a first portion 104A and a second portion 104B as shown in FIGS. Portion 104B is located on first portion 104A. The gate insulating layer 104 spatially separates the source region 118 and the drain region 120 from the gate 108 to be formed in a subsequent process (eg, refer to FIG. 10 ). In some embodiments, the gate insulating layer 104 includes silicon dioxide and is formed by In-Situ Steam Generation (ISSG), which performs an in-situ rapid thermal annealing process on the surface of the groove 103 , using oxygen mixed with a small amount of hydrogen as the reaction gas, a chemical reaction similar to combustion is carried out on the surface of the substrate 102 at a high temperature, wherein a large amount of oxygen free radicals are generated, so that the silicon on the surface of the substrate 102 is rapidly oxidized into silicon dioxide, and Forming the gate insulating layer 104 as shown in FIGS. 4 to 5 , forming the gate insulating layer 104 by using the on-site steam generation technique is not only fast, but also has a small thermal budget and good temperature uniformity. In some embodiments, the first portion 104A of the gate insulating layer 104 is located in the p-type region 102P of the substrate 102 , and the second portion 104B of the gate insulating layer 104 is located in the n-type region 102N of the substrate 102 .

Next, in operation 206 , a first barrier layer 110 is formed on the first portion 104A of the gate insulating layer 104 . In some embodiments, as shown in FIG. 4 , the first barrier layer 110 is fully deposited on the gate insulating layer 104 in the groove 103 and on the substrate 102 outside the groove 103 . In some embodiments, the first barrier layer 110 includes titanium nitride, tungsten nitride, tantalum nitride or a combination thereof.

Then, in operation 208 , a conductive layer 106 is formed on the first barrier layer 110 , wherein the conductive layer 106 is spatially separated from the gate insulating layer 104 by the first barrier layer 110 . In some embodiments, the conductive layer 106 is fully deposited on the first barrier layer 110 as shown in FIG. 4 .

After operation 208, the method 200 of forming the semiconductor structure 100 of the present disclosure further includes removing the portion of the first barrier layer 110 formed in operation 206, and removing the portion of the conductive layer 106 formed in operation 208, as Figure 5 shows. In some embodiments, the first barrier layer 110 located on the second portion 104B and part of the first portion 104A of the gate insulating layer 104 is removed, and the first barrier layer 110 located outside the groove 103 is removed. , to form the first barrier layer 110 in the semiconductor structure 100 shown in FIG. 1 in FIG. 5 . In some embodiments, the conductive layer 106 located on the second portion 104B of the gate insulating layer 104 and part of the first portion 104A is removed, and the conductive layer 106 located outside the groove 103 is removed, so that in FIG. 5 The conductive layer 106 in the semiconductor structure 100 as shown in FIG. 1 is formed. In some embodiments, removing the above-mentioned portion of the first barrier layer 110 and the above-mentioned portion of the conductive layer 106 may be performed through an etching process at the same time, so that the remaining first barrier layer 110 and the remaining conductive layer 106 are as in the fifth step. flush as shown.

The operation 210 in the method 200 of forming the semiconductor structure 100 in FIG. 2 is described in detail, and referring to FIGS. 6 to 7 correspondingly, the second barrier layer 112 is formed to cover the upper surface 106S of the conductive layer 106 . In some embodiments, as shown in FIG. on the outer substrate 102, and in the subsequent process, as shown in FIG. The second barrier layer 112 outside the trench 103 is removed to form the second barrier layer 112 in the semiconductor structure 100 as shown in FIG. 1 . In some embodiments, the second barrier layer 112 includes titanium nitride, tungsten nitride, tantalum nitride or a combination thereof. In some embodiments, the material of the second barrier layer 112 is different from the material of the first barrier layer 110 . In some embodiments, the material of the second barrier layer 112 is the same as that of the first barrier layer 110 .

The first barrier layer 110, the conductive layer 106, and the second barrier layer 112 are formed through the above operations 206, 208, and 210, so that the first barrier layer 110 and the second barrier layer 112 jointly surround the conductive layer 106, and the conductive layer 106 is spaced apart from the gate insulating layer 104 to prevent impurities from the substrate 102 from diffusing into the conductive layer 106 to form pollution, and to space the conductive layer 106 from the gate 108 that will be formed in subsequent processes. separated (for example, refer to FIG. 10 ), to prevent the impurity of the gate 108 from diffusing into the conductive layer 106 to form pollution. In addition, the bonding ability between the first barrier layer 110 , the second barrier layer 112 and the conductive layer 106 is good, so as to prevent the conductive layer 106 from falling off from the semiconductor structure 100 .

Operation 212 and operation 214 in the method 200 for forming the semiconductor structure 100 in FIG. 2 are described in detail, and reference is made to FIG. 8 to FIG. 10 correspondingly.

First, in operation 212 , a first oxide layer 114 is formed on the second barrier layer 112 and the second portion 104B of the gate insulating layer 104 . In some embodiments, as shown in FIG. 8, the first oxide layer 114 is fully and conformally deposited on the second barrier layer 112 and the gate insulating layer 104 by atomic layer deposition (Atomic Layer Deposition, ALD). On the second part 104B of the gate insulating layer 104 and on the substrate 102 outside the groove 103, and in the subsequent process, as shown in FIG. 114, and remove the first oxide layer 114 on the remaining part RP of the second portion 104B of the gate insulating layer 104, and remove the first oxide layer 114 on the substrate 102 outside the groove 103, forming as The first oxide layer 114 in the semiconductor structure 100 shown in FIG. 1 . In some embodiments, the first oxide layer 114 includes silicon dioxide, silicon oxynitride, silicon nitride or a combination thereof.

Next, in operation 214 , the gate 108 is formed on the first oxide layer 114 , wherein the first oxide layer 114 surrounds the lower surface 108B and the sidewall 108S of the gate 108 . In some embodiments, the gate 108 is fully deposited on the first oxide layer 114 as shown in FIG. 9 , and the second portion located on the gate insulating layer 104 is reserved in a subsequent process as shown in FIG. 10 . The gate 108 on the portion P of 104B, and remove the gate 108 on the remaining portion RP of the second portion 104B of the gate insulating layer 104, and remove the gate 108 on the substrate 102 outside the groove 103, A gate 108 is formed in the semiconductor structure 100 as shown in FIG. 1 . In some embodiments, the gate 108 includes polysilicon and can be formed through a thermal annealing process. In some embodiments, removing the above-mentioned portion of the first oxide layer 114 and the above-mentioned portion of the gate electrode 108 may be performed through an etching process at the same time, so that the remaining first oxide layer 114 and the remaining gate electrode 108 are as in the tenth embodiment. flush as shown.

The operation 216 in the method 200 of forming the semiconductor structure 100 in FIG. 2 is described in detail, and correspondingly refer to FIG. 11 . A second oxide layer 116 is formed covering the upper surface 108U of the gate 108 . In some embodiments, as shown in FIG. 11 , the second oxide layer 116 is deposited on the first oxide layer 114 , the gate 108 and the gate fully and conformally by atomic layer deposition (Atomic Layer Deposition, ALD). On the remaining part RP of the second part 104B of the insulating layer 104 and on the substrate 102 outside the groove 103 . That is to say, in addition to the portion 116A of the second oxide layer 116 covering the upper surface 108U of the gate electrode 108, the second oxide layer 116 further includes a first extension portion 116B and a second extension portion 116C. Refer to the above for details, here I won't repeat them here. In some embodiments, the second oxide layer 116 includes silicon dioxide, silicon oxynitride, silicon nitride or a combination thereof. In some embodiments, the material of the first oxide layer 114 is different from the material of the second oxide layer 116 . In some embodiments, the material of the first oxide layer 114 is the same as that of the second oxide layer 116 . In some embodiments, after forming the second oxide layer 116 , it further includes forming a second insulating layer 124 on the second oxide layer 116 to form the semiconductor structure 100 as shown in FIG. 1 . In some embodiments, the second insulating layer 124 includes silicon nitride.

The first oxide layer 114, the gate electrode 108, and the second oxide layer 116 are formed by the above operation 212, operation 214, and operation 216, so that the first oxide layer 114 and the second oxide layer 116 jointly surround the gate electrode 108, and because the bonding ability between the first oxide layer 114, the second oxide layer 116 and the gate 108 is good, the gate 108 is prevented from falling off from the semiconductor structure 100, and the bonding tightness can be improved by the thermal annealing process (Example: performing a thermal annealing process after depositing the gate 108). In addition, because the second oxide layer 116 further includes the first extension portion 116B and the second extension portion 116C, the gate electrode 108 is more firmly positioned in the semiconductor structure 100 , details are referred to above, and will not be repeated here.

With the method 200 for forming a semiconductor structure described above, there is a first oxide layer 114 between the gate 108 and the second barrier layer 112, and a second oxide layer 116 is located on the gate 108, so that the gate 108 is solved. Due to the weak bonding ability between the gate electrode 108 and the second barrier layer 112 , the gate electrode 108 is detached from the semiconductor structure 100 and affects the function and operation of the word line. The semiconductor structure 100 formed by the above-described method 200 of forming a semiconductor structure allows the gate 108 to be more firmly located in the buried word line.

While the disclosure has been described in some detail in terms of some embodiments, other embodiments are possible, and the description of the embodiments contained herein should not limit the spirit and scope of the appended claims.

Various modifications and changes to this disclosure will occur to those having ordinary skill in the art without departing from the spirit and scope of this disclosure. For the aforementioned cases, the present disclosure also intends to cover the modifications and changes to the present disclosure, as long as these modifications and changes fall within the spirit and scope of the appended claims.

100: Semiconductor Structures

102: Substrate

102N: n-type region

102P: p-type region

103: Groove

103S: surface

104: Gate insulating layer

104A: Part I

104B: Part Two

106: Conductive layer

106S: upper surface

108: Gate

108B: lower surface

108S: side wall

108U: upper surface

110: The first barrier layer

112: Second barrier layer

114: first oxide layer

116: second oxide layer

116A: part

116B: first extension

116C: Second extension

118: source region

120: Drain area

122: The first insulating layer

124: Second insulating layer

200: method

202: Operation

204: Operation

206: Operation

208: Operation

210: Operation

212: Operation

214: Operation

216: Operation

A: Angle

P: part

RP: remainder

When reading the drawings that accompany this disclosure, it is suggested that the various aspects of the disclosure be understood from the following descriptions. It is to be noted that, in accordance with the standard practice in the industry, the dimensions of various features are not drawn to scale. The various feature dimensions may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 is a cross-sectional view of a semiconductor structure formed according to some embodiments of the present disclosure. FIG. 2 is a flowchart of a method of forming a semiconductor structure according to some embodiments of the present disclosure. 3-11 are cross-sectional views of intermediate processes in the formation of semiconductor structures according to some embodiments of the present disclosure.

Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

100: Semiconductor Structures

102: Substrate

102N: n-type region

102P: p-type region

103: Groove

103S: surface

104: Gate insulating layer

104A: Part I

104B: Part Two

106: Conductive layer

108: Gate

108B: lower surface

108S: side wall

108U: upper surface

110: The first barrier layer

112: Second barrier layer

114: first oxide layer

116: second oxide layer

116A: part

116B: first extension

116C: Second extension

118: source region

120: Drain area

122: The first insulating layer

124: Second insulating layer

A: Angle

P: part

RP: remainder

Claims (10)

A semiconductor structure, comprising: a substrate with a groove; a gate insulating layer covering a surface of the groove, wherein the gate insulating layer has a first portion and a second portion, and the second portion is located on the On the first part; a conductive layer, the first part of the gate insulating layer surrounds the conductive layer; a gate, the second part of the gate insulating layer surrounds the gate; a first barrier layer is located on the between the conductive layer and the gate insulating layer; a second barrier layer located between the conductive layer and the gate; a first oxide layer located on the second barrier layer and surrounding the gate The lower surface and sidewall of the first oxide layer completely separate the gate from the second barrier layer; and a second oxide layer covers an upper surface of the gate. The semiconductor structure of claim 1, wherein the first oxide layer and the second oxide layer directly contact the gate. The semiconductor structure as claimed in claim 1, wherein the second oxide layer further comprises a first extension higher than a portion of the second oxide layer covering the upper surface of the gate, and the first extension covering the second portion of the gate insulating layer. The semiconductor structure as claimed in claim 3, wherein the second The oxide layer further includes a second extension located outside the groove and on the substrate. The semiconductor structure according to claim 1, wherein the first oxide layer comprises silicon dioxide, silicon oxynitride, silicon nitride or a combination thereof, and the second oxide layer comprises silicon dioxide, silicon oxynitride, silicon nitride Silicon or a combination thereof, and the gate comprises polysilicon. The semiconductor structure according to claim 1 further includes a source region and a drain region located in the substrate and located on both sides of the gate. A method of forming a semiconductor structure, comprising: forming a groove in a substrate; forming a gate insulating layer covering a surface of the groove, wherein the gate insulating layer has a first portion and a second portion, the first Two parts are located on the first part; a first barrier layer is formed on the first part; a conductive layer is formed on the first barrier layer, wherein the conductive layer is connected by the first barrier layer and the gate The insulating layer is spaced apart; forming a second barrier layer covering an upper surface of the conductive layer; forming a first oxide layer on the second barrier layer and the second portion of the gate insulating layer; forming a gate on the first oxide layer, wherein the first oxide layer surrounding the lower surface and sidewall of the gate; and forming a second oxide layer to cover an upper surface of the gate. The method of claim 7, wherein forming the gate includes forming the gate in direct contact with the first oxide layer, and forming the second oxide layer includes forming the second oxide layer in direct contact with the gate touch. The method as claimed in claim 7, wherein when forming the second oxide layer, the second oxide layer further includes a first extension higher than the second oxide layer covering the upper surface of the gate A part, and the first extension part covers the second part of the gate insulating layer. The method as claimed in claim 9, wherein when forming the second oxide layer, the second oxide layer further includes a second extension portion outside the groove and on the substrate.

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