TWI809952B - Semiconductor device with multi-carbon-concentration dielectrics and method for fabricating the same - Google Patents
Semiconductor device with multi-carbon-concentration dielectrics and method for fabricating the same Download PDFInfo
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Abstract
Description
本申請案主張美國第17/740,527及17/741,365號專利申請案之優先權(即優先權日為「2022年5月10日」),其內容以全文引用之方式併入本文中。This application claims priority to US Patent Application Nos. 17/740,527 and 17/741,365 (ie, the priority date is "May 10, 2022"), the contents of which are incorporated herein by reference in their entirety.
本揭露涉及一種半導體元件及其製備方法,更具體地,涉及一種具有多重碳濃度介電層的半導體元件及其製備方法。The present disclosure relates to a semiconductor element and a manufacturing method thereof, more particularly, to a semiconductor element having multiple carbon-concentrated dielectric layers and a manufacturing method thereof.
半導體元件被用於各種電子應用中,例如個人計算機,行動電話,數位相機和其他電子設備。為滿足對計算能力不斷增長的需求,半導體元件的尺寸不斷地縮小。然而,縮小尺寸導致了製程中出現各種問題,並且這些問題更不斷衍生出不同狀況。因此,在提高半導體元件的性能、質量、良率和可靠性以及降低複雜度等方面仍然面臨挑戰。Semiconductor components are used in various electronic applications such as personal computers, mobile phones, digital cameras and other electronic devices. To meet the ever-increasing demand for computing power, the dimensions of semiconductor components continue to shrink. However, the shrinking size has caused various problems in the process, and these problems have continuously spawned different situations. Therefore, challenges remain in improving the performance, quality, yield, and reliability of semiconductor devices, and reducing complexity.
上文之「先前技術」說明僅係提供背景技術,並未承認上文之「先前技術」說明揭示本揭露之標的,不構成本揭露之先前技術,且上文之「先前技術」之任何說明均不應作為本案之任一部分。The above "prior art" description is only to provide background technology, and does not acknowledge that the above "prior art" description discloses the subject of this disclosure, and does not constitute the prior art of this disclosure, and any description of the above "prior art" shall not form part of this case.
本發明的一個方面提供了一種半導體元件,包括一第一絕緣層,設置於一基底上;一底部插塞,設置於該第一絕緣層中;一底部介電層、一下中間介電層、上中間介電層及一頂部介電層,依序堆疊於該第一絕緣層上;及一導電結構包括一底部部分,設置於該底部介電層中及位於該底部插塞上,一下中間部分,設置於該底部部分上及位於該下中間介電層中,一上中間部分,設置於該下中間部分上及位於該上中間介電層中,及一頂部部分,設置於該上中間部分上及位於該頂部介電層中。該下中間介電層的碳濃度大於該底部介電層的碳濃度。One aspect of the present invention provides a semiconductor device, including a first insulating layer disposed on a substrate; a bottom plug disposed in the first insulating layer; a bottom dielectric layer, a lower intermediate dielectric layer, an upper middle dielectric layer and a top dielectric layer are sequentially stacked on the first insulating layer; and a conductive structure includes a bottom portion disposed in the bottom dielectric layer and on the bottom plug, one in the middle part, disposed on the bottom part and in the lower intermediate dielectric layer, an upper middle part, disposed on the lower middle part and in the upper middle dielectric layer, and a top part, disposed in the upper middle partially on and in the top dielectric layer. The carbon concentration of the lower middle dielectric layer is greater than the carbon concentration of the bottom dielectric layer.
本發明的另一方面提供了一種半導體元件,包括一第一絕緣層,設置於一基底上;一底部插塞,設置於該第一絕緣層中;一底部介電層、一下中間介電層、上中間介電層及一頂部介電層,依序堆疊於該第一絕緣層上;及一導電結構包括一底部部分,設置於該底部介電層中及位於該底部插塞上,一下中間部分,設置於該底部部分上及位於該下中間介電層中,一上中間部分,設置於該下中間部分上及位於該上中間介電層中,及一頂部部分,設置於該上中間部分上及位於該頂部介電層中。該上中間介電層的碳濃度大於該底部介電層的碳濃度。Another aspect of the present invention provides a semiconductor device, including a first insulating layer disposed on a substrate; a bottom plug disposed in the first insulating layer; a bottom dielectric layer, a lower intermediate dielectric layer , an upper middle dielectric layer and a top dielectric layer are sequentially stacked on the first insulating layer; and a conductive structure includes a bottom portion disposed in the bottom dielectric layer and on the bottom plug, once a middle portion disposed on the bottom portion and in the lower intermediate dielectric layer, an upper middle portion disposed on the lower middle portion and in the upper intermediate dielectric layer, and a top portion disposed on the upper The middle portion is on and in the top dielectric layer. The carbon concentration of the upper middle dielectric layer is greater than the carbon concentration of the bottom dielectric layer.
本發明的另一方面提供一種製備半導體元件的方法,包括形成一第一絕緣層於一基底上;形成一底部插塞於該第一絕緣層中;依次形成一底部介電層、一下中間介電層、一上中間介電層及一頂部介電層於該第一絕緣層上;進行一開口蝕刻製程,以形成沿該頂部介電層、該上中間介電層、該下中間介電層及該底部介電層的一開口,並藉以暴露該底部插塞;及形成一導電結構於該開口中。該下中間介電層的碳濃度大於該底部介電層的碳濃度。Another aspect of the present invention provides a method for preparing a semiconductor device, comprising forming a first insulating layer on a substrate; forming a bottom plug in the first insulating layer; sequentially forming a bottom dielectric layer, a lower interposer An electrical layer, an upper intermediate dielectric layer, and a top dielectric layer are on the first insulating layer; an opening etching process is performed to form the top dielectric layer, the upper intermediate dielectric layer, and the lower intermediate dielectric layer layer and an opening of the bottom dielectric layer, thereby exposing the bottom plug; and forming a conductive structure in the opening. The carbon concentration of the lower middle dielectric layer is greater than the carbon concentration of the bottom dielectric layer.
由於本公開的半導體元件的設計,通過對絕緣堆疊的不同層採用不同的碳濃度,即使對絕緣堆疊的不同層使用相同的蝕刻化學也可以控制臨界尺寸,結果,可以改善導電結構對底部插塞的覆蓋此外,由於導電結構的上中間部分臨界尺寸較小,源自相鄰導電結構的寄生電容可以保持在低水平。Due to the design of the semiconductor element of the present disclosure, by using different carbon concentrations for different layers of the insulating stack, the critical dimension can be controlled even if the same etch chemistry is used for the different layers of the insulating stack. As a result, the conductive structure can be improved. In addition, due to the small critical dimension of the upper middle part of the conductive structure, the parasitic capacitance originating from the adjacent conductive structure can be kept at a low level.
上文已相當廣泛地概述本揭露之技術特徵及優點,俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解,可相當容易地利用下文揭示之概念與特定實施例可作為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解,這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。The technical features and advantages of the present disclosure have been broadly summarized above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the disclosure defined by the appended claims.
本揭露之以下說明伴隨併入且組成說明書之一部分的圖式,說明本揭露之實施例,然而本揭露並不受限於該實施例。此外,以下的實施例可適當整合以下實施例以完成另一實施例。The following description of the disclosure, accompanied by the drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the disclosure, however, the disclosure is not limited to such embodiments. In addition, the following embodiments can be properly integrated to complete another embodiment.
「一實施例」、「實施例」、「例示實施例」、「其他實施例」、「另一實施例」等係指本揭露所描述之實施例可包含特定特徵、結構或是特性,然而並非每一實施例必須包含該特定特徵、結構或是特性。再者,重複使用「在實施例中」一語並非必須指相同實施例,然而可為相同實施例。"An embodiment," "an embodiment," "an exemplary embodiment," "another embodiment," "another embodiment" and the like refer to embodiments described in the present disclosure that may include a particular feature, structure, or characteristic, but Not every embodiment must include the particular feature, structure or characteristic. Also, repeated use of the phrase "in an embodiment" does not necessarily refer to the same embodiment, but could be the same embodiment.
為了使得本揭露可被完全理解,以下說明提供詳細的步驟與結構。顯然,本揭露的實施不會限制該技藝中的技術人士已知的特定細節。此外,已知的結構與步驟不再詳述,以免不必要地限制本揭露。本揭露的較佳實施例詳述如下。然而,除了詳細說明之外,本揭露亦可廣泛實施於其他實施例中。本揭露的範圍不限於詳細說明的內容,而是由申請專利範圍定義。In order to make the present disclosure fully understandable, the following description provides detailed steps and structures. Obviously, practice of the present disclosure is not limited to specific details known to those skilled in the art. In addition, known structures and steps are not described in detail so as not to limit the present disclosure unnecessarily. Preferred embodiments of the present disclosure are described in detail as follows. However, the present disclosure may be broadly implemented in other embodiments than those described in detail. The scope of the present disclosure is not limited to the content of the detailed description, but is defined by the claims.
在本揭露中,半導體元件通常是指可以通過利用半導體特性來起作用的裝置。如電光裝置、發光顯示裝置、半導體電路和電子裝置都將包括在半導體元件的類別中。In the present disclosure, a semiconductor element generally refers to a device that can function by utilizing semiconductor characteristics. Such as electro-optical devices, light-emitting display devices, semiconductor circuits and electronic devices will be included in the category of semiconductor components.
需要說明的是,在本發明的描述中,之上(或上)對應於Z方向的箭頭方向,之下(或下)對應於Z方向箭頭的相反方向。It should be noted that, in the description of the present invention, above (or up) corresponds to the direction of the arrow in the Z direction, and below (or down) corresponds to the opposite direction of the arrow in the Z direction.
圖1為流程圖,例示本揭露一實施例的一種半導體元件1A的製備方法10。圖2至圖6為剖面示意圖,例示本揭露一實施例之製備半導體元件的部分流程。圖7例示形成本揭露一實施例之第一阻障層的製程條件。FIG. 1 is a flowchart illustrating a method 10 for manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. 2 to 6 are schematic cross-sectional views illustrating a part of the process for preparing a semiconductor device according to an embodiment of the present disclosure. FIG. 7 illustrates the process conditions for forming the first barrier layer according to an embodiment of the present disclosure.
參照圖1及圖2,於步驟S11,提供一基底101,形成一第一絕緣層103在基底101上,形成多個底部插塞105在第一絕緣層103中,形成一絕緣堆疊200於第一絕緣層103上,及形成一硬遮罩層501於絕緣堆疊200上。1 and 2, in step S11, a substrate 101 is provided, a first insulating layer 103 is formed on the substrate 101, a plurality of bottom plugs 105 are formed in the first insulating layer 103, and an insulating stack 200 is formed on the first insulating layer 103. An insulating layer 103 is formed, and a hard mask layer 501 is formed on the insulating stack 200 .
參照圖2,基底101包括完全由至少一種半導體材料構成的塊狀半導體基底、多個裝置元件(為清楚起見未示出)、多個介電層(為清楚起見未示出)和多個導電特徵(為清楚起見未示出)。塊狀半導體基底係由如矽或鍺的半導體元素所形成;或由矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、銻化銦、或其他III-V族或II-VI族半導體材料等半導體化合物所形成;或由上述組合所形成。Referring to FIG. 2, substrate 101 includes a bulk semiconductor substrate composed entirely of at least one semiconductor material, a plurality of device elements (not shown for clarity), a plurality of dielectric layers (not shown for clarity), and multiple conductive features (not shown for clarity). Bulk semiconductor substrates are formed from semiconductor elements such as silicon or germanium; or from silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other III-V group Or formed by semiconductor compounds such as II-VI semiconductor materials; or formed by the above-mentioned combination.
在一些實施例中,基底101包括絕緣體上半導體結構,其從底部到頂部由處理基底、絕緣體層和最頂部半導體材料層組成。處理基底和最頂部半導體材料層由與上述塊狀半導體基底相同的材料所形成。絕緣體層為結晶或非結晶介電材料,例如氧化物和/或氮化物。例如,絕緣體層為介電氧化物,如氧化矽。又例如,絕緣體層為介電氮化物,如氮化矽或氮化硼。再例如,絕緣體層包括介電氧化物和介電氮化物的堆疊,如以任意順序堆疊的氧化矽及氮化矽或氮化硼。絕緣體層具有約10奈米和200奈米之間的厚度。In some embodiments, the substrate 101 includes a semiconductor-on-insulator structure consisting, from bottom to top, of a handle substrate, an insulator layer, and a topmost layer of semiconductor material. The handle substrate and the topmost semiconductor material layer are formed from the same material as the bulk semiconductor substrate described above. The insulator layer is a crystalline or amorphous dielectric material, such as oxide and/or nitride. For example, the insulator layer is a dielectric oxide, such as silicon oxide. For another example, the insulator layer is a dielectric nitride, such as silicon nitride or boron nitride. As another example, the insulator layer includes a stack of dielectric oxide and dielectric nitride, such as silicon oxide and silicon nitride or boron nitride stacked in any order. The insulator layer has a thickness between about 10 nanometers and 200 nanometers.
於本揭露中,用於修飾成分(ingredient)、部件(component)、反應物的量(quantity )之術語「約」或「約當」係指例如通過用於製備濃縮物或溶液的典型測量和液體處理程序可能發生的數值變化。此外,變化亦可能源自量測程序中的非故意失誤、製造組合物或實施方法時等情況中所使用之成分的製造、來源或純度上之差異。在一些方面,術語「約」或「約當」係指所示數值10%以內之變化。在另一些方面,術語「大約」或「約當」係指所示數值5%以內之變化。在其他方面,術語「大約」或「約當」係指所示數值10%、9%、8%、7%、6%、5%、4%、3%、2%或 1%以內之變化。In this disclosure, the term "about" or "about" used to modify the amount of an ingredient, component, or reactant means, for example, by typical measurements used to prepare concentrates or solutions and Possible numerical changes for liquid handlers. In addition, variations may also arise from inadvertent errors in measurement procedures, differences in the manufacture, source or purity of ingredients used in making compositions or performing methods, etc. In some aspects, the term "about" or "about" refers to a variation of within 10% of the stated numerical value. In other aspects, the term "about" or "about" refers to a variation of within 5% of the stated value. In other respects, the term "about" or "about" means a variation of within 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, or 1% of the stated value .
參照圖2,裝置元件形成於塊狀半導體基底或最頂部半導體材料層上。裝置元件的一些部分形成於塊狀半導體基底中或最頂部半導體材料層中。裝置元件為晶體管,例如互補金屬氧化物半導體晶體管、金屬氧化物半導體場效應晶體管、鰭式場效應晶體管等、或其組合。Referring to FIG. 2, device elements are formed on a bulk semiconductor substrate or topmost layer of semiconductor material. Portions of the device elements are formed in the bulk semiconductor substrate or in the topmost layer of semiconductor material. The device element is a transistor, such as a CMOS transistor, a MOSFET, a FinFET, etc., or a combination thereof.
參照圖2,介電層形成於塊狀半導體基底或最頂部半導體材料層上,並覆蓋裝置元件。在一些實施例中,介電層由如氧化矽、硼磷矽酸鹽玻璃、未摻雜的矽酸鹽玻璃、氟化矽酸鹽玻璃、低介電常數介電材料等、或其組合所形成。低介電常數介電材料的介電常數小於3.0甚至小於2.5。在一些實施例中,低介電常數介電材料的介電常數小於2.0。介電層通過如化學氣相沉積、電漿增強化學氣相沉積等的沉積製程形成。沉積製程後執行平坦化製程,以去除多餘的材料,並為後續處理步驟提供實質上平坦的表面。Referring to FIG. 2 , a dielectric layer is formed on the bulk semiconductor substrate or the topmost semiconductor material layer and covers the device components. In some embodiments, the dielectric layer is made of silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric materials, etc., or combinations thereof. form. The dielectric constant of the low dielectric constant dielectric material is less than 3.0 or even less than 2.5. In some embodiments, the dielectric constant of the low-k dielectric material is less than 2.0. The dielectric layer is formed by deposition processes such as chemical vapor deposition, plasma enhanced chemical vapor deposition, and the like. A planarization process is performed after the deposition process to remove excess material and provide a substantially planar surface for subsequent processing steps.
參照圖2,導電特徵包括多個互連層和多個導電通孔。互連層間彼此分離並且沿著方向Z水平地設置於介電層中。導電通孔連接沿著方向Z相鄰的互連層以及連接相鄰的裝置元件及互連層。在一些實施例中,導電通孔可以改善散熱且可以提供結構支撐。在一些實施例中,導電特徵由如鎢、鈷、鋯、鉭、鈦、鋁、釕、銅、金屬碳化物(例如,碳化鉭、碳化鈦、碳化鉭鎂)、金屬形成氮化物(例如氮化鈦)、過渡金屬鋁化物、或其組合所形成。導電特徵於形成介電層期間形成。Referring to FIG. 2 , the conductive features include a plurality of interconnect layers and a plurality of conductive vias. The interconnection layers are separated from each other and arranged horizontally in the dielectric layer along the direction Z. The conductive vias connect adjacent interconnect layers along direction Z and connect adjacent device elements and interconnect layers. In some embodiments, conductive vias can improve heat dissipation and can provide structural support. In some embodiments, the conductive features are formed from metals such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal-forming nitrides (e.g., nitrogen titanium oxide), transition metal aluminides, or combinations thereof. The conductive features are formed during the formation of the dielectric layer.
在一些實施例中,裝置元件和導電特徵一起構成基底101中的多個功能單元。在本揭示的描述中,功能單元通常是指出於功能目的而被劃分為不同單元的功能相關電路。在一些實施例中,功能單元通常是高度複雜的電路,例如處理器內核、存儲器控制器、或加速器單元。在一些其他實施例中,功能單元的複雜性和作用性的程度可視實際需求而定。In some embodiments, device elements and conductive features together constitute multiple functional units in substrate 101 . In the description of the present disclosure, functional units generally refer to functionally related circuits that are divided into different units for functional purposes. In some embodiments, functional units are typically highly complex circuits such as processor cores, memory controllers, or accelerator units. In some other embodiments, the degree of complexity and functionality of the functional units may depend on actual needs.
參照圖2,第一絕緣層103形成於基底101上且由如二氧化矽、未摻雜的矽酸鹽玻璃、氟矽酸鹽玻璃、硼磷矽酸鹽玻璃、旋塗低介電常數介電層、化學氣相沉積低介電常數介電層、或其組合所形成。在一些實施例中,第一絕緣層103包括如旋塗玻璃的自平坦化材料或如SiLK TM的旋塗低介電常數介電材料。使用自平坦化介電材料可以避免執行後續平坦化製程的需要。在一些實施例中,第一絕緣層103可以通過沉積製程形成,包括如化學氣相沉積、等離子體增強化學氣相沉積、蒸鍍、或旋塗。在一些實施例中,可以執行平坦化製程,例如化學機械拋光,以為後續處理步驟提供實質上平坦的表面。Referring to FIG. 2, the first insulating layer 103 is formed on the substrate 101 and is made of silicon dioxide, undoped silicate glass, fluorosilicate glass, borophosphosilicate glass, spin-coated low-k dielectric Electrical layer, chemical vapor deposition low-k dielectric layer, or a combination thereof. In some embodiments, the first insulating layer 103 includes a self-planarizing material such as spin-on-glass or a spin-on low-k dielectric material such as SiLK™. Using a self-planarizing dielectric material can avoid the need to perform a subsequent planarization process. In some embodiments, the first insulating layer 103 can be formed by a deposition process, including, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, evaporation, or spin coating. In some embodiments, a planarization process, such as chemical mechanical polishing, may be performed to provide a substantially planar surface for subsequent processing steps.
參照圖2,底部插塞105沿著第一絕緣層103形成,且通過基底101的對應導電特徵電耦合到基底101的裝置元件。在一些實施例中,底部插塞105由如鎢、鈷、鋯、鉭、鈦、鋁、釕、銅、金屬碳化物(例如,碳化鉭、碳化鈦、碳化鉭鎂)、金屬氮化物(例如氮化鈦)、過渡金屬鋁化物、或其組合所形成。底部插塞105通過如嵌入式製程或其他可應用的製程來形成。Referring to FIG. 2 , bottom plugs 105 are formed along first insulating layer 103 and are electrically coupled to device elements of substrate 101 through corresponding conductive features of substrate 101 . In some embodiments, bottom plug 105 is made of materials such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g. titanium nitride), transition metal aluminides, or combinations thereof. The bottom plug 105 is formed by, for example, an embedded process or other applicable processes.
參照圖2,絕緣堆疊200包括一底部介電層201、一下中間介電層203、一上中間介電層205及一頂部介電層207。Referring to FIG. 2 , the insulating stack 200 includes a bottom dielectric layer 201 , a lower intermediate dielectric layer 203 , an upper intermediate dielectric layer 205 and a top dielectric layer 207 .
參照圖2,底部介電層201形成於第一絕緣層103上。在一些實施例中,底部介電層201由如二氧化矽、未摻雜的矽酸鹽玻璃、氟矽酸鹽玻璃、硼磷矽酸鹽玻璃、氮化矽、氧氮化矽、氮氧化矽、磷矽酸鹽玻璃、或其組合所形成。在一些實施例中,底部介電層201為高介電常數介電材料(介電常數大於7.0),包括但不限於金屬氧化物,如氧化鉿、氧化鉿矽、鉿矽氧氮化物、鑭氧化物、鑭鋁氧化物、鋯氧化物、鋯矽氧化物、鋯矽氧氮化物、鉭氧化物、鈦氧化物、鋇鍶鈦氧化物、鋇鈦氧化物、鍶鈦氧化物、釔氧化物、氧化鋁、鉛鈧鉭氧化物、及鉛鋅鈮酸鹽。在本實施例中,底部介電層201為氧化矽或氮化矽。Referring to FIG. 2 , a bottom dielectric layer 201 is formed on the first insulating layer 103 . In some embodiments, the bottom dielectric layer 201 is made of silicon dioxide, undoped silicate glass, fluorosilicate glass, borophosphosilicate glass, silicon nitride, silicon oxynitride, oxynitride silicon, phosphosilicate glass, or a combination thereof. In some embodiments, the bottom dielectric layer 201 is a high-k dielectric material (dielectric constant greater than 7.0), including but not limited to metal oxides, such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum Oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide , alumina, lead scandium tantalum oxide, and lead zinc niobate. In this embodiment, the bottom dielectric layer 201 is silicon oxide or silicon nitride.
參照圖2,下中間介電層203形成於底部介電層201上。在一些實施例中,下中間介電層203由如碳摻雜氧化物或有機矽酸鹽玻璃形成。在一些實施例中,下中間介電層203由如旋塗低介電常數介電層、化學氣相沉積低介電常數介電層、多孔聚合物材料、或其組合所形成。Referring to FIG. 2 , a lower intermediate dielectric layer 203 is formed on the bottom dielectric layer 201 . In some embodiments, the lower interlayer dielectric layer 203 is formed of, for example, carbon-doped oxide or organosilicate glass. In some embodiments, the lower interlayer dielectric layer 203 is formed by spin-coating low-k dielectric layer, chemical vapor deposition low-k dielectric layer, porous polymer material, or a combination thereof.
參照圖2,上中間介電層205形成於下中間介電層203上。在一些實施例中,上中間介電層205由如碳摻雜氧化物或有機矽酸鹽玻璃形成。在一些實施例中,上中間介電層205由如旋塗低介電常數介電層、化學氣相沉積低介電常數介電層、多孔聚合物材料、或其組合所形成。Referring to FIG. 2 , an upper intermediate dielectric layer 205 is formed on the lower intermediate dielectric layer 203 . In some embodiments, the upper interlayer dielectric layer 205 is formed of, for example, carbon-doped oxide or organosilicate glass. In some embodiments, the upper interlayer dielectric layer 205 is formed by, for example, spin-coated low-k dielectric layer, chemical vapor deposition low-k dielectric layer, porous polymer material, or a combination thereof.
參照圖2,頂部介電層207形成於上中間介電層205上。在一些實施例中,頂部介電層207由如碳摻雜氧化物或有機矽酸鹽玻璃形成。在一些實施例中,頂部介電層207由如旋塗低介電常數介電層、化學氣相沉積低介電常數介電層、多孔聚合物材料、或其組合所形成。在一些實施例中,下中間介電層203及頂部介電層207由相同的材料所形成。Referring to FIG. 2 , a top dielectric layer 207 is formed on the upper middle dielectric layer 205 . In some embodiments, the top dielectric layer 207 is formed of, for example, carbon doped oxide or organosilicate glass. In some embodiments, the top dielectric layer 207 is formed by, for example, spin-coated low-k dielectric layer, chemical vapor deposited low-k dielectric layer, porous polymer material, or a combination thereof. In some embodiments, the lower middle dielectric layer 203 and the top dielectric layer 207 are formed of the same material.
在一些實施例中,下中間介電層203、上中間介電層205及頂部介電層207為通過將能量可去除材料(energy-removable material)暴露於如熱、光或其組合的能量源而形成的多孔層。當使用熱作為能量源時,能量處理的溫度在約800℃和約900℃之間。當使用光作為能源時,可以使用紫外光。In some embodiments, the lower interlayer dielectric layer 203, the upper interlayer dielectric layer 205, and the top dielectric layer 207 are formed by exposing the energy-removable material to an energy source such as heat, light, or a combination thereof. to form a porous layer. When heat is used as the energy source, the temperature of the energy treatment is between about 800°C and about 900°C. When using light as an energy source, ultraviolet light can be used.
在一些實施例中,多孔層包括骨架和設置在骨架之間的多個空間。空間之間可相互連接且充滿空氣。骨架包括低介電材料或甲基倍半矽氧烷(methylsilsesquioxane)。多孔層具有25%至75%之間的孔隙率。由於前述空間,多孔層充滿空氣,結果,多孔層的介電常數將顯著低於由例如氧化矽所形成的層。因此,多孔層將顯著降低形成於其中的導電特徵之間的寄生電容。In some embodiments, the porous layer includes skeletons and a plurality of spaces disposed between the skeletons. Spaces are interconnected and filled with air. The frame includes low dielectric material or methylsilsesquioxane. The porous layer has a porosity between 25% and 75%. Due to the aforementioned spaces, the porous layer is filled with air and, as a result, the dielectric constant of the porous layer will be significantly lower than a layer formed of, for example, silicon oxide. Thus, the porous layer will significantly reduce the parasitic capacitance between conductive features formed therein.
在一些實施例中,能量可去除材料包括如熱可分解材料、光子可分解材料、電子束可分解材料、或其組合。例如,能量可去除材料包括基材和可分解的致孔劑材料,致孔劑材料在暴露於能量源時被犧牲性地移除。在一些實施例中,可分解的致孔劑材料包括致孔劑有機化合物,其賦予孔隙率於能量可去除材料的基材。In some embodiments, energy-removable materials include, for example, thermally decomposable materials, photon-decomposable materials, electron beam-decomposable materials, or combinations thereof. For example, an energy-removable material includes a substrate and a decomposable porogen material that is sacrificially removed upon exposure to an energy source. In some embodiments, the decomposable porogen material includes a porogen organic compound that imparts porosity to the substrate of the energy-removable material.
在一些實施例中,下中間介電層203(或頂部介電層207)的孔隙率大於上中間介電層205的孔隙率。在一些實施例中,下中間介電層203的孔隙率和頂部介電層207的孔隙率實質地相同。在一些實施例中,下中間介電層203的孔隙率和頂部介電層207的孔隙率不同。例如,頂部介電層207的孔隙率大於下中間介電層203的孔隙率。In some embodiments, the porosity of the lower intermediate dielectric layer 203 (or the top dielectric layer 207 ) is greater than the porosity of the upper intermediate dielectric layer 205 . In some embodiments, the porosity of the lower middle dielectric layer 203 and the porosity of the top dielectric layer 207 are substantially the same. In some embodiments, the porosity of the lower middle dielectric layer 203 and the porosity of the top dielectric layer 207 are different. For example, the porosity of the top dielectric layer 207 is greater than that of the lower middle dielectric layer 203 .
參照圖2,在一些實施例中,下中間介電層203(或頂部介電層207)的碳濃度大於上中間介電層205的碳濃度。上中間介電層205的碳濃度大於底部介電層201的碳濃度。在一些實施例中,下中間介電層203的碳濃度和頂部介電層207的碳濃度實質地相同。在一些實施例中,下中間介電層203的碳濃度和頂部介電層207的碳濃度不同。例如,下中間介電層203的碳濃度大於或小於頂部介電層207的碳濃度。Referring to FIG. 2 , in some embodiments, the carbon concentration of the lower intermediate dielectric layer 203 (or the top dielectric layer 207 ) is greater than the carbon concentration of the upper intermediate dielectric layer 205 . The carbon concentration of the upper middle dielectric layer 205 is greater than that of the bottom dielectric layer 201 . In some embodiments, the carbon concentration of the lower interlayer dielectric layer 203 and the carbon concentration of the top dielectric layer 207 are substantially the same. In some embodiments, the carbon concentration of the lower interlayer dielectric layer 203 and the carbon concentration of the top dielectric layer 207 are different. For example, the carbon concentration of the lower middle dielectric layer 203 is greater than or less than the carbon concentration of the top dielectric layer 207 .
參照圖2,在一些實施例中,下中間介電層203(或頂部介電層207)的介電常數小於上中間介電層205的介電常數。上中間介電層205的介電常數小於底部介電層201的介電常數。Referring to FIG. 2 , in some embodiments, the dielectric constant of the lower intermediate dielectric layer 203 (or the top dielectric layer 207 ) is smaller than the dielectric constant of the upper intermediate dielectric layer 205 . The dielectric constant of the upper middle dielectric layer 205 is smaller than that of the bottom dielectric layer 201 .
參照圖2,在一些實施例中,下中間介電層203的厚度T1小於上中間介電層205的厚度T2。在一些實施例中,厚度T2大於頂部介電層207的厚度T3。Referring to FIG. 2 , in some embodiments, the thickness T1 of the lower intermediate dielectric layer 203 is smaller than the thickness T2 of the upper intermediate dielectric layer 205 . In some embodiments, the thickness T2 is greater than the thickness T3 of the top dielectric layer 207 .
在一些實施例中,下中間介電層203的厚度T1和頂部介電層207的厚度T3實質地相同。在一些實施例中,下中間介電層203的厚度T1和頂部介電層207的厚度T3不同。例如,下中間介電層203的厚度T1大於頂部介電層207的厚度T3。In some embodiments, the thickness T1 of the lower middle dielectric layer 203 and the thickness T3 of the top dielectric layer 207 are substantially the same. In some embodiments, the thickness T1 of the lower middle dielectric layer 203 is different from the thickness T3 of the top dielectric layer 207 . For example, the thickness T1 of the lower middle dielectric layer 203 is greater than the thickness T3 of the top dielectric layer 207 .
在一些實施例中,下中間介電層203的厚度T1和底部介電層201的厚度T4實質地相同。在一些實施例中,下中間介電層203的厚度T1和底部介電層201的厚度T4不同。例如,底部介電層201的厚度T4大於下中間介電層203的厚度T1。In some embodiments, the thickness T1 of the lower intermediate dielectric layer 203 and the thickness T4 of the bottom dielectric layer 201 are substantially the same. In some embodiments, the thickness T1 of the lower intermediate dielectric layer 203 is different from the thickness T4 of the bottom dielectric layer 201 . For example, the thickness T4 of the bottom dielectric layer 201 is greater than the thickness T1 of the lower intermediate dielectric layer 203 .
參照圖2,硬遮罩層501形成於頂部介電層207上。在一些實施例中,硬遮罩層501由如氮化硼、氮化硼矽、磷氮化硼、硼碳氮化矽等所形成。硬遮罩層501可通過成膜製程及處理製程形成。詳細地,於成膜製程中,可於頂部介電層207上方引入第一前驅物以形成一硼基層,第一前驅物為基於硼的前驅物。隨後,在處理製程中,可引入第二前驅物以與硼基層反應,且將硼基層轉變為硬遮罩層501,第二前驅物為基於氮的前驅物。在一些實施例中,第一前驅物為如乙硼烷、環硼氮烷或環硼氮烷的烷基取代的硼衍生物。在一些實施例中,第二前驅物為例如氨或肼。Referring to FIG. 2 , a hard mask layer 501 is formed on top dielectric layer 207 . In some embodiments, the hard mask layer 501 is formed of boron nitride, silicon boron nitride, boron phosphorus nitride, silicon boron carbon nitride, and the like. The hard mask layer 501 can be formed by a film forming process and a treatment process. In detail, in the film forming process, a first precursor can be introduced above the top dielectric layer 207 to form a boron-based layer, and the first precursor is a boron-based precursor. Subsequently, in the treatment process, a second precursor may be introduced to react with the boron-based layer and transform the boron-based layer into a hard mask layer 501 , the second precursor being a nitrogen-based precursor. In some embodiments, the first precursor is, for example, diborane, borazine, or an alkyl-substituted boron derivative of borazine. In some embodiments, the second precursor is, for example, ammonia or hydrazine.
參照圖1、3及4,於步驟S13,圖案化硬遮罩層501以形成多個硬遮罩開口503。Referring to FIGS. 1 , 3 and 4 , in step S13 , the hard mask layer 501 is patterned to form a plurality of hard mask openings 503 .
參照圖3,於硬遮罩層501上形成一遮罩層505。遮罩層505為光刻膠層,且包括硬遮罩開口503的圖案。Referring to FIG. 3 , a mask layer 505 is formed on the hard mask layer 501 . The mask layer 505 is a photoresist layer and includes a pattern of hard mask openings 503 .
參照圖4,執行一硬遮罩蝕刻製程去除硬遮罩層501的部分以形成硬遮罩開口503。頂部介電層207的部分將通過硬遮罩開口503暴露。於形成硬遮罩開口503後,遮罩層505可通過例如灰化製程或其他可應用的製程移除。Referring to FIG. 4 , a hard mask etch process is performed to remove portions of the hard mask layer 501 to form hard mask openings 503 . Portions of the top dielectric layer 207 will be exposed through the hard mask opening 503 . After the hard mask opening 503 is formed, the mask layer 505 can be removed by, for example, an ashing process or other applicable processes.
參照圖1及5,於步驟S15,沿著絕緣堆疊200形成多個開口400以暴露底部插塞105。Referring to FIGS. 1 and 5 , in step S15 , a plurality of openings 400 are formed along the insulating stack 200 to expose the bottom plugs 105 .
為了描述的簡潔、清楚和方便起見,僅描述了一個開口400。For brevity, clarity and convenience of description, only one opening 400 is depicted.
參照圖5,進行一開口蝕刻製程去除頂部介電層207、上中間介電層205、下中間中介電層203及底部介電層201的部分,以形成開口400。在一些實施例中,於開口蝕刻製程期間,頂部介電層207、上中間介電層205及下中間介電層203的蝕刻化學(etching chemistries)係相同。然而,於開口蝕刻製程中,上中間介電層205的蝕刻速率與頂部介電層207(或下中間介電層203)的蝕刻速率係不同。在一些實施例中,開口蝕刻製程期間的蝕刻速率與對應層的碳濃度有關。例如,對下中間介電層203(具有較高碳濃度)的蝕刻速率高於對上中間介電層205(具有較低碳濃度)的蝕刻速率。Referring to FIG. 5 , an opening etching process is performed to remove portions of the top dielectric layer 207 , the upper intermediate dielectric layer 205 , the lower intermediate dielectric layer 203 and the bottom dielectric layer 201 to form openings 400 . In some embodiments, the etching chemistries of the top dielectric layer 207 , the upper ILD layer 205 , and the lower ILD layer 203 are the same during the opening etch process. However, in the opening etching process, the etching rate of the upper interlayer dielectric layer 205 is different from the etching rate of the top dielectric layer 207 (or the lower interlayer dielectric layer 203 ). In some embodiments, the etch rate during the opening etch process is related to the carbon concentration of the corresponding layer. For example, the etch rate of the lower ILD layer 203 (with a higher carbon concentration) is higher than the etch rate of the upper ILD layer 205 (with a lower carbon concentration).
因此,開口400的最終輪廓將與不同層的蝕刻速率有關。例如,對於具有較高碳濃度的頂部介電層207(或下中間介電層203),較高的蝕刻速率可導致橫向擴展的擴展側壁輪廓。相反地,對於具有較低碳濃度的上中間介電層205,較低的蝕刻速率將導致類雙曲線的側壁輪廓。Therefore, the final profile of the opening 400 will depend on the etch rates of the different layers. For example, for top dielectric layer 207 (or lower interlayer dielectric layer 203 ) having a higher carbon concentration, a higher etch rate may result in a laterally extended extended sidewall profile. Conversely, for the upper interlayer dielectric layer 205 with a lower carbon concentration, a lower etch rate will result in a hyperbolic-like sidewall profile.
參照圖5,在開口蝕刻製程中,下中間介電層203的蝕刻化學與底部介電層201的蝕刻化學不同。例如,開口蝕刻製程是兩階段蝕刻製程,第一階段用於蝕刻頂部介電層207、上中間介電層205和下中間介電層203,第二階段用於蝕刻底部介電層201。所產生的側壁輪廓將與蝕刻化學有關。在一些實施例中,與底部介電層201對應的開口400的側壁輪廓是錐形的。在一些實施例中,與底部介電層201對應的開口400的寬度可以沿Z方向由下向上逐漸變寬。在一些實施例中,與底部介電層201對應的開口400的側壁輪廓為整體具有一個均勻的斜率。Referring to FIG. 5 , in the opening etching process, the etch chemistry of the lower interlayer dielectric layer 203 is different from that of the bottom dielectric layer 201 . For example, the opening etching process is a two-stage etching process, the first stage is used to etch the top dielectric layer 207 , the upper intermediate dielectric layer 205 and the lower intermediate dielectric layer 203 , and the second stage is used to etch the bottom dielectric layer 201 . The resulting sidewall profile will be etch chemistry dependent. In some embodiments, the sidewall profile of the opening 400 corresponding to the bottom dielectric layer 201 is tapered. In some embodiments, the width of the opening 400 corresponding to the bottom dielectric layer 201 may gradually become wider along the Z direction from bottom to top. In some embodiments, the sidewall profile of the opening 400 corresponding to the bottom dielectric layer 201 has a uniform slope as a whole.
需要注意的是,在開口蝕刻製程之後可能會留下一些蝕刻殘留物(為清楚起見未示出)。蝕刻殘留物可以是開口蝕刻製程後,開口400的內表面上的殘留物質。取決於要蝕刻的材料,蝕刻殘留物可以具有不同的構成。蝕刻殘留物可能對所得半導體元件1A的產量和/或可靠性產生不利影響。可以執行清潔製程以去除蝕刻殘留物。然而,使用稀釋的氟化氫的傳統清潔製程可能導致底部插塞105的底切,這可能導致在開口400的後續沉積期間的電子遷移。結果,可能影響所製得的半導體元件1A的產量和/或可靠性。Note that some etch residue may be left after the opening etch process (not shown for clarity). The etch residue may be the residual substance on the inner surface of the opening 400 after the opening etching process. Depending on the material to be etched, the etch residue can have different compositions. The etching residue may adversely affect the yield and/or reliability of the resulting semiconductor element 1A. A cleaning process may be performed to remove etch residues. However, conventional cleaning processes using dilute hydrogen fluoride may result in undercutting of the bottom plug 105 , which may result in electron migration during subsequent deposition of the opening 400 . As a result, the yield and/or reliability of the manufactured semiconductor element 1A may be affected.
在一些實施例中,可以在清潔製程之前執行預清潔處理以減少傳統清潔製程的不利影響(例如,底部插塞105的底切)。In some embodiments, a pre-clean process may be performed prior to the cleaning process to reduce adverse effects of conventional cleaning processes (eg, undercutting of the bottom plug 105 ).
預清潔處理處理期間,圖5所示(在開口蝕刻製程之後)的半導體元件半成品將以大約10 rpm及大約2000 rpm之間或大約100 rpm和1000 rpm之間的速率旋轉。預清潔溶液將噴灑到半導體元件半成品上以覆蓋半導體元件半成品的整個正面。在將預清潔溶液施加到半導體元件半成品的正面的同時,可以將水或其他合適的溶液施加到半導體元件半成品的背面以清潔半導體元件半成品的背面。During the pre-cleaning process, the semi-finished semiconductor device shown in FIG. 5 (after the opening etch process) will be rotated at a rate between about 10 rpm and about 2000 rpm or between about 100 rpm and 1000 rpm. The pre-cleaning solution is to be sprayed onto the semiconductor component blank to cover the entire front side of the semiconductor component blank. Simultaneously with the application of the pre-cleaning solution to the front side of the semiconductor component blank, water or other suitable solution may be applied to the backside of the semiconductor component blank to clean the backside of the semiconductor component blank.
在一些實施例中,預清潔溶液包括螯合劑、腐蝕抑製劑、胺氟化物(amine fluoride)、表面活性劑、或溶劑。在一些實施例中,胺氟化物和表面活性劑是可選的。In some embodiments, the pre-cleaning solution includes chelating agents, corrosion inhibitors, amine fluorides, surfactants, or solvents. In some embodiments, amine fluorides and surfactants are optional.
通常地,螯合劑也可稱為絡合劑或鉗合劑。螯合劑具有稱為配位子的帶負電荷的離子,其與游離金屬離子結合並形成可溶的組合錯合物。螯合劑可用於從半導體元件半成品中去除金屬離子。不受任何特定理論的限制,螯合劑還可以減少或避免通過開口400暴露的底部插塞105被腐蝕。Generally, chelating agents may also be referred to as complexing agents or sequestering agents. Chelating agents have negatively charged ions called ligands, which bind to free metal ions and form soluble combined complexes. Chelating agents can be used to remove metal ions from semiconductor component semi-finished products. Without being bound by any particular theory, the chelating agent may also reduce or prevent corrosion of the bottom plug 105 exposed through the opening 400 .
在一些實施例中,預清潔溶液的螯合劑包括乙二胺四乙酸、聚丙烯酸酯、碳酸鹽、膦酸鹽、葡糖酸鹽、N, N'-雙(2-羥基苯基)乙二亞氨基二乙酸、三乙烯四氨基六乙酸、去鐵鐵胺B、N, N', N"-三[2-(N-羥基羰基)乙基]-1,3,5-苯三甲酰胺和/或乙二胺二鄰羥基苯乙酸。在一些實施例中,螯合劑的濃度在約0.001 mg/L和約300 mg/L之間或在約0.01 mg/L和約3 mg/L之間。在一些實施例中,或者,螯合劑的濃度在預清潔溶液的1 ppm和約400 ppm之間,或優選地在預清潔溶液的約40 ppm。In some embodiments, the chelating agent of the pre-cleaning solution includes ethylenediaminetetraacetic acid, polyacrylates, carbonates, phosphonates, gluconates, N, N'-bis(2-hydroxyphenyl) Iminodiacetic acid, triethylenetetraaminohexaacetic acid, deferoxamine B, N, N', N"-tris[2-(N-hydroxycarbonyl)ethyl]-1,3,5-benzenetricarboxamide and and/or ethylenediamine di-o-hydroxyphenylacetic acid. In some embodiments, the concentration of the chelating agent is between about 0.001 mg/L and about 300 mg/L or between about 0.01 mg/L and about 3 mg/L In some embodiments, alternatively, the concentration of the chelating agent is between 1 ppm and about 400 ppm of the pre-cleaning solution, or preferably about 40 ppm of the pre-cleaning solution.
預清潔溶液的腐蝕抑製劑係用於減少或避免在隨後的清潔製程中的金屬腐蝕。在一些實施例中,腐蝕抑製劑包括在分子中具有至少一個巰基的脂肪醇化合物。構成醇化合物的碳原子數為2個以上,與巰基鍵合的碳原子及與羥基鍵合的另一碳原子相鄰鍵合。例如,腐蝕抑製劑為2-巰基乙醇和/或硫代甘油。在一些實施例中,預清潔溶液中腐蝕抑製劑的濃度為約0.0001重量%至約10重量%或約0.001重量%至約1重量%。當濃度太低時,腐蝕抑制效果可能被限制在不能令人滿意的程度。然而,過高的濃度並不總是提供進一步增加的腐蝕抑制效果,且由於帶有巰基的化合物特有的氣味,將使其難以處理。Corrosion inhibitors for pre-cleaning solutions are used to reduce or prevent metal corrosion during subsequent cleaning processes. In some embodiments, the corrosion inhibitor includes a fatty alcohol compound having at least one mercapto group in the molecule. The number of carbon atoms constituting the alcohol compound is 2 or more, and the carbon atom bonded to the mercapto group and the other carbon atom bonded to the hydroxyl group are bonded adjacently. For example, corrosion inhibitors are 2-mercaptoethanol and/or thioglycerol. In some embodiments, the concentration of the corrosion inhibitor in the pre-cleaning solution is from about 0.0001% to about 10% by weight or from about 0.001% to about 1% by weight. When the concentration is too low, the corrosion inhibiting effect may be limited to an unsatisfactory level. However, an excessively high concentration does not always provide a further increased corrosion inhibiting effect, and will make it difficult to handle due to the characteristic odor of the compound having a mercapto group.
或者,在一些實施例中,預清潔溶液的腐蝕抑製劑包括芳烴化合物,例如苯並三唑和/或5-甲基苯並咪唑。或者,在一些實施例中,預清潔溶液的腐蝕抑製劑包括尿酸、腺嘌呤、咖啡因和/或嘌呤。Alternatively, in some embodiments, the corrosion inhibitor of the pre-cleaning solution includes an aromatic compound such as benzotriazole and/or 5-methylbenzimidazole. Alternatively, in some embodiments, the corrosion inhibitor of the pre-clean solution includes uric acid, adenine, caffeine, and/or purines.
或者,在一些實施例中,預清潔溶液的腐蝕抑製劑包括乙醛酸。由於作為還原材料的乙醛酸的存在,即使金屬材料在預清潔處理過程中暴露,通過調節其中的乙醛酸濃度來控制預清潔溶液的氧化還原電位,介於 預清潔溶液與暴露的金屬材料之間的電子轉移可以被控制,故金屬材料的腐蝕將可被避免。Alternatively, in some embodiments, the corrosion inhibitor of the pre-clean solution includes glyoxylic acid. Due to the presence of glyoxylic acid as a reducing material, even if the metal material is exposed during the pre-cleaning process, the redox potential of the pre-cleaning solution is controlled by adjusting the concentration of glyoxylic acid in it, between the pre-cleaning solution and the exposed metal material The electron transfer between them can be controlled, so the corrosion of metal materials can be avoided.
或者,在一些實施例中,預清潔溶液的腐蝕抑製劑包括2-巰基乙醇、硫代甘油、苯並三唑、5-甲基苯並咪唑、尿酸、腺嘌呤、咖啡因、嘌呤和/或乙醛酸。Alternatively, in some embodiments, the corrosion inhibitor of the pre-clean solution includes 2-mercaptoethanol, thioglycerol, benzotriazole, 5-methylbenzimidazole, uric acid, adenine, caffeine, purine and/or glyoxylic acid.
在一些實施例中,預清潔溶液的胺氟化物包括氫氟酸甲胺、氫氟酸乙胺、氫氟酸丙胺、氟化四甲銨、氟化四乙銨、氫氟乙醇胺、氫氟酸甲基乙醇胺、氫氟酸二甲基乙醇胺和/或氫氟酸三乙二胺。胺氟化物可用於去除蝕刻殘留物。In some embodiments, the amine fluorides of the pre-cleaning solution include methylamine hydrofluorate, ethylamine hydrofluoride, propylamine hydrofluoride, tetramethylammonium fluoride, tetraethylammonium fluoride, hydrofluoroethanolamine, hydrofluoric acid Methylethanolamine, dimethylethanolamine hydrofluoride and/or triethylenediamine hydrofluoride. Amine fluoride can be used to remove etch residues.
在一些實施例中,預清潔溶液中胺氟化物的濃度可以根據蝕刻殘留物的成分來決定。例如,胺氟化物的濃度可以在預清潔溶液的整個組成的約0.1質量%和約5質量%之間,或在預清潔溶液的整個組成的約0.2質量%和約3質量%之間。通過將胺氟化物的濃度設置在上述範圍內,可以保證預清潔溶液中的胺氟化物能夠去除蝕刻殘留物,同時防止胺氟化物腐蝕通過開口400暴露的底部插塞105的金屬材料及抑制對通過開口400暴露的介電層的蝕刻。即,如果預清潔溶液中的胺氟化物濃度過低,去除殘留物的能力將不足;如果濃度過高,金屬材料可能會被腐蝕,且暴露的介電層可能會被蝕刻或發生結構變化。In some embodiments, the concentration of amine fluoride in the pre-clean solution may be determined according to the composition of the etch residue. For example, the concentration of amine fluoride may be between about 0.1% and about 5% by mass of the total composition of the pre-cleaning solution, or between about 0.2% and about 3% by mass of the total composition of the pre-cleaning solution. By setting the concentration of the amine fluoride within the above-mentioned range, it can be ensured that the amine fluoride in the pre-cleaning solution can remove the etching residue, while preventing the amine fluoride from corroding the metal material of the bottom plug 105 exposed through the opening 400 and inhibiting the Etching of the dielectric layer exposed through the opening 400 . That is, if the concentration of amine fluoride in the pre-cleaning solution is too low, the ability to remove residues will be insufficient; if the concentration is too high, metallic materials may be corroded, and exposed dielectric layers may be etched or undergo structural changes.
表面活性劑的目的是防止顆粒在從半導體元件半成品上移開後重新附著或重新沉積回半導體元件半成品上。防止顆粒重新附著至關重要,因為顆粒的重新附著將會增加整個處理的時間。表面活性劑的目的還包括賦予對防水材料層的親和性。通常地,表面活性劑是長烴鏈,通常包含親水性(極性水溶性基團)和疏水性基團(非極性水不溶性基團)。表面活性劑以其非極性基團附著到粒子以及半導體元件半成品的正面。結果,表面活性劑的極性基團將背離晶片且背離顆粒指向覆蓋半導體元件半成品正面的預清潔溶液。由於顆粒及半導體元件半成品正面上的表面活性劑的極性基團,因此溶液中被表面活性劑結合的顆粒將被半導體元件半成品的正面靜電排斥。The purpose of the surfactant is to prevent the particles from reattaching or redepositing back onto the semiconductor component semifinished product after being removed from the semiconductor component semifinished product. Preventing particle reattachment is critical, as particle reattachment will increase the overall processing time. The purpose of the surfactant is also to impart an affinity for the waterproof material layer. Typically, surfactants are long hydrocarbon chains, usually containing hydrophilic (polar water-soluble groups) and hydrophobic groups (non-polar water-insoluble groups). Surfactants are attached with their non-polar groups to the particles as well as to the front side of the semi-finished semiconductor component. As a result, the polar groups of the surfactant will point away from the wafer and away from the particles towards the pre-cleaning solution covering the front side of the semi-finished semiconductor component. Due to the polar groups of the surfactant on the particles and on the front side of the semiconductor component semi-finished product, the particles bound by the surfactant in solution will be electrostatically repelled by the front side of the semiconductor component semi-finished product.
在一些實施例中,預清潔溶液的表面活性劑包括非離子、陰離子或非離子和陰離子化合物的混合物。非離子是指表面活性劑的極性端具有靜電而非離子電荷,陰離子是指表面活性劑的極性端具有負離子電荷。非離子表面活性劑可以是例如聚氧乙烯丁基苯基醚,陰離子表面活性劑可以是例如聚氧乙烯烷基苯基硫酸鹽。在一些實施例中,預清潔溶液的一種或多種表面活性劑的濃度在約1 ppm和約100 ppm之間。在一些實施例中,非離子表面活性劑在預清潔溶液中的濃度為約30ppm,並且陰離子表面活性劑在預清潔溶液中的濃度為約30ppm。在一些實施例中,預清潔溶液的表面活性劑的濃度為預清潔溶液的整個組成的0.0001質量%至10質量%,或預清潔溶液的整個組成約0.001質量%至約5質量%。通過將濃度設定在上述範圍內,可以確保向半導體元件半成品的正面的潤濕性與表面活性劑的濃度相稱。In some embodiments, the surfactant of the pre-cleaning solution includes nonionic, anionic, or a mixture of nonionic and anionic compounds. Nonionic means that the polar end of the surfactant has an electrostatic rather than ionic charge, and anionic means that the polar end of the surfactant has a negative ionic charge. The nonionic surfactant may be, for example, polyoxyethylene butylphenyl ether, and the anionic surfactant may be, for example, polyoxyethylene alkylphenyl sulfate. In some embodiments, the concentration of one or more surfactants of the pre-cleaning solution is between about 1 ppm and about 100 ppm. In some embodiments, the concentration of nonionic surfactant in the pre-cleaning solution is about 30 ppm and the concentration of anionic surfactant in the pre-cleaning solution is about 30 ppm. In some embodiments, the concentration of the surfactant of the pre-cleaning solution is 0.0001% to 10% by mass of the entire composition of the pre-cleaning solution, or about 0.001% to about 5% by mass of the entire composition of the pre-cleaning solution. By setting the concentration within the above range, wettability to the front surface of the semiconductor element semi-finished product can be ensured commensurate with the concentration of the surfactant.
在一些實施例中,預清潔溶液的溶劑可以是去離子水。In some embodiments, the solvent of the pre-cleaning solution may be deionized water.
在一些實施例中,圖5中所示的半導體元件半成品的正面是將被預清潔溶液覆蓋(或浸泡)約2分鐘。接下來,可以使用去離子水清洗半導體元件半成品以去除預清潔溶液。In some embodiments, the front side of the semi-finished semiconductor device shown in FIG. 5 is to be covered (or soaked) with the pre-cleaning solution for about 2 minutes. Next, the semi-finished semiconductor component can be washed with deionized water to remove the pre-cleaning solution.
在一些實施例中,可以在預清潔處理之後執行一乾燥製程。乾燥製程的執行係通過在約100 rpm及約6000 rpm之間或約3000 rpm之間旋轉約20秒,且使用氣流以乾燥半導體元件半成品。在一些實施例中,氮或異丙醇可用於促進乾燥製程。在一些實施例中,乾燥製程是可選的,即,清潔製程可以在預清潔溶液潤洗後直接進行。In some embodiments, a drying process may be performed after the pre-cleaning process. The drying process is performed by rotating between about 100 rpm and about 6000 rpm or about 3000 rpm for about 20 seconds, and using an air flow to dry the semi-finished semiconductor device. In some embodiments, nitrogen or isopropanol may be used to facilitate the drying process. In some embodiments, the drying process is optional, ie, the cleaning process can be performed directly after rinsing with the pre-cleaning solution.
傳統上,清潔製程可以單獨使用稀釋的氫氟酸進行,無需任何預清潔處理。在將導電材料填充到開口400中之後,下面的底部插塞105可能被損壞以引起輪廓缺陷(例如,底切)或電子遷移。相反地,在本實施例中,下面的底部插塞105可以被預清潔溶液中包含的螯合劑和/或腐蝕抑製劑保護,結果,可以減少或避免輪廓缺陷或電子遷移。因此,可以提高所得半導體元件1A的產量和可靠性。Traditionally, the cleaning process can be performed with dilute hydrofluoric acid alone without any pre-cleaning treatment. After filling the conductive material into the opening 400 , the underlying bottom plug 105 may be damaged to cause contour defects (eg, undercuts) or electron migration. Conversely, in this embodiment, the underlying bottom plug 105 may be protected by chelating agents and/or corrosion inhibitors contained in the pre-cleaning solution, and as a result, profile defects or electromigration may be reduced or avoided. Therefore, the yield and reliability of the resulting semiconductor element 1A can be improved.
參照圖1、6和7,於步驟S17,在開口400中共形地形成一第一阻障層601。Referring to FIGS. 1 , 6 and 7 , in step S17 , a first barrier layer 601 is conformally formed in the opening 400 .
參照圖6和圖7,第一阻障層601可以通過化學氣相沉積(也稱為第一化學氣相沉積製程)形成。詳細地,第一阻障層601的形成可以包括一氣體源引入步驟、一第一吹掃步驟、一反應物流動步驟和一第二吹掃步驟。氣體源引入步驟、第一吹掃步驟、反應物流動步驟和第二吹掃步驟可以視為一個循環。可以執行多個循環以獲得第一阻障層601的期望厚度。Referring to FIGS. 6 and 7 , the first barrier layer 601 may be formed by chemical vapor deposition (also referred to as a first chemical vapor deposition process). In detail, the formation of the first barrier layer 601 may include a gas source introducing step, a first purging step, a reactant flowing step and a second purging step. The gas source introduction step, first purge step, reactant flow step, and second purge step can be considered as one cycle. Multiple cycles may be performed to obtain the desired thickness of the first barrier layer 601 .
例如,圖5所示(預清潔製程和清潔製程之後)的半導體元件半成品的部件將被載入反應室中。於氣體源引入步驟中,在時段P1期間,可以將包含前驅物和反應物的氣體源引入反應室。前驅物和反應物可以擴散穿過邊界層並到達圖5所示的半導體元件半成品的表面(即,硬遮罩層501的頂面和開口400的內表面)。前驅物和反應物可以吸附並隨後於上述表面上遷移。被吸附的前驅物和被吸附的反應物可以在上述表面上發生反應並形成固體的副產物。固體的副產物可以在上述表面上形成核。核可以成長成島,並且島可以在上述表面上合併成連續的薄膜。於第一吹掃步驟中,在時段P2期間,可以將如氬氣的吹掃氣體注入反應室以吹掃出氣態副產物、未反應的前驅物和未反應的反應物。For example, parts of semi-finished semiconductor devices as shown in FIG. 5 (after pre-cleaning process and cleaning process) will be loaded into the reaction chamber. In the gas source introducing step, a gas source including precursors and reactants may be introduced into the reaction chamber during a period P1. The precursors and reactants can diffuse through the boundary layer and reach the surfaces of the semi-finished semiconductor device shown in FIG. 5 (ie, the top surface of the hard mask layer 501 and the inner surface of the opening 400). Precursors and reactants can be adsorbed and subsequently migrate across the above-mentioned surfaces. Adsorbed precursors and adsorbed reactants can react on the surface and form solid by-products. Solid by-products can form nuclei on the aforementioned surfaces. The nuclei can grow into islands, and the islands can merge into a continuous film on the above-mentioned surface. In the first purge step, a purge gas such as argon may be injected into the reaction chamber to purge out gaseous by-products, unreacted precursors, and unreacted reactants during a period P2.
於反應物流動步驟中,在時間P3期間,反應物可以單獨引入反應室以將連續的薄膜變成第一阻障層601。在第二吹掃步驟中,在時段P4期間,可以將如氬氣的吹掃氣體注入反應室以吹掃出氣態副產物和未反應的反應物。In the reactant flowing step, during time P3, the reactants may be introduced into the reaction chamber individually to turn the continuous thin film into the first barrier layer 601 . In a second purge step, a purge gas such as argon may be injected into the reaction chamber during period P4 to purge out gaseous by-products and unreacted reactants.
在一些實施例中,前驅物是四氯化鈦。反應物是氨。由於四氯化鈦和氨之間的不完全反應,四氯化鈦和氨可能在表面上反應並形成包含高氯化物污染的氮化鈦膜。反應物流動步驟中的氨可降低氮化鈦膜的氯化物含量。氨處理後的氮化鈦膜可視為第一阻障層601。In some embodiments, the precursor is titanium tetrachloride. The reactant is ammonia. Due to the incomplete reaction between titanium tetrachloride and ammonia, titanium tetrachloride and ammonia may react on the surface and form a titanium nitride film containing high chloride contamination. The ammonia in the reactant flow step reduces the chloride content of the titanium nitride film. The titanium nitride film after ammonia treatment can be regarded as the first barrier layer 601 .
在一些實施例中,使用化學氣相沉積的第一阻障層601的形成可以在等離子體的幫助下進行。等離子體源可以為氬氣、氫氣、或其的組合。In some embodiments, the formation of the first barrier layer 601 using chemical vapor deposition can be performed with the help of plasma. The plasma source can be argon, hydrogen, or a combination thereof.
需要說明的是,通過第一化學氣相沉積形成的第一阻障層601與通過原子層沉積製程所形成的層相比,其具有較大的晶粒尺寸。結果,由第一化學氣相沉積形成的第一阻障層601的導電性將得到提升。It should be noted that the first barrier layer 601 formed by the first chemical vapor deposition has a larger grain size than the layer formed by the atomic layer deposition process. As a result, the conductivity of the first barrier layer 601 formed by the first chemical vapor deposition will be improved.
圖8為剖面示意圖,例示本揭露一實施例之半導體元件1A的製備方法的部分流程。圖9例示本揭露一實施例之後處理中還原劑的脈衝及間隔時間。圖10例示本揭露另一實施例之後處理中還原劑的脈衝及間隔時間,縱軸表示氣流,橫軸表示時間。圖11及圖12為剖面示意圖,例示本揭露一實施例之半導體元件1A的製備方法的部分流程。FIG. 8 is a schematic cross-sectional view illustrating a part of the process of the manufacturing method of the semiconductor device 1A according to an embodiment of the present disclosure. FIG. 9 illustrates pulses and intervals of reducing agents in post-processing according to an embodiment of the present disclosure. FIG. 10 exemplifies the pulse and interval time of the reducing agent in the subsequent treatment according to another embodiment of the present disclosure. The vertical axis represents air flow, and the horizontal axis represents time. FIG. 11 and FIG. 12 are cross-sectional schematic diagrams illustrating a part of the process of the manufacturing method of the semiconductor device 1A according to an embodiment of the present disclosure.
參照圖1及圖8至圖12,於步驟S19,在第一阻障層601上共形地形成一第二阻障層603,且在開口400中形成多個導電結構300。Referring to FIG. 1 and FIGS. 8 to 12 , in step S19 , a second barrier layer 603 is conformally formed on the first barrier layer 601 , and a plurality of conductive structures 300 are formed in the opening 400 .
參照圖8,第二阻障層603共形地形成在第二阻障層603上且位於開口400中。在一些實施例中,第二阻障層603由例如銅、銅合金、銀、金、鎢、鋁、鎳等所形成。在本實施例中,第二阻障層603由鎢所形成。Referring to FIG. 8 , a second barrier layer 603 is conformally formed on the second barrier layer 603 and located in the opening 400 . In some embodiments, the second barrier layer 603 is formed of copper, copper alloy, silver, gold, tungsten, aluminum, nickel, etc., for example. In this embodiment, the second barrier layer 603 is formed of tungsten.
參照圖8,可以通過例如脈衝成核層法(pulsed nucleation layer method,也稱為第二化學氣相沉積製程)來形成第二阻障層603。通常地,在脈衝成核層法中,反應物(例如還原劑或前驅物)的脈衝可以被依序地注入反應室,並通常通過反應物的脈衝之間的吹掃氣體脈衝將反應物從反應室中清除。第一反應物可以被吸附到基底(例如,第一阻障層601)上,且可用於與下一個反應物(例如,第二反應物)反應。以循環方式(也稱為沈積循環)重複上述過程,直到達到所需的厚度。Referring to FIG. 8 , the second barrier layer 603 may be formed by, for example, a pulsed nucleation layer method (also referred to as a second chemical vapor deposition process). Generally, in the pulsed nucleation layer method, pulses of reactants (such as reducing agents or precursors) can be sequentially injected into the reaction chamber, and the reactants are usually removed from the Cleared from the reaction chamber. A first reactant can be adsorbed onto a substrate (eg, first barrier layer 601 ) and available to react with a next reactant (eg, second reactant). This process is repeated in a cyclic fashion (also known as a deposition cycle) until the desired thickness is achieved.
應該注意的是,脈衝成核層法通常藉由其更高的操作壓力範圍(大於1 Torr)和其更高的每循環生長速率(大於每循環1個單層膜生長),而與原子層沉積有所區別。於脈衝成核層法期間,腔室的壓力在從約1 Torr到約400 Torr的範圍。It should be noted that the pulsed nucleation layer method is usually compared with the atomic layer by its higher operating pressure range (greater than 1 Torr) and its higher growth rate per cycle (greater than 1 monolayer growth per cycle). Sedimentation is different. During the pulsed nucleation layer process, the pressure of the chamber ranges from about 1 Torr to about 400 Torr.
例如,第二化學氣相沉積製程的沉積循環步驟包括含矽還原劑的脈衝和含鎢前驅物的脈衝。第一阻障層601最初暴露於含矽還原劑的脈衝,接著暴露於含鎢前驅物的脈衝。暴露於含矽還原劑的脈衝及含鎢前驅物的脈衝可以定義為一個沉積循環。可以重複沉積循環直到實現第二阻障層603的期望厚度。通過增加第二化學氣相沉積製程的沉積循環的重複次數,第二阻障層603的側壁覆蓋率將提升,且在開口400的頂端具有更少的懸垂。For example, the deposition cycle steps of the second chemical vapor deposition process include pulses of a silicon-containing reducing agent and pulses of a tungsten-containing precursor. The first barrier layer 601 is initially exposed to pulses of a silicon-containing reducing agent, followed by pulses of a tungsten-containing precursor. Exposure to pulses of silicon-containing reducing agents and pulses of tungsten-containing precursors can be defined as a deposition cycle. The deposition cycle may be repeated until the desired thickness of the second barrier layer 603 is achieved. By increasing the number of repetitions of the deposition cycle of the second chemical vapor deposition process, the sidewall coverage of the second barrier layer 603 will be increased and have less overhang at the top of the opening 400 .
矽烷和相關化合物得吸附到金屬氮化物表面,例如在某些集成電路應用中,用作阻擋層材料的氮化鈦和氮化鎢。任何合適的矽烷或矽烷衍生物都作為含矽還原劑,包括矽烷的有機衍生物。通常理解的是,矽烷以自限方式吸附在基材表面上,以產生名義上的單層矽烷物質。因此,吸附物質的量很大程度上與矽烷用量無關。Silanes and related compounds are adsorbed to the surface of metal nitrides, such as titanium nitride and tungsten nitride, which are used as barrier layer materials in some integrated circuit applications. Any suitable silane or silane derivative can be used as the silicon-containing reducing agent, including organic derivatives of silane. It is generally understood that silanes adsorb on the substrate surface in a self-limiting manner to produce a nominally monolayer silane species. Therefore, the amount of adsorbed species is largely independent of the amount of silane used.
在一些實施例中,於暴露於沉積循環的含矽還原劑的脈衝期間,基底溫度在約200°C和約475°C之間、在約300°C和約400°C之間、或約300℃。在一些實施例中,於暴露於沉積循環的含矽還原劑的脈衝期間,腔室壓力在約1 Torr和約350 Torr之間、或固定在約40 Torr。暴露時間(或脈衝時間)部分取決於劑量和腔室條件。在一些實施例中,第一阻障層601被暴露直到表面被至少一飽和的矽烷物質層充分且均勻地覆蓋。在一些實施方案中,含矽還原劑係單獨提供。在一些實施例中,含矽還原劑與載體氣體一同提供,載體氣體為例如氬或氬-氫混合物。In some embodiments, the substrate temperature is between about 200°C and about 475°C, between about 300°C and about 400°C, or about 300°C. In some embodiments, the chamber pressure is between about 1 Torr and about 350 Torr, or fixed at about 40 Torr, during exposure to pulses of the silicon-containing reducing agent of the deposition cycle. Exposure time (or pulse time) depends in part on dose and chamber conditions. In some embodiments, the first barrier layer 601 is exposed until the surface is sufficiently and uniformly covered with at least one saturated layer of silane species. In some embodiments, the silicon-containing reducing agent is provided alone. In some embodiments, the silicon-containing reducing agent is provided with a carrier gas such as argon or an argon-hydrogen mixture.
一旦第一阻障層601被矽烷物質充分覆蓋,含矽還原劑的脈衝將停止。可以執行一吹掃製程以清除第一阻障層601表面附近的殘留氣體反應物。可以使用如氬氣、氫氣、氮氣或氦氣的載體氣體來執行吹掃製程。Once the first barrier layer 601 is sufficiently covered by the silane substance, the pulse of the silicon-containing reducing agent is stopped. A purge process may be performed to remove residual gaseous reactants near the surface of the first barrier layer 601 . The purging process may be performed using a carrier gas such as argon, hydrogen, nitrogen or helium.
在一些實施例中,含鎢前驅物包括六氟化鎢、六氯化鎢或六羰基鎢。在一些實施例中,含鎢前驅物包括不含氟的有機金屬化合物,例如MDNOW(甲基環戊二烯基-二羰基亞硝基-鎢)和EDNOW(乙基環戊二烯基-二羰基亞硝基-鎢)。在一些實施例中,含鎢前驅物以稀釋氣體的形式提供,同時伴隨氣體如氬氣、氮氣、氫氣、或其組合。In some embodiments, the tungsten-containing precursor includes tungsten hexafluoride, tungsten hexachloride, or tungsten hexacarbonyl. In some embodiments, tungsten-containing precursors include fluorine-free organometallic compounds such as MDNOW (methylcyclopentadienyl-dicarbonylnitroso-tungsten) and EDNOW (ethylcyclopentadienyl-dicarbonyl- carbonyl nitroso-tungsten). In some embodiments, the tungsten-containing precursor is provided in the form of a diluent gas along with an accompanying gas such as argon, nitrogen, hydrogen, or combinations thereof.
在一些實施例中,於暴露於沉積循環的含鎢前驅物的脈衝期間,基底溫度在約200°C和約475°C之間、在約300°C和約400°C之間、或約300°C。在一些實施例中,於暴露於沉積循環的含鎢前驅物的脈衝期間,腔室壓力在約1 Torr和約350 Torr之間。含鎢前驅物的劑量和基底暴露時間(或脈衝時間)將根據許多因素而變化。通常,可以進行曝光直到吸附的矽烷物質與含鎢前驅物反應被充分消耗,以產生第二阻障層603。此後,可以停止含鎢前驅物的脈衝,且使用如氬氣、氫氣、氮氣或氦氣的載體氣體來執行吹掃製程。In some embodiments, the substrate temperature is between about 200°C and about 475°C, between about 300°C and about 400°C, or about 300°C. In some embodiments, the chamber pressure is between about 1 Torr and about 350 Torr during exposure to the pulse of the tungsten-containing precursor of the deposition cycle. Dosage of tungsten-containing precursor and substrate exposure time (or pulse time) will vary according to many factors. Typically, exposure can be performed until the adsorbed silane species reacts with the tungsten-containing precursor to be sufficiently consumed to produce the second barrier layer 603 . Thereafter, the pulsing of the tungsten-containing precursor may be stopped and a purge process performed using a carrier gas such as argon, hydrogen, nitrogen, or helium.
傳統上,需使用原子層沉積以形成一額外的層來改善第二阻障層603的側壁覆蓋率;相比之下,在本實施例中,通過增加第二化學氣相沉積製程的沉積循環的重複次數來提高側壁覆蓋率,因此,不需要額外的層;結果,可以降低製備半導體元件1A的複雜性和成本。Traditionally, atomic layer deposition is used to form an additional layer to improve the sidewall coverage of the second barrier layer 603; in contrast, in this embodiment, by increasing the deposition cycle of the second chemical vapor deposition process The number of repetitions increases the sidewall coverage, and therefore, no additional layers are required; as a result, the complexity and cost of manufacturing the semiconductor element 1A can be reduced.
在一些實施例中,第二化學氣相沉積製程包括在脈衝成核層法(即,第二化學氣相沉積)的沉積循環之前執行一初始沉積步驟。在一些實施例中,初始沉積步驟包括提供含硼烷前驅物的脈衝和隨後的含鎢前驅物的脈衝,各脈衝後皆跟著一吹掃脈衝。在一些實施例中,初始沉積步驟的含硼烷前驅物為例如硼烷、乙硼烷、三硼烷或具有氫的滷化硼(例如BF 3、BCl 3)。在一些實施例中,初始沉積步驟的含硼烷前驅物以稀釋氣體的形式提供,其伴隨有氣體如氬氣、氮氣、氫氣、矽烷、或其組合。例如,乙硼烷提供自稀釋的來源(例如,5%乙硼烷和95%氮)。 In some embodiments, the second chemical vapor deposition process includes performing an initial deposition step prior to the deposition cycle of the pulsed nucleation layer method (ie, second chemical vapor deposition). In some embodiments, the initial deposition step includes providing a pulse of a borane-containing precursor followed by a pulse of a tungsten-containing precursor, each pulse followed by a purge pulse. In some embodiments, the borane-containing precursor of the initial deposition step is, for example, borane, diborane, triborane, or a boron halide with hydrogen (eg, BF 3 , BCl 3 ). In some embodiments, the borane-containing precursor of the initial deposition step is provided in the form of a diluent gas, which is accompanied by a gas such as argon, nitrogen, hydrogen, silane, or combinations thereof. For example, diborane provides a self-diluting source (eg, 5% diborane and 95% nitrogen).
在一些實施例中,於初始沉積步驟的含硼烷前驅物的脈衝期間,基底溫度介於約200℃與約475℃之間、約300℃與約400℃之間、或約300℃。在一些實施例中,於初始沉積步驟的含硼烷前驅物的脈衝期間,腔室壓力在約1 Torr和約350 Torr之間。In some embodiments, the substrate temperature is between about 200°C and about 475°C, between about 300°C and about 400°C, or about 300°C during the pulse of the borane-containing precursor in the initial deposition step. In some embodiments, the chamber pressure is between about 1 Torr and about 350 Torr during the pulse of the borane-containing precursor in the initial deposition step.
在一些實施例中,初始沉積步驟的含鎢前驅物包括六氟化鎢、六氯化鎢或六羰基鎢,或不含氟的有機金屬化合物,例如MDNOW(甲基環戊二烯基-二羰基亞硝基-鎢)和EDNOW(乙基環戊二烯基-二羰基亞硝基-鎢)。在一些實施例中,初始沉積步驟的含鎢前驅物以稀釋氣體的形式提供,其伴隨有氣體如氬氣、氮氣、氫氣、或其組合。In some embodiments, the tungsten-containing precursor for the initial deposition step includes tungsten hexafluoride, tungsten hexachloride, or tungsten hexacarbonyl, or an organometallic compound that does not contain fluorine, such as MDNOW (methylcyclopentadienyl-di carbonylnitroso-tungsten) and EDNOW (ethylcyclopentadienyl-dicarbonylnitroso-tungsten). In some embodiments, the tungsten-containing precursor of the initial deposition step is provided in the form of a diluent gas, which is accompanied by a gas such as argon, nitrogen, hydrogen, or a combination thereof.
在一些實施例中,於暴露於含鎢前驅物期間,基底溫度在約200℃和約475℃之間、在約300℃和約400℃之間、或約300℃。在一些實施例中,於暴露於含鎢前驅物期間,腔室壓力在約1 Torr和約350 Torr之間。In some embodiments, the substrate temperature is between about 200°C and about 475°C, between about 300°C and about 400°C, or about 300°C during exposure to the tungsten-containing precursor. In some embodiments, the chamber pressure is between about 1 Torr and about 350 Torr during exposure to the tungsten-containing precursor.
參照圖9,在一些實施例中,在形成第二阻障層603之後,可以對第二阻障層603進行後處理。於後處理期間,在第二阻障層603上形成隨後的導電層之前,可以將第二阻障層603暴露於一個或多個還原劑的脈衝。暴露於還原劑的脈衝可以提高包括第二阻障層603和隨後的導電層的整體結構的電阻率。Referring to FIG. 9 , in some embodiments, after the second barrier layer 603 is formed, post-processing may be performed on the second barrier layer 603 . During post-processing, the second barrier layer 603 may be exposed to pulses of one or more reducing agents prior to forming a subsequent conductive layer on the second barrier layer 603 . Exposure to pulses of reducing agents can increase the resistivity of the overall structure including the second barrier layer 603 and subsequent conductive layers.
參照圖9,第二阻障層603將暴露於多個還原劑的脈衝,脈衝之間具有間隔時間。於間隔時間內,沒有還原劑流向第二阻障層603。在一些實施例中,還原劑為乙硼烷,亦可使用其他還原劑。在一些實施例中,於脈衝期間,還原劑的流速在約100標準立方厘米每分鐘(sccm)和500 sccm之間。在一些實施例中,每個還原劑的脈衝的脈衝時間(或脈衝持續時間)在約0.5秒和約5秒之間,或在約1秒和2秒之間。在一些實施例中,還原劑的脈衝的數量在 2 和 8 之間。在一些實施例中,後處理的製程壓力在約2 Torr和約100 Torr之間,或在約20 Torr和約40 Torr之間。Referring to Figure 9, the second barrier layer 603 will be exposed to a plurality of pulses of reducing agent with an interval time between the pulses. During the interval, no reducing agent flows to the second barrier layer 603 . In some embodiments, the reducing agent is diborane, although other reducing agents may also be used. In some embodiments, the flow rate of the reducing agent is between about 100 standard cubic centimeters per minute (seem) and 500 seem during the pulse. In some embodiments, the pulse time (or pulse duration) of each pulse of reducing agent is between about 0.5 seconds and about 5 seconds, or between about 1 second and 2 seconds. In some embodiments, the number of pulses of reducing agent is between 2 and 8. In some embodiments, the post-treatment process pressure is between about 2 Torr and about 100 Torr, or between about 20 Torr and about 40 Torr.
在一些實施例中,還原劑以稀釋氣體的形式提供,其伴隨有氣體如氬氣、氮氣、氫氣、矽烷、或其組合。例如,乙硼烷提供自稀釋的來源(例如,5%乙硼烷和95%氮)。在一些實施例中,惰性氣體/氫氣混合物可以在還原劑脈衝和後處理的間隔時間期間連續地流向第二阻障層603。在一些實施例中,惰性氣體為氬氣。相反地,在後處理的間隔時間期間,除了連續流動的惰性氣體/氫氣混合物或其他背景氣體之外,沒有其他氣體流到第二阻障層603,即,在還原劑的脈衝之間的間隔時間內,沒有介入脈衝操作。In some embodiments, the reducing agent is provided in the form of a diluent gas, which is accompanied by a gas such as argon, nitrogen, hydrogen, silane, or combinations thereof. For example, diborane provides a self-diluting source (eg, 5% diborane and 95% nitrogen). In some embodiments, the inert gas/hydrogen mixture may flow continuously to the second barrier layer 603 during the interval between the reductant pulse and the post-treatment. In some embodiments, the inert gas is argon. Conversely, no gas other than the continuous flow of inert gas/hydrogen mixture or other background gas flows to the second barrier layer 603 during the post-processing interval, i.e., the interval between pulses of reducing agent During this time, there is no intervening pulse operation.
在一些實施例中,在後處理之前,可以將圖8所示的半導體元件半成品預熱到約375°C和約415°C之間,或約395°C以穩定半導體元件半成品。在一些實施例中,後處理之後的半導體元件半成品可以被加熱到約375°C和約415°C之間,或大約395°C。暴露後處理之前的預熱過程和後處理之後的熱處理可以增強膜的附著力並改善薄層電阻的不均勻性。In some embodiments, the semiconductor component blank shown in FIG. 8 may be preheated to between about 375° C. and about 415° C., or about 395° C. to stabilize the semiconductor component blank prior to post-processing. In some embodiments, the post-processed semiconductor component blank may be heated to between about 375°C and about 415°C, or about 395°C. The preheating process before the post-exposure treatment and the heat treatment after the post-treatment can enhance the adhesion of the film and improve the non-uniformity of the sheet resistance.
在一些實施例中,在後處理之後,將第二阻障層603暴露於額外的含鎢前驅物,以在隨後將導電層沉積在第二阻障層603上之前形成第二阻障層603的額外部分。可以使用任何合適的含鎢前驅物。例如,含鎢前驅物包括六氟化鎢、六氯化鎢或六羰基鎢。含鎢前驅物可以稀釋氣體的形式提供,其伴隨氣體如氬氣、氮氣、氫氣、或其組合。In some embodiments, after post-processing, the second barrier layer 603 is exposed to additional tungsten-containing precursors to form the second barrier layer 603 before subsequently depositing a conductive layer on the second barrier layer 603 additional part of . Any suitable tungsten-containing precursor may be used. For example, tungsten-containing precursors include tungsten hexafluoride, tungsten hexachloride, or tungsten hexacarbonyl. The tungsten-containing precursor may be provided in the form of a diluent gas with an accompanying gas such as argon, nitrogen, hydrogen, or combinations thereof.
參照圖10,備選地,在一些實施例中,第二阻障層603交替地暴露於多種還原劑的脈衝,在脈衝之間具有間隔時間。在間隔時間,沒有還原劑流向第二阻障層603。在一些實施例中,如乙硼烷和含鎢前驅物的還原劑可以交替地流入(或引入)到第二阻障層603。Referring to FIG. 10 , alternatively, in some embodiments, the second barrier layer 603 is alternately exposed to pulses of multiple reducing agents with an interval between pulses. During the interval, no reducing agent flows to the second barrier layer 603 . In some embodiments, reducing agents such as diborane and tungsten-containing precursors may be alternately flowed (or introduced) into the second barrier layer 603 .
在一些實施例中,乙硼烷的流速在約100 sccm和約500 sccm之間,或約300 sccm。在一些實施例中,含鎢前驅物包括例如六氟化鎢、六氯化鎢或六羰基鎢。含鎢前驅物的流速在約100 sccm和約500 sccm之間,或約100 sccm。在一些實施例中,脈衝時間(或脈衝持續時間)在約0.5秒和5秒之間,或在約1秒和2秒之間。在一些實施例中,每個脈衝之間的間隔時間在大約2秒和大約5秒之間。在一些實施例中,脈衝的數量在 2 和 8 之間。在一些實施例中,腔室壓力在約2 Torr和約100 Torr之間,或在約20 Torr和約40 Torr之間。In some embodiments, the flow rate of diborane is between about 100 seem and about 500 seem, or about 300 seem. In some embodiments, the tungsten-containing precursor includes, for example, tungsten hexafluoride, tungsten hexachloride, or tungsten hexacarbonyl. The flow rate of the tungsten-containing precursor is between about 100 seem and about 500 seem, or about 100 seem. In some embodiments, the pulse time (or pulse duration) is between about 0.5 seconds and 5 seconds, or between about 1 second and 2 seconds. In some embodiments, the interval between each pulse is between about 2 seconds and about 5 seconds. In some embodiments, the number of pulses is between 2 and 8. In some embodiments, the chamber pressure is between about 2 Torr and about 100 Torr, or between about 20 Torr and about 40 Torr.
在一些實施例中,脈衝時間應該足夠短以確保沒有或實質上沒有鎢沉積。在一些實施例中,在後處理期間施加到第二阻障層603的含鎢前驅物的量小於在形成第二阻障層603期間施加到第一阻障層601的含鎢前驅物的量。在一些實施例中,在後處理期間施加到第二阻障層603的含鎢前驅物的脈衝時間小於在形成第二阻障層603期間施加到第一阻障層601的含鎢前驅物的脈衝時間。In some embodiments, the pulse time should be short enough to ensure no or substantially no tungsten deposition. In some embodiments, the amount of the tungsten-containing precursor applied to the second barrier layer 603 during post-processing is less than the amount of the tungsten-containing precursor applied to the first barrier layer 601 during the formation of the second barrier layer 603 . In some embodiments, the pulse time of the tungsten-containing precursor applied to the second barrier layer 603 during post-processing is less than that of the tungsten-containing precursor applied to the first barrier layer 601 during the formation of the second barrier layer 603. pulse time.
在某些實施例中,還原劑和含鎢前驅物脈衝可以短至小於1秒。在一個示例中,乙硼烷 (B2H6) 將脈衝 1 秒,接著 1 秒的吹掃,然後接著 1 秒的六氟化鎢 (WF6) 脈衝,最後接著 2.5 秒的吹掃。該循環將重複四次。In certain embodiments, the reducing agent and tungsten-containing precursor pulses can be as short as less than 1 second. In one example, diborane (B2H6) would be pulsed for 1 second, followed by a 1 second purge, followed by a 1 second pulse of tungsten hexafluoride (WF6), followed by a 2.5 second purge. This cycle will repeat four times.
不受特定理論的限制,在乙硼烷脈衝之間引入六氟化鎢脈衝可以幫助從第二阻障層603的表面清除未反應的乙硼烷,否則其會促進微剝離的發生。Without being bound by a particular theory, the introduction of tungsten hexafluoride pulses between diborane pulses can help clear unreacted diborane from the surface of the second barrier layer 603, which would otherwise promote micro-lifting.
在一些實施例中,後處理將被執行在約10秒至約50秒之間,或約10秒至約30秒之間。較長的後處理時間(或持續時間)可能會導致乙硼烷分解,這對後續導電層的電阻率有不利影響。In some embodiments, post-processing will be performed for between about 10 seconds and about 50 seconds, or between about 10 seconds and about 30 seconds. Longer post-treatment times (or durations) may lead to the decomposition of diborane, which has an adverse effect on the resistivity of subsequent conductive layers.
在一些實施例中,可以在形成第二阻障層603之後執行蝕刻製程以去除在開口400的頂端處的第二阻障層603的懸垂(如果有的話)。在一些實施例中,蝕刻製程可以是各向異性蝕刻製程。在一些實施例中,可以在後處理之前執行蝕刻製程。在一些實施例中,蝕刻製程可以在後處理之後進行。In some embodiments, an etching process may be performed after forming the second barrier layer 603 to remove the overhang (if any) of the second barrier layer 603 at the top of the opening 400 . In some embodiments, the etching process may be an anisotropic etching process. In some embodiments, an etch process may be performed prior to post-processing. In some embodiments, the etch process may be performed after post-processing.
參照圖11,可以在第二阻障層603上形成一層導電材料507並完全填充開口400。在一些實施例中,導電材料507可以是與第二阻障層603相同的材料(例如,鎢)。導電材料層507可以通過例如物理氣相沉積、原子層沉積、分子層沉積、化學氣相沉積、原位自由基輔助沉積、金屬有機化學氣相沉積、分子束外延、濺射、電鍍、蒸發、離子束沉積、電子束沉積、激光輔助沉積、化學溶液沉積、或其組合所形成。在本實施例中,導電材料層507是通過化學氣相沉積(也稱為第三化學氣相沉積)形成。Referring to FIG. 11 , a layer of conductive material 507 may be formed on the second barrier layer 603 and completely fill the opening 400 . In some embodiments, the conductive material 507 may be the same material as the second barrier layer 603 (eg, tungsten). The conductive material layer 507 can be deposited by, for example, physical vapor deposition, atomic layer deposition, molecular layer deposition, chemical vapor deposition, in-situ free radical assisted deposition, metal organic chemical vapor deposition, molecular beam epitaxy, sputtering, electroplating, evaporation, Formed by ion beam deposition, electron beam deposition, laser assisted deposition, chemical solution deposition, or combinations thereof. In this embodiment, the conductive material layer 507 is formed by chemical vapor deposition (also referred to as third chemical vapor deposition).
在一些實施例中,第三化學氣相沉積包括初始沉積步驟、沉積循環和本體步驟。第三化學氣相沉積的初始沉積步驟通過類似於圖8所示的第二化學氣相沉積的初始沉積步驟的程序來執行,於此不再贅述。第三化學氣相沉積的沉積循環通過類似於圖8所示的第二化學氣相沉積的沉積循環步驟的程序來執行,於此不再贅述。第三化學氣相沉積的主體步驟包括將含鎢前驅物和如還原劑的共反應物流入(或引入)到包括第二阻障層603的半導體元件半成品。第三化學氣相沉積的主體步驟的示例製程壓力在約10 Torr和約500 Torr之間。第三化學氣相沉積的主體步驟的示例基底溫度在約250℃和約495℃之間。第三化學氣相沉積的本體步驟的含鎢前驅物為例如六氟化鎢、氯化鎢或六羰基鎢。第三化學氣相沉積的本體步驟的還原劑為例如氫氣、矽烷、乙矽烷、肼、乙硼烷或鍺烷。通過包括主體步驟而不是依賴於沉積循環,可以在更短的時間內填充開口400。In some embodiments, the third chemical vapor deposition includes an initial deposition step, a deposition cycle, and a bulk step. The initial deposition step of the third chemical vapor deposition is performed by a procedure similar to that of the initial deposition step of the second chemical vapor deposition shown in FIG. 8 , which will not be repeated here. The deposition cycle of the third chemical vapor deposition is performed through a program similar to the steps of the deposition cycle of the second chemical vapor deposition shown in FIG. 8 , which will not be repeated here. The main step of the third chemical vapor deposition includes flowing (or introducing) a tungsten-containing precursor and a co-reactant such as a reducing agent into the semi-finished semiconductor device including the second barrier layer 603 . An example process pressure for the main step of the third chemical vapor deposition is between about 10 Torr and about 500 Torr. An exemplary substrate temperature for the main step of the third chemical vapor deposition is between about 250°C and about 495°C. The tungsten-containing precursor of the bulk step of the third chemical vapor deposition is, for example, tungsten hexafluoride, tungsten chloride or tungsten hexacarbonyl. The reducing agent for the bulk step of the third chemical vapor deposition is, for example, hydrogen, silane, disilane, hydrazine, diborane or germane. By including bulk steps rather than relying on deposition cycles, the opening 400 can be filled in less time.
由於採用第二化學氣相沉積法形成的第二阻障層603可以提供良好的側壁覆蓋率,因此後續形成的導電材料層507可以填滿開口400而不會形成空隙。因此,形成的導電材料層507可以具有改良的導電性。Since the second barrier layer 603 formed by the second chemical vapor deposition method can provide good sidewall coverage, the subsequently formed conductive material layer 507 can fill the opening 400 without forming a void. Accordingly, the formed conductive material layer 507 may have improved conductivity.
在一些實施例中,第三化學氣相沉積的沉積循環步驟的重複次數少於第二化學氣相沉積的沉積循環步驟的重複次數。在一些實施例中,第三化學氣相沉積的沉積循環步驟的重複次數和第二化學氣相沉積的沉積循環步驟的重複次數可以相同或實質地相同。In some embodiments, the number of repetitions of the deposition cycle step of the third chemical vapor deposition is less than the number of repetitions of the deposition cycle step of the second chemical vapor deposition. In some embodiments, the number of repetitions of the deposition cycle step of the third chemical vapor deposition and the number of repetitions of the deposition cycle step of the second chemical vapor deposition may be the same or substantially the same.
在一些實施例中,導電材料層507中鎢的晶粒尺寸大於30nm、大於50nm、大於70nm、大於80nm、大於85nm、或大於87nm。在一些實施例中,導電材料層507包括α相鎢。In some embodiments, the grain size of tungsten in the conductive material layer 507 is greater than 30 nm, greater than 50 nm, greater than 70 nm, greater than 80 nm, greater than 85 nm, or greater than 87 nm. In some embodiments, the layer of conductive material 507 includes alpha-phase tungsten.
參照圖12,執行平坦化製程,例如化學機械拋光,直到頂部介電層207的頂表面被暴露以去除多餘材料並為後續處理步驟提供實質上平坦的表面。在平坦化製程之後,開口400中剩餘的導電材料507被視為該些導電結構300。為了描述的簡潔、清楚和方便起見,僅描述一個導電結構300。Referring to FIG. 12, a planarization process, such as chemical mechanical polishing, is performed until the top surface of the top dielectric layer 207 is exposed to remove excess material and provide a substantially planar surface for subsequent processing steps. After the planarization process, the remaining conductive material 507 in the opening 400 is regarded as the conductive structures 300 . For brevity, clarity and convenience of description, only one conductive structure 300 is described.
參照圖12,導電結構300包括在底部介電層201中的一底部部分301、在下中間介電層203中和在底部部分301上的一下中間部分303、在上中間介電層205中和在下中間介電層203上的一上中間部分305、及在上介電層207和上中間部分305上的一頂部307。12, the conductive structure 300 includes a bottom portion 301 in the bottom dielectric layer 201, a lower intermediate portion 303 in the lower intermediate dielectric layer 203 and on the bottom portion 301, in the upper intermediate dielectric layer 205 and in the lower An upper middle portion 305 on the middle dielectric layer 203 , and a top portion 307 on the upper dielectric layer 207 and the upper middle portion 305 .
需要注意的是,導電結構300的形狀由開口400決定。例如,頂部介電層207或下中間介電層203包括擴展的側壁輪廓。上中間部分305包括類雙曲線狀的側壁輪廓。底部部分301包括錐形側壁輪廓。因此,上中間部分305的臨界尺寸CD2小於下中間部分303的臨界尺寸CD1或頂部307的臨界尺寸CD3。底部部分301的臨界尺寸CD4小於下中間部分303的臨界尺寸CD1。在一些實施例中,下中間部分303的臨界尺寸CD1和臨界尺寸CD3實質地相同。在一些實施例中,下中間部分303的臨界尺寸CD1和臨界尺寸CD3不同。由於上中間部分305的臨界尺寸CD2較小,故相鄰上中間部分305之間的距離可以增加,結果,可以減少相鄰導電結構300的寄生電容。It should be noted that the shape of the conductive structure 300 is determined by the opening 400 . For example, the top dielectric layer 207 or the lower intermediate dielectric layer 203 includes an extended sidewall profile. The upper middle portion 305 includes a hyperbolic-like sidewall profile. The bottom portion 301 includes a tapered sidewall profile. Therefore, the critical dimension CD2 of the upper middle portion 305 is smaller than the critical dimension CD1 of the lower middle portion 303 or CD3 of the top portion 307 . The critical dimension CD4 of the bottom portion 301 is smaller than the critical dimension CD1 of the lower middle portion 303 . In some embodiments, the CD1 and CD3 of the lower middle portion 303 are substantially the same. In some embodiments, the CD1 and CD3 of the lower middle portion 303 are different. Since the critical dimension CD2 of the upper middle portion 305 is smaller, the distance between adjacent upper middle portions 305 can be increased, and as a result, the parasitic capacitance of adjacent conductive structures 300 can be reduced.
在一些實施例中,上中間部分305的臨界尺寸CD2小於底部部分301的臨界尺寸CD4。在一些實施例中,上中間部分305的臨界尺寸CD2和底部部分301的臨界尺寸CD4實質地相同。In some embodiments, the critical dimension CD2 of the upper middle portion 305 is less than the critical dimension CD4 of the bottom portion 301 . In some embodiments, CD2 of upper middle portion 305 and CD4 of bottom portion 301 are substantially the same.
通過對絕緣堆疊200的不同層採用不同的碳濃度,即使對絕緣堆疊200的不同層使用相同的蝕刻化學,也可以控制臨界尺寸,結果,可以改善導電結構300對底部插塞105的覆蓋(overlay),同時將源自相鄰導電結構300的寄生電容保持在低水平。By using different carbon concentrations for different layers of the insulating stack 200, CD can be controlled even if the same etch chemistry is used for the different layers of the insulating stack 200, and as a result, the overlay of the bottom plug 105 by the conductive structure 300 can be improved. ), while keeping the parasitic capacitance from adjacent conductive structures 300 low.
圖13為剖面示意圖,例示本揭露另一實施例之的半導體元件1B。FIG. 13 is a schematic cross-sectional view illustrating a semiconductor device 1B according to another embodiment of the present disclosure.
參照圖13,半導體元件1B具有與圖12所示類似的結構。圖13與圖12相同或相似的元件已經用相似的元件標號標記,並且省略了重複的描述。Referring to FIG. 13 , a semiconductor element 1B has a structure similar to that shown in FIG. 12 . Components in FIG. 13 that are the same as or similar to those in FIG. 12 have been labeled with similar component numbers, and repeated descriptions have been omitted.
參照圖13,絕緣堆疊200僅包括底部介電層201、上中間介電層205和頂部介電層207。上中間介電層205設置在底部介電層201上。導電結構300包括底部部分301、上中間部分305和頂部307。上中間部分305設置在底部部分301上和上中間介電層205中。Referring to FIG. 13 , the insulation stack 200 includes only a bottom dielectric layer 201 , an upper intermediate dielectric layer 205 and a top dielectric layer 207 . The upper intermediate dielectric layer 205 is disposed on the bottom dielectric layer 201 . Conductive structure 300 includes a bottom portion 301 , an upper middle portion 305 and a top 307 . The upper middle part 305 is disposed on the bottom part 301 and in the upper middle dielectric layer 205 .
本發明的一個方面提供了一種半導體元件,包括一第一絕緣層,設置於一基底上;一底部插塞,設置於該第一絕緣層中;一底部介電層、一下中間介電層、上中間介電層及一頂部介電層,依序堆疊於該第一絕緣層上;及一導電結構包括一底部部分,設置於該底部介電層中及位於該底部插塞上,一下中間部分,設置於該底部部分上及位於該下中間介電層中,一上中間部分,設置於該下中間部分上及位於該上中間介電層中,及一頂部部分,設置於該上中間部分上及位於該頂部介電層中。該下中間介電層的碳濃度大於該底部介電層的碳濃度。One aspect of the present invention provides a semiconductor device, including a first insulating layer disposed on a substrate; a bottom plug disposed in the first insulating layer; a bottom dielectric layer, a lower intermediate dielectric layer, an upper middle dielectric layer and a top dielectric layer are sequentially stacked on the first insulating layer; and a conductive structure includes a bottom portion disposed in the bottom dielectric layer and on the bottom plug, one in the middle part, disposed on the bottom part and in the lower intermediate dielectric layer, an upper middle part, disposed on the lower middle part and in the upper middle dielectric layer, and a top part, disposed in the upper middle partially on and in the top dielectric layer. The carbon concentration of the lower middle dielectric layer is greater than the carbon concentration of the bottom dielectric layer.
本發明的另一方面提供了一種半導體元件,包括一第一絕緣層,設置於一基底上;一底部插塞,設置於該第一絕緣層中;一底部介電層、一下中間介電層、上中間介電層及一頂部介電層,依序堆疊於該第一絕緣層上;及一導電結構包括一底部部分,設置於該底部介電層中及位於該底部插塞上,一下中間部分,設置於該底部部分上及位於該下中間介電層中,一上中間部分,設置於該下中間部分上及位於該上中間介電層中,及一頂部部分,設置於該上中間部分上及位於該頂部介電層中。該上中間介電層的碳濃度大於該底部介電層的碳濃度。Another aspect of the present invention provides a semiconductor device, including a first insulating layer disposed on a substrate; a bottom plug disposed in the first insulating layer; a bottom dielectric layer, a lower intermediate dielectric layer , an upper middle dielectric layer and a top dielectric layer are sequentially stacked on the first insulating layer; and a conductive structure includes a bottom portion disposed in the bottom dielectric layer and on the bottom plug, once a middle portion disposed on the bottom portion and in the lower intermediate dielectric layer, an upper middle portion disposed on the lower middle portion and in the upper intermediate dielectric layer, and a top portion disposed on the upper The middle portion is on and in the top dielectric layer. The carbon concentration of the upper middle dielectric layer is greater than the carbon concentration of the bottom dielectric layer.
本發明的另一方面提供一種製備半導體元件的方法,包括形成一第一絕緣層於一基底上;形成一底部插塞於該第一絕緣層中;依次形成一底部介電層、一下中間介電層、一上中間介電層及一頂部介電層於該第一絕緣層上;進行一開口蝕刻製程,以形成沿該頂部介電層、該上中間介電層、該下中間介電層及該底部介電層的一開口,並藉以暴露該底部插塞;及形成一導電結構於該開口中。該下中間介電層的碳濃度大於該底部介電層的碳濃度。Another aspect of the present invention provides a method for preparing a semiconductor device, comprising forming a first insulating layer on a substrate; forming a bottom plug in the first insulating layer; sequentially forming a bottom dielectric layer, a lower interposer An electrical layer, an upper intermediate dielectric layer, and a top dielectric layer are on the first insulating layer; an opening etching process is performed to form the top dielectric layer, the upper intermediate dielectric layer, and the lower intermediate dielectric layer layer and an opening of the bottom dielectric layer, thereby exposing the bottom plug; and forming a conductive structure in the opening. The carbon concentration of the lower middle dielectric layer is greater than the carbon concentration of the bottom dielectric layer.
由於本公開的半導體元件的設計,通過對絕緣堆疊200的不同層採用不同的碳濃度,即使對絕緣堆疊200的不同層使用相同的蝕刻化學也可以控制臨界尺寸,結果,可以改善導電結構300對底部插塞105的覆蓋。此外,由於導電結構300的上中間部分305的臨界尺寸較小,源自相鄰導電結構300的寄生電容可以保持在低水平。Due to the design of the semiconductor element of the present disclosure, by using different carbon concentrations for different layers of the insulating stack 200, even using the same etch chemistry for different layers of the insulating stack 200 can control the critical dimension, and as a result, the conductive structure 300 can be improved to Covering of the bottom plug 105 . Furthermore, due to the small critical dimension of the upper middle portion 305 of the conductive structure 300, the parasitic capacitance originating from the adjacent conductive structure 300 can be kept at a low level.
雖然已詳述本揭露及其優點,然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如,可用不同的方法實施上述的許多製程,並且以其他製程或其組合替代上述的許多製程。Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.
再者,本申請案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質上相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此,此等製程、機械、製造、物質組成物、手段、方法、或步驟係包含於本申請案之申請專利範圍內。Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, A composition of matter, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patent scope of this application.
1A:半導體元件1A: Semiconductor components
1B:半導體元件1B: Semiconductor components
101:基底101: Base
103:第一絕緣層103: The first insulating layer
105:底部插塞105: Bottom plug
200:絕緣堆疊200: insulation stack
201:底部介電層201: bottom dielectric layer
203:下中間介電層203: lower intermediate dielectric layer
205:上中間介電層205: upper intermediate dielectric layer
207:頂部介電層207: top dielectric layer
300:導電結構300: conductive structure
301:底部部分301: Bottom part
303:下中間部分303: lower middle part
305:上中間部分305: upper middle part
307:頂部部分307: top part
400:開口400: opening
501:硬遮罩層501: hard mask layer
503:開口503: opening
505:遮罩層505: mask layer
507:導電材料507: Conductive material
601:第一阻障層601: The first barrier layer
603:第二阻障層603: Second barrier layer
CD1:臨界尺寸CD1: critical dimension
CD2:臨界尺寸CD2: critical dimension
CD3:臨界尺寸CD3: critical dimension
CD4:臨界尺寸CD4: critical dimension
T1:厚度T1: Thickness
T2:厚度T2: Thickness
T3:厚度T3: Thickness
T4:厚度T4: Thickness
參閱實施方式與申請專利範圍合併考量圖式時,可得以更全面了解本申請案之揭示內容,圖式中相同的元件符號係指相同的元件。 圖1為流程圖,例示本揭露一實施例的一種半導體元件的製備方法; 圖2至圖6為剖面示意圖,例示本揭露一實施例之製備半導體元件的部分流程; 圖7例示形成本揭露一實施例之第一阻障層的製程條件; 圖8為剖面示意圖,例示本揭露一實施例之製備半導體元件的部分流程; 圖9例示本揭露一實施例之後處理中還原劑的脈衝及間隔時間; 圖10例示本揭露另一實施例之後處理中還原劑的脈衝及間隔時間; 圖11及圖12為剖面示意圖,例示本揭露一實施例之製備半導體元件的部分流程; 圖13為剖面示意圖,例示本揭露另一實施例之的半導體元件。 The disclosure content of the present application can be understood more fully when the drawings are combined with the embodiments and the patent scope of the application. The same reference numerals in the drawings refer to the same components. FIG. 1 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure; 2 to 6 are schematic cross-sectional views illustrating a partial process for preparing a semiconductor device according to an embodiment of the present disclosure; FIG. 7 illustrates the process conditions for forming the first barrier layer according to an embodiment of the present disclosure; FIG. 8 is a schematic cross-sectional view illustrating a partial process of preparing a semiconductor device according to an embodiment of the present disclosure; FIG. 9 illustrates the pulse and interval time of the reducing agent in the subsequent treatment according to an embodiment of the present disclosure; FIG. 10 illustrates the pulse and interval time of the reducing agent in the subsequent treatment according to another embodiment of the present disclosure; 11 and FIG. 12 are cross-sectional schematic diagrams illustrating a part of the process for preparing a semiconductor device according to an embodiment of the present disclosure; FIG. 13 is a schematic cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure.
1A:半導體元件 1A: Semiconductor components
101:基底 101: Base
103:第一絕緣層 103: The first insulating layer
105:底部插塞 105: Bottom plug
200:絕緣堆疊 200: insulation stack
201:底部介電層 201: bottom dielectric layer
203:下中間介電層 203: lower intermediate dielectric layer
205:上中間介電層 205: upper intermediate dielectric layer
207:頂部介電層 207: top dielectric layer
300:導電結構 300: conductive structure
301:底部部分 301: Bottom part
303:下中間部分 303: lower middle part
305:上中間部分 305: upper middle part
307:頂部部分 307: top part
400:開口 400: opening
501:硬遮罩層 501: hard mask layer
503:開口 503: opening
505:遮罩層 505: mask layer
507:導電材料 507: Conductive material
601:第一阻障層 601: The first barrier layer
603:第二阻障層 603: Second barrier layer
CD1:臨界尺寸 CD1: critical dimension
CD2:臨界尺寸 CD2: critical dimension
CD3:臨界尺寸 CD3: critical dimension
CD4:臨界尺寸 CD4: critical dimension
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US17/741,365 US20230369097A1 (en) | 2022-05-10 | 2022-05-10 | Method for fabricating semiconductor device with multi-carbon-concentration dielectrics |
US17/740,527 | 2022-05-10 |
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US20030042605A1 (en) * | 2001-08-31 | 2003-03-06 | Ebrahim Andideh | Concentration graded carbon doped oxide |
US20160218219A1 (en) * | 2015-01-26 | 2016-07-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
TW201733069A (en) * | 2016-03-11 | 2017-09-16 | 台灣積體電路製造股份有限公司 | Structure and formation method of interconnect structure of semiconductor device |
US20180082917A1 (en) * | 2016-09-16 | 2018-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Info structure with copper pillar having reversed profile |
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US20030042605A1 (en) * | 2001-08-31 | 2003-03-06 | Ebrahim Andideh | Concentration graded carbon doped oxide |
US20160218219A1 (en) * | 2015-01-26 | 2016-07-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
TW201733069A (en) * | 2016-03-11 | 2017-09-16 | 台灣積體電路製造股份有限公司 | Structure and formation method of interconnect structure of semiconductor device |
US20180082917A1 (en) * | 2016-09-16 | 2018-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Info structure with copper pillar having reversed profile |
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