TWI809952B - Semiconductor device with multi-carbon-concentration dielectrics and method for fabricating the same - Google Patents

Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first insulating layer positioned on a substrate; a bottom contact positioned in the first insulating layer; a bottom dielectric layer, a lower middle dielectric layer, a higher middle dielectric layer, and a top dielectric layer sequentially stacked on the first insulating layer; and a conductive structure including a bottom portion positioned in the bottom dielectric layer and on the bottom contact, a lower middle portion positioned on the bottom portion and in the lower middle dielectric layer, a higher middle portion positioned on the lower middle portion and in the higher middle dielectric layer, and a top portion positioned on the higher middle portion and in the top dielectric layer. A carbon concentration of the lower middle dielectric layer is greater than a carbon concentration of the bottom dielectric layer.

Description

Semiconductor element with multiple carbon-concentrated dielectric layers and method for making the same

This application claims priority to US Patent Application Nos. 17/740,527 and 17/741,365 (ie, the priority date is "May 10, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor element and a manufacturing method thereof, more particularly, to a semiconductor element having multiple carbon-concentrated dielectric layers and a manufacturing method thereof.

Semiconductor components are used in various electronic applications such as personal computers, mobile phones, digital cameras and other electronic devices. To meet the ever-increasing demand for computing power, the dimensions of semiconductor components continue to shrink. However, the shrinking size has caused various problems in the process, and these problems have continuously spawned different situations. Therefore, challenges remain in improving the performance, quality, yield, and reliability of semiconductor devices, and reducing complexity.

The above "prior art" description is only to provide background technology, and does not acknowledge that the above "prior art" description discloses the subject of this disclosure, and does not constitute the prior art of this disclosure, and any description of the above "prior art" shall not form part of this case.

One aspect of the present invention provides a semiconductor device, including a first insulating layer disposed on a substrate; a bottom plug disposed in the first insulating layer; a bottom dielectric layer, a lower intermediate dielectric layer, an upper middle dielectric layer and a top dielectric layer are sequentially stacked on the first insulating layer; and a conductive structure includes a bottom portion disposed in the bottom dielectric layer and on the bottom plug, one in the middle part, disposed on the bottom part and in the lower intermediate dielectric layer, an upper middle part, disposed on the lower middle part and in the upper middle dielectric layer, and a top part, disposed in the upper middle partially on and in the top dielectric layer. The carbon concentration of the lower middle dielectric layer is greater than the carbon concentration of the bottom dielectric layer.

Another aspect of the present invention provides a semiconductor device, including a first insulating layer disposed on a substrate; a bottom plug disposed in the first insulating layer; a bottom dielectric layer, a lower intermediate dielectric layer , an upper middle dielectric layer and a top dielectric layer are sequentially stacked on the first insulating layer; and a conductive structure includes a bottom portion disposed in the bottom dielectric layer and on the bottom plug, once a middle portion disposed on the bottom portion and in the lower intermediate dielectric layer, an upper middle portion disposed on the lower middle portion and in the upper intermediate dielectric layer, and a top portion disposed on the upper The middle portion is on and in the top dielectric layer. The carbon concentration of the upper middle dielectric layer is greater than the carbon concentration of the bottom dielectric layer.

Another aspect of the present invention provides a method for preparing a semiconductor device, comprising forming a first insulating layer on a substrate; forming a bottom plug in the first insulating layer; sequentially forming a bottom dielectric layer, a lower interposer An electrical layer, an upper intermediate dielectric layer, and a top dielectric layer are on the first insulating layer; an opening etching process is performed to form the top dielectric layer, the upper intermediate dielectric layer, and the lower intermediate dielectric layer layer and an opening of the bottom dielectric layer, thereby exposing the bottom plug; and forming a conductive structure in the opening. The carbon concentration of the lower middle dielectric layer is greater than the carbon concentration of the bottom dielectric layer.

Due to the design of the semiconductor element of the present disclosure, by using different carbon concentrations for different layers of the insulating stack, the critical dimension can be controlled even if the same etch chemistry is used for the different layers of the insulating stack. As a result, the conductive structure can be improved. In addition, due to the small critical dimension of the upper middle part of the conductive structure, the parasitic capacitance originating from the adjacent conductive structure can be kept at a low level.

The technical features and advantages of the present disclosure have been broadly summarized above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the disclosure defined by the appended claims.

The following description of the disclosure, accompanied by the drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the disclosure, however, the disclosure is not limited to such embodiments. In addition, the following embodiments can be properly integrated to complete another embodiment.

"An embodiment," "an embodiment," "an exemplary embodiment," "another embodiment," "another embodiment" and the like refer to embodiments described in the present disclosure that may include a particular feature, structure, or characteristic, but Not every embodiment must include the particular feature, structure or characteristic. Also, repeated use of the phrase "in an embodiment" does not necessarily refer to the same embodiment, but could be the same embodiment.

In order to make the present disclosure fully understandable, the following description provides detailed steps and structures. Obviously, practice of the present disclosure is not limited to specific details known to those skilled in the art. In addition, known structures and steps are not described in detail so as not to limit the present disclosure unnecessarily. Preferred embodiments of the present disclosure are described in detail as follows. However, the present disclosure may be broadly implemented in other embodiments than those described in detail. The scope of the present disclosure is not limited to the content of the detailed description, but is defined by the claims.

In the present disclosure, a semiconductor element generally refers to a device that can function by utilizing semiconductor characteristics. Such as electro-optical devices, light-emitting display devices, semiconductor circuits and electronic devices will be included in the category of semiconductor components.

It should be noted that, in the description of the present invention, above (or up) corresponds to the direction of the arrow in the Z direction, and below (or down) corresponds to the opposite direction of the arrow in the Z direction.

FIG. 1 is a flowchart illustrating a method 10 for manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. 2 to 6 are schematic cross-sectional views illustrating a part of the process for preparing a semiconductor device according to an embodiment of the present disclosure. FIG. 7 illustrates the process conditions for forming the first barrier layer according to an embodiment of the present disclosure.

1 and 2, in step S11, a substrate 101 is provided, a first insulating layer 103 is formed on the substrate 101, a plurality of bottom plugs 105 are formed in the first insulating layer 103, and an insulating stack 200 is formed on the first insulating layer 103. An insulating layer 103 is formed, and a hard mask layer 501 is formed on the insulating stack 200 .

Referring to FIG. 2, substrate 101 includes a bulk semiconductor substrate composed entirely of at least one semiconductor material, a plurality of device elements (not shown for clarity), a plurality of dielectric layers (not shown for clarity), and multiple conductive features (not shown for clarity). Bulk semiconductor substrates are formed from semiconductor elements such as silicon or germanium; or from silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other III-V group Or formed by semiconductor compounds such as II-VI semiconductor materials; or formed by the above-mentioned combination.

In some embodiments, the substrate 101 includes a semiconductor-on-insulator structure consisting, from bottom to top, of a handle substrate, an insulator layer, and a topmost layer of semiconductor material. The handle substrate and the topmost semiconductor material layer are formed from the same material as the bulk semiconductor substrate described above. The insulator layer is a crystalline or amorphous dielectric material, such as oxide and/or nitride. For example, the insulator layer is a dielectric oxide, such as silicon oxide. For another example, the insulator layer is a dielectric nitride, such as silicon nitride or boron nitride. As another example, the insulator layer includes a stack of dielectric oxide and dielectric nitride, such as silicon oxide and silicon nitride or boron nitride stacked in any order. The insulator layer has a thickness between about 10 nanometers and 200 nanometers.

In this disclosure, the term "about" or "about" used to modify the amount of an ingredient, component, or reactant means, for example, by typical measurements used to prepare concentrates or solutions and Possible numerical changes for liquid handlers. In addition, variations may also arise from inadvertent errors in measurement procedures, differences in the manufacture, source or purity of ingredients used in making compositions or performing methods, etc. In some aspects, the term "about" or "about" refers to a variation of within 10% of the stated numerical value. In other aspects, the term "about" or "about" refers to a variation of within 5% of the stated value. In other respects, the term "about" or "about" means a variation of within 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, or 1% of the stated value .

Referring to FIG. 2, device elements are formed on a bulk semiconductor substrate or topmost layer of semiconductor material. Portions of the device elements are formed in the bulk semiconductor substrate or in the topmost layer of semiconductor material. The device element is a transistor, such as a CMOS transistor, a MOSFET, a FinFET, etc., or a combination thereof.

Referring to FIG. 2 , a dielectric layer is formed on the bulk semiconductor substrate or the topmost semiconductor material layer and covers the device components. In some embodiments, the dielectric layer is made of silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric materials, etc., or combinations thereof. form. The dielectric constant of the low dielectric constant dielectric material is less than 3.0 or even less than 2.5. In some embodiments, the dielectric constant of the low-k dielectric material is less than 2.0. The dielectric layer is formed by deposition processes such as chemical vapor deposition, plasma enhanced chemical vapor deposition, and the like. A planarization process is performed after the deposition process to remove excess material and provide a substantially planar surface for subsequent processing steps.

Referring to FIG. 2 , the conductive features include a plurality of interconnect layers and a plurality of conductive vias. The interconnection layers are separated from each other and arranged horizontally in the dielectric layer along the direction Z. The conductive vias connect adjacent interconnect layers along direction Z and connect adjacent device elements and interconnect layers. In some embodiments, conductive vias can improve heat dissipation and can provide structural support. In some embodiments, the conductive features are formed from metals such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal-forming nitrides (e.g., nitrogen titanium oxide), transition metal aluminides, or combinations thereof. The conductive features are formed during the formation of the dielectric layer.

In some embodiments, device elements and conductive features together constitute multiple functional units in substrate 101 . In the description of the present disclosure, functional units generally refer to functionally related circuits that are divided into different units for functional purposes. In some embodiments, functional units are typically highly complex circuits such as processor cores, memory controllers, or accelerator units. In some other embodiments, the degree of complexity and functionality of the functional units may depend on actual needs.

Referring to FIG. 2, the first insulating layer 103 is formed on the substrate 101 and is made of silicon dioxide, undoped silicate glass, fluorosilicate glass, borophosphosilicate glass, spin-coated low-k dielectric Electrical layer, chemical vapor deposition low-k dielectric layer, or a combination thereof. In some embodiments, the first insulating layer 103 includes a self-planarizing material such as spin-on-glass or a spin-on low-k dielectric material such as SiLK™. Using a self-planarizing dielectric material can avoid the need to perform a subsequent planarization process. In some embodiments, the first insulating layer 103 can be formed by a deposition process, including, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, evaporation, or spin coating. In some embodiments, a planarization process, such as chemical mechanical polishing, may be performed to provide a substantially planar surface for subsequent processing steps.

Referring to FIG. 2 , bottom plugs 105 are formed along first insulating layer 103 and are electrically coupled to device elements of substrate 101 through corresponding conductive features of substrate 101 . In some embodiments, bottom plug 105 is made of materials such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g. titanium nitride), transition metal aluminides, or combinations thereof. The bottom plug 105 is formed by, for example, an embedded process or other applicable processes.

Referring to FIG. 2 , the insulating stack 200 includes a bottom dielectric layer 201 , a lower intermediate dielectric layer 203 , an upper intermediate dielectric layer 205 and a top dielectric layer 207 .

Referring to FIG. 2 , a bottom dielectric layer 201 is formed on the first insulating layer 103 . In some embodiments, the bottom dielectric layer 201 is made of silicon dioxide, undoped silicate glass, fluorosilicate glass, borophosphosilicate glass, silicon nitride, silicon oxynitride, oxynitride silicon, phosphosilicate glass, or a combination thereof. In some embodiments, the bottom dielectric layer 201 is a high-k dielectric material (dielectric constant greater than 7.0), including but not limited to metal oxides, such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum Oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide , alumina, lead scandium tantalum oxide, and lead zinc niobate. In this embodiment, the bottom dielectric layer 201 is silicon oxide or silicon nitride.

Referring to FIG. 2 , a lower intermediate dielectric layer 203 is formed on the bottom dielectric layer 201 . In some embodiments, the lower interlayer dielectric layer 203 is formed of, for example, carbon-doped oxide or organosilicate glass. In some embodiments, the lower interlayer dielectric layer 203 is formed by spin-coating low-k dielectric layer, chemical vapor deposition low-k dielectric layer, porous polymer material, or a combination thereof.

Referring to FIG. 2 , an upper intermediate dielectric layer 205 is formed on the lower intermediate dielectric layer 203 . In some embodiments, the upper interlayer dielectric layer 205 is formed of, for example, carbon-doped oxide or organosilicate glass. In some embodiments, the upper interlayer dielectric layer 205 is formed by, for example, spin-coated low-k dielectric layer, chemical vapor deposition low-k dielectric layer, porous polymer material, or a combination thereof.

Referring to FIG. 2 , a top dielectric layer 207 is formed on the upper middle dielectric layer 205 . In some embodiments, the top dielectric layer 207 is formed of, for example, carbon doped oxide or organosilicate glass. In some embodiments, the top dielectric layer 207 is formed by, for example, spin-coated low-k dielectric layer, chemical vapor deposited low-k dielectric layer, porous polymer material, or a combination thereof. In some embodiments, the lower middle dielectric layer 203 and the top dielectric layer 207 are formed of the same material.

In some embodiments, the lower interlayer dielectric layer 203, the upper interlayer dielectric layer 205, and the top dielectric layer 207 are formed by exposing the energy-removable material to an energy source such as heat, light, or a combination thereof. to form a porous layer. When heat is used as the energy source, the temperature of the energy treatment is between about 800°C and about 900°C. When using light as an energy source, ultraviolet light can be used.

In some embodiments, the porous layer includes skeletons and a plurality of spaces disposed between the skeletons. Spaces are interconnected and filled with air. The frame includes low dielectric material or methylsilsesquioxane. The porous layer has a porosity between 25% and 75%. Due to the aforementioned spaces, the porous layer is filled with air and, as a result, the dielectric constant of the porous layer will be significantly lower than a layer formed of, for example, silicon oxide. Thus, the porous layer will significantly reduce the parasitic capacitance between conductive features formed therein.

In some embodiments, energy-removable materials include, for example, thermally decomposable materials, photon-decomposable materials, electron beam-decomposable materials, or combinations thereof. For example, an energy-removable material includes a substrate and a decomposable porogen material that is sacrificially removed upon exposure to an energy source. In some embodiments, the decomposable porogen material includes a porogen organic compound that imparts porosity to the substrate of the energy-removable material.

In some embodiments, the porosity of the lower intermediate dielectric layer 203 (or the top dielectric layer 207 ) is greater than the porosity of the upper intermediate dielectric layer 205 . In some embodiments, the porosity of the lower middle dielectric layer 203 and the porosity of the top dielectric layer 207 are substantially the same. In some embodiments, the porosity of the lower middle dielectric layer 203 and the porosity of the top dielectric layer 207 are different. For example, the porosity of the top dielectric layer 207 is greater than that of the lower middle dielectric layer 203 .

Referring to FIG. 2 , in some embodiments, the carbon concentration of the lower intermediate dielectric layer 203 (or the top dielectric layer 207 ) is greater than the carbon concentration of the upper intermediate dielectric layer 205 . The carbon concentration of the upper middle dielectric layer 205 is greater than that of the bottom dielectric layer 201 . In some embodiments, the carbon concentration of the lower interlayer dielectric layer 203 and the carbon concentration of the top dielectric layer 207 are substantially the same. In some embodiments, the carbon concentration of the lower interlayer dielectric layer 203 and the carbon concentration of the top dielectric layer 207 are different. For example, the carbon concentration of the lower middle dielectric layer 203 is greater than or less than the carbon concentration of the top dielectric layer 207 .

Referring to FIG. 2 , in some embodiments, the dielectric constant of the lower intermediate dielectric layer 203 (or the top dielectric layer 207 ) is smaller than the dielectric constant of the upper intermediate dielectric layer 205 . The dielectric constant of the upper middle dielectric layer 205 is smaller than that of the bottom dielectric layer 201 .

Referring to FIG. 2 , in some embodiments, the thickness T1 of the lower intermediate dielectric layer 203 is smaller than the thickness T2 of the upper intermediate dielectric layer 205 . In some embodiments, the thickness T2 is greater than the thickness T3 of the top dielectric layer 207 .

In some embodiments, the thickness T1 of the lower middle dielectric layer 203 and the thickness T3 of the top dielectric layer 207 are substantially the same. In some embodiments, the thickness T1 of the lower middle dielectric layer 203 is different from the thickness T3 of the top dielectric layer 207 . For example, the thickness T1 of the lower middle dielectric layer 203 is greater than the thickness T3 of the top dielectric layer 207 .

In some embodiments, the thickness T1 of the lower intermediate dielectric layer 203 and the thickness T4 of the bottom dielectric layer 201 are substantially the same. In some embodiments, the thickness T1 of the lower intermediate dielectric layer 203 is different from the thickness T4 of the bottom dielectric layer 201 . For example, the thickness T4 of the bottom dielectric layer 201 is greater than the thickness T1 of the lower intermediate dielectric layer 203 .

Referring to FIG. 2 , a hard mask layer 501 is formed on top dielectric layer 207 . In some embodiments, the hard mask layer 501 is formed of boron nitride, silicon boron nitride, boron phosphorus nitride, silicon boron carbon nitride, and the like. The hard mask layer 501 can be formed by a film forming process and a treatment process. In detail, in the film forming process, a first precursor can be introduced above the top dielectric layer 207 to form a boron-based layer, and the first precursor is a boron-based precursor. Subsequently, in the treatment process, a second precursor may be introduced to react with the boron-based layer and transform the boron-based layer into a hard mask layer 501 , the second precursor being a nitrogen-based precursor. In some embodiments, the first precursor is, for example, diborane, borazine, or an alkyl-substituted boron derivative of borazine. In some embodiments, the second precursor is, for example, ammonia or hydrazine.

Referring to FIGS. 1 , 3 and 4 , in step S13 , the hard mask layer 501 is patterned to form a plurality of hard mask openings 503 .

Referring to FIG. 3 , a mask layer 505 is formed on the hard mask layer 501 . The mask layer 505 is a photoresist layer and includes a pattern of hard mask openings 503 .

Referring to FIG. 4 , a hard mask etch process is performed to remove portions of the hard mask layer 501 to form hard mask openings 503 . Portions of the top dielectric layer 207 will be exposed through the hard mask opening 503 . After the hard mask opening 503 is formed, the mask layer 505 can be removed by, for example, an ashing process or other applicable processes.

Referring to FIGS. 1 and 5 , in step S15 , a plurality of openings 400 are formed along the insulating stack 200 to expose the bottom plugs 105 .

For brevity, clarity and convenience of description, only one opening 400 is depicted.

Referring to FIG. 5 , an opening etching process is performed to remove portions of the top dielectric layer 207 , the upper intermediate dielectric layer 205 , the lower intermediate dielectric layer 203 and the bottom dielectric layer 201 to form openings 400 . In some embodiments, the etching chemistries of the top dielectric layer 207 , the upper ILD layer 205 , and the lower ILD layer 203 are the same during the opening etch process. However, in the opening etching process, the etching rate of the upper interlayer dielectric layer 205 is different from the etching rate of the top dielectric layer 207 (or the lower interlayer dielectric layer 203 ). In some embodiments, the etch rate during the opening etch process is related to the carbon concentration of the corresponding layer. For example, the etch rate of the lower ILD layer 203 (with a higher carbon concentration) is higher than the etch rate of the upper ILD layer 205 (with a lower carbon concentration).

Therefore, the final profile of the opening 400 will depend on the etch rates of the different layers. For example, for top dielectric layer 207 (or lower interlayer dielectric layer 203 ) having a higher carbon concentration, a higher etch rate may result in a laterally extended extended sidewall profile. Conversely, for the upper interlayer dielectric layer 205 with a lower carbon concentration, a lower etch rate will result in a hyperbolic-like sidewall profile.

Referring to FIG. 5 , in the opening etching process, the etch chemistry of the lower interlayer dielectric layer 203 is different from that of the bottom dielectric layer 201 . For example, the opening etching process is a two-stage etching process, the first stage is used to etch the top dielectric layer 207 , the upper intermediate dielectric layer 205 and the lower intermediate dielectric layer 203 , and the second stage is used to etch the bottom dielectric layer 201 . The resulting sidewall profile will be etch chemistry dependent. In some embodiments, the sidewall profile of the opening 400 corresponding to the bottom dielectric layer 201 is tapered. In some embodiments, the width of the opening 400 corresponding to the bottom dielectric layer 201 may gradually become wider along the Z direction from bottom to top. In some embodiments, the sidewall profile of the opening 400 corresponding to the bottom dielectric layer 201 has a uniform slope as a whole.

Note that some etch residue may be left after the opening etch process (not shown for clarity). The etch residue may be the residual substance on the inner surface of the opening 400 after the opening etching process. Depending on the material to be etched, the etch residue can have different compositions. The etching residue may adversely affect the yield and/or reliability of the resulting semiconductor element 1A. A cleaning process may be performed to remove etch residues. However, conventional cleaning processes using dilute hydrogen fluoride may result in undercutting of the bottom plug 105 , which may result in electron migration during subsequent deposition of the opening 400 . As a result, the yield and/or reliability of the manufactured semiconductor element 1A may be affected.

In some embodiments, a pre-clean process may be performed prior to the cleaning process to reduce adverse effects of conventional cleaning processes (eg, undercutting of the bottom plug 105 ).

During the pre-cleaning process, the semi-finished semiconductor device shown in FIG. 5 (after the opening etch process) will be rotated at a rate between about 10 rpm and about 2000 rpm or between about 100 rpm and 1000 rpm. The pre-cleaning solution is to be sprayed onto the semiconductor component blank to cover the entire front side of the semiconductor component blank. Simultaneously with the application of the pre-cleaning solution to the front side of the semiconductor component blank, water or other suitable solution may be applied to the backside of the semiconductor component blank to clean the backside of the semiconductor component blank.

In some embodiments, the pre-cleaning solution includes chelating agents, corrosion inhibitors, amine fluorides, surfactants, or solvents. In some embodiments, amine fluorides and surfactants are optional.

Generally, chelating agents may also be referred to as complexing agents or sequestering agents. Chelating agents have negatively charged ions called ligands, which bind to free metal ions and form soluble combined complexes. Chelating agents can be used to remove metal ions from semiconductor component semi-finished products. Without being bound by any particular theory, the chelating agent may also reduce or prevent corrosion of the bottom plug 105 exposed through the opening 400 .

In some embodiments, the chelating agent of the pre-cleaning solution includes ethylenediaminetetraacetic acid, polyacrylates, carbonates, phosphonates, gluconates, N, N'-bis(2-hydroxyphenyl) Iminodiacetic acid, triethylenetetraaminohexaacetic acid, deferoxamine B, N, N', N"-tris[2-(N-hydroxycarbonyl)ethyl]-1,3,5-benzenetricarboxamide and and/or ethylenediamine di-o-hydroxyphenylacetic acid. In some embodiments, the concentration of the chelating agent is between about 0.001 mg/L and about 300 mg/L or between about 0.01 mg/L and about 3 mg/L In some embodiments, alternatively, the concentration of the chelating agent is between 1 ppm and about 400 ppm of the pre-cleaning solution, or preferably about 40 ppm of the pre-cleaning solution.

Corrosion inhibitors for pre-cleaning solutions are used to reduce or prevent metal corrosion during subsequent cleaning processes. In some embodiments, the corrosion inhibitor includes a fatty alcohol compound having at least one mercapto group in the molecule. The number of carbon atoms constituting the alcohol compound is 2 or more, and the carbon atom bonded to the mercapto group and the other carbon atom bonded to the hydroxyl group are bonded adjacently. For example, corrosion inhibitors are 2-mercaptoethanol and/or thioglycerol. In some embodiments, the concentration of the corrosion inhibitor in the pre-cleaning solution is from about 0.0001% to about 10% by weight or from about 0.001% to about 1% by weight. When the concentration is too low, the corrosion inhibiting effect may be limited to an unsatisfactory level. However, an excessively high concentration does not always provide a further increased corrosion inhibiting effect, and will make it difficult to handle due to the characteristic odor of the compound having a mercapto group.

Alternatively, in some embodiments, the corrosion inhibitor of the pre-cleaning solution includes an aromatic compound such as benzotriazole and/or 5-methylbenzimidazole. Alternatively, in some embodiments, the corrosion inhibitor of the pre-clean solution includes uric acid, adenine, caffeine, and/or purines.

Alternatively, in some embodiments, the corrosion inhibitor of the pre-clean solution includes glyoxylic acid. Due to the presence of glyoxylic acid as a reducing material, even if the metal material is exposed during the pre-cleaning process, the redox potential of the pre-cleaning solution is controlled by adjusting the concentration of glyoxylic acid in it, between the pre-cleaning solution and the exposed metal material The electron transfer between them can be controlled, so the corrosion of metal materials can be avoided.

Alternatively, in some embodiments, the corrosion inhibitor of the pre-clean solution includes 2-mercaptoethanol, thioglycerol, benzotriazole, 5-methylbenzimidazole, uric acid, adenine, caffeine, purine and/or glyoxylic acid.

In some embodiments, the amine fluorides of the pre-cleaning solution include methylamine hydrofluorate, ethylamine hydrofluoride, propylamine hydrofluoride, tetramethylammonium fluoride, tetraethylammonium fluoride, hydrofluoroethanolamine, hydrofluoric acid Methylethanolamine, dimethylethanolamine hydrofluoride and/or triethylenediamine hydrofluoride. Amine fluoride can be used to remove etch residues.

In some embodiments, the concentration of amine fluoride in the pre-clean solution may be determined according to the composition of the etch residue. For example, the concentration of amine fluoride may be between about 0.1% and about 5% by mass of the total composition of the pre-cleaning solution, or between about 0.2% and about 3% by mass of the total composition of the pre-cleaning solution. By setting the concentration of the amine fluoride within the above-mentioned range, it can be ensured that the amine fluoride in the pre-cleaning solution can remove the etching residue, while preventing the amine fluoride from corroding the metal material of the bottom plug 105 exposed through the opening 400 and inhibiting the Etching of the dielectric layer exposed through the opening 400 . That is, if the concentration of amine fluoride in the pre-cleaning solution is too low, the ability to remove residues will be insufficient; if the concentration is too high, metallic materials may be corroded, and exposed dielectric layers may be etched or undergo structural changes.

The purpose of the surfactant is to prevent the particles from reattaching or redepositing back onto the semiconductor component semifinished product after being removed from the semiconductor component semifinished product. Preventing particle reattachment is critical, as particle reattachment will increase the overall processing time. The purpose of the surfactant is also to impart an affinity for the waterproof material layer. Typically, surfactants are long hydrocarbon chains, usually containing hydrophilic (polar water-soluble groups) and hydrophobic groups (non-polar water-insoluble groups). Surfactants are attached with their non-polar groups to the particles as well as to the front side of the semi-finished semiconductor component. As a result, the polar groups of the surfactant will point away from the wafer and away from the particles towards the pre-cleaning solution covering the front side of the semi-finished semiconductor component. Due to the polar groups of the surfactant on the particles and on the front side of the semiconductor component semi-finished product, the particles bound by the surfactant in solution will be electrostatically repelled by the front side of the semiconductor component semi-finished product.

In some embodiments, the surfactant of the pre-cleaning solution includes nonionic, anionic, or a mixture of nonionic and anionic compounds. Nonionic means that the polar end of the surfactant has an electrostatic rather than ionic charge, and anionic means that the polar end of the surfactant has a negative ionic charge. The nonionic surfactant may be, for example, polyoxyethylene butylphenyl ether, and the anionic surfactant may be, for example, polyoxyethylene alkylphenyl sulfate. In some embodiments, the concentration of one or more surfactants of the pre-cleaning solution is between about 1 ppm and about 100 ppm. In some embodiments, the concentration of nonionic surfactant in the pre-cleaning solution is about 30 ppm and the concentration of anionic surfactant in the pre-cleaning solution is about 30 ppm. In some embodiments, the concentration of the surfactant of the pre-cleaning solution is 0.0001% to 10% by mass of the entire composition of the pre-cleaning solution, or about 0.001% to about 5% by mass of the entire composition of the pre-cleaning solution. By setting the concentration within the above range, wettability to the front surface of the semiconductor element semi-finished product can be ensured commensurate with the concentration of the surfactant.

In some embodiments, the solvent of the pre-cleaning solution may be deionized water.

In some embodiments, the front side of the semi-finished semiconductor device shown in FIG. 5 is to be covered (or soaked) with the pre-cleaning solution for about 2 minutes. Next, the semi-finished semiconductor component can be washed with deionized water to remove the pre-cleaning solution.

In some embodiments, a drying process may be performed after the pre-cleaning process. The drying process is performed by rotating between about 100 rpm and about 6000 rpm or about 3000 rpm for about 20 seconds, and using an air flow to dry the semi-finished semiconductor device. In some embodiments, nitrogen or isopropanol may be used to facilitate the drying process. In some embodiments, the drying process is optional, ie, the cleaning process can be performed directly after rinsing with the pre-cleaning solution.

Traditionally, the cleaning process can be performed with dilute hydrofluoric acid alone without any pre-cleaning treatment. After filling the conductive material into the opening 400 , the underlying bottom plug 105 may be damaged to cause contour defects (eg, undercuts) or electron migration. Conversely, in this embodiment, the underlying bottom plug 105 may be protected by chelating agents and/or corrosion inhibitors contained in the pre-cleaning solution, and as a result, profile defects or electromigration may be reduced or avoided. Therefore, the yield and reliability of the resulting semiconductor element 1A can be improved.

Referring to FIGS. 1 , 6 and 7 , in step S17 , a first barrier layer 601 is conformally formed in the opening 400 .

Referring to FIGS. 6 and 7 , the first barrier layer 601 may be formed by chemical vapor deposition (also referred to as a first chemical vapor deposition process). In detail, the formation of the first barrier layer 601 may include a gas source introducing step, a first purging step, a reactant flowing step and a second purging step. The gas source introduction step, first purge step, reactant flow step, and second purge step can be considered as one cycle. Multiple cycles may be performed to obtain the desired thickness of the first barrier layer 601 .

For example, parts of semi-finished semiconductor devices as shown in FIG. 5 (after pre-cleaning process and cleaning process) will be loaded into the reaction chamber. In the gas source introducing step, a gas source including precursors and reactants may be introduced into the reaction chamber during a period P1. The precursors and reactants can diffuse through the boundary layer and reach the surfaces of the semi-finished semiconductor device shown in FIG. 5 (ie, the top surface of the hard mask layer 501 and the inner surface of the opening 400). Precursors and reactants can be adsorbed and subsequently migrate across the above-mentioned surfaces. Adsorbed precursors and adsorbed reactants can react on the surface and form solid by-products. Solid by-products can form nuclei on the aforementioned surfaces. The nuclei can grow into islands, and the islands can merge into a continuous film on the above-mentioned surface. In the first purge step, a purge gas such as argon may be injected into the reaction chamber to purge out gaseous by-products, unreacted precursors, and unreacted reactants during a period P2.

In the reactant flowing step, during time P3, the reactants may be introduced into the reaction chamber individually to turn the continuous thin film into the first barrier layer 601 . In a second purge step, a purge gas such as argon may be injected into the reaction chamber during period P4 to purge out gaseous by-products and unreacted reactants.

In some embodiments, the precursor is titanium tetrachloride. The reactant is ammonia. Due to the incomplete reaction between titanium tetrachloride and ammonia, titanium tetrachloride and ammonia may react on the surface and form a titanium nitride film containing high chloride contamination. The ammonia in the reactant flow step reduces the chloride content of the titanium nitride film. The titanium nitride film after ammonia treatment can be regarded as the first barrier layer 601 .

In some embodiments, the formation of the first barrier layer 601 using chemical vapor deposition can be performed with the help of plasma. The plasma source can be argon, hydrogen, or a combination thereof.

It should be noted that the first barrier layer 601 formed by the first chemical vapor deposition has a larger grain size than the layer formed by the atomic layer deposition process. As a result, the conductivity of the first barrier layer 601 formed by the first chemical vapor deposition will be improved.

FIG. 8 is a schematic cross-sectional view illustrating a part of the process of the manufacturing method of the semiconductor device 1A according to an embodiment of the present disclosure. FIG. 9 illustrates pulses and intervals of reducing agents in post-processing according to an embodiment of the present disclosure. FIG. 10 exemplifies the pulse and interval time of the reducing agent in the subsequent treatment according to another embodiment of the present disclosure. The vertical axis represents air flow, and the horizontal axis represents time. FIG. 11 and FIG. 12 are cross-sectional schematic diagrams illustrating a part of the process of the manufacturing method of the semiconductor device 1A according to an embodiment of the present disclosure.

Referring to FIG. 1 and FIGS. 8 to 12 , in step S19 , a second barrier layer 603 is conformally formed on the first barrier layer 601 , and a plurality of conductive structures 300 are formed in the opening 400 .

Referring to FIG. 8 , a second barrier layer 603 is conformally formed on the second barrier layer 603 and located in the opening 400 . In some embodiments, the second barrier layer 603 is formed of copper, copper alloy, silver, gold, tungsten, aluminum, nickel, etc., for example. In this embodiment, the second barrier layer 603 is formed of tungsten.

Referring to FIG. 8 , the second barrier layer 603 may be formed by, for example, a pulsed nucleation layer method (also referred to as a second chemical vapor deposition process). Generally, in the pulsed nucleation layer method, pulses of reactants (such as reducing agents or precursors) can be sequentially injected into the reaction chamber, and the reactants are usually removed from the Cleared from the reaction chamber. A first reactant can be adsorbed onto a substrate (eg, first barrier layer 601 ) and available to react with a next reactant (eg, second reactant). This process is repeated in a cyclic fashion (also known as a deposition cycle) until the desired thickness is achieved.

It should be noted that the pulsed nucleation layer method is usually compared with the atomic layer by its higher operating pressure range (greater than 1 Torr) and its higher growth rate per cycle (greater than 1 monolayer growth per cycle). Sedimentation is different. During the pulsed nucleation layer process, the pressure of the chamber ranges from about 1 Torr to about 400 Torr.

For example, the deposition cycle steps of the second chemical vapor deposition process include pulses of a silicon-containing reducing agent and pulses of a tungsten-containing precursor. The first barrier layer 601 is initially exposed to pulses of a silicon-containing reducing agent, followed by pulses of a tungsten-containing precursor. Exposure to pulses of silicon-containing reducing agents and pulses of tungsten-containing precursors can be defined as a deposition cycle. The deposition cycle may be repeated until the desired thickness of the second barrier layer 603 is achieved. By increasing the number of repetitions of the deposition cycle of the second chemical vapor deposition process, the sidewall coverage of the second barrier layer 603 will be increased and have less overhang at the top of the opening 400 .

Silanes and related compounds are adsorbed to the surface of metal nitrides, such as titanium nitride and tungsten nitride, which are used as barrier layer materials in some integrated circuit applications. Any suitable silane or silane derivative can be used as the silicon-containing reducing agent, including organic derivatives of silane. It is generally understood that silanes adsorb on the substrate surface in a self-limiting manner to produce a nominally monolayer silane species. Therefore, the amount of adsorbed species is largely independent of the amount of silane used.

In some embodiments, the substrate temperature is between about 200°C and about 475°C, between about 300°C and about 400°C, or about 300°C. In some embodiments, the chamber pressure is between about 1 Torr and about 350 Torr, or fixed at about 40 Torr, during exposure to pulses of the silicon-containing reducing agent of the deposition cycle. Exposure time (or pulse time) depends in part on dose and chamber conditions. In some embodiments, the first barrier layer 601 is exposed until the surface is sufficiently and uniformly covered with at least one saturated layer of silane species. In some embodiments, the silicon-containing reducing agent is provided alone. In some embodiments, the silicon-containing reducing agent is provided with a carrier gas such as argon or an argon-hydrogen mixture.

Once the first barrier layer 601 is sufficiently covered by the silane substance, the pulse of the silicon-containing reducing agent is stopped. A purge process may be performed to remove residual gaseous reactants near the surface of the first barrier layer 601 . The purging process may be performed using a carrier gas such as argon, hydrogen, nitrogen or helium.

In some embodiments, the tungsten-containing precursor includes tungsten hexafluoride, tungsten hexachloride, or tungsten hexacarbonyl. In some embodiments, tungsten-containing precursors include fluorine-free organometallic compounds such as MDNOW (methylcyclopentadienyl-dicarbonylnitroso-tungsten) and EDNOW (ethylcyclopentadienyl-dicarbonyl- carbonyl nitroso-tungsten). In some embodiments, the tungsten-containing precursor is provided in the form of a diluent gas along with an accompanying gas such as argon, nitrogen, hydrogen, or combinations thereof.

In some embodiments, the substrate temperature is between about 200°C and about 475°C, between about 300°C and about 400°C, or about 300°C. In some embodiments, the chamber pressure is between about 1 Torr and about 350 Torr during exposure to the pulse of the tungsten-containing precursor of the deposition cycle. Dosage of tungsten-containing precursor and substrate exposure time (or pulse time) will vary according to many factors. Typically, exposure can be performed until the adsorbed silane species reacts with the tungsten-containing precursor to be sufficiently consumed to produce the second barrier layer 603 . Thereafter, the pulsing of the tungsten-containing precursor may be stopped and a purge process performed using a carrier gas such as argon, hydrogen, nitrogen, or helium.

Traditionally, atomic layer deposition is used to form an additional layer to improve the sidewall coverage of the second barrier layer 603; in contrast, in this embodiment, by increasing the deposition cycle of the second chemical vapor deposition process The number of repetitions increases the sidewall coverage, and therefore, no additional layers are required; as a result, the complexity and cost of manufacturing the semiconductor element 1A can be reduced.

In some embodiments, the second chemical vapor deposition process includes performing an initial deposition step prior to the deposition cycle of the pulsed nucleation layer method (ie, second chemical vapor deposition). In some embodiments, the initial deposition step includes providing a pulse of a borane-containing precursor followed by a pulse of a tungsten-containing precursor, each pulse followed by a purge pulse. In some embodiments, the borane-containing precursor of the initial deposition step is, for example, borane, diborane, triborane, or a boron halide with hydrogen (eg, BF ₃ , BCl ₃ ). In some embodiments, the borane-containing precursor of the initial deposition step is provided in the form of a diluent gas, which is accompanied by a gas such as argon, nitrogen, hydrogen, silane, or combinations thereof. For example, diborane provides a self-diluting source (eg, 5% diborane and 95% nitrogen).

In some embodiments, the substrate temperature is between about 200°C and about 475°C, between about 300°C and about 400°C, or about 300°C during the pulse of the borane-containing precursor in the initial deposition step. In some embodiments, the chamber pressure is between about 1 Torr and about 350 Torr during the pulse of the borane-containing precursor in the initial deposition step.

In some embodiments, the tungsten-containing precursor for the initial deposition step includes tungsten hexafluoride, tungsten hexachloride, or tungsten hexacarbonyl, or an organometallic compound that does not contain fluorine, such as MDNOW (methylcyclopentadienyl-di carbonylnitroso-tungsten) and EDNOW (ethylcyclopentadienyl-dicarbonylnitroso-tungsten). In some embodiments, the tungsten-containing precursor of the initial deposition step is provided in the form of a diluent gas, which is accompanied by a gas such as argon, nitrogen, hydrogen, or a combination thereof.

In some embodiments, the substrate temperature is between about 200°C and about 475°C, between about 300°C and about 400°C, or about 300°C during exposure to the tungsten-containing precursor. In some embodiments, the chamber pressure is between about 1 Torr and about 350 Torr during exposure to the tungsten-containing precursor.

Referring to FIG. 9 , in some embodiments, after the second barrier layer 603 is formed, post-processing may be performed on the second barrier layer 603 . During post-processing, the second barrier layer 603 may be exposed to pulses of one or more reducing agents prior to forming a subsequent conductive layer on the second barrier layer 603 . Exposure to pulses of reducing agents can increase the resistivity of the overall structure including the second barrier layer 603 and subsequent conductive layers.

Referring to Figure 9, the second barrier layer 603 will be exposed to a plurality of pulses of reducing agent with an interval time between the pulses. During the interval, no reducing agent flows to the second barrier layer 603 . In some embodiments, the reducing agent is diborane, although other reducing agents may also be used. In some embodiments, the flow rate of the reducing agent is between about 100 standard cubic centimeters per minute (seem) and 500 seem during the pulse. In some embodiments, the pulse time (or pulse duration) of each pulse of reducing agent is between about 0.5 seconds and about 5 seconds, or between about 1 second and 2 seconds. In some embodiments, the number of pulses of reducing agent is between 2 and 8. In some embodiments, the post-treatment process pressure is between about 2 Torr and about 100 Torr, or between about 20 Torr and about 40 Torr.

In some embodiments, the reducing agent is provided in the form of a diluent gas, which is accompanied by a gas such as argon, nitrogen, hydrogen, silane, or combinations thereof. For example, diborane provides a self-diluting source (eg, 5% diborane and 95% nitrogen). In some embodiments, the inert gas/hydrogen mixture may flow continuously to the second barrier layer 603 during the interval between the reductant pulse and the post-treatment. In some embodiments, the inert gas is argon. Conversely, no gas other than the continuous flow of inert gas/hydrogen mixture or other background gas flows to the second barrier layer 603 during the post-processing interval, i.e., the interval between pulses of reducing agent During this time, there is no intervening pulse operation.

In some embodiments, the semiconductor component blank shown in FIG. 8 may be preheated to between about 375° C. and about 415° C., or about 395° C. to stabilize the semiconductor component blank prior to post-processing. In some embodiments, the post-processed semiconductor component blank may be heated to between about 375°C and about 415°C, or about 395°C. The preheating process before the post-exposure treatment and the heat treatment after the post-treatment can enhance the adhesion of the film and improve the non-uniformity of the sheet resistance.

In some embodiments, after post-processing, the second barrier layer 603 is exposed to additional tungsten-containing precursors to form the second barrier layer 603 before subsequently depositing a conductive layer on the second barrier layer 603 additional part of . Any suitable tungsten-containing precursor may be used. For example, tungsten-containing precursors include tungsten hexafluoride, tungsten hexachloride, or tungsten hexacarbonyl. The tungsten-containing precursor may be provided in the form of a diluent gas with an accompanying gas such as argon, nitrogen, hydrogen, or combinations thereof.

Referring to FIG. 10 , alternatively, in some embodiments, the second barrier layer 603 is alternately exposed to pulses of multiple reducing agents with an interval between pulses. During the interval, no reducing agent flows to the second barrier layer 603 . In some embodiments, reducing agents such as diborane and tungsten-containing precursors may be alternately flowed (or introduced) into the second barrier layer 603 .

In some embodiments, the flow rate of diborane is between about 100 seem and about 500 seem, or about 300 seem. In some embodiments, the tungsten-containing precursor includes, for example, tungsten hexafluoride, tungsten hexachloride, or tungsten hexacarbonyl. The flow rate of the tungsten-containing precursor is between about 100 seem and about 500 seem, or about 100 seem. In some embodiments, the pulse time (or pulse duration) is between about 0.5 seconds and 5 seconds, or between about 1 second and 2 seconds. In some embodiments, the interval between each pulse is between about 2 seconds and about 5 seconds. In some embodiments, the number of pulses is between 2 and 8. In some embodiments, the chamber pressure is between about 2 Torr and about 100 Torr, or between about 20 Torr and about 40 Torr.

In some embodiments, the pulse time should be short enough to ensure no or substantially no tungsten deposition. In some embodiments, the amount of the tungsten-containing precursor applied to the second barrier layer 603 during post-processing is less than the amount of the tungsten-containing precursor applied to the first barrier layer 601 during the formation of the second barrier layer 603 . In some embodiments, the pulse time of the tungsten-containing precursor applied to the second barrier layer 603 during post-processing is less than that of the tungsten-containing precursor applied to the first barrier layer 601 during the formation of the second barrier layer 603. pulse time.

In certain embodiments, the reducing agent and tungsten-containing precursor pulses can be as short as less than 1 second. In one example, diborane (B2H6) would be pulsed for 1 second, followed by a 1 second purge, followed by a 1 second pulse of tungsten hexafluoride (WF6), followed by a 2.5 second purge. This cycle will repeat four times.

Without being bound by a particular theory, the introduction of tungsten hexafluoride pulses between diborane pulses can help clear unreacted diborane from the surface of the second barrier layer 603, which would otherwise promote micro-lifting.

In some embodiments, post-processing will be performed for between about 10 seconds and about 50 seconds, or between about 10 seconds and about 30 seconds. Longer post-treatment times (or durations) may lead to the decomposition of diborane, which has an adverse effect on the resistivity of subsequent conductive layers.

In some embodiments, an etching process may be performed after forming the second barrier layer 603 to remove the overhang (if any) of the second barrier layer 603 at the top of the opening 400 . In some embodiments, the etching process may be an anisotropic etching process. In some embodiments, an etch process may be performed prior to post-processing. In some embodiments, the etch process may be performed after post-processing.

Referring to FIG. 11 , a layer of conductive material 507 may be formed on the second barrier layer 603 and completely fill the opening 400 . In some embodiments, the conductive material 507 may be the same material as the second barrier layer 603 (eg, tungsten). The conductive material layer 507 can be deposited by, for example, physical vapor deposition, atomic layer deposition, molecular layer deposition, chemical vapor deposition, in-situ free radical assisted deposition, metal organic chemical vapor deposition, molecular beam epitaxy, sputtering, electroplating, evaporation, Formed by ion beam deposition, electron beam deposition, laser assisted deposition, chemical solution deposition, or combinations thereof. In this embodiment, the conductive material layer 507 is formed by chemical vapor deposition (also referred to as third chemical vapor deposition).

In some embodiments, the third chemical vapor deposition includes an initial deposition step, a deposition cycle, and a bulk step. The initial deposition step of the third chemical vapor deposition is performed by a procedure similar to that of the initial deposition step of the second chemical vapor deposition shown in FIG. 8 , which will not be repeated here. The deposition cycle of the third chemical vapor deposition is performed through a program similar to the steps of the deposition cycle of the second chemical vapor deposition shown in FIG. 8 , which will not be repeated here. The main step of the third chemical vapor deposition includes flowing (or introducing) a tungsten-containing precursor and a co-reactant such as a reducing agent into the semi-finished semiconductor device including the second barrier layer 603 . An example process pressure for the main step of the third chemical vapor deposition is between about 10 Torr and about 500 Torr. An exemplary substrate temperature for the main step of the third chemical vapor deposition is between about 250°C and about 495°C. The tungsten-containing precursor of the bulk step of the third chemical vapor deposition is, for example, tungsten hexafluoride, tungsten chloride or tungsten hexacarbonyl. The reducing agent for the bulk step of the third chemical vapor deposition is, for example, hydrogen, silane, disilane, hydrazine, diborane or germane. By including bulk steps rather than relying on deposition cycles, the opening 400 can be filled in less time.

Since the second barrier layer 603 formed by the second chemical vapor deposition method can provide good sidewall coverage, the subsequently formed conductive material layer 507 can fill the opening 400 without forming a void. Accordingly, the formed conductive material layer 507 may have improved conductivity.

In some embodiments, the number of repetitions of the deposition cycle step of the third chemical vapor deposition is less than the number of repetitions of the deposition cycle step of the second chemical vapor deposition. In some embodiments, the number of repetitions of the deposition cycle step of the third chemical vapor deposition and the number of repetitions of the deposition cycle step of the second chemical vapor deposition may be the same or substantially the same.

In some embodiments, the grain size of tungsten in the conductive material layer 507 is greater than 30 nm, greater than 50 nm, greater than 70 nm, greater than 80 nm, greater than 85 nm, or greater than 87 nm. In some embodiments, the layer of conductive material 507 includes alpha-phase tungsten.

Referring to FIG. 12, a planarization process, such as chemical mechanical polishing, is performed until the top surface of the top dielectric layer 207 is exposed to remove excess material and provide a substantially planar surface for subsequent processing steps. After the planarization process, the remaining conductive material 507 in the opening 400 is regarded as the conductive structures 300 . For brevity, clarity and convenience of description, only one conductive structure 300 is described.

12, the conductive structure 300 includes a bottom portion 301 in the bottom dielectric layer 201, a lower intermediate portion 303 in the lower intermediate dielectric layer 203 and on the bottom portion 301, in the upper intermediate dielectric layer 205 and in the lower An upper middle portion 305 on the middle dielectric layer 203 , and a top portion 307 on the upper dielectric layer 207 and the upper middle portion 305 .

It should be noted that the shape of the conductive structure 300 is determined by the opening 400 . For example, the top dielectric layer 207 or the lower intermediate dielectric layer 203 includes an extended sidewall profile. The upper middle portion 305 includes a hyperbolic-like sidewall profile. The bottom portion 301 includes a tapered sidewall profile. Therefore, the critical dimension CD2 of the upper middle portion 305 is smaller than the critical dimension CD1 of the lower middle portion 303 or CD3 of the top portion 307 . The critical dimension CD4 of the bottom portion 301 is smaller than the critical dimension CD1 of the lower middle portion 303 . In some embodiments, the CD1 and CD3 of the lower middle portion 303 are substantially the same. In some embodiments, the CD1 and CD3 of the lower middle portion 303 are different. Since the critical dimension CD2 of the upper middle portion 305 is smaller, the distance between adjacent upper middle portions 305 can be increased, and as a result, the parasitic capacitance of adjacent conductive structures 300 can be reduced.

In some embodiments, the critical dimension CD2 of the upper middle portion 305 is less than the critical dimension CD4 of the bottom portion 301 . In some embodiments, CD2 of upper middle portion 305 and CD4 of bottom portion 301 are substantially the same.

By using different carbon concentrations for different layers of the insulating stack 200, CD can be controlled even if the same etch chemistry is used for the different layers of the insulating stack 200, and as a result, the overlay of the bottom plug 105 by the conductive structure 300 can be improved. ), while keeping the parasitic capacitance from adjacent conductive structures 300 low.

FIG. 13 is a schematic cross-sectional view illustrating a semiconductor device 1B according to another embodiment of the present disclosure.

Referring to FIG. 13 , a semiconductor element 1B has a structure similar to that shown in FIG. 12 . Components in FIG. 13 that are the same as or similar to those in FIG. 12 have been labeled with similar component numbers, and repeated descriptions have been omitted.

Referring to FIG. 13 , the insulation stack 200 includes only a bottom dielectric layer 201 , an upper intermediate dielectric layer 205 and a top dielectric layer 207 . The upper intermediate dielectric layer 205 is disposed on the bottom dielectric layer 201 . Conductive structure 300 includes a bottom portion 301 , an upper middle portion 305 and a top 307 . The upper middle part 305 is disposed on the bottom part 301 and in the upper middle dielectric layer 205 .

One aspect of the present invention provides a semiconductor device, including a first insulating layer disposed on a substrate; a bottom plug disposed in the first insulating layer; a bottom dielectric layer, a lower intermediate dielectric layer, an upper middle dielectric layer and a top dielectric layer are sequentially stacked on the first insulating layer; and a conductive structure includes a bottom portion disposed in the bottom dielectric layer and on the bottom plug, one in the middle part, disposed on the bottom part and in the lower intermediate dielectric layer, an upper middle part, disposed on the lower middle part and in the upper middle dielectric layer, and a top part, disposed in the upper middle partially on and in the top dielectric layer. The carbon concentration of the lower middle dielectric layer is greater than the carbon concentration of the bottom dielectric layer.

Another aspect of the present invention provides a semiconductor device, including a first insulating layer disposed on a substrate; a bottom plug disposed in the first insulating layer; a bottom dielectric layer, a lower intermediate dielectric layer , an upper middle dielectric layer and a top dielectric layer are sequentially stacked on the first insulating layer; and a conductive structure includes a bottom portion disposed in the bottom dielectric layer and on the bottom plug, once a middle portion disposed on the bottom portion and in the lower intermediate dielectric layer, an upper middle portion disposed on the lower middle portion and in the upper intermediate dielectric layer, and a top portion disposed on the upper The middle portion is on and in the top dielectric layer. The carbon concentration of the upper middle dielectric layer is greater than the carbon concentration of the bottom dielectric layer.

Another aspect of the present invention provides a method for preparing a semiconductor device, comprising forming a first insulating layer on a substrate; forming a bottom plug in the first insulating layer; sequentially forming a bottom dielectric layer, a lower interposer An electrical layer, an upper intermediate dielectric layer, and a top dielectric layer are on the first insulating layer; an opening etching process is performed to form the top dielectric layer, the upper intermediate dielectric layer, and the lower intermediate dielectric layer layer and an opening of the bottom dielectric layer, thereby exposing the bottom plug; and forming a conductive structure in the opening. The carbon concentration of the lower middle dielectric layer is greater than the carbon concentration of the bottom dielectric layer.

Due to the design of the semiconductor element of the present disclosure, by using different carbon concentrations for different layers of the insulating stack 200, even using the same etch chemistry for different layers of the insulating stack 200 can control the critical dimension, and as a result, the conductive structure 300 can be improved to Covering of the bottom plug 105 . Furthermore, due to the small critical dimension of the upper middle portion 305 of the conductive structure 300, the parasitic capacitance originating from the adjacent conductive structure 300 can be kept at a low level.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, A composition of matter, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patent scope of this application.

1A: Semiconductor components

1B: Semiconductor components

101: Base

103: The first insulating layer

105: Bottom plug

200: insulation stack

201: bottom dielectric layer

203: lower intermediate dielectric layer

205: upper intermediate dielectric layer

207: top dielectric layer

300: conductive structure

301: Bottom part

303: lower middle part

305: upper middle part

307: top part

400: opening

501: hard mask layer

503: opening

505: mask layer

507: Conductive material

601: The first barrier layer

603: Second barrier layer

CD1: critical dimension

CD2: critical dimension

CD3: critical dimension

CD4: critical dimension

T1: Thickness

T2: Thickness

T3: Thickness

T4: Thickness

The disclosure content of the present application can be understood more fully when the drawings are combined with the embodiments and the patent scope of the application. The same reference numerals in the drawings refer to the same components. FIG. 1 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure; 2 to 6 are schematic cross-sectional views illustrating a partial process for preparing a semiconductor device according to an embodiment of the present disclosure; FIG. 7 illustrates the process conditions for forming the first barrier layer according to an embodiment of the present disclosure; FIG. 8 is a schematic cross-sectional view illustrating a partial process of preparing a semiconductor device according to an embodiment of the present disclosure; FIG. 9 illustrates the pulse and interval time of the reducing agent in the subsequent treatment according to an embodiment of the present disclosure; FIG. 10 illustrates the pulse and interval time of the reducing agent in the subsequent treatment according to another embodiment of the present disclosure; 11 and FIG. 12 are cross-sectional schematic diagrams illustrating a part of the process for preparing a semiconductor device according to an embodiment of the present disclosure; FIG. 13 is a schematic cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure.

1A: Semiconductor components

101: Base

103: The first insulating layer

105: Bottom plug

200: insulation stack

201: bottom dielectric layer

203: lower intermediate dielectric layer

205: upper intermediate dielectric layer

207: top dielectric layer

300: conductive structure

301: Bottom part

303: lower middle part

305: upper middle part

307: top part

400: opening

501: hard mask layer

503: opening

505: mask layer

507: Conductive material

601: The first barrier layer

603: Second barrier layer

CD1: critical dimension

CD2: critical dimension

CD3: critical dimension

CD4: critical dimension

Claims (17)

A semiconductor element, comprising: a first insulating layer disposed on a base; a bottom plug disposed in the first insulating layer; a bottom dielectric layer, an upper middle dielectric layer and a top dielectric layer , stacked sequentially on the first insulating layer; and a conductive structure comprising: a bottom portion disposed in the bottom dielectric layer and on the bottom plug, and including a tapered sidewall profile; an upper middle a portion disposed on the bottom portion and in the upper middle dielectric layer and comprising a type of hyperbolic sidewall profile; and a top portion disposed on the upper middle portion and in the top dielectric layer, and It includes an extended sidewall profile; wherein the carbon concentration of the upper intermediate dielectric layer is greater than the carbon concentration of the bottom dielectric layer; and wherein the carbon concentration of the upper intermediate dielectric layer is less than the carbon concentration of the top dielectric layer. The semiconductor device as claimed in claim 1, wherein the tapered sidewall profile of the bottom portion gradually becomes wider from bottom to top. The semiconductor device as claimed in claim 2, wherein the critical dimension of the upper middle portion is smaller than the critical dimension of the top portion. The semiconductor device as claimed in claim 3, wherein the critical dimension of the upper middle portion is smaller than the critical dimension of the bottom portion. The semiconductor device as claimed in claim 3, wherein the critical dimension of the upper middle portion is substantially the same as that of the bottom portion. The semiconductor device as claimed in claim 3, wherein the dielectric constant of the bottom dielectric layer is greater than the dielectric constant of the upper middle dielectric layer. The semiconductor device as claimed in claim 6, wherein the dielectric constant of the upper middle dielectric layer is greater than the dielectric constant of the top dielectric layer. The semiconductor device as claimed in claim 7, wherein the bottom dielectric layer comprises silicon oxide and silicon nitride. The semiconductor device as claimed in claim 3, wherein the thickness of the upper middle dielectric layer is greater than the thickness of the top dielectric layer. The semiconductor device as claimed in claim 1, further comprising a lower intermediate dielectric layer located between the bottom dielectric layer and the upper intermediate dielectric layer, wherein the carbon concentration of the lower intermediate dielectric layer and the top dielectric layer The layers have substantially the same carbon concentration, and wherein the conductive structure further includes a lower middle portion disposed between the upper middle portion and the bottom portion and in the lower middle dielectric layer and including an extended sidewall profile. The semiconductor device as claimed in claim 10, wherein the critical dimension of the upper middle portion is smaller than the critical dimension of the lower middle portion. A method for manufacturing a semiconductor element, comprising: forming a first insulating layer on a substrate; forming a bottom plug in the first insulating layer; sequentially forming a bottom dielectric layer, a lower middle dielectric layer, and an upper middle A dielectric layer and a top dielectric layer are on the first insulating layer; an opening etching process is performed to form layer, and thereby expose the bottom plug, wherein the opening etching process includes a first phase and a second phase, wherein the first phase is used to etch the top dielectric layer, the upper intermediate dielectric layer and the lower intermediate dielectric layer, and the second stage is used to etch the bottom dielectric layer, and wherein the etch chemistry of the first stage is different from the etch chemistry of the second stage; and forming a conductive structure in the opening; wherein the carbon concentration of the lower interlayer dielectric layer is greater than the carbon concentration of the bottom dielectric layer; wherein a rate at which the lower intervening dielectric layer is etched is higher than a rate at which the upper intervening dielectric layer is etched, and the top dielectric layer is etched layer at a rate higher than the rate at which the upper interlayer dielectric layer is etched. The method of manufacturing a semiconductor device as claimed in claim 12, wherein the carbon concentration of the upper interlayer dielectric layer is smaller than the carbon concentration of the lower interlayer dielectric layer. The method of manufacturing a semiconductor device as claimed in claim 13, wherein the carbon concentration of the top dielectric layer is greater than the carbon concentration of the upper middle dielectric layer. The method of manufacturing a semiconductor device as claimed in claim 14, wherein the carbon concentration of the upper middle dielectric layer is greater than the carbon concentration of the bottom dielectric layer. The method of manufacturing a semiconductor device as claimed in claim 15, wherein the dielectric constant of the bottom dielectric layer is greater than the dielectric constant of the upper middle dielectric layer. The method of manufacturing a semiconductor element as claimed in claim 16, wherein the dielectric constant of the upper intermediate dielectric layer is greater than that of the lower intermediate dielectric layer.