TW202345329A - Semiconductor device with multi-carbon-concentration dielectrics - Google Patents

Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first insulating layer positioned on a substrate; a bottom contact positioned in the first insulating layer; a bottom dielectric layer, a lower middle dielectric layer, a higher middle dielectric layer, and a top dielectric layer sequentially stacked on the first insulating layer; and a conductive structure including a bottom portion positioned in the bottom dielectric layer and on the bottom contact, a lower middle portion positioned on the bottom portion and in the lower middle dielectric layer, a higher middle portion positioned on the lower middle portion and in the higher middle dielectric layer, and a top portion positioned on the higher middle portion and in the top dielectric layer. A carbon concentration of the lower middle dielectric layer is greater than a carbon concentration of the bottom dielectric layer.

Description

Semiconductor components with multiple carbon concentration dielectric layers

This application claims priority to U.S. Patent Application Nos. 17/740,527 and 17/741,365 (that is, the priority date is "May 10, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device having a multiple carbon concentration dielectric layer and a manufacturing method thereof.

Semiconductor components are used in a variety of electronic applications such as personal computers, mobile phones, digital cameras and other electronic devices. To meet the growing demand for computing power, semiconductor components continue to shrink in size. However, shrinking the size has led to various problems in the manufacturing process, and these problems have continuously led to different situations. Therefore, challenges remain in improving the performance, quality, yield, and reliability of semiconductor components, as well as reducing complexity.

The above description of "prior art" is only to provide background technology, and does not admit that the above description of "prior art" reveals the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and any description of the above "prior art" None should form any part of this case.

One aspect of the present invention provides a semiconductor component, including a first insulating layer disposed on a substrate; a bottom plug disposed in the first insulating layer; a bottom dielectric layer, an intermediate dielectric layer, An upper middle dielectric layer and a top dielectric layer are sequentially stacked on the first insulating layer; and a conductive structure includes a bottom portion disposed in the bottom dielectric layer and on the bottom plug, below the middle a portion disposed on the bottom portion and in the lower middle dielectric layer, an upper middle portion disposed on the lower middle portion and in the upper middle dielectric layer, and a top portion disposed on the upper middle portion portion on and in the top dielectric layer. The carbon concentration of the lower middle dielectric layer is greater than the carbon concentration of the bottom dielectric layer.

Another aspect of the present invention provides a semiconductor element, including a first insulating layer disposed on a substrate; a bottom plug disposed in the first insulating layer; a bottom dielectric layer and an intermediate dielectric layer , an upper middle dielectric layer and a top dielectric layer are sequentially stacked on the first insulating layer; and a conductive structure includes a bottom portion disposed in the bottom dielectric layer and on the bottom plug, below a middle portion disposed on the bottom portion and in the lower middle dielectric layer, an upper middle portion disposed on the lower middle portion and in the upper middle dielectric layer, and a top portion disposed on the upper middle dielectric layer The middle portion is on and in the top dielectric layer. The carbon concentration of the upper middle dielectric layer is greater than the carbon concentration of the bottom dielectric layer.

Another aspect of the present invention provides a method for preparing a semiconductor device, which includes forming a first insulating layer on a substrate; forming a bottom plug in the first insulating layer; and sequentially forming a bottom dielectric layer and an intermediate interposer. electrical layer, an upper middle dielectric layer and a top dielectric layer on the first insulating layer; an opening etching process is performed to form a layer along the top dielectric layer, the upper middle dielectric layer and the lower middle dielectric layer. layer and an opening in the bottom dielectric layer, thereby exposing the bottom plug; and forming a conductive structure in the opening. The carbon concentration of the lower middle dielectric layer is greater than the carbon concentration of the bottom dielectric layer.

Due to the design of the semiconductor element of the present disclosure, by using different carbon concentrations for different layers of the insulating stack, the critical dimensions can be controlled even using the same etch chemistry for different layers of the insulating stack, and as a result, the conductive structure can be improved for the bottom plug In addition, due to the smaller critical size of the upper middle portion of the conductive structure, the parasitic capacitance originating from the adjacent conductive structure can be kept at a low level.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

The following description of the disclosure, accompanied by the drawings, which are incorporated in and constitute a part of the specification, illustrates embodiments of the disclosure, but the disclosure is not limited to the embodiments. In addition, the following embodiments may be appropriately integrated to complete another embodiment.

"One embodiment", "an embodiment", "exemplary embodiment", "other embodiments", "another embodiment", etc. mean that the embodiments described in the present disclosure may include specific features, structures or characteristics. However, Not every embodiment must include a particular feature, structure, or characteristic. Furthermore, repeated use of the phrase "in an embodiment" does not necessarily refer to the same embodiment, but may.

In order that the disclosure may be fully understood, the following description provides detailed steps and structures. Obviously, the practice of the present disclosure will not be limited to the specific details known to those skilled in the art. In addition, known structures and steps are not described in detail to avoid unnecessarily limiting the present disclosure. Preferred embodiments of the present disclosure are described in detail below. However, in addition to the detailed description, the present disclosure can also be widely implemented in other embodiments. The scope of the present disclosure is not limited to the contents of the detailed description, but is defined by the patent claims.

In this disclosure, a semiconductor element generally refers to a device that can function by taking advantage of semiconductor properties. For example, electro-optical devices, light-emitting display devices, semiconductor circuits and electronic devices will all be included in the category of semiconductor components.

It should be noted that in the description of the present invention, above (or upper) corresponds to the direction of the Z-direction arrow, and lower (or lower) corresponds to the opposite direction of the Z-direction arrow.

FIG. 1 is a flow chart illustrating a method 10 for manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. 2 to 6 are schematic cross-sectional views illustrating part of the process of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 7 illustrates process conditions for forming the first barrier layer according to an embodiment of the present disclosure.

Referring to Figures 1 and 2, in step S11, a substrate 101 is provided, a first insulating layer 103 is formed on the substrate 101, a plurality of bottom plugs 105 are formed in the first insulating layer 103, and an insulating stack 200 is formed in the first insulating layer 103. on an insulating layer 103, and a hard mask layer 501 is formed on the insulating stack 200.

2, substrate 101 includes a bulk semiconductor substrate composed entirely of at least one semiconductor material, a plurality of device elements (not shown for clarity), a plurality of dielectric layers (not shown for clarity), and a plurality of conductive features (not shown for clarity). The bulk semiconductor substrate is formed of semiconductor elements such as silicon or germanium; or silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other III-V groups Or formed by semiconductor compounds such as II-VI semiconductor materials; or formed by a combination of the above.

In some embodiments, substrate 101 includes a semiconductor-on-insulator structure consisting, from bottom to top, of a processing substrate, an insulator layer, and a topmost semiconductor material layer. The handle substrate and the topmost semiconductor material layer are formed from the same material as the bulk semiconductor substrate described above. The insulator layer is a crystalline or amorphous dielectric material, such as an oxide and/or nitride. For example, the insulator layer is a dielectric oxide, such as silicon oxide. For another example, the insulator layer is a dielectric nitride, such as silicon nitride or boron nitride. As another example, the insulator layer includes a stack of dielectric oxide and dielectric nitride, such as silicon oxide and silicon nitride or boron nitride stacked in any order. The insulator layer has a thickness of between approximately 10 nanometers and 200 nanometers.

In this disclosure, the term "about" or "approximately" used to modify the quantity of an ingredient, component, or reactant means, for example, by typical measurements used to prepare a concentrate or solution and Possible numerical changes in liquid handling procedures. In addition, variations may arise from inadvertent errors in measurement procedures, differences in the manufacture, source, or purity of ingredients used in making compositions or performing methods, for example. In some aspects, the term "about" or "approximately" refers to a change within 10% of the indicated value. In other aspects, the term "about" or "approximately" means a variation within 5% of the indicated value. In other respects, the term "about" or "approximately" means a change within 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2% or 1% of the indicated value. .

Referring to Figure 2, device elements are formed on a bulk semiconductor substrate or topmost layer of semiconductor material. Some portions of the device elements are formed in the bulk semiconductor substrate or in the topmost semiconductor material layer. The device elements are transistors, such as complementary metal oxide semiconductor transistors, metal oxide semiconductor field effect transistors, fin field effect transistors, etc., or combinations thereof.

Referring to FIG. 2, a dielectric layer is formed on a bulk semiconductor substrate or topmost semiconductor material layer and covers the device components. In some embodiments, the dielectric layer is made of silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric materials, etc., or combinations thereof. form. Low dielectric constant dielectric materials have a dielectric constant less than 3.0 or even less than 2.5. In some embodiments, the low-k dielectric material has a dielectric constant less than 2.0. The dielectric layer is formed through a deposition process such as chemical vapor deposition, plasma enhanced chemical vapor deposition, etc. A planarization process is performed after the deposition process to remove excess material and provide a substantially flat surface for subsequent processing steps.

Referring to Figure 2, the conductive features include a plurality of interconnect layers and a plurality of conductive vias. The interconnect layers are separated from each other and are arranged horizontally in the dielectric layer along the direction Z. The conductive vias connect adjacent interconnect layers along direction Z and connect adjacent device components and interconnect layers. In some embodiments, conductive vias can improve heat dissipation and can provide structural support. In some embodiments, the conductive features are formed from metal carbides such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (eg, tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (eg, nitrogen Titanium oxide), transition metal aluminides, or combinations thereof. The conductive features are formed during formation of the dielectric layer.

In some embodiments, device elements and conductive features together constitute multiple functional units in substrate 101 . In the description of the present disclosure, a functional unit generally refers to a functionally related circuit that is divided into different units for functional purposes. In some embodiments, functional units are typically highly complex circuits, such as processor cores, memory controllers, or accelerator units. In some other embodiments, the degree of complexity and functionality of the functional units may depend on actual needs.

Referring to FIG. 2 , the first insulating layer 103 is formed on the substrate 101 and is made of, for example, silicon dioxide, undoped silicate glass, fluorosilicate glass, borophosphosilicate glass, spin-coated low dielectric constant dielectric. An electrical layer, a chemical vapor deposition low-k dielectric layer, or a combination thereof. In some embodiments, the first insulating layer 103 includes a self-planarizing material such as spin-on glass or a spin-on low-k dielectric material such as SiLK™. Using self-planarizing dielectric materials can avoid the need to perform subsequent planarization processes. In some embodiments, the first insulating layer 103 may be formed by a deposition process, including chemical vapor deposition, plasma enhanced chemical vapor deposition, evaporation, or spin coating. In some embodiments, a planarization process, such as chemical mechanical polishing, may be performed to provide a substantially planar surface for subsequent processing steps.

Referring to FIG. 2 , bottom plugs 105 are formed along first insulating layer 103 and are electrically coupled to device elements of substrate 101 through corresponding conductive features of substrate 101 . In some embodiments, bottom plug 105 is made of materials such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (eg, tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (eg, Titanium nitride), transition metal aluminides, or combinations thereof. The bottom plug 105 is formed by, for example, an embedded process or other applicable processes.

Referring to FIG. 2 , the insulation stack 200 includes a bottom dielectric layer 201 , a lower middle dielectric layer 203 , an upper middle dielectric layer 205 and a top dielectric layer 207 .

Referring to FIG. 2 , a bottom dielectric layer 201 is formed on the first insulating layer 103 . In some embodiments, the bottom dielectric layer 201 is made of, for example, silicon dioxide, undoped silicate glass, fluorosilicate glass, borophosphosilicate glass, silicon nitride, silicon oxynitride, oxynitride Formed from silicon, phosphosilicate glass, or combinations thereof. In some embodiments, the bottom dielectric layer 201 is a high-k dielectric material (dielectric constant greater than 7.0), including but not limited to metal oxides, such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum Oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide , alumina, lead scandium tantalum oxide, and lead zinc niobate. In this embodiment, the bottom dielectric layer 201 is silicon oxide or silicon nitride.

Referring to FIG. 2 , a lower middle dielectric layer 203 is formed on the bottom dielectric layer 201 . In some embodiments, lower intermediary dielectric layer 203 is formed of, for example, carbon-doped oxide or organosilicate glass. In some embodiments, the lower middle dielectric layer 203 is formed of, for example, a spin-coated low-k dielectric layer, a chemical vapor-deposited low-k dielectric layer, a porous polymer material, or a combination thereof.

Referring to FIG. 2 , an upper middle dielectric layer 205 is formed on the lower middle dielectric layer 203 . In some embodiments, upper intermediary dielectric layer 205 is formed from, for example, carbon-doped oxide or organosilicate glass. In some embodiments, the upper middle dielectric layer 205 is formed of, for example, a spin-coated low-k dielectric layer, a chemical vapor-deposited low-k dielectric layer, a porous polymer material, or a combination thereof.

Referring to FIG. 2 , a top dielectric layer 207 is formed on the upper middle dielectric layer 205 . In some embodiments, top dielectric layer 207 is formed of, for example, carbon-doped oxide or organosilicate glass. In some embodiments, top dielectric layer 207 is formed of, for example, a spin-coated low-k dielectric layer, a chemical vapor-deposited low-k dielectric layer, a porous polymer material, or a combination thereof. In some embodiments, the lower middle dielectric layer 203 and the top dielectric layer 207 are formed of the same material.

In some embodiments, the lower middle dielectric layer 203 , the upper middle dielectric layer 205 , and the top dielectric layer 207 are formed by exposing an energy-removable material to an energy source such as heat, light, or a combination thereof. The porous layer formed. When heat is used as the energy source, the temperature of the energy treatment is between about 800°C and about 900°C. When using light as an energy source, ultraviolet light can be used.

In some embodiments, the porous layer includes a skeleton and a plurality of spaces disposed between the skeleton. The spaces are interconnected and filled with air. The backbone includes a low dielectric material or methylsilsesquioxane. The porous layer has a porosity between 25% and 75%. Due to the aforementioned spaces, the porous layer is filled with air, and as a result, the dielectric constant of the porous layer will be significantly lower than a layer formed of, for example, silicon oxide. Therefore, the porous layer will significantly reduce the parasitic capacitance between the conductive features formed therein.

In some embodiments, energy removable materials include, for example, thermally decomposable materials, photon decomposable materials, electron beam decomposable materials, or combinations thereof. For example, energy-removable materials include a substrate and a decomposable porogen material that is sacrificially removed upon exposure to an energy source. In some embodiments, the decomposable porogen material includes a porogen organic compound that imparts porosity to a substrate of energy-removable material.

In some embodiments, the porosity of the lower middle dielectric layer 203 (or the top dielectric layer 207) is greater than the porosity of the upper middle dielectric layer 205. In some embodiments, the porosity of lower middle dielectric layer 203 and the porosity of top dielectric layer 207 are substantially the same. In some embodiments, the porosity of the lower middle dielectric layer 203 and the top dielectric layer 207 are different. For example, the porosity of the top dielectric layer 207 is greater than the porosity of the lower middle dielectric layer 203 .

Referring to FIG. 2 , in some embodiments, the carbon concentration of lower middle dielectric layer 203 (or top dielectric layer 207 ) is greater than the carbon concentration of upper middle dielectric layer 205 . The carbon concentration of the upper middle dielectric layer 205 is greater than the carbon concentration of the bottom dielectric layer 201 . In some embodiments, the carbon concentration of lower middle dielectric layer 203 and the carbon concentration of top dielectric layer 207 are substantially the same. In some embodiments, the carbon concentration of lower middle dielectric layer 203 and the carbon concentration of top dielectric layer 207 are different. For example, the carbon concentration of the lower middle dielectric layer 203 is greater or less than the carbon concentration of the top dielectric layer 207 .

Referring to FIG. 2 , in some embodiments, the dielectric constant of the lower middle dielectric layer 203 (or the top dielectric layer 207 ) is less than the dielectric constant of the upper middle dielectric layer 205 . The dielectric constant of the upper middle dielectric layer 205 is smaller than the dielectric constant of the bottom dielectric layer 201 .

Referring to FIG. 2 , in some embodiments, the thickness T1 of the lower middle dielectric layer 203 is less than the thickness T2 of the upper middle dielectric layer 205 . In some embodiments, thickness T2 is greater than thickness T3 of top dielectric layer 207 .

In some embodiments, the thickness T1 of the lower middle dielectric layer 203 and the thickness T3 of the top dielectric layer 207 are substantially the same. In some embodiments, the thickness T1 of the lower middle dielectric layer 203 and the thickness T3 of the top dielectric layer 207 are different. For example, the thickness T1 of the lower middle dielectric layer 203 is greater than the thickness T3 of the top dielectric layer 207 .

In some embodiments, the thickness T1 of the lower middle dielectric layer 203 and the thickness T4 of the bottom dielectric layer 201 are substantially the same. In some embodiments, the thickness T1 of the lower middle dielectric layer 203 and the thickness T4 of the bottom dielectric layer 201 are different. For example, the thickness T4 of the bottom dielectric layer 201 is greater than the thickness T1 of the lower middle dielectric layer 203 .

Referring to FIG. 2 , a hard mask layer 501 is formed on the top dielectric layer 207 . In some embodiments, the hard mask layer 501 is formed of, for example, boron nitride, silicon boron nitride, boron nitride phosphorus, silicon boron carbon nitride, or the like. The hard mask layer 501 can be formed through a film forming process and a processing process. Specifically, during the film formation process, a first precursor may be introduced above the top dielectric layer 207 to form a boron-based layer, and the first precursor is a boron-based precursor. Subsequently, during the processing process, a second precursor, which is a nitrogen-based precursor, may be introduced to react with the boron-based layer and convert the boron-based layer into the hard mask layer 501 . In some embodiments, the first precursor is an alkyl-substituted boron derivative such as diborane, borazine, or borazane. In some embodiments, the second precursor is, for example, ammonia or hydrazine.

Referring to FIGS. 1 , 3 and 4 , in step S13 , the hard mask layer 501 is patterned to form a plurality of hard mask openings 503 .

Referring to FIG. 3 , a mask layer 505 is formed on the hard mask layer 501 . Mask layer 505 is a photoresist layer and includes a pattern of hard mask openings 503 .

Referring to FIG. 4 , a hard mask etching process is performed to remove portions of the hard mask layer 501 to form hard mask openings 503 . Portions of top dielectric layer 207 will be exposed through hard mask opening 503 . After the hard mask opening 503 is formed, the mask layer 505 can be removed by, for example, an ashing process or other applicable processes.

Referring to FIGS. 1 and 5 , in step S15 , a plurality of openings 400 are formed along the insulation stack 200 to expose the bottom plug 105 .

For simplicity, clarity and convenience of description, only one opening 400 is described.

Referring to FIG. 5 , an opening etching process is performed to remove portions of the top dielectric layer 207 , the upper middle dielectric layer 205 , the lower middle dielectric layer 203 and the bottom dielectric layer 201 to form an opening 400 . In some embodiments, the etching chemistries of the top dielectric layer 207, the upper middle dielectric layer 205, and the lower middle dielectric layer 203 are the same during the opening etch process. However, during the opening etching process, the etching rate of the upper middle dielectric layer 205 is different from the etching rate of the top dielectric layer 207 (or the lower middle dielectric layer 203). In some embodiments, the etch rate during the opening etching process is related to the carbon concentration of the corresponding layer. For example, the etch rate for the lower middle dielectric layer 203 (which has a higher carbon concentration) is higher than the etch rate for the upper middle dielectric layer 205 (which has a lower carbon concentration).

Therefore, the final profile of the opening 400 will be related to the etch rate of the different layers. For example, for top dielectric layer 207 (or lower middle dielectric layer 203) with a higher carbon concentration, a higher etch rate may result in a laterally expanded expanded sidewall profile. Conversely, for upper intermediary dielectric layer 205 with a lower carbon concentration, a lower etch rate will result in a hyperbolic-like sidewall profile.

Referring to FIG. 5 , in the opening etching process, the etching chemistry of the lower middle dielectric layer 203 is different from the etching chemistry of the bottom dielectric layer 201 . For example, the opening etching process is a two-stage etching process. The first stage is used to etch the top dielectric layer 207 , the upper middle dielectric layer 205 and the lower middle dielectric layer 203 , and the second stage is used to etch the bottom dielectric layer 201 . The resulting sidewall profile will be dependent on the etch chemistry. In some embodiments, the sidewall profile of the opening 400 corresponding to the bottom dielectric layer 201 is tapered. In some embodiments, the width of the opening 400 corresponding to the bottom dielectric layer 201 may gradually widen from bottom to top along the Z direction. In some embodiments, the sidewall profile of the opening 400 corresponding to the bottom dielectric layer 201 has a uniform slope as a whole.

It should be noted that some etch residue may be left after the opening etching process (not shown for clarity). The etching residue may be residual material on the inner surface of the opening 400 after the opening etching process. Depending on the material to be etched, the etching residue can have different compositions. Etching residues may adversely affect the yield and/or reliability of the resulting semiconductor component 1A. A cleaning process can be performed to remove etching residues. However, conventional cleaning processes using dilute hydrogen fluoride may result in undercutting of bottom plug 105 , which may result in electron migration during subsequent deposition of opening 400 . As a result, the yield and/or reliability of the produced semiconductor element 1A may be affected.

In some embodiments, a pre-cleaning process may be performed prior to the cleaning process to reduce adverse effects of traditional cleaning processes (eg, undercutting of the bottom plug 105).

During the pre-cleaning process, the semi-finished semiconductor device shown in FIG. 5 (after the opening etching process) will rotate at a speed between about 10 rpm and about 2000 rpm or between about 100 rpm and 1000 rpm. The pre-cleaning solution will be sprayed onto the semiconductor component semi-finished product to cover the entire front surface of the semiconductor component semi-finished product. While the pre-cleaning solution is applied to the front side of the semiconductor element semi-finished product, water or other suitable solution may be applied to the back side of the semiconductor element semi-finished product to clean the back side of the semiconductor element semi-finished product.

In some embodiments, the pre-cleaning solution includes chelating agents, corrosion inhibitors, amine fluorides, surfactants, or solvents. In some embodiments, amine fluoride and surfactants are optional.

Generally, chelating agents are also called complexing agents or clamping agents. Chelating agents have negatively charged ions called ligands that combine with free metal ions and form soluble combinatorial complexes. Chelating agents can be used to remove metal ions from semi-finished semiconductor components. Without being bound by any particular theory, the chelating agent may also reduce or prevent corrosion of the bottom plug 105 exposed through the opening 400.

In some embodiments, chelating agents for the pre-cleaning solution include ethylenediaminetetraacetic acid, polyacrylates, carbonates, phosphonates, gluconates, N, N'-bis(2-hydroxyphenyl)ethylene glycol Iminodiacetic acid, triethylenetetraminhexaacetic acid, deferoxamine B, N, N', N"-tris[2-(N-hydroxycarbonyl)ethyl]-1,3,5-benzenetricarboxamide and / or ethylenediamine di-ortho-hydroxyphenylacetic acid. In some embodiments, the concentration of the chelating agent is between about 0.001 mg/L and about 300 mg/L or between about 0.01 mg/L and about 3 mg/L In some embodiments, alternatively, the chelating agent concentration is between 1 ppm and about 400 ppm of the pre-cleaning solution, or preferably about 40 ppm of the pre-cleaning solution.

Corrosion inhibitors in pre-cleaning solutions are used to reduce or avoid metal corrosion during subsequent cleaning processes. In some embodiments, the corrosion inhibitor includes a fatty alcohol compound having at least one sulfhydryl group in the molecule. The number of carbon atoms constituting the alcohol compound is 2 or more, and the carbon atom bonded to the mercapto group and the other carbon atom bonded to the hydroxyl group are adjacently bonded. For example, corrosion inhibitors are 2-mercaptoethanol and/or thioglycerol. In some embodiments, the concentration of corrosion inhibitor in the pre-cleaning solution is from about 0.0001% to about 10% by weight or from about 0.001% to about 1% by weight. When the concentration is too low, the corrosion inhibition effect may be limited to an unsatisfactory level. However, too high a concentration does not always provide a further increased corrosion inhibition effect and will make it difficult to handle due to the characteristic odor of compounds containing sulfhydryl groups.

Alternatively, in some embodiments, the corrosion inhibitor of the pre-cleaning solution includes aromatic hydrocarbon compounds, such as benzotriazole and/or 5-methylbenzimidazole. Alternatively, in some embodiments, the corrosion inhibitor of the pre-cleaning solution includes uric acid, adenine, caffeine, and/or purines.

Alternatively, in some embodiments, the corrosion inhibitor of the pre-cleaning solution includes glyoxylic acid. Due to the presence of glyoxylic acid as a reducing material, even if the metal material is exposed during the pre-cleaning process, the redox potential of the pre-cleaning solution is controlled by adjusting the concentration of glyoxylic acid, which is between the pre-cleaning solution and the exposed metal material. The electron transfer between them can be controlled, so corrosion of metal materials can be avoided.

Alternatively, in some embodiments, the corrosion inhibitor of the pre-cleaning solution includes 2-mercaptoethanol, thioglycerol, benzotriazole, 5-methylbenzimidazole, uric acid, adenine, caffeine, purine, and/or Glyoxylic acid.

In some embodiments, the amine fluoride of the pre-cleaning solution includes methylamine hydrofluoride, ethylamine hydrofluoride, propylamine hydrofluoride, tetramethylammonium fluoride, tetraethylammonium fluoride, ethanolamine hydrofluoride, hydrofluoric acid Methyl ethanolamine, dimethylethanolamine hydrofluoride and/or triethylenediamine hydrofluoride. Amine fluorides can be used to remove etching residues.

In some embodiments, the concentration of amine fluoride in the pre-clean solution can be determined based on the composition of the etch residue. For example, the concentration of the amine fluoride may be between about 0.1 mass % and about 5 mass % of the entire composition of the pre-cleaning solution, or between about 0.2 mass % and about 3 mass % of the entire composition of the pre-cleaning solution. By setting the concentration of the amine fluoride within the above range, it can be ensured that the amine fluoride in the pre-cleaning solution can remove etching residues, while preventing the amine fluoride from corroding the metal material of the bottom plug 105 exposed through the opening 400 and inhibiting corrosion. Etching of the dielectric layer exposed through opening 400 . That is, if the concentration of amine fluoride in the pre-cleaning solution is too low, the ability to remove residues will be insufficient; if the concentration is too high, the metal material may be corroded, and the exposed dielectric layer may be etched or undergo structural changes.

The purpose of the surfactant is to prevent the particles from reattaching or redepositing back onto the semi-finished semiconductor component after they have been removed from the semi-finished semiconductor component. Preventing particle re-attachment is critical as particle re-attachment will increase the overall processing time. The purpose of surfactants is also to impart affinity to the layer of waterproofing material. Typically, surfactants are long hydrocarbon chains, often containing hydrophilic (polar water-soluble groups) and hydrophobic groups (non-polar water-insoluble groups). Surfactants attach their non-polar groups to the particles and to the front side of semi-finished semiconductor components. As a result, the polar groups of the surfactant will point away from the wafer and away from the particles towards the pre-cleaning solution covering the front side of the semi-finished semiconductor component. Due to the polar groups of the surfactant on the front surface of the particles and the semiconductor element semi-finished product, the particles bound by the surfactant in the solution will be electrostatically repelled by the front surface of the semiconductor element semi-finished product.

In some embodiments, the surfactant of the precleaning solution includes nonionic, anionic, or a mixture of nonionic and anionic compounds. Nonionic means that the polar end of the surfactant has an electrostatic rather than ionic charge, and anionic means that the polar end of the surfactant has a negative ionic charge. The nonionic surfactant may be, for example, polyoxyethylene butyl phenyl ether, and the anionic surfactant may be, for example, polyoxyethylene alkylphenyl sulfate. In some embodiments, the pre-cleaning solution has a concentration of one or more surfactants between about 1 ppm and about 100 ppm. In some embodiments, the concentration of nonionic surfactant in the precleaning solution is about 30 ppm and the concentration of anionic surfactant in the precleaning solution is about 30 ppm. In some embodiments, the surfactant concentration of the pre-cleaning solution is from 0.0001 to 10 mass % of the entire composition of the pre-cleaning solution, or from about 0.001 to about 5 mass % of the entire composition of the pre-cleaning solution. By setting the concentration within the above range, wettability to the front surface of the semiconductor element semi-finished product can be ensured commensurate with the concentration of the surfactant.

In some embodiments, the solvent of the pre-cleaning solution may be deionized water.

In some embodiments, the front side of the semiconductor device semi-finished product shown in FIG. 5 will be covered (or soaked) in the pre-cleaning solution for about 2 minutes. Next, the semi-finished semiconductor component can be cleaned using deionized water to remove the pre-cleaning solution.

In some embodiments, a drying process may be performed after the pre-cleaning process. The drying process is performed by rotating between about 100 rpm and about 6000 rpm or between about 3000 rpm for about 20 seconds and using air flow to dry the semi-finished semiconductor device. In some embodiments, nitrogen or isopropanol may be used to facilitate the drying process. In some embodiments, the drying process is optional, that is, the cleaning process can be performed directly after rinsing with the pre-cleaning solution.

Traditionally, the cleaning process can be performed using dilute hydrofluoric acid alone without any pre-cleaning treatment. After filling conductive material into opening 400, the underlying bottom plug 105 may be damaged to cause profile defects (eg, undercutting) or electron migration. Conversely, in this embodiment, the underlying bottom plug 105 may be protected by chelating agents and/or corrosion inhibitors contained in the pre-cleaning solution, and as a result, profile defects or electron migration may be reduced or avoided. Therefore, the yield and reliability of the resulting semiconductor element 1A can be improved.

Referring to FIGS. 1 , 6 and 7 , in step S17 , a first barrier layer 601 is conformally formed in the opening 400 .

Referring to FIGS. 6 and 7 , the first barrier layer 601 may be formed by chemical vapor deposition (also called a first chemical vapor deposition process). In detail, the formation of the first barrier layer 601 may include a gas source introduction step, a first purge step, a reactant flow step and a second purge step. The gas source introduction step, the first purge step, the reactant flow step and the second purge step can be regarded as a cycle. Multiple cycles may be performed to obtain the desired thickness of first barrier layer 601.

For example, components of the semiconductor device semi-finished product shown in FIG. 5 (after the pre-cleaning process and the cleaning process) will be loaded into the reaction chamber. In the gas source introduction step, during the period P1, a gas source including precursors and reactants may be introduced into the reaction chamber. The precursors and reactants can diffuse through the boundary layer and reach the surface of the semi-finished semiconductor device shown in FIG. 5 (ie, the top surface of the hard mask layer 501 and the inner surface of the opening 400). Precursors and reactants can adsorb and subsequently migrate on such surfaces. Adsorbed precursors and adsorbed reactants can react on the surface and form solid by-products. Solid by-products can nucleate on such surfaces. Cores can grow into islands, and islands can coalesce into continuous films on the surface. In the first purging step, during the period P2, a purging gas such as argon can be injected into the reaction chamber to purge out gaseous by-products, unreacted precursors and unreacted reactants.

In the reactant flow step, during time P3, reactants may be individually introduced into the reaction chamber to turn the continuous film into the first barrier layer 601. In the second purge step, during period P4, a purge gas such as argon may be injected into the reaction chamber to purge out gaseous by-products and unreacted reactants.

In some embodiments, the precursor is titanium tetrachloride. The reactant is ammonia. Due to the incomplete reaction between titanium tetrachloride and ammonia, titanium tetrachloride and ammonia may react on the surface and form a titanium nitride film containing high chloride contamination. Ammonia in the reactant flow step reduces the chloride content of the titanium nitride film. The ammonia-treated titanium nitride film can be regarded as the first barrier layer 601 .

In some embodiments, the formation of the first barrier layer 601 using chemical vapor deposition may be performed with the help of plasma. The plasma source may be argon, hydrogen, or a combination thereof.

It should be noted that the first barrier layer 601 formed by the first chemical vapor deposition has a larger grain size than the layer formed by the atomic layer deposition process. As a result, the conductivity of the first barrier layer 601 formed by the first chemical vapor deposition will be improved.

FIG. 8 is a schematic cross-sectional view illustrating part of the process of a method for manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. FIG. 9 illustrates the pulse and interval time of the reducing agent in post-processing according to an embodiment of the present disclosure. Figure 10 illustrates the pulse and interval time of the reducing agent in post-processing according to another embodiment of the present disclosure. The vertical axis represents air flow and the horizontal axis represents time. 11 and 12 are schematic cross-sectional views illustrating part of the process of a method of manufacturing a semiconductor device 1A according to an embodiment of the present disclosure.

Referring to FIG. 1 and FIG. 8 to FIG. 12 , in step S19 , a second barrier layer 603 is conformally formed on the first barrier layer 601 , and a plurality of conductive structures 300 are formed in the opening 400 .

Referring to FIG. 8 , a second barrier layer 603 is conformally formed on the second barrier layer 603 and located in the opening 400 . In some embodiments, the second barrier layer 603 is formed of, for example, copper, copper alloy, silver, gold, tungsten, aluminum, nickel, or the like. In this embodiment, the second barrier layer 603 is formed of tungsten.

Referring to FIG. 8 , the second barrier layer 603 may be formed by, for example, a pulsed nucleation layer method (also called a second chemical vapor deposition process). Typically, in pulsed nucleation layer methods, pulses of reactants (e.g., reducing agents or precursors) can be injected sequentially into the reaction chamber, and the reactants are removed from the reaction chamber, typically by pulses of purge gas between the pulses of the reactants. Purge the reaction chamber. The first reactant can be adsorbed to the substrate (eg, first barrier layer 601) and available to react with the next reactant (eg, second reactant). The above process is repeated in a cyclic fashion (also called a sedimentation cycle) until the desired thickness is achieved.

It should be noted that the pulse nucleation layer method is usually compared with the atomic layer by its higher operating pressure range (greater than 1 Torr) and its higher growth rate per cycle (greater than 1 monolayer per cycle). Deposition is different. During the pulse nucleation layer method, the chamber pressure ranges from about 1 Torr to about 400 Torr.

For example, the deposition cycle step of the second chemical vapor deposition process includes pulses of a silicon-containing reducing agent and pulses of a tungsten-containing precursor. The first barrier layer 601 is initially exposed to a pulse of a silicon-containing reducing agent and then to a pulse of a tungsten-containing precursor. Exposure to pulses of silicon-containing reducing agents and pulses of tungsten-containing precursors can be defined as a deposition cycle. The deposition cycle may be repeated until the desired thickness of second barrier layer 603 is achieved. By increasing the number of repetitions of the deposition cycle of the second chemical vapor deposition process, the sidewall coverage of the second barrier layer 603 will be improved and there will be less overhang at the top of the opening 400 .

Silanes and related compounds are adsorbed to metal nitride surfaces, such as titanium nitride and tungsten nitride, which are used as barrier materials in some integrated circuit applications. Any suitable silane or silane derivative serves as the silicon-containing reducing agent, including organic derivatives of silane. It is generally understood that silane adsorbs on the substrate surface in a self-limiting manner to produce a nominal monolayer of silane species. Therefore, the amount of adsorbed species is largely independent of the silane dosage.

In some embodiments, the substrate temperature is between about 200°C and about 475°C, between about 300°C and about 400°C, or about 300℃. In some embodiments, the chamber pressure is between about 1 Torr and about 350 Torr, or fixed at about 40 Torr, during pulse exposure to the silicon-containing reducing agent of the deposition cycle. Exposure time (or pulse time) depends in part on dose and chamber conditions. In some embodiments, first barrier layer 601 is exposed until the surface is sufficiently and uniformly covered by at least one saturated silane material layer. In some embodiments, the silicon-containing reducing agent is provided separately. In some embodiments, the silicon-containing reducing agent is provided with a carrier gas, such as argon or an argon-hydrogen mixture.

Once the first barrier layer 601 is sufficiently covered by the silane species, the pulsing of the silicon-containing reducing agent will cease. A purge process may be performed to remove residual gas reactants near the surface of the first barrier layer 601. The purge process can be performed using a carrier gas such as argon, hydrogen, nitrogen or helium.

In some embodiments, the tungsten-containing precursor includes tungsten hexafluoride, tungsten hexachloride, or tungsten hexacarbonyl. In some embodiments, the tungsten-containing precursor includes fluorine-free organometallic compounds, such as MDNOW (methylcyclopentadienyl-dicarbonylnitroso-tungsten) and EDNOW (ethylcyclopentadienyl-dicarbonylnitroso-tungsten). carbonylnitroso-tungsten). In some embodiments, the tungsten-containing precursor is provided as a diluent gas, along with an accompanying gas such as argon, nitrogen, hydrogen, or combinations thereof.

In some embodiments, the substrate temperature is between about 200°C and about 475°C, between about 300°C and about 400°C, or about 300°C. In some embodiments, the chamber pressure is between about 1 Torr and about 350 Torr during pulse exposure to the tungsten-containing precursor of the deposition cycle. The dosage of the tungsten-containing precursor and the substrate exposure time (or pulse time) will vary depending on many factors. Generally, the exposure may be performed until the adsorbed silane species is fully consumed by the reaction with the tungsten-containing precursor to produce the second barrier layer 603 . Thereafter, the pulsing of the tungsten-containing precursor can be stopped and a purge process performed using a carrier gas such as argon, hydrogen, nitrogen, or helium.

Traditionally, atomic layer deposition is needed to form an additional layer to improve the sidewall coverage of the second barrier layer 603; in contrast, in this embodiment, by increasing the deposition cycle of the second chemical vapor deposition process The number of repetitions is used to increase the sidewall coverage, and therefore, no additional layers are required; as a result, the complexity and cost of preparing the semiconductor element 1A can be reduced.

In some embodiments, the second chemical vapor deposition process includes performing an initial deposition step before the deposition cycle of the pulse nucleation layer method (ie, the second chemical vapor deposition). In some embodiments, the initial deposition step includes providing a pulse of a borane-containing precursor followed by a pulse of a tungsten-containing precursor, each pulse followed by a purge pulse. In some embodiments, the borane-containing precursor of the initial deposition step is, for example, borane, diborane, triborane, or a boron halide with hydrogen (eg, BF ₃ , BCl ₃ ). In some embodiments, the borane-containing precursor of the initial deposition step is provided in the form of a diluent gas accompanied by a gas such as argon, nitrogen, hydrogen, silane, or combinations thereof. For example, diborane provides a self-diluting source (eg, 5% diborane and 95% nitrogen).

In some embodiments, the substrate temperature is between about 200°C and about 475°C, between about 300°C and about 400°C, or about 300°C during the pulsing of the borane-containing precursor in the initial deposition step. In some embodiments, during the pulsing of the borane-containing precursor in the initial deposition step, the chamber pressure is between about 1 Torr and about 350 Torr.

In some embodiments, the tungsten-containing precursor for the initial deposition step includes tungsten hexafluoride, tungsten hexachloride, or tungsten hexacarbonyl, or a fluorine-free organometallic compound, such as MDNOW (methylcyclopentadienyl-dihydrogen). carbonylnitroso-tungsten) and EDNOW (ethylcyclopentadienyl-dicarbonylnitroso-tungsten). In some embodiments, the tungsten-containing precursor of the initial deposition step is provided in the form of a diluent gas accompanied by a gas such as argon, nitrogen, hydrogen, or combinations thereof.

In some embodiments, during exposure to the tungsten-containing precursor, the substrate temperature is between about 200°C and about 475°C, between about 300°C and about 400°C, or about 300°C. In some embodiments, the chamber pressure is between about 1 Torr and about 350 Torr during exposure to the tungsten-containing precursor.

Referring to FIG. 9 , in some embodiments, after the second barrier layer 603 is formed, the second barrier layer 603 may be post-processed. During post-processing, the second barrier layer 603 may be exposed to pulses of one or more reducing agents before forming a subsequent conductive layer thereon. Pulses of exposure to the reducing agent may increase the resistivity of the overall structure including the second barrier layer 603 and the subsequent conductive layer.

Referring to Figure 9, the second barrier layer 603 will be exposed to multiple pulses of the reducing agent with intervals between pulses. During the interval, no reducing agent flows to the second barrier layer 603 . In some embodiments, the reducing agent is diborane, but other reducing agents may also be used. In some embodiments, the flow rate of the reducing agent during the pulse is between about 100 standard cubic centimeters per minute (sccm) and 500 sccm. In some embodiments, the pulse time (or pulse duration) of each pulse of reducing agent is between about 0.5 seconds and about 5 seconds, or between about 1 second and 2 seconds. In some embodiments, the number of pulses of reducing agent is between 2 and 8. In some embodiments, the post-processing process pressure is between about 2 Torr and about 100 Torr, or between about 20 Torr and about 40 Torr.

In some embodiments, the reducing agent is provided as a diluent gas accompanied by a gas such as argon, nitrogen, hydrogen, silane, or combinations thereof. For example, diborane provides a self-diluting source (eg, 5% diborane and 95% nitrogen). In some embodiments, the inert gas/hydrogen mixture may flow continuously to the second barrier layer 603 during intervals between reductant pulses and post-processing. In some embodiments, the inert gas is argon. Conversely, no other gas flows to the second barrier layer 603 other than a continuous flow of the inert gas/hydrogen mixture or other background gases during the intervals of post-processing, i.e., the intervals between pulses of the reducing agent During this time, there is no intervening pulse operation.

In some embodiments, before post-processing, the semiconductor element semi-finished product shown in FIG. 8 can be preheated to between about 375°C and about 415°C, or about 395°C to stabilize the semiconductor element semi-finished product. In some embodiments, the semi-finished semiconductor device after post-processing may be heated to between about 375°C and about 415°C, or about 395°C. The preheating process before exposure post-treatment and the heat treatment after post-treatment can enhance the adhesion of the film and improve the non-uniformity of sheet resistance.

In some embodiments, after post-processing, the second barrier layer 603 is exposed to an additional tungsten-containing precursor to form the second barrier layer 603 before subsequently depositing a conductive layer thereon. of extra parts. Any suitable tungsten-containing precursor may be used. For example, tungsten-containing precursors include tungsten hexafluoride, tungsten hexachloride or tungsten hexacarbonyl. The tungsten-containing precursor may be provided in the form of a diluent gas, accompanied by a gas such as argon, nitrogen, hydrogen, or a combination thereof.

Referring to Figure 10, alternatively, in some embodiments, the second barrier layer 603 is alternately exposed to pulses of a plurality of reducing agents with intervals between pulses. During the interval, no reducing agent flows to the second barrier layer 603 . In some embodiments, reducing agents such as diborane and tungsten-containing precursors may alternately flow (or be introduced) into the second barrier layer 603 .

In some embodiments, the flow rate of diborane is between about 100 sccm and about 500 sccm, or about 300 sccm. In some embodiments, the tungsten-containing precursor includes, for example, tungsten hexafluoride, tungsten hexachloride, or tungsten hexacarbonyl. The flow rate of the tungsten-containing precursor is between about 100 sccm and about 500 sccm, or about 100 sccm. In some embodiments, the pulse time (or pulse duration) is between about 0.5 seconds and 5 seconds, or between about 1 second and 2 seconds. In some embodiments, the time between each pulse is between about 2 seconds and about 5 seconds. In some embodiments, the number of pulses is between 2 and 8. In some embodiments, the chamber pressure is between about 2 Torr and about 100 Torr, or between about 20 Torr and about 40 Torr.

In some embodiments, the pulse time should be short enough to ensure no or substantially no tungsten deposition. In some embodiments, the amount of tungsten-containing precursor applied to second barrier layer 603 during post-processing is less than the amount of tungsten-containing precursor applied to first barrier layer 601 during formation of second barrier layer 603 . In some embodiments, the pulse time of the tungsten-containing precursor applied to the second barrier layer 603 during post-processing is less than the tungsten-containing precursor applied to the first barrier layer 601 during the formation of the second barrier layer 603 . pulse time.

In certain embodiments, the reducing agent and tungsten-containing precursor pulses can be as short as less than 1 second. In one example, diborane (B2H6) will be pulsed for 1 second, followed by a 1 second purge, then followed by a 1 second pulse of tungsten hexafluoride (WF6), and finally followed by a 2.5 second purge. This cycle will be repeated four times.

Without being bound by a particular theory, introducing tungsten hexafluoride pulses between diborane pulses can help clear unreacted diborane from the surface of second barrier layer 603, which would otherwise promote the occurrence of microstripping.

In some embodiments, post-processing will be performed between about 10 seconds and about 50 seconds, or between about 10 seconds and about 30 seconds. Longer post-processing times (or durations) may cause diborane to decompose, which can adversely affect the resistivity of subsequent conductive layers.

In some embodiments, an etching process may be performed after forming the second barrier layer 603 to remove the overhang of the second barrier layer 603 at the top of the opening 400 , if any. In some embodiments, the etching process may be an anisotropic etching process. In some embodiments, the etching process may be performed before post-processing. In some embodiments, the etching process may be performed after post-processing.

Referring to FIG. 11 , a layer of conductive material 507 may be formed on the second barrier layer 603 and completely fill the opening 400 . In some embodiments, conductive material 507 may be the same material as second barrier layer 603 (eg, tungsten). The conductive material layer 507 can be formed by, for example, physical vapor deposition, atomic layer deposition, molecular layer deposition, chemical vapor deposition, in-situ radical-assisted deposition, metal-organic chemical vapor deposition, molecular beam epitaxy, sputtering, electroplating, evaporation, Formed by ion beam deposition, electron beam deposition, laser-assisted deposition, chemical solution deposition, or a combination thereof. In this embodiment, the conductive material layer 507 is formed by chemical vapor deposition (also called third chemical vapor deposition).

In some embodiments, the third chemical vapor deposition includes an initial deposition step, a deposition cycle, and a bulk step. The initial deposition step of the third chemical vapor deposition is performed by a procedure similar to the initial deposition step of the second chemical vapor deposition shown in FIG. 8 , which will not be described again. The deposition cycle of the third chemical vapor deposition is performed through a procedure similar to the deposition cycle steps of the second chemical vapor deposition shown in FIG. 8 , which will not be described again. The main step of the third chemical vapor deposition includes flowing (or introducing) a tungsten-containing precursor and a coreactant such as a reducing agent into the semi-finished semiconductor device including the second barrier layer 603 . An example process pressure for the third bulk step of chemical vapor deposition is between about 10 Torr and about 500 Torr. Example substrate temperatures for the third bulk step of chemical vapor deposition are between about 250°C and about 495°C. The tungsten-containing precursor of the third bulk step of chemical vapor deposition is, for example, tungsten hexafluoride, tungsten chloride or tungsten hexacarbonyl. The reducing agent of the third bulk step of chemical vapor deposition is, for example, hydrogen, silane, ethylsilane, hydrazine, diborane or germane. By including a bulk step rather than relying on a deposition cycle, opening 400 can be filled in less time.

Since the second barrier layer 603 formed by the second chemical vapor deposition method can provide good sidewall coverage, the subsequently formed conductive material layer 507 can fill the opening 400 without forming voids. Therefore, the formed conductive material layer 507 may have improved conductivity.

In some embodiments, the number of repetitions of the deposition cycle steps of the third chemical vapor deposition is less than the number of repetitions of the deposition cycle steps of the second chemical vapor deposition. In some embodiments, the number of repetitions of the deposition cycle steps of the third chemical vapor deposition and the number of repetitions of the deposition cycle steps of the second chemical vapor deposition may be the same or substantially the same.

In some embodiments, the grain size of tungsten in the conductive material layer 507 is greater than 30 nm, greater than 50 nm, greater than 70 nm, greater than 80 nm, greater than 85 nm, or greater than 87 nm. In some embodiments, conductive material layer 507 includes alpha phase tungsten.

Referring to Figure 12, a planarization process, such as chemical mechanical polishing, is performed until the top surface of top dielectric layer 207 is exposed to remove excess material and provide a substantially planar surface for subsequent processing steps. After the planarization process, the remaining conductive material 507 in the opening 400 is regarded as the conductive structures 300 . For simplicity, clarity and convenience of description, only one conductive structure 300 is described.

Referring to FIG. 12 , the conductive structure 300 includes a bottom portion 301 in the bottom dielectric layer 201 , a lower middle portion 303 in the lower middle dielectric layer 203 and on the bottom portion 301 , a lower middle portion 303 in the upper middle dielectric layer 205 and a lower middle dielectric layer 205 . an upper middle portion 305 on the middle dielectric layer 203, and a top portion 307 on the upper dielectric layer 207 and the upper middle portion 305.

It should be noted that the shape of the conductive structure 300 is determined by the opening 400 . For example, top dielectric layer 207 or lower middle dielectric layer 203 includes an expanded sidewall profile. The upper intermediate portion 305 includes a hyperbolic-like sidewall profile. Bottom portion 301 includes a tapered sidewall profile. Therefore, the critical dimension CD2 of the upper middle portion 305 is smaller than the critical dimension CD1 of the lower middle portion 303 or the critical dimension CD3 of the top portion 307 . The critical dimension CD4 of the bottom portion 301 is smaller than the critical dimension CD1 of the lower middle portion 303 . In some embodiments, critical dimension CD1 and critical dimension CD3 of lower middle portion 303 are substantially the same. In some embodiments, critical dimension CD1 and critical dimension CD3 of lower middle portion 303 are different. Since the critical dimension CD2 of the upper middle portion 305 is smaller, the distance between adjacent upper middle portions 305 can be increased, and as a result, the parasitic capacitance of adjacent conductive structures 300 can be reduced.

In some embodiments, the critical dimension CD2 of the upper middle portion 305 is less than the critical dimension CD4 of the bottom portion 301 . In some embodiments, the critical dimension CD2 of the upper middle portion 305 and the critical dimension CD4 of the bottom portion 301 are substantially the same.

By using different carbon concentrations for different layers of the insulating stack 200, the critical dimensions can be controlled even when using the same etch chemistry for different layers of the insulating stack 200. As a result, the overlay of the bottom plug 105 by the conductive structure 300 can be improved. ), while keeping parasitic capacitances originating from adjacent conductive structures 300 low.

FIG. 13 is a schematic cross-sectional view illustrating a semiconductor device 1B according to another embodiment of the present disclosure.

Referring to FIG. 13 , the semiconductor element 1B has a similar structure to that shown in FIG. 12 . The same or similar elements in FIG. 13 as in FIG. 12 have been labeled with similar element numbers, and repeated descriptions have been omitted.

Referring to FIG. 13 , the insulation stack 200 includes only a bottom dielectric layer 201 , an upper middle dielectric layer 205 and a top dielectric layer 207 . The upper middle dielectric layer 205 is disposed on the bottom dielectric layer 201 . Conductive structure 300 includes a bottom portion 301 , an upper middle portion 305 and a top portion 307 . The upper middle portion 305 is disposed on the bottom portion 301 and in the upper middle dielectric layer 205 .

One aspect of the present invention provides a semiconductor component, including a first insulating layer disposed on a substrate; a bottom plug disposed in the first insulating layer; a bottom dielectric layer, an intermediate dielectric layer, An upper middle dielectric layer and a top dielectric layer are sequentially stacked on the first insulating layer; and a conductive structure includes a bottom portion disposed in the bottom dielectric layer and on the bottom plug, below the middle a portion disposed on the bottom portion and in the lower middle dielectric layer, an upper middle portion disposed on the lower middle portion and in the upper middle dielectric layer, and a top portion disposed on the upper middle portion portion on and in the top dielectric layer. The carbon concentration of the lower middle dielectric layer is greater than the carbon concentration of the bottom dielectric layer.

Another aspect of the present invention provides a semiconductor element, including a first insulating layer disposed on a substrate; a bottom plug disposed in the first insulating layer; a bottom dielectric layer and an intermediate dielectric layer , an upper middle dielectric layer and a top dielectric layer are sequentially stacked on the first insulating layer; and a conductive structure includes a bottom portion disposed in the bottom dielectric layer and on the bottom plug, below a middle portion disposed on the bottom portion and in the lower middle dielectric layer, an upper middle portion disposed on the lower middle portion and in the upper middle dielectric layer, and a top portion disposed on the upper middle dielectric layer The middle portion is on and in the top dielectric layer. The carbon concentration of the upper middle dielectric layer is greater than the carbon concentration of the bottom dielectric layer.

Another aspect of the present invention provides a method for preparing a semiconductor device, which includes forming a first insulating layer on a substrate; forming a bottom plug in the first insulating layer; and sequentially forming a bottom dielectric layer and an intermediate interposer. electrical layer, an upper middle dielectric layer and a top dielectric layer on the first insulating layer; an opening etching process is performed to form a layer along the top dielectric layer, the upper middle dielectric layer and the lower middle dielectric layer. layer and an opening in the bottom dielectric layer, thereby exposing the bottom plug; and forming a conductive structure in the opening. The carbon concentration of the lower middle dielectric layer is greater than the carbon concentration of the bottom dielectric layer.

Due to the design of the semiconductor device of the present disclosure, by using different carbon concentrations for different layers of the insulating stack 200, the critical dimensions can be controlled even using the same etch chemistry for different layers of the insulating stack 200. As a result, the conductive structure 300 can be improved. Bottom plug 105 is covered. Furthermore, due to the smaller critical dimension of the upper middle portion 305 of the conductive structure 300, parasitic capacitance originating from adjacent conductive structures 300 can be kept at a low level.

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the claimed claims. For example, many of the processes described above may be implemented in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, etc. that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patentable scope of this application.

1A: Semiconductor components 1B:Semiconductor components 101: Base 103: First insulation layer 105: Bottom plug 200: Insulation stack 201: Bottom dielectric layer 203:Lower middle dielectric layer 205: Upper middle dielectric layer 207:Top dielectric layer 300:Conductive structure 301: Bottom part 303: Lower middle part 305: Upper middle part 307:Top part 400:Open your mouth 501: Hard mask layer 503:Open your mouth 505: Mask layer 507: Conductive materials 601: First barrier layer 603: Second barrier layer CD1: critical dimension CD2: critical dimension CD3: critical dimension CD4: critical dimension T1:Thickness T2:Thickness T3:Thickness T4:Thickness

The disclosure content of this application can be more fully understood by referring to the embodiments and the patent scope combined with the drawings. The same element symbols in the drawings refer to the same elements. FIG. 1 is a flow chart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure; 2 to 6 are cross-sectional schematic diagrams illustrating part of the process of preparing a semiconductor device according to an embodiment of the present disclosure; FIG. 7 illustrates the process conditions for forming the first barrier layer according to an embodiment of the present disclosure; 8 is a schematic cross-sectional view illustrating part of the process of preparing a semiconductor device according to an embodiment of the present disclosure; Figure 9 illustrates the pulse and interval time of the reducing agent in post-processing according to an embodiment of the present disclosure; Figure 10 illustrates the pulse and interval time of the reducing agent in post-processing according to another embodiment of the present disclosure; 11 and 12 are schematic cross-sectional views illustrating part of the process of preparing a semiconductor device according to an embodiment of the present disclosure; FIG. 13 is a schematic cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure.

1A: Semiconductor components

101: Base

103: First insulation layer

105: Bottom plug

200: Insulation stack

201: Bottom dielectric layer

203:Lower middle dielectric layer

205: Upper middle dielectric layer

207:Top dielectric layer

300:Conductive structure

301: Bottom part

303: Lower middle part

305: Upper middle part

307:Top part

400:Open your mouth

501: Hard mask layer

503:Open your mouth

505: Mask layer

507: Conductive materials

601: First barrier layer

603: Second barrier layer

CD1: critical dimension

CD2: critical dimension

CD3: critical dimension

CD4: critical dimension

Claims (13)

A semiconductor component including: a first insulating layer disposed on a substrate; A bottom plug is provided in the first insulating layer; A bottom dielectric layer, a lower middle dielectric layer, an upper middle dielectric layer and a top dielectric layer are sequentially stacked on the first insulating layer; and An electrically conductive structure, including: a bottom portion disposed in the bottom dielectric layer and on the bottom plug; a lower middle portion disposed on the bottom portion and located in the lower middle dielectric layer; an upper middle portion disposed on the lower middle portion and located in the upper middle dielectric layer; and a top portion disposed on the upper middle portion and located in the top dielectric layer; The carbon concentration of the lower middle dielectric layer is greater than the carbon concentration of the bottom dielectric layer. The semiconductor device of claim 1, wherein the carbon concentration of the upper middle dielectric layer is less than the carbon concentration of the lower middle dielectric layer. The semiconductor device of claim 2, wherein the carbon concentration of the top dielectric layer is greater than the carbon concentration of the upper middle dielectric layer. The semiconductor device of claim 3, wherein the carbon concentration of the upper middle dielectric layer is greater than the carbon concentration of the bottom dielectric layer. The semiconductor device of claim 4, wherein the critical dimension of the lower middle portion is larger than the critical dimension of the bottom portion. The semiconductor device of claim 4, wherein the critical dimension of the upper middle portion is smaller than the critical dimension of the lower middle portion. The semiconductor device of claim 4, wherein the dielectric constant of the bottom dielectric layer is greater than the dielectric constant of the upper middle dielectric layer. The semiconductor device of claim 7, wherein the dielectric constant of the upper middle dielectric layer is greater than the dielectric constant of the lower middle dielectric layer. The semiconductor device of claim 8, wherein the dielectric constant of the lower middle dielectric layer and the dielectric constant of the top dielectric layer are substantially the same. The semiconductor device of claim 9, wherein the bottom dielectric layer includes silicon oxide and silicon nitride. The semiconductor device according to claim 9, wherein the thickness of the upper middle dielectric layer is greater than the thickness of the lower middle dielectric layer. The semiconductor device of claim 9, wherein the bottom portion includes a tapered sidewall profile. The semiconductor device of claim 9, wherein the upper intermediate dielectric layer includes a hyperbolic sidewall profile.