TWI808464B - Modulation circuit of power drive stage - Google Patents

Abstract

The invention is a modulation circuit of power drive stage, which includes a pulse conversion control unit group and a drive-level control unit group. The pulse conversion control unit group includes a side-by-side conversion device. The drive-level control unit group includes a first slew rate conversion module, a first current switch, a second slew rate mapping module, and a second current switch. The first slew rate switch module and the second slew rate module are electrically connecting to the edge conversion module. And the first current switch and the second current switch are electrically connecting a first slew rate module, an output terminal, a high voltage terminal and a ground terminal. The invention can adjust the speed and delay time according to the weight between the signals to fast conversion and reducing output high-frequency noise, by the each module, switch and transistor.

Description

Modulation circuit of a power drive stage

The present invention relates to a modulation circuit of a power drive stage, in particular to a modulation circuit of a power drive stage which can use a weight adjustment method for delayed signals through a first current switch and a second current switch to control the output switching speed to avoid overshoot.

Power drivers are widely used, and the common product name is Low-side Driver. However, when the operating frequency of the power driver is increased, the connection line will cause poor dynamic response of the overall circuit due to the influence of inductive reactance, and cause high-frequency noise such as overshoot and oscillation.

Therefore, the current known technology is to delay and buffer the inductive reactance effect in the way of time-delay dispersing weights. However, in the conventional delay method, when the high-speed conversion of the power drive is performed, because the switching time is too fast, the time of dispersing the weights is delayed so as not to respond quickly. Therefore, the conventional time-delay dispersing weight method cannot meet the requirements of high-speed conversion, nor can it realize more efficient and finer adjustment of the power drive, which in turn affects the quality of the drive circuit and the efficacy of the output.

Therefore, how to provide a fast-switching power drive adjustment circuit to avoid overshoot and oscillation by controlling the switching speed of the output to reduce the high-frequency noise of the output is an issue and focus that those skilled in the art should think about.

One object of the present invention is to provide a modulation circuit of a power drive stage capable of modulating output power.

Another object of the present invention is to provide a power drive regulation circuit that can switch quickly and control the switching speed of the output to avoid overshoot.

The modulation circuit of the power drive stage of the present invention is used to modulate the output power, and includes a pulse conversion control unit group and a drive stage control unit group. The pulse and conversion control unit group provides a delayed pulse signal. The drive stage control unit group is electrically connected to the pulse conversion control unit group, and performs weight control according to the delayed pulse signal to generate a slew rate configuration signal. The delayed pulse signal has a first delayed pulse signal and a second delayed pulse signal. The pulse conversion control unit group includes an edge pulse conversion module. The rate configuration signal has a first slew rate configuration signal and a second slew rate configuration signal, and the driver stage control unit group includes a first slew rate mapping module, a first current switch, a second slew rate mapping module and a second current switch. The edge pulse conversion module receives a data signal and an output enable signal, and generates a first delayed pulse signal and a second delayed pulse signal. The first slew rate mapping module is electrically connected to the edge pulse conversion module and receives the first delayed pulse signal for generating the first slew rate configuration signal. The first current switch is electrically connected to the first slew rate mapping module, an output terminal, a high voltage terminal and a ground terminal, and is used for receiving a previous output signal, a first slew rate configuration signal and a bias signal. The second slew rate mapping module is electrically connected to the edge pulse conversion module for generating a second slew rate configuration signal. The second current switch is electrically connected to the second slew rate mapping module, the output terminal, the high voltage terminal and a ground terminal, and is used for receiving the output signal of the previous stage, the second slew rate configuration signal and the bias signal.

The modulation circuit of the power drive stage mentioned above, wherein the edge pulse conversion module includes: an AND gate, which receives the data signal and outputs the enable signal; an inverse AND gate, which receives the data signal and outputs the enable signal; a plurality of first variable delay units are connected in series and electrically connected to the AND gate, and receive the logic signal output by the AND gate to output the first delayed pulse signal; Outputting the second delayed pulse signal.

The modulation circuit of the power drive stage mentioned above, wherein the first slew rate mapping module includes multiple sets of first switch groups, and these multiple sets of first switch groups respectively include a plurality of first switch units, and each of the first switch units of the first switch groups respectively receives the first delay pulse signals of the first variable delay units, the first slew rate configuration signal and the bias signal; wherein the second slew rate mapping module includes multiple sets of second switch groups, and these multiple sets of second switch groups respectively include multiple second switch units, the second switch groups Each of the second switch units receives the second delayed pulse signals of the second variable delay units, the second slew rate configuration signal and the bias signal respectively.

The modulation circuit of the power drive stage mentioned above, wherein the first current switch and the second current switch respectively include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor, and respectively have a first terminal, a second terminal and a control terminal; wherein the first terminal of the first transistor is electrically connected to the high voltage terminal; the first terminal of the second transistor is electrically connected to the high voltage terminal and the first terminal of the first transistor, the control The terminal is electrically connected to the control terminal of the first transistor, and the second terminal is electrically connected to the output terminal; the control terminal of the third transistor receives the output signal of the previous stage, and the first terminal is electrically connected to the second terminal of the first transistor, the control terminal and the control terminal of the second transistor; the first terminal of the fourth transistor is electrically connected to the second terminal of the second transistor and the output terminal, and the control terminal is electrically connected to the second terminal of the second transistor. The first end of the third transistor, the second end of the first transistor, the control end of the first transistor, and the control end of the second transistor, the second end is electrically connected to the second end of the third transistor; the second end of the fifth transistor receives the bias signal; the control end of the sixth transistor receives the first slew rate configuration signal and is electrically connected to the control end of the fifth transistor, the first end is electrically connected to the first end of the fifth transistor, and the second end is electrically connected The ground terminal; the first end of the seventh transistor is electrically connected to the second end of the fourth transistor and the second end of the third transistor; the control end is electrically connected to the first end of the fifth transistor and the first end of the sixth transistor; the second end is electrically connected to the second end of the sixth transistor and the ground; wherein the control end of the fifth transistor of the first current switch receives the first slew rate configuration signal; The second slew rate configuration signal.

In the modulation circuit of the above-mentioned power driving stage, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are respectively field effect transistors.

In the modulation circuit of the power drive stage mentioned above, the first transistor, the second transistor and the fifth transistor are each an N-type field effect transistor, and the third transistor, the fourth transistor, the sixth transistor and the seventh transistor are each a P-type field effect transistor.

The modulation circuit of the power drive stage mentioned above further includes a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor, and has a first terminal, a second terminal and a control terminal respectively; wherein the seventh transistor system is arranged between the first current switch and the electrical circuit of the high voltage terminal, the first terminal of the seventh transistor is electrically connected to the first current switch, the second terminal is electrically connected to the high voltage terminal, and the control terminal is electrically connected to the first terminal and the first current switch; Between the loop and the eighth transistor, the first end is electrically connected to the output end, and the second end is The control terminal is electrically connected to the high voltage terminal, the control terminal is electrically connected to the control terminal of the seventh transistor and the first current switch; the ninth transistor system is arranged between the second current switch and the electrical loop of the ground terminal, the first terminal of the ninth transistor is electrically connected to the second current switch, the second terminal is electrically connected to the ground terminal, and the control terminal is electrically connected to the first terminal and the second current switch; It is electrically connected to the ground terminal, and the control terminal is electrically connected to the control terminal of the ninth transistor and the second current switch

In the modulation circuit of the above-mentioned power driving stage, the seventh transistor, the eighth transistor, the ninth transistor and the tenth transistor are respectively field effect transistors.

In the modulation circuit of the above-mentioned power driving stage, the seventh transistor and the eighth transistor are respectively a P-type field effect transistor, and the ninth transistor and the tenth transistor are respectively an N-type field effect transistor.

The modulation circuit of the above-mentioned power driving stage further includes a delay module, which provides a delay signal to edge pulse conversion module.

A: Pulse conversion control unit group

B: Drive level control unit group

1: Edge pulse conversion module

2: The first slew rate mapping module

3: The first current switch

4: The second slew rate mapping module

5: Second current switch

7: Delay module

P: the first variable delay unit

N: second variable delay unit

11: and gate

12: Reverse and gate

Data: data signal

OE: output enable signal

En: The first slew rate configuration signal

Fn: Second slew rate configuration signal

Vb: bias signal

Vcc: high voltage end

Vout: output terminal

Gnd: ground terminal

31, 51: the first transistor

32, 52: second transistor

33, 53: the third transistor

34, 54: The fourth transistor

35, 55: fifth transistor

36, 56: the sixth transistor

37, 57: the seventh transistor

68: Eighth transistor

69: ninth transistor

60: Tenth transistor

61: Eleventh transistor

311, 511, 321, 521, 331, 531, 341, 541, 351, 551, 361, 561, 371, 571, 611, 681, 691, 601: first end

312, 512, 322, 522, 332, 532, 342, 542, 352, 552, 362, 562, 372, 572, 612, 682, 692, 602: the second end

310, 510, 320, 520, 330, 530, 340, 540, 350, 550, 360, 560, 370, 570, 610, 680, 690, 600: control terminal

Figure 1 shows a schematic diagram of the modulation circuit of the power drive stage;

Figure 2 is a schematic diagram of the edge pulse conversion module;

FIG. 3 is a schematic diagram of a first slew rate mapping module;

FIG. 4 is a schematic diagram of the second slew rate mapping module;

Figures 5 and 6 show schematic diagrams of transistors; and

FIG. 7 is a schematic diagram of a current switch.

The diagrams of the present invention are all schematic, and are mainly used to represent the connection relationship of each module of the circuit and the transmission relationship between various signals. As for the circuit, signal waveform and frequency, they are not drawn to scale.

Please refer to FIG. 1 . FIG. 1 is a schematic diagram of a modulation circuit of a power driving stage. In one embodiment, the modulation circuit of the power driver stage includes a pulse conversion control unit group A and a driver stage control unit group B. The pulse conversion control unit group A provides a delayed pulse signal. The driver stage control unit group is electrically connected to the pulse conversion control unit group A, and performs weight control according to the delayed pulse signal to generate a slew rate configuration signal. The delayed pulse signal has a first delayed pulse signal P _signal and a second delayed pulse signal N _signal . The slew rate configuration signal has a first The slew rate configuration signal En and a second slew rate configuration signal Fn. In this example, the pulse conversion control unit group includes an edge pulse conversion module 1, and the driver stage control unit group includes a first slew rate mapping module 2, a first current switch 3, a second slew rate mapping module 4, and a second current switch 5, wherein the modulation circuit in this example also includes a delay module 7.

Wherein, the edge pulse conversion module 1 receives a data signal DATA and an output enable signal OE, and generates a first delayed pulse signal P_signaland the second delayed pulse signal N_signalThe first slew rate mapping module 2 is electrically connected to the edge pulse conversion module 1, the first current switch 3 is connected to the first slew rate mapping module 2, an output terminal Vout, a high voltage terminal Vcc and a ground terminal Gnd, and the second slew rate mapping module is electrically connected to the edge pulse conversion module 1, and the second current switch 5 is electrically connected to the second slew rate mapping module, the output terminal Vout, the high voltage terminal Vcc and the ground terminal Gnd, and the modulation circuit of the power drive stage further includes a The delay module 7 is used to provide the delay signal to the edge pulse conversion module 1 .

Referring to FIG. 2 together, in this embodiment, the edge pulse conversion module 1 includes an AND gate 11 , an inverse-AND gate 12 , a plurality of first variable delay units P and a plurality of second variable delay units N. The AND gate 11 and the inverse AND gate 12 receive the data signal Data and output the enable signal OE. In one embodiment, the first variable delay units P are connected in series and electrically connected to the AND gate 11 , and can be used to receive the logic signal output by the AND gate 11 , thereby converting and outputting the first delayed pulse signal P _signal . In addition, in one embodiment, the second variable delay units N are connected in series and electrically connected to the NAND gate 12, and are used to receive the logic signal output by the NAND gate 12, thereby converting and outputting the second delayed pulse signal. It should be noted that the edge pulse conversion module 1 allocates corresponding weights according to the received data signal Data and the output enable signal OE, and outputs the first delayed pulse signal P _signal and the second delayed pulse signal N _signal with corresponding weights through the first variable delay unit P and the second variable delay unit N, so as to facilitate the fast switching of the power drive through weight adjustment without overshooting.

Please continue to refer to FIG. 3 , which is a schematic diagram of the first slew rate mapping module. In one embodiment, the first slew rate mapping module 2 includes a plurality of first switch groups 21, each of which includes a plurality of first switch units 211, and the first switch units 211 respectively receive the first delay pulse signal P _signal of the first variable delay unit P, the first slew rate configuration signal En(E ₀₀ ~E _m0 , E ₀₁ ~E _m1 , E _0k ~E _mk ) and the bias signal Vb (V bias). Continue to refer to FIG. 4 , which is a schematic diagram of the second slew rate mapping module. In one embodiment, the second slew rate mapping module 4 includes a plurality of second switch groups 41. The second switch groups 41 respectively include a plurality of second switch units 411. The second switch units 411 respectively receive the second delay pulse signal N _signal , the second slew rate configuration signal Fn (F ₀₀ ~F _m0 , F ₀₁ ~F _m1 , F _0k ~F _mk ) and the bias signal Vb (Vbias) of the second variable delay units N. .

Please continue to refer to FIG. 5 and FIG. 6 . FIG. 5 and FIG. 6 are schematic diagrams of the transistor in FIG. 1 . In one embodiment, the first current switch 3 and the second current switch 5 respectively include a first transistor 31. A first transistor 51, a second transistor 32, a second transistor 52, a third transistor 33, a third transistor 53, a fourth transistor 34, a fourth transistor 54, a fifth transistor 35, a fifth transistor 55, a sixth transistor 36, a sixth transistor 56, a seventh transistor 37 and a seventh transistor 57, these transistors are field effect transistors. In this embodiment, the first transistor 31, the first transistor 51, the second transistor 32, the second transistor 52, the fifth transistor 35 and the fifth transistor 55 are respectively an N-type field effect transistor. In addition, the third transistor 33, the third transistor 53, the fourth transistor 34, the fourth transistor 54, the sixth transistor 36, the sixth transistor 56, the seventh transistor 37 and the seventh transistor 57 are respectively a P-type field effect transistor. These transistors also have a first terminal 311, a first terminal 511, a second terminal 312, a second terminal 512, a control terminal 310, a control terminal 510, a first terminal 321, a first terminal 521, a second terminal 322, a second terminal 522, a control terminal 320, a control terminal 520, a first terminal 331, a first terminal 531, a second terminal 332, a second terminal 532 and a control terminal. 330, a control terminal 530, a first terminal 341, a first terminal 541, a second terminal 342, a second terminal 542 and a control terminal 340, a control terminal 540, a first terminal 351, a first terminal 551, a second terminal 352, a second terminal 552 and a control terminal 350, a control terminal 550, a first terminal 361, a first terminal 561, a second terminal 362, a second terminal 562 and A control terminal 360 , a control terminal 560 , a first terminal 371 , a first terminal 571 , a second terminal 372 , a second terminal 572 , a control terminal 370 and a control terminal 570 .

In one embodiment, the first terminal 311 of the first transistor 31 is electrically connected to the high voltage terminal Vcc, the first terminal 321 of the second transistor 32 is electrically connected to the high voltage terminal Vcc and the first terminal 311 of the first transistor 31, the control terminal 320 is electrically connected to the control terminal 310 of the first transistor 31, the second terminal 322 is electrically connected to the output terminal Vout, and the control terminal 330 of the third transistor 33 is used to receive the previous output signal Sn. The end 331 is electrically connected to the second end 312 of the first transistor 31, the control end 310 and the control end 320 of the second transistor 32; the first end 341 of the fourth transistor 34 is electrically connected to the second end 322 of the second transistor 32 and the output The terminal Vout and the control terminal 340 are electrically connected to the first terminal 331 of the third transistor 33 , the second terminal 312 of the first transistor 31 , the control terminal 310 of the first transistor 31 and the control terminal 320 of the second transistor 32 , and the second terminal is electrically connected to the second terminal 332 of the third transistor 33 .

In another embodiment, the first terminal 511 of the first transistor 51 is electrically connected to the high voltage terminal Vcc, the first terminal 521 of the second transistor 52 is electrically connected to the high voltage terminal Vcc and the first terminal 511 of the first transistor 51, the control terminal 520 is electrically connected to the control terminal 510 of the first transistor 51, the second terminal 522 is electrically connected to the output terminal Vout, and the control terminal 530 of the third transistor 53 receives the output signal Sn of the previous stage. The terminal 531 is electrically connected to the second terminal 512 of the first transistor 51, the control terminal 510 and the control terminal 520 of the second transistor 52; the first terminal 541 of the fourth transistor 54 is electrically connected to the second terminal 522 of the second transistor 52 and the output terminal Vout; The control end 520 of the crystal 52 and the second end are electrically connected to the second end 532 of the third transistor 53 .

In one embodiment, the second terminal 352 of the fifth transistor 35 receives the bias signal Vb, the control terminal 360 of the sixth transistor receives the first slew rate configuration signal En and is electrically connected to the control terminal 350 of the fifth transistor 35, the first terminal 361 is electrically connected to the first terminal 351 of the fifth transistor, the second terminal 362 is electrically connected to the ground terminal Gnd, and the first terminal 371 of the seventh transistor 37 is electrically connected to the second terminal 34 of the fourth transistor 34 2 and the second terminal 332 of the third transistor 33, the control terminal 370 is electrically connected to the first terminal 351 of the fifth transistor 35 and the first terminal 361 of the sixth transistor 36, the second terminal 372 is electrically connected to the second terminal 362 of the sixth transistor 36 and the ground terminal Gnd, wherein the control terminal 350 of the fifth transistor 35 of the first current switch 3 receives the first slew rate configuration signal En, and the control terminal 550 of the fifth transistor 55 of the second current switch 5 receives the second The slew rate configuration signal Fn.

In another embodiment, the second terminal 552 of the fifth transistor 55 receives the bias signal Vb, the control terminal 560 of the sixth transistor receives the second slew rate configuration signal Fn and is electrically connected to the control terminal 550 of the fifth transistor 55. The first terminal 561 is electrically connected to the first terminal 551 of the fifth transistor, and the second terminal 562 is electrically connected to the ground terminal Gnd. The first terminal 551 of the fifth transistor 55 is connected to the first terminal 561 of the sixth transistor 56. The second terminal 572 is electrically connected to the second terminal 562 of the sixth transistor 56 and the ground terminal Gnd. The control terminal 350 of the fifth transistor 35 of the first current switch 3 receives the first slew rate configuration signal En, and the control terminal 550 of the fifth transistor 55 of the second current switch 5 receives the second slew rate configuration signal Fn.

Please continue to refer to FIG. 7 , which is a schematic circuit diagram between the first current switch 3 and the second current switch 5 shown in FIG. 1 and the transistor. In one embodiment, the modulating circuit of the power driving stage further includes an eleventh transistor 61 , an eighth transistor 68 , a ninth transistor 69 and a tenth transistor 60 , and these transistors are field effect transistors. In this embodiment, the eleventh transistor 61 and the eighth transistor 68 are respectively a P-type field effect transistor, and the ninth transistor and the tenth transistor are respectively an N-type field effect transistor, and these transistors have a first terminal 611, 681, 691, 601, a second terminal 612, 682, 692, 602 and a control terminal 610, 680, 690, 600 respectively. In this embodiment, the eleventh transistor 61 is disposed between the first current switch 3 and the electrical loop of the high voltage terminal (Vcc), and the first terminal 611 of the eleventh transistor 61 is electrically connected to the first current switch 3, the second terminal 612 of the eleventh transistor 61 is electrically connected to the high voltage terminal Vcc, and the control terminal 610 of the eleventh transistor 61 is disposed between the first current switch 3 and the electrical loop of the high voltage terminal Vcc and the output terminal Vout.

In this embodiment, the first terminal 681 of the eighth transistor 68 is electrically connected to the output terminal Vout, the second terminal 682 is electrically connected to the high voltage terminal Vcc, the control terminal 680 is electrically connected to the control terminal 610 of the eleventh transistor 61 and the first current switch 3, and the ninth transistor 69 is arranged between the second current switch 5 and the ground. Between the electrical circuit of the terminal Gnd, the first terminal 691 of the ninth transistor 69 is electrically connected to the second current switch 5, the second terminal 692 is electrically connected to the ground terminal Gnd, the control terminal 690 is electrically connected to the first terminal 691 and the second current switch 5, the tenth transistor 60 is arranged between the second current switch 5 and the electrical circuit between the ground terminal Gnd and the output terminal Vout, and the first terminal 601 of the tenth transistor 60 is electrically connected to the output terminal Vout and the first terminal of the eighth transistor 68 681 , the second terminal 602 is electrically connected to the ground terminal Gnd, and the control terminal 600 is electrically connected to the control terminal 690 of the ninth transistor 69 and the second current switch 5 .

Through the various modules, switches and transistors of the modulation circuit of the power drive stage described in the above embodiments, the weight adjustment between signals and the speed of delay time can be quickly converted and output high-frequency noise can be reduced. Through the modulation circuit of the power driving stage of the present invention, a more efficient and more subdivided power driving adjustment circuit can be realized, and the quality and efficacy can be improved.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as defined by the scope of the appended patent application.

A: Pulse conversion control unit group

B: Drive level control unit group

1: Edge pulse conversion module

2: The first slew rate mapping module

3: The first current switch

4: The second slew rate mapping module

5: Second current switch

7: Delay module

P: the first variable delay unit

N: second variable delay unit

11: and gate

12: Reverse and gate

Data: data signal

OE: output enable signal

Vout: output terminal

Claims (7)

A modulation circuit of a power drive stage is used for modulating output power, comprising: a pulse conversion control unit group, which provides a delayed pulse signal, and the delayed pulse signal has a first delayed pulse signal and a second delayed pulse signal, wherein the pulse conversion control unit group includes an edge pulse conversion module, and the edge pulse conversion module receives a data signal and an output enable signal, and generates the first delayed pulse signal and the second delayed pulse signal; converting the control unit group, and performing weight control according to the delayed pulse signal to generate a weight-adjusted slew rate configuration signal, wherein the slew rate configuration signal has a first slew rate configuration signal and a second slew rate configuration signal; The mapping module includes a plurality of first switch groups, each of which includes a plurality of first switch units, each of the first switch units of the first switch groups respectively receives the first delayed pulse signals of the first variable delay units, the first slew rate configuration signal before weight adjustment and the bias signal; a second slew rate mapping module is electrically connected to the edge pulse conversion module and the second current switch, and receives the second delayed pulse signal for generating the second slew rate configuration signal after weight adjustment number, wherein the second slew rate mapping module includes multiple sets of second switch groups, and these multiple sets of second switch groups respectively include multiple second switch units, and the second switch groups of these second switch groups Each of the second switch units is to receive each of the second delay pulse signals of the second variable delay units, the second slew rate configuration signal before the weight adjustment and the bias signal; a first current switch is electrically connected to an output terminal, a high voltage terminal and a ground terminal, and is used to receive a previous output signal, the weight adjusted The first slew rate configuration signal and a bias signal; and a second current switch is electrically connected to the output terminal, the high voltage terminal and the ground terminal, and is used to receive a The pre-stage output signal, the weight-adjusted second slew rate configuration signal and the bias signal. The modulation circuit of the power drive stage as described in claim 1, wherein the edge pulse conversion module includes: an AND gate, which receives the data signal and the output enable signal; an inverse AND gate, which receives the data signal and the output enable signal; a plurality of first variable delay units are connected in series and electrically connected to the AND gate, and receive the logic signal output by the AND gate to output the first delayed pulse signal; and a plurality of second variable delay units are connected in series and electrically connected to the invert gate, and Receive the logic signal output by the NAND gate to output the second delayed pulse signal. The modulation circuit of the power drive stage as described in claim 1, wherein the first current switch and the second current switch respectively include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor, and have a first terminal, a second terminal and a control terminal respectively; wherein the first terminal of the first transistor The first end of the second transistor is electrically connected to the high voltage end and the first end of the first transistor; the control end is electrically connected to the control end of the first transistor; The end is electrically connected to the second end of the second transistor and the output end, the control end is electrically connected to the first end of the third transistor, the second end of the first transistor, the control end of the first transistor, and the control end of the second transistor, the second end is electrically connected to the second end of the third transistor; the second end of the fifth transistor receives the bias signal; the control end of the sixth transistor receives the first slew rate configuration signal and is electrically connected to the fifth transistor. The control end, the first end is electrically connected to the first end of the fifth transistor, the second end is electrically connected to the ground end; the first end of the seventh transistor is electrically connected to the second end of the fourth transistor and the second end of the third transistor, the control end is electrically connected to the first end of the fifth transistor and the first end of the sixth transistor, and the second end is electrically connected to the second end of the sixth transistor and the ground end; wherein the control of the fifth transistor of the first current switch The terminal receives the first slew rate configuration signal; wherein the control terminal of the fifth transistor of the second current switch receives the second slew rate configuration signal. The modulation circuit of the power drive stage as described in claim 3, wherein the first transistor, the second transistor, and the fifth transistor are each an N-type field effect transistor, and wherein the third transistor, the fourth transistor, the sixth transistor, and the seventh transistor are each a P-type field effect transistor. The modulation circuit of the power drive stage as described in claim item 1 further includes an eleventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor, each having a first terminal, a second terminal, and a control terminal; wherein the eleventh transistor system is arranged between the first current switch and the electrical circuit of the high voltage terminal, the first terminal of the eleventh transistor is electrically connected to the first current switch, the second terminal is electrically connected to the high voltage terminal, and the control terminal is electrically connected to the first terminal and the first current switch; The transistor system is arranged between the first current switch, the high voltage end and the electrical loop of the output end, the first end of the eighth transistor is electrically connected to the output end, the second end is electrically connected to the high voltage end, the control end is electrically connected to the control end of the eleventh transistor and the first current switch; the ninth transistor system is arranged between the second current switch and the electrical loop of the ground end, the first end of the ninth transistor is electrically connected to the second current switch, and the second end is electrically connected to the ground end. The control terminal is electrically connected to the first terminal and the second current switch; the tenth transistor system is arranged between the second current switch, the ground terminal and the electrical loop of the output terminal, the first terminal of the tenth transistor is electrically connected to the output terminal and the first terminal of the eighth transistor, the second terminal is electrically connected to the ground terminal, and the control terminal is electrically connected to the control terminal of the ninth transistor and the second current switch. The modulation circuit of the power drive stage as described in Claim 5, wherein the eleventh transistor and the eighth transistor are respectively a P-type field effect transistor, and the ninth transistor and the tenth transistor are respectively an N-type field effect transistor. The modulation circuit of the power drive stage as described in Claim 1 further includes a delay module for providing a delay signal to the edge pulse conversion module.

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