TWI806542B - Apparatus for noise reduction in audio signal processing - Google Patents

Abstract

An apparatus for noise reduction in audio signal processing includes a power amplifier, a zero-crossing detector, and a threshold detector. The power amplifier has an input signal terminal for receiving an audio input signal and an output signal terminal. The audio input signal is a digital-to-analog converted version according to a version of a digital audio signal. The power amplifier has an analog gain which is controllable in response to an analog gain control signal. The zero-crossing detector determines a zero-crossing detection signal according to an internal signal provided between the input signal terminal and the output signal terminal. The threshold detector determines a gain setting according to the digital audio signal and the zero-crossing detection signal to generate the analog gain control signal indicating the gain setting, wherein the threshold detector controls the analog gain of the power amplifier according to the analog gain control signal.

Description

Equipment for noise suppression in audio signal processing

This application relates to an integrated circuit, especially a noise suppression device for audio signal processing.

Current electronic systems usually include digital processing modules, data converters and analog processing modules. In sound signal processing systems, such as audio reproduction devices, the sound signal is digitally processed before being converted to an analog signal. The digital processing module may include a digital signal processor for receiving digital audio signals and providing various digital processing, such as filtering, frequency up-sampling, and/or other digital signal processing. The output of the digital processing module can be coupled to a digital-to-analog converter to convert the processed digital signal into an analog signal. An analog processing module may include processing circuitry such as a power amplifier to drive subsequent stages.

In the signal path, the power amplifier can be a variable gain amplifier to provide a signal with sufficient gain to subsequent stages to achieve a wider dynamic range. However, noise can still be introduced into the signal path and unnecessarily amplified by the power amplifier.

An object of the embodiments of the present application is to provide a device for noise suppression in audio signal processing with analog gain control.

In order to achieve the above purpose, the embodiment of the present application provides a noise suppression device for audio signal processing. The device includes a power amplifier, a zero crossing detector and a threshold detector. The power amplifier has an input signal end and an output signal end, wherein the input signal end is used to receive an audio input signal, and the audio input signal is converted from a digital to analog version according to a digital audio signal, and the power amplifier has a response to The analog gain control signal is a controllable analog gain. The zero-crossing detector is used for determining a zero-crossing detection signal according to an internal signal provided between the input signal terminal and the output signal terminal. The threshold detector is used to determine a gain setting according to the digital audio signal and the zero-crossing detection signal to generate the analog gain control signal to represent the gain setting, wherein the threshold detector is controlled according to the analog gain control signal The analog gain of the power amplifier.

In some embodiments, when the threshold detector detects that the digital audio signal changes within a first reference range and the zero-crossing detection signal indicates a zero-crossing state, the threshold detector sets the gain The setting is determined as a first gain parameter; otherwise, the threshold detector determines the gain setting as a second gain parameter.

In some embodiments, the power amplifier has multiple gain setting states, and the power amplifier is set to one of the multiple gain setting states according to the gain setting indicated in the analog gain control signal, wherein the first A gain parameter indicates one of the plurality of gain setting states such that the power amplifier has a lower gain.

In some embodiments, the internal signal includes an analog signal that varies according to the signal at the input signal terminal and the signal at the output signal terminal.

In some embodiments, the zero-crossing detector includes a comparator circuit for generating the zero-crossing detection signal according to a comparison between the analog signal and a reference signal.

In some embodiments, the internal signal includes a first signal and a second signal, the first signal and the second signal vary according to the signal at the input signal terminal and the signal at the output signal terminal, and the first signal and the The second signal is an analog differential signal.

In some embodiments, the zero crossing detector includes a first comparator circuit and a second comparator circuit. The first comparator circuit generates a first comparison result signal according to the comparison between the first signal and a reference signal. The second comparator circuit generates a second comparison result signal according to the comparison between the second signal and the reference signal. The zero-crossing detector generates the zero-crossing detection signal according to the first comparison result signal and the second comparison result signal.

In some embodiments, the internal signal includes a first signal and a second signal, the first signal and the second signal vary according to the signal at the input signal terminal and the signal at the output signal terminal, and the first signal and the The second signal is a pulse width modulation signal.

In some embodiments, the zero-crossing detector includes: a first comparator circuit, a second comparator circuit, and a zero-crossing determining circuit. The first comparator circuit generates a first comparison result signal according to the comparison between the first signal and a reference signal. The second comparator circuit generates a second comparison result signal according to the comparison between the second signal and the reference signal. The zero-crossing determination circuit generates the zero-crossing detection signal according to the comparison between the first comparison result signal and the second result comparison signal. When one of the first signal and the second signal indicates a high state, the zero-crossing determining circuit starts to compare whether the first signal and the second signal are equal. When the first signal and the second signal are equal, and after the first signal and the second signal transition to a low state, there is a signal indicating the high state state, the zero-crossing determination circuit generates the zero-crossing detection signal to represent a zero-crossing state; otherwise, the zero-crossing determination circuit generates the zero-crossing detection signal to represent a non-zero crossing state.

In some embodiments, the power amplifier is based on a class D amplifier.

In some embodiments, the device further includes a digital-to-analog converter that generates the audio input signal based on a version of the digital audio signal to perform digital-to-analog conversion.

As above, the present application provides various embodiments of an apparatus for noise suppression for audio signal processing. The device can be used to control the analog gain, so that when conditions such as low signal output (eg: near zero output or small signal output) occur, the noise level can be reduced. Because the device controls the power amplifier when at least two conditions including a zero crossing condition and a small signal condition are detected, analog gain control can be performed more accurately and in a timely manner. Therefore, the average noise level of the output of the power amplifier can be reduced.

5: Digital circuit

9: Digital to analog converter

10, 10A: power amplifier

20, 20A: Zero-crossing detector

21: Comparator circuit

21A: the first comparator circuit

22A: Second comparator circuit

23: Logic device

30:Threshold detector

110: Error amplifier stage

120: Comparator stage

130: output stage

210: the first comparator circuit

220: the second comparator circuit

230: Zero crossing determination circuit

310: Logic Circuits

320: control circuit

C ₁ , C ₂ : capacitance

G _PWM : Gain

PWM_P, PWM_N: pulse width modulation signal

R _i , R _f , R _z : resistance

Sda: digital audio signal

Sgc: Analog gain control signal

V _op , V _op1 , V _on , V _on1 : output signal

FIG. 1 is a schematic diagram showing an exemplary architecture of an apparatus for noise suppression for audio signal processing, which represents various embodiments of the present application.

FIG. 2 is a block diagram showing an embodiment of an apparatus for noise suppression in audio signal processing for use in the exemplary architecture of FIG. 1 .

Figure 3A is a block diagram showing one embodiment of a zero-crossing detector.

Figure 3B is a block diagram showing one embodiment of a zero-crossing detector.

FIG. 4 is a block diagram showing another embodiment of an apparatus for noise suppression for audio signal processing in the exemplary architecture of FIG. 1 .

Figure 5A is a block diagram showing one embodiment of a zero-crossing detector.

FIG. 5B is a schematic diagram showing an embodiment of zero-crossing detection.

FIG. 6 is a schematic diagram showing an embodiment of threshold detection.

Figure 7 is a block diagram showing an embodiment of a threshold detector.

In order to facilitate the understanding of the purpose, features, and effects of the present application, the present application provides multiple embodiments and drawings to describe the disclosed content of the present application in detail.

Please refer to FIG. 1 , which shows a schematic diagram of an exemplary architecture of an apparatus for noise suppression for audio signal processing, which represents various embodiments of the present application. As shown in FIG. 1 , a noise suppression device for audio signal processing includes a power amplifier 10 , a zero-crossing detector 20 and a threshold detector 30 . The device can be applied to a sound signal processing path, such as a path including a digital circuit 5, a digital-to-analog converter (digital-to-analog convcrtcr, DAC) 9 and the power amplifier 10, wherein a digital sound signal (Sda ) is applied to the sound signal processing path, and the output of the power amplifier 10 can then be applied for reproduction, for example by loudspeakers, headphones, earphones, etc. In addition, the digital circuit 5 is optional, and it is used to perform digital signal processing, such as filtering, frequency up-sampling, equalization, sound effects or other suitable sound processing. In some embodiments, the device can be further implemented as a digital input audio amplifier or audio reproduction device.

The power amplifier 10 has at least one input signal terminal and at least one output signal terminal. An audio input signal is applied to the input signal terminal. As shown in Figure 1, the sound input signal is, for example, a A digital-to-analog converted version is obtained from a version of the digital audio signal (Sda) by the digital-to-analog converter 9 . The power amplifier 10 has an analog gain controllable in response to an analog gain control signal (Sgc).

The zero-crossing detector 20 determines a zero-crossing detection signal according to an internal signal provided between the input signal terminal and the output signal terminal.

The threshold detector 30 is used to determine a gain setting according to the digital audio signal and the zero-crossing detection signal to generate the analog gain control signal to represent the gain setting, wherein the threshold detector 30 is based on the analog gain control The signal controls the analog gain of the power amplifier 10 .

In some embodiments, when the threshold detector 30 detects that the digital audio signal is within a first reference range (such as 0.01%, 0.1%, 1%, 2% of the maximum allowable signal amplitude (or digitized value) range) and the zero-crossing detection signal indicates a zero-crossing state, the threshold detector 30 determines the gain setting as a first gain parameter; otherwise, the threshold detector 30 sets the gain The setting is determined as a second gain parameter.

In some embodiments, the power amplifier 10 has multiple gain setting states (for example: 3.52dB (1.5 times), 6dB (2 times), 8dB (2.5 times), 9.5dB (3 times), 11.5dB (3.75 times) ), 13dB (4.5 times), 14dB (5 times), 15.5dB (6 times) gain), and the power amplifier 10 is set to the gain setting state according to the gain setting indicated in the analog gain control signal One of them, wherein the first gain parameter represents one of the plurality of gain setting states so that the power amplifier 10 has a lower gain (for example: 3.52dB (1.5 times)).

In one example, when set to the lowest gain setting (for example: 3.52dB (1.5 times)), the power amplifier 10 has the characteristics of the lowest noise level, when the signal output of the power amplifier 10 is almost equal to zero or close to zero , the user of the power amplifier 10 will be very sensitive to any noise. In this kind of In some cases, when the signal output of the power amplifier 10 is almost zero or close to zero, the device of this embodiment can control the power amplifier 10 to be set to the lowest gain setting state to reduce noise. Thereby, the average noise level can be reduced by the above method.

In some embodiments, the device may further include the digital-to-analog converter 9 for performing digital-to-analog conversion according to a version of the digital sound signal to generate the sound input signal.

Please refer to FIG. 2 . FIG. 2 shows an embodiment of an apparatus for noise suppression used in audio signal processing in the exemplary architecture of FIG. 1 . As shown in FIG. 2 , a noise suppression device for audio signal processing includes a power amplifier 10A, a zero-crossing detector 20A and a threshold detector 30 . In FIG. 2 , the power amplifier 10A is based on a class D amplifier and includes an error amplifier stage 110 , a comparator stage 120 and an output stage 130 .

For example, the error amplifier stage 110 receives the audio input signal from the DAC 9 and outputs signals V _op1 and V _on1 to the comparator stage 120 . The error amplifier stage 110 includes an amplifier, resistors R _i , R _z and capacitors C ₁ , C ₂ . The comparator stage 120 includes a plurality of comparators to compare the signals V _op1 and V _on1 with a triangle wave and output signals (such as pulse width modulation signals) to the output stage 130 . The output stage 130 is an output stage circuit with a gain denoted as G _PWM , which generates output signals V _op and V _on that can be reproduced (eg, reproduced by speakers or headphones). In addition, the output signals V _op and V _on are fed back to the error amplifier stage 110 through the resistor R _f . In some embodiments, the power amplifier 10A may be implemented as a digitally controlled variable gain amplifier, and one or more components (eg, R _i , R _f , or other components) may be implemented as digitally controlled variable components to control the gain . Of course, implementation of the present application is not limited to this example of the power amplifier 10A. In some embodiments, any power amplifier based on a Class D amplifier and/or a power amplifier that can provide a signal between the input signal terminal and the output signal terminal of the power amplifier for zero-crossing detection can be used to implement the described method. Noise suppression equipment for audio signal processing.

In some embodiments, the internal signal includes an analog signal that varies according to the signal at the input signal terminal and the signal at the output signal terminal. For example, signals from the error amplifier stage 110 , such as V _op1 and V _on1 shown in FIG. 2 , can be used as the analog signals. In some embodiments, as shown in FIG. 3A , the zero-crossing detector 20A may include a comparator circuit 21 to detect a signal based on the analog signal and a reference signal (such as 0.01 of the maximum allowable signal amplitude (or digitized value) %, 0.1%, 1%, 2% range) to generate the zero-crossing detection signal.

In some embodiments, the internal signal includes a first signal and a second signal (such as V _op1 or V _on1 shown in FIG. 2 ), the first signal and the second signal are based on the signal at the input signal terminal and the output The signal at the signal terminal changes, and the first signal and the second signal are analog differential signals. In some embodiments, as shown in FIG. 3B , the zero-crossing detector 20A includes a first comparator circuit 21A and a second comparator circuit 22A. The first comparator circuit 21A generates a first comparison result signal according to the comparison between the first signal and a reference signal. The second comparator circuit 22A generates a second comparison result signal according to the comparison between the second signal and the reference signal. The zero-crossing detector 20 generates the zero-crossing detection signal according to the first comparison result signal and the second comparison result signal, for example, in the form of a logic device 23 .

Please refer to FIG. 4 . FIG. 4 is another embodiment of the noise suppression device used in the audio signal processing of the exemplary architecture shown in FIG. 1 . As shown in FIG. 4 , a noise suppression device for audio signal processing includes a power amplifier 10A, a zero-crossing detector 20B and a threshold detector 30 .

In some embodiments, the internal signal includes a first signal and a second signal, the first signal and the second signal vary according to the signal at the input signal terminal and the signal at the output signal terminal, and the first signal and the The second signal is a pulse width modulation signal. For example, from the The signals of the comparator stage 120 , such as the pulse width modulation signals PWM_P and PWM_N shown in FIG. 4 , can be used as the first signal and the second signal.

In some embodiments, as shown in FIG. 5A , the zero-crossing detector 20B includes a first comparator circuit 210 , a second comparator circuit 220 and a zero-crossing determining circuit 230 .

The first comparator circuit 210 generates a first comparison result signal according to the comparison between the first signal and a reference signal. The second comparator circuit 220 generates a second comparison result signal according to the comparison between the second signal and the reference signal. The zero-crossing determination circuit 230 generates the zero-crossing detection signal according to the comparison between the first comparison result signal and the second comparison result signal.

Please refer to FIG. 5A and FIG. 5B, when one of the first signal and the second signal (eg, pulse width modulation signal PWM_P, PWM_N) indicates a high state, the zero-crossing determination circuit 230 starts to compare the Whether the first signal and the second signal are equal. For example, a sampling clock signal can be used to sample or count the pulse width modulation signals PWM_P, PWM_N for comparison or detection, wherein the sampling clock signal has a sampling frequency (for example, 25MHz), and the sampling The frequency is higher than the operating frequency (for example, 384kHz) of the pulse width modulation signals PWM_P, PWM_N.

Please refer to FIG. 5A and FIG. 5B, when the first signal and the second signal are equal, and the first signal and the second signal turn to a low state (for example, two or more clock cycle), there is the same interval (for example, PWM interval) used to represent the high state, the zero crossing determination circuit 230 generates the zero crossing detection signal to represent a zero crossing state; otherwise, the zero crossing The more certain circuit 230 generates the zero-crossing detection signal to indicate a non-zero-crossing state.

Please refer to FIG. 6 , which is a schematic diagram showing an embodiment of threshold detection. The threshold detector 30 can be configured such that when the threshold detector 30 detects that the digital sound signal is within a first reference range (for example, 0.01%, 0.1%, 0.1% of the maximum allowable signal amplitude (or digitized value), 1%, 2% range)) and vary, As shown in FIG. 6, when the attack threshold (attack threshold) is shown, and the zero-crossing detection signal indicates a zero-crossing state, the threshold detector 30 determines the gain setting as a first gain parameter, as mentioned above. As described in the embodiment of FIG. 1; otherwise, the threshold detector 30 determines the gain setting as a second gain parameter.

For example, please refer to FIG. 6, the threshold detector 30 can be configured to include a logic circuit (such as 310 shown in FIG. 7), to determine whether the digital audio signal (Sda) is within Within the first reference range (eg trigger threshold). If the digital audio signal (Sda) is within the first reference range (for example, the signal amplitude (or absolute value) of the digital audio signal (Sda) is equal to or greater than a trigger threshold), a trigger count starts counting from zero until reaching a Count threshold (e.g. 2047 or other suitable value). If the counting threshold is reached, a trigger signal can be generated, as shown in FIG. 6 , the trigger signal is asserted by a pulse. In addition, if the digital audio signal (Sda) is outside the first reference range and falls within the second reference range (for example, the signal amplitude (or absolute value) of the digital audio signal (Sda) is equal to or greater than a release threshold ( release threshold)), the trigger count is reset to zero. Otherwise, if the digital sound signal (Sda) between the first reference range and the second reference range (for example, the signal amplitude (or absolute value) of the digital sound signal (Sda) is greater than the trigger threshold or less than the release threshold) , the trigger count remains constant.

In one embodiment, the threshold detector 30 may be configured to include a control circuit (for example, 320 in FIG. 7 ) to determine the analog gain control according to the trigger signal and the zero-crossing detection signal for example above. Signal (Sgc). For example, the analog gain control signal (Sgc) can represent the value B[2:0] as shown in Table 1, so as to control the power amplifier 10A to operate in a gain setting state.

Table 1 illustrates embodiments of some gain setting state values supported by the power amplifier 10A, wherein the analog gain of the power amplifier 10A is determined according to resistors R _f and R _i . In some embodiments, the power amplifier 10A can be realized by a digitally controlled variable gain amplifier, wherein the analog gain control signal (Sgc) represents the value B[2:0]. In other embodiments, the power amplifier 10A can be realized by an analog (for example, voltage) controlled variable gain amplifier, wherein the analog gain control signal represents a voltage signal corresponding to a gain setting.

For example, in order to minimize the noise level, when the threshold detector 30 detects that the digital audio signal is within a first reference range (such as 0.01%, 0.1%, 0.1% of the maximum allowable signal amplitude (or digitized value), 1%, 2% range) (such as a small signal state), and when the zero-crossing detection signal indicates a zero-crossing state, the threshold detector 30 determines the gain setting as a first gain parameter (eg, B[2:0]=111).

In some embodiments, the threshold detector 30 may be configured to optionally determine the gain setting as other gain parameters (e.g., back to previous or another gain parameter other than the first gain parameter).

As above, the present application provides various embodiments of an apparatus for noise suppression for audio signal processing. The device can be used to control the analog gain, so that when conditions such as low signal output (eg: near zero output or small signal output) occur, the noise level can be reduced. Because the device controls the power amplifier when at least two conditions including a zero crossing condition and a small signal condition are detected, analog gain control can be performed more accurately and in a timely manner. Therefore, the average noise level of the output of the power amplifier can be reduced.

Although the content disclosed in this application has been described with the help of specific embodiments, those skilled in the art may make many modifications and changes to it without departing from the content disclosed in this application described in the patent scope of the application. category and spirit.

5: Digital circuit

9: Digital to analog converter

10: Power amplifier

20: Zero crossing detector

30:Threshold detector

Sda: digital audio signal

Sgc: Analog gain control signal

Claims (8)

A noise suppression device for audio signal processing, which includes: a power amplifier with an input signal end and an output signal end, wherein the input signal end is used to receive an audio input signal, and the audio input signal is According to a digital-to-analog converted version of a digital audio signal version, the power amplifier has an analog gain controllable in response to an analog gain control signal; The internal signal provided between the output signal terminals determines a zero-crossing detection signal, the internal signal includes a first signal and a second signal, the first signal and the second signal are based on the signal at the input signal terminal and the The signal at the output signal terminal changes, and the first signal and the second signal are pulse width modulated signals, and the zero-crossing detector includes: a first comparator circuit, according to the relationship between the first signal and a reference signal a comparison between the two to generate a first comparison result signal; a second comparator circuit to generate a second comparison result signal according to the comparison between the second signal and the reference signal; and a zero-crossing determination circuit to generate a second comparison result signal according to The comparison between the first comparison result signal and the second comparison result signal generates the zero crossing detection signal, wherein when one of the first signal and the second signal indicates a high state, the zero crossing The more certain the circuit starts to compare whether the first signal and the second signal are equal; wherein, when the first signal and the second signal are equal and after the first signal and the second signal turn to a low state, there is a represent the same interval of the high state that the zero crossing determines the power The circuit generates the zero-crossing detection signal to indicate a zero-crossing state; otherwise, the zero-crossing determination circuit generates the zero-crossing detection signal to indicate a non-zero-crossing state; and a threshold detector, used The gain setting is represented by determining a gain setting according to the digital audio signal and the zero-crossing detection signal to generate the analog gain control signal, wherein the threshold detector controls the analog of the power amplifier according to the analog gain control signal gain. The device as claimed in claim 1, wherein when the threshold detector detects that the digital audio signal changes within a first reference range and the zero-crossing detection signal indicates a zero-crossing state, the threshold detector The detector determines the gain setting as a first gain parameter; otherwise, the threshold detector determines the gain setting as a second gain parameter. The apparatus of claim 2, wherein the power amplifier has a plurality of gain setting states, and the power amplifier is set to one of the plurality of gain setting states according to the gain setting indicated in the analog gain control signal , wherein the first gain parameter represents one of the plurality of gain setting states such that the power amplifier has a lower gain. The device as described in claim 1, wherein the internal signal includes an analog signal, and the analog signal changes according to the signal at the input signal terminal and the signal at the output signal terminal. The apparatus as claimed in claim 4, wherein the zero-crossing detector includes a comparator circuit, and the comparator circuit generates the zero-crossing detection signal according to a comparison between the analog signal and a reference signal. The apparatus as claimed in claim 1, wherein the power amplifier is a class D amplifier. The device as claimed in claim 1, wherein the device further comprises a digital-to-analog converter for performing digital-to-analog conversion according to a version of the digital sound signal to generate the sound input signal. The device as described in Claim 1, wherein the device is a digital input audio amplifier or an audio reproduction device.

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