TW202341651A - Apparatus for noise reduction in audio signal processing - Google Patents

Abstract

An apparatus for noise reduction in audio signal processing includes a power amplifier, a zero-crossing detector, and a threshold detector. The power amplifier has an input signal terminal for receiving an audio input signal and an output signal terminal. The audio input signal is a digital-to-analog converted version according to a version of a digital audio signal. The power amplifier has an analog gain which is controllable in response to an analog gain control signal. The zero-crossing detector determines a zero-crossing detection signal according to an internal signal provided between the input signal terminal and the output signal terminal. The threshold detector determines a gain setting according to the digital audio signal and the zero-crossing detection signal to generate the analog gain control signal indicating the gain setting, wherein the threshold detector controls the analog gain of the power amplifier according to the analog gain control signal.

Description

Noise suppression equipment for sound signal processing

The present application relates to an integrated circuit, and in particular to a noise suppression device for sound signal processing.

Current electronic systems usually include digital processing modules, data converters and analog processing modules. In sound signal processing systems, such as audio reproduction devices, sound signals are digitally processed before being converted into analog signals. The digital processing module may include a digital signal processor for receiving digital sound signals and providing various digital processing, such as filtering, frequency upsampling, and/or other digital signal processing. The output of the digital processing module can be coupled to a digital-to-analog converter to convert the processed digital signal into an analog signal. Analog processing modules may include processing circuitry (eg, power amplifiers) to drive subsequent stages.

In the signal path, the power amplifier can be a variable gain amplifier to provide signals with sufficient gain to subsequent stages to achieve a wider dynamic range. However, it is still possible for noise to be introduced into the signal path and unnecessarily amplified by the power amplifier.

An object of embodiments of the present application is to provide a device for noise suppression and analog gain control for sound signal processing.

In order to achieve the above object, embodiments of the present application provide a device for noise suppression in voice signal processing. The device includes a power amplifier, a zero-crossing detector and a threshold detector. The power amplifier has an input signal terminal and an output signal terminal, wherein the input signal terminal is used to receive a sound input signal, and the sound input signal is based on a digital-to-analog conversion version of a digital sound signal, and the power amplifier has a response to An analog gain controls the signal and is a controllable analog gain. The zero-crossing detector is used to determine a zero-crossing detection signal based on an internal signal provided between the input signal terminal and the output signal terminal. The threshold detector is used to determine a gain setting according to the digital sound signal and the zero-crossing detection signal to generate the analog gain control signal to represent the gain setting, wherein the threshold detector is controlled according to the analog gain control signal The analog gain of the power amplifier.

In some embodiments, when the threshold detector detects that the digital sound signal changes within a first reference range and the zero-crossing detection signal indicates a zero-crossing state, the threshold detector changes the gain The setting is determined as a first gain parameter; otherwise, the threshold detector determines the gain setting as a second gain parameter.

In some embodiments, the power amplifier has a plurality of gain setting states, and the power amplifier is set to one of the plurality of gain setting states according to the gain setting represented in the analog gain control signal, wherein the first A gain parameter represents one of the plurality of gain setting states such that the power amplifier has a lower gain.

In some embodiments, the internal signal includes an analog signal that changes according to the signal at the input signal terminal and the signal at the output signal terminal.

In some embodiments, the zero-crossing detector includes a comparator circuit that generates the zero-crossing detection signal based on a comparison between the analog signal and a reference signal.

In some embodiments, the internal signal includes a first signal and a second signal, the first signal and the second signal change according to the signal of the input signal terminal and the signal of the output signal terminal, and the first signal and The second signal is an analog differential signal.

In some embodiments, the zero-crossing detector includes a first comparator circuit and a second comparator circuit. The first comparator circuit generates a first comparison result signal based on comparison of the first signal and a reference signal. The second comparator circuit generates a second comparison result signal based on comparison of the second signal and the reference signal. The zero-crossing detector generates the zero-crossing detection signal according to the first comparison result signal and the second comparison result signal.

In some embodiments, the internal signal includes a first signal and a second signal, the first signal and the second signal change according to the signal of the input signal terminal and the signal of the output signal terminal, and the first signal and The second signal is a pulse width modulation signal.

In some embodiments, the zero-crossing detector includes: a first comparator circuit, a second comparator circuit, and a zero-crossing determination circuit. The first comparator circuit generates a first comparison result signal based on comparison of the first signal and a reference signal. The second comparator circuit generates a second comparison result signal based on comparison of the second signal and the reference signal. The zero-crossing determination circuit generates the zero-crossing detection signal based on the comparison between the first comparison result signal and the second result comparison signal. When one of the first signal and the second signal indicates a high state, the zero-crossing determination circuit begins to compare whether the first signal and the second signal are equal. When the first signal and the second signal are equal and have the same interval representing the high state after the first signal and the second signal transition to the low state, the zero-crossing determination circuit generates the zero-crossing detection The zero-crossing detection signal is generated to indicate a zero-crossing state; otherwise, the zero-crossing determination circuit generates the zero-crossing detection signal to indicate a non-zero-crossing state.

In some embodiments, the power amplifier is based on a class D amplifier.

In some embodiments, the device further includes a digital-to-analog converter that generates the sound input signal based on a version of the digital sound signal to perform digital-to-analog conversion.

As mentioned above, the present application provides various embodiments of a noise suppression device for sound signal processing. This device can be used to control analog gain so that when conditions such as lower signal output (eg near zero output or small signal output) occur, the noise level can be reduced. Because the device controls the power amplifier when at least two conditions including a zero-crossing state and a small-signal state are detected, analog gain control can be performed more accurately and in a timely manner. Therefore, the average noise level of the output of the power amplifier can be reduced.

In order to facilitate understanding of the purpose, features, and effects of the present application, the present application provides multiple embodiments and drawings to explain the disclosure content of the present application in detail.

Please refer to FIG. 1 , which shows a schematic diagram of an exemplary architecture of a noise suppression device for sound signal processing, which represents multiple embodiments of the present application. As shown in FIG. 1 , a sound signal processing and noise suppression device includes a power amplifier 10 , a zero-crossing detector 20 and a threshold detector 30 . The device can be applied to a sound signal processing path, for example a path including a digital circuit 5, a digital-to-analog converter (DAC) 9 and the power amplifier 10, in which a digital sound signal (Sda ) is applied to the sound signal processing path, and the output of the power amplifier 10 can then be used for reproduction, for example by speakers, headphones, headphones, etc. In addition, the digital circuit 5 is optional and is used to perform digital signal processing, such as filtering, frequency upsampling, equalization, sound effects or other suitable sound processing. In some embodiments, the device may be further implemented as a digital input audio amplifier or audio reproduction device.

The power amplifier 10 has at least one input signal terminal and at least one output signal terminal. A sound input signal is applied to the input signal terminal. As shown in FIG. 1 , the sound input signal is, for example, a digital-to-analog conversion version, which is obtained by the digital-to-analog converter 9 according to a version of the digital sound signal (Sda). The power amplifier 10 has an analog gain controllable in response to an analog gain control signal (Sgc).

The zero-crossing detector 20 determines a zero-crossing detection signal based on an internal signal provided between the input signal terminal and the output signal terminal.

The threshold detector 30 is used to determine a gain setting according to the digital sound signal and the zero-crossing detection signal to generate the analog gain control signal to represent the gain setting, wherein the threshold detector 30 is based on the analog gain control signal. The signal controls the analog gain of the power amplifier 10 .

In some embodiments, when the threshold detector 30 detects the digital sound signal in a first reference range (such as 0.01%, 0.1%, 1%, 2% of the maximum allowable signal amplitude (or digitized value) changes within the range) and the zero-crossing detection signal indicates a zero-crossing state, the threshold detector 30 determines the gain setting as a first gain parameter; otherwise, the threshold detector 30 determines the gain setting The setting is determined as a second gain parameter.

In some embodiments, the power amplifier 10 has multiple gain setting states (for example: 3.52dB (1.5 times), 6 dB (2 times), 8 dB (2.5 times), 9.5 dB (3 times), 11.5 dB ( 3.75 times), 13 dB (4.5 times), 14 dB (5 times), 15.5 dB (6 times) gain), and the power amplifier 10 is set to the gain setting represented in the analog gain control signal. One of the gain setting states, wherein the first gain parameter represents one of the plurality of gain setting states so that the power amplifier 10 has a lower gain (for example: 3.52 dB (1.5 times)).

In one example, when set to the lowest gain setting (for example: 3.52 dB (1.5 times)), the power amplifier 10 has the characteristics of the lowest noise level, and when the signal output of the power amplifier 10 is almost zero or close to zero At this time, the user of the power amplifier 10 will be very sensitive to any noise. In this case, when the signal output of the power amplifier 10 is almost equal to zero or close to zero, the device of this embodiment can control the power amplifier 10 to be set to the lowest gain setting state to reduce noise. Thereby, the average noise level can be reduced using the above method.

In some embodiments, the device may further include the digital-to-analog converter 9 for performing digital-to-analog conversion according to a version of the digital sound signal to generate the sound input signal.

Please refer to FIG. 2 , which illustrates an embodiment of an apparatus for noise suppression in sound signal processing used in the exemplary architecture of FIG. 1 . As shown in FIG. 2 , a noise suppression device for sound signal processing includes a power amplifier 10A, a zero-crossing detector 20A and a threshold detector 30 . In FIG. 2 , the power amplifier 10A is based on a class D amplifier and includes an error amplifier stage 110 , a comparator stage 120 and an output stage 130 .

For example, the error amplifier stage 110 receives the sound input signal from the digital-to-analog converter 9 and outputs the signals V _op1 and V _on1 to the comparator stage 120 . The error amplifier stage 110 includes an amplifier, resistors _Ri , _Rz , and capacitors _C1 , _C2 . The comparator stage 120 includes a plurality of comparators to compare the signals V _op1 and V _on1 with a triangular wave and output signals (eg, pulse width modulation signals) to the output stage 130 . The output stage 130 is an output stage circuit with a gain expressed as G _PWM , which generates output signals V _op and V _on that can be reproduced (for example, by speakers or headphones). In addition, the output signals V _op and V _on are fed back to the error amplifier stage 110 through the resistor R _f . In some embodiments, the power amplifier 10A may be implemented as a digitally controlled variable gain amplifier, and one or more components (eg, R _i , R _f or other components) may be implemented as digitally controlled variable components to control the gain. . Of course, implementation of the present application is not limited to this example of power amplifier 10A. In some embodiments, any power amplifier based on a Class D amplifier and/or a power amplifier that can provide a signal between an input signal terminal and an output signal terminal of the power amplifier for zero-crossing detection can be used to implement the described application. Noise suppression equipment based on sound signal processing.

In some embodiments, the internal signal includes an analog signal that changes according to the signal at the input signal terminal and the signal at the output signal terminal. For example, signals from the error amplifier stage 110, such as V _op1 and V _on1 shown in FIG. 2, can be used as the analog signal. In some embodiments, as shown in FIG. 3A , the zero-crossing detector 20A may include a comparator circuit 21 to detect the analog signal and a reference signal (eg, 0.01 of the maximum allowable signal amplitude (or digitized value)). %, 0.1%, 1%, 2%) to generate the zero-crossing detection signal.

In some embodiments, the internal signal includes a first signal and a second signal (such as V _op1 or V _on1 shown in FIG. 2 ). The first signal and the second signal are based on the signal at the input signal terminal and the output. The first signal and the second signal are analog differential signals. In some embodiments, as shown in FIG. 3B , the zero-crossing detector 20A includes a first comparator circuit 21A and a second comparator circuit 22A. The first comparator circuit 21A generates a first comparison result signal based on the comparison between the first signal and a reference signal. The second comparator circuit 22A generates a second comparison result signal based on the comparison between the second signal and the reference signal. The zero-crossing detector 20 generates the zero-crossing detection signal according to the first comparison result signal and the second comparison result signal, for example, in the form of a logic device 23 .

Please refer to FIG. 4 , which illustrates another embodiment of a device for noise suppression of sound signal processing used in the exemplary architecture of FIG. 1 . As shown in FIG. 4 , a sound signal processing and noise suppression device includes a power amplifier 10A, a zero-crossing detector 20B and a threshold detector 30 .

In some embodiments, the internal signal includes a first signal and a second signal, the first signal and the second signal change according to the signal of the input signal terminal and the signal of the output signal terminal, and the first signal and The second signal is a pulse width modulation signal. For example, signals from the comparator stage 120, such as the pulse width modulation signals PWM_P and PWM_N shown in FIG. 4, can be used as the first signal and the second signal.

In some embodiments, as shown in FIG. 5A , the zero-crossing detector 20B includes a first comparator circuit 210 , a second comparator circuit 220 and a zero-crossing determination circuit 230 .

The first comparator circuit 210 generates a first comparison result signal based on comparison between the first signal and a reference signal. The second comparator circuit 220 generates a second comparison result signal based on the comparison between the second signal and the reference signal. The zero-crossing determination circuit 230 generates the zero-crossing detection signal based on comparison of the first comparison result signal and the second comparison result signal.

Referring to FIG. 5A and FIG. 5B , when one of the first signal and the second signal (eg, pulse width modulation signal PWM_P, PWM_N) indicates a high state, the zero-crossing determination circuit 230 starts to compare the Whether the first signal and the second signal are equal. For example, a sampling clock signal can be used to sample or count the pulse width modulation signals PWM_P, PWM_N for comparison or detection, wherein the sampling clock signal has a sampling frequency (for example, 25 MHz), and the The sampling frequency is greater than the operating frequency of the pulse width modulation signals PWM_P and PWM_N (for example, 384 kHz).

Please refer to Figure 5A and Figure 5B. When the first signal and the second signal are equal, and the first signal and the second signal transition to a low state (for example, two or more transitions to the low state After the clock cycle), there is the same interval (such as a PWM interval) used to represent the high state, the zero-crossing determination circuit 230 generates the zero-crossing detection signal to represent a zero-crossing state; otherwise, the zero-crossing determination circuit 230 The overdetermination circuit 230 generates the zero-crossing detection signal to indicate a non-zero-crossing state.

Please refer to FIG. 6 , which is a schematic diagram showing an embodiment of threshold detection. The threshold detector 30 may be configured such that when the threshold detector 30 detects the digital sound signal in a first reference range (for example, 0.01%, 0.1%, or 0.1% of the maximum allowable signal amplitude (or digitized value), varies within the range of 1% and 2%), as shown in Figure 6. When the zero-crossing detection signal indicates a zero-crossing state, the threshold detector 30 changes the gain The setting is determined as a first gain parameter, as described above with reference to the embodiment of FIG. 1 ; otherwise, the threshold detector 30 determines the gain setting as a second gain parameter.

For example, please refer to FIG. 6. The threshold detector 30 may be configured to include a logic circuit (such as 310 shown in FIG. 7) to determine whether the digital sound signal (Sda) is within the threshold value by comparing and counting. Within the first reference range (such as trigger threshold). If the digital sound signal (Sda) is within the first reference range (for example, the signal amplitude (or absolute value) of the digital sound signal (Sda) is equal to or greater than a trigger threshold), a trigger count starts counting from zero until reaching a trigger threshold. Count threshold (e.g. 2047 or other suitable value). If the counting threshold is reached, a trigger signal can be generated, as shown in Figure 6. The trigger signal uses a pulse to indicate that it is in an active state (asserted). In addition, if the digital sound signal (Sda) is outside the first reference range and falls within the second reference range (for example, the signal amplitude (or absolute value) of the digital sound signal (Sda) is equal to or greater than a release threshold ( release threshold)), the trigger count is reset to zero. Otherwise, if the first reference range and the second reference range of the digital sound signal (Sda) (for example, the signal amplitude (or absolute value) of the digital sound signal (Sda) is greater than the trigger threshold or less than the release threshold) time, the trigger count remains unchanged.

In one embodiment, the threshold detector 30 may be configured to include a control circuit (eg, 320 of FIG. 7 ) to determine the analog gain control according to the above example trigger signal and the zero-crossing detection signal. Signal (Sgc). For example, the analog gain control signal (Sgc) may represent a value B[2:0] as shown in Table 1, thereby controlling the power amplifier 10A to operate in a gain setting state.

Table 1 illustrates some embodiments of gain setting state values that the power amplifier 10A can support, wherein the analog gain of the power amplifier 10A is determined according to the resistors R _f and R _i . In some embodiments, the power amplifier 10A may be implemented by a digitally controlled variable gain amplifier, where the analog gain control signal (Sgc) represents the value B[2:0]. In other embodiments, the power amplifier 10A may be implemented by an analog (eg, voltage) controlled variable gain amplifier, where the analog gain control signal represents a voltage signal corresponding to a gain setting. Table 1 bit numerical value Function (analog gain control) _f R _i B[2:0] 000 X6(+15.5dB) 480K 60K 001 X5(14dB) 480K 96K 010 X4.5(13dB) 480K 106.6K 011 X3.75(11.5dB) 480K 128K 100 X3(9.5dB) 480K 160K 101 X2.5(8dB) 480K 192K 110 X2(6dB) 480K 240K 111 X1.5(3.5dB) 480K 320K

For example, in order to minimize the noise level, when the threshold detector 30 detects that the digital sound signal is within a first reference range (such as 0.01%, 0.1%, When the zero-crossing detection signal indicates a zero-crossing state, the threshold detector 30 determines the gain setting as a first gain parameter. (For example, B[2:0]=111).

In some embodiments, when the small signal condition and the zero-crossing condition are not met, the threshold detector 30 may be configured to optionally determine the gain setting as another gain parameter (e.g., back to previous or another gain parameter other than the first gain parameter).

As mentioned above, the present application provides various embodiments of a noise suppression device for sound signal processing. This device can be used to control analog gain so that when conditions such as lower signal output (eg near zero output or small signal output) occur, the noise level can be reduced. Because the device controls the power amplifier when at least two conditions including a zero-crossing state and a small-signal state are detected, analog gain control can be performed more accurately and in a timely manner. Therefore, the average noise level of the output of the power amplifier can be reduced.

Although the contents disclosed in this application have been described with reference to specific embodiments, those skilled in the art may make numerous modifications and variations without departing from the contents disclosed in this application as set forth within the scope of the patent application. Category and spirit.

5: Digital circuit 9: Digital-to-analog converter 10, 10A: Power amplifier 20, 20A: Zero-crossing detector 21: Comparator circuit 21A: First comparator circuit 22A: Second comparator circuit 23: Logic device 30 : Threshold detector 110: Error amplifier stage 120: Comparator stage 130: Output stage 210: First comparator circuit 220: Second comparator circuit 230: Zero-crossing determination circuit 310: Logic circuit 320: Control circuit C ₁ , C ₂ : Capacitor G _PWM : Gain PWM_P, PWM_N: Pulse width modulation signal Ri, _{R f} , R _z Resistor Sda: Digital sound signal Sgc: Analog gain control signal V _op , V _op1 , V _on , V _on1 : Output signal

FIG. 1 is a schematic diagram showing an exemplary architecture of a noise suppression device for sound signal processing, which represents multiple embodiments of the present application. FIG. 2 is a block diagram illustrating an embodiment of an apparatus for noise suppression of sound signal processing used in the exemplary architecture of FIG. 1 . Figure 3A is a block diagram showing an embodiment of a zero-crossing detector. Figure 3B is a block diagram showing an embodiment of a zero-crossing detector. FIG. 4 is a block diagram illustrating another embodiment of a noise suppression device used in the exemplary architecture of FIG. 1 for audio signal processing. Figure 5A is a block diagram showing an embodiment of a zero-crossing detector. FIG. 5B is a schematic diagram showing an embodiment of zero-crossing detection. FIG. 6 is a schematic diagram showing an embodiment of threshold detection. Figure 7 is a block diagram showing an embodiment of a threshold detector.

5:Digital circuit

9: Digital to analog converter

10:Power amplifier

20: Zero-crossing detector

30:Threshold detector

Sda: digital audio signal

Sgc: analog gain control signal

Claims (12)

A device for noise suppression in sound signal processing, which includes: A power amplifier has an input signal terminal and an output signal terminal, wherein the input signal terminal is used to receive a sound input signal, and the sound input signal is a digital-to-analog conversion version based on a digital sound signal version, and the power The amplifier has an analog gain controllable in response to an analog gain control signal; a zero-crossing detector for determining a zero-crossing detection signal based on an internal signal provided between the input signal terminal and the output signal terminal; and a threshold detector for determining a gain setting based on the digital sound signal and the zero-crossing detection signal to generate the analog gain control signal to represent the gain setting, The threshold detector controls the analog gain of the power amplifier according to the analog gain control signal. The device of claim 1, wherein when the threshold detector detects that the digital sound signal changes within a first reference range and the zero-crossing detection signal indicates a zero-crossing state, the threshold detector The detector determines the gain setting as a first gain parameter; otherwise, the threshold detector determines the gain setting as a second gain parameter. The device of claim 2, wherein the power amplifier has a plurality of gain setting states, and the power amplifier is set to one of the plurality of gain setting states according to the gain setting represented in the analog gain control signal. , wherein the first gain parameter represents one of the plurality of gain setting states so that the power amplifier has a lower gain. The device according to claim 1, wherein the internal signal includes an analog signal, and the analog signal changes according to the signal at the input signal terminal and the signal at the output signal terminal. The device of claim 4, wherein the zero-crossing detector includes a comparator circuit that generates the zero-crossing detection signal based on a comparison between the analog signal and a reference signal. The device as described in claim 1, wherein the internal signal includes a first signal and a second signal, the first signal and the second signal change according to the signal of the input signal terminal and the signal of the output signal terminal, and the The first signal and the second signal are analog differential signals. The device of claim 6, wherein the zero-crossing detector includes: a first comparator circuit that generates a first comparison result signal based on the comparison between the first signal and a reference signal; and a second comparator circuit that generates a second comparison result signal based on the comparison between the second signal and the reference signal, The zero-crossing detector generates the zero-crossing detection signal according to the first comparison result signal and the second comparison result signal. The device as described in claim 1, wherein the internal signal includes a first signal and a second signal, the first signal and the second signal change according to the signal of the input signal terminal and the signal of the output signal terminal, and the The first signal and the second signal are pulse width modulation signals. The device of claim 8, wherein the zero-crossing detector includes: a first comparator circuit that generates a first comparison result signal based on the comparison between the first signal and a reference signal; a second comparator circuit that generates a second comparison result signal based on the comparison between the second signal and the reference signal; and A zero-crossing determination circuit generates the zero-crossing detection signal based on the comparison between the first comparison result signal and the second comparison result signal, Wherein, when one of the first signal and the second signal indicates a high state, the zero-crossing determination circuit starts to compare whether the first signal and the second signal are equal; Wherein, when the first signal and the second signal are equal and have the same interval used to represent the high state after the first signal and the second signal turn to the low state, the zero-crossing determination circuit generates the zero The cross-over detection signal represents a zero-crossing state; otherwise, the zero-crossing determination circuit generates the zero-crossing detection signal to represent a non-zero-crossing state. The device of claim 1, wherein the power amplifier is a class D amplifier. The device of claim 1, wherein the device further includes a digital-to-analog converter for performing digital-to-analog conversion according to a version of the digital sound signal to generate the sound input signal. The device according to claim 1, wherein the device is a digital input audio amplifier or an audio reproduction device.

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