TWI806188B - Power supply device - Google Patents

Abstract

A power supply device is provided. The power supply device includes a power converter, an error detection circuit and a voltage stabilizing circuit. The power converter provides an output voltage through an output terminal. The error detection circuit detects a variation error of the output voltage, and provides an error voltage signal according to the variation error. When a voltage value of the error voltage signal is greater than a threshold value, the voltage stabilizing circuit gradually increases a capacitance value between the output terminal and a ground terminal over time, thereby reducing the variation error.

Description

power supply unit

The present invention relates to a power supply device, and in particular to a power supply device capable of limiting fluctuation error of output voltage.

Generally speaking, under the condition of the same high output power, the power supply device will provide higher output voltage and lower output current. Therefore, the heat energy generated by the power supply device can be reduced. In this way, the power supply device may require fewer cooling elements.

However, as shown in Figure 1, when the voltage value of the output voltage VO increases, the fluctuation error (or fluctuation) of the output voltage VO will also increase, and then the voltage value of the output voltage VO exceeds the upper fluctuation limit value VH0 and Change the range defined by the lower limit value VL0. For example, when the voltage value of the output voltage VO is increased by 48 volts, the variation of the voltage value of the output voltage VO may exceed the upper limit value VH0 (eg, 50.4 volts) and the lower limit value VL0 (eg, 45.6 volts). ) defined range. The above-mentioned large changes may cause misoperation of electronic devices receiving the output voltage VO (such as devices such as notebook computers, tablet computers, and smart phones). Misoperations include, for example, abnormal startup, abnormalities when charging the battery module, and other misoperations.

Therefore, how to control the fluctuation error of the output voltage of the power supply device is one of the research focuses of those skilled in the art.

The invention provides a power supply device capable of effectively controlling the variation error of the output voltage.

The power supply device of the present invention includes a power converter, an error detection circuit and a voltage stabilizing circuit. The power converter provides an output voltage through an output terminal of the power converter. The error detection circuit is coupled to the power converter. The error detection circuit detects the variation error of the output voltage, and provides an error voltage signal according to the variation error. The variable error is directly related to the voltage value of the error voltage signal. The voltage stabilizing circuit is coupled to the error detection circuit and the power converter. When the voltage value of the error voltage signal is greater than the threshold value, the voltage stabilizing circuit gradually increases the capacitance between the output terminal of the power converter and the ground terminal over time, so as to reduce the variation error.

Based on the above, when the voltage value of the error voltage signal is greater than the threshold value, the voltage stabilizing circuit gradually increases the capacitance between the output terminal of the power converter and the ground terminal over time. In this way, the fluctuation error of the output voltage can be reduced.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

Parts of the embodiments of the present invention will be described in detail with reference to the accompanying drawings. For the referenced reference symbols in the following description, when the same reference symbols appear in different drawings, they will be regarded as the same or similar components. These embodiments are only a part of the present invention, and do not reveal all possible implementation modes of the present invention. Rather, these embodiments are only examples within the scope of the patent application of the present invention.

Please refer to FIG. 2 , which is a schematic diagram of a power supply device according to a first embodiment of the present invention. In this embodiment, the power supply device 100 includes a power converter 110 , an error detection circuit 120 and a voltage stabilizing circuit 130 . The power converter 110 provides the output voltage VO through the output terminal of the power converter 110 itself. The error detection circuit 120 is coupled to the power converter 110 . The error detection circuit 120 detects a variation error EV of the output voltage VO, and provides an error voltage signal SC according to the variation error EV. The voltage stabilizing circuit 130 is coupled to the error detection circuit 120 and the power converter 110 . The voltage stabilizing circuit 130 judges the error voltage signal SC. When the voltage value of the error voltage signal SC is greater than the threshold, the voltage stabilizing circuit 130 gradually increases the capacitance between the output terminal and the ground terminal over time, so as to reduce the variation error EV. In this way, the stability of the output voltage VO is improved.

On the other hand, when the voltage value of the error voltage signal SC is less than or equal to the threshold, the voltage stabilizing circuit 130 will not increase the capacitance between the output terminal and the ground terminal.

Furthermore, the variation error EV of the output voltage VO is positively correlated with the voltage value of the error voltage signal SC. That is to say, the larger the variation error EV is, the larger the voltage value of the error voltage signal SC is. The smaller the variation error EV is, the smaller the voltage value of the error voltage signal SC is. In this embodiment, when the voltage value of the error voltage signal SC is greater than the threshold, it means that the variation error EV of the output voltage VO is too large. Therefore, the voltage stabilizing circuit 130 increases the capacitance CV1 between the output terminal and the ground to the capacitance CV2 at the first time point, and increases the capacitance CV2 to the capacitance CV3 at the second time point.

It should be noted here that when the voltage value of the error voltage signal SC is greater than the threshold value, the voltage stabilizing circuit 130 gradually increases the capacitance between the output terminal and the ground terminal over time. Therefore, the voltage stabilizing circuit 130 can avoid problems such as compensation feedback and electromagnetic interference (EMI) derived from the output voltage VO being rapidly limited.

Please refer to FIG. 3 , which is a schematic diagram of a power supply device according to a second embodiment of the present invention. In this embodiment, the power supply device 200 includes a power converter 210 , an error detection circuit 220 and a voltage stabilizing circuit 230 . The power converter 210 includes a rectifier BR, a transformer TR, a magnetizing inductor LM, a power switch Q1, an output diode DO1 and an output capacitor CO1. The rectifier BR is, for example, a full bridge rectifier. The transformer TR includes a primary winding NP and a secondary winding NS. The magnetizing inductor LM is connected in parallel to the primary side winding NP. The first end of the magnetizing inductor LM is coupled to the rectifier BR. A first end of the power switch Q1 is coupled to a second end of the magnetizing inductor LM. The second terminal of the power switch Q1 is coupled to the ground terminal GND1. The control terminal of the power switch Q1 receives a control signal (not shown). The first end of the secondary winding NS is coupled to the anode of the output diode DO1. The second terminal of the secondary winding NS is coupled to the ground terminal GND2. The cathode of the output diode DO1 is the output terminal of the power converter 210 . The first terminal of the output capacitor CO1 is coupled to the output terminal of the power converter 210 . The second terminal of the output capacitor CO1 is coupled to the ground terminal GND2. In this embodiment, the power converter 210 may be composed of a rectifier BR and a flyback converter. Based on the switching operation of the power switch Q1, the power converter 210 can convert the input voltage VIN into the output voltage VO.

In some embodiments, the power converter 210 can be implemented by at least one converter. For example, the power converter 210 may include at least one of a boost converter, a buck converter, and an LLC resonant converter.

In this embodiment, the error detection circuit 220 includes an error amplifier EC and a voltage amplifier AMP. The error amplifier EC provides an error signal according to the variable error (eg, the variable error EV shown in FIG. 2 ) within the sampling time interval. For example, the sampling time interval is designed to be 40-200 microseconds. The voltage amplifier AMP is coupled to the error amplifier EC. The non-inverting input terminal of the error amplifier EC is coupled to the first terminal of the output capacitor CO1. The inverting input terminal of the error amplifier EC is coupled to the second terminal of the output capacitor CO1. The output terminal of the error amplifier EC is coupled to the voltage amplifier AMP. The error amplifier EC provides an error signal to the voltage amplifier AMP through the output terminal of the error amplifier EC itself. The voltage amplifier AMP amplifies the error signal to generate the error voltage signal SC.

In this embodiment, the error detection circuit 220 can also adjust the error voltage signal SC. In this embodiment, the error detection circuit 220 further includes a voltage dividing circuit 221 and a filter 222 . The voltage dividing circuit 221 is coupled to the voltage amplifier AMP. The voltage dividing circuit 221 divides the voltage value of the error voltage signal SC. The filter 222 is coupled to the voltage amplifier AMP. The filter 222 performs a filtering operation on the error voltage signal SC. In this embodiment, the voltage dividing circuit 221 includes resistors R1, R2. The resistor R1 is coupled between the voltage amplifier AMP and the voltage stabilizing circuit 230 . The resistor R2 is coupled between the voltage stabilizing circuit 230 and the ground terminal GND2. The voltage dividing circuit 221 adjusts the voltage value of the error voltage signal SC based on the resistance value of the resistor R1 and the resistance value of the resistor R2 . Filter 222 includes capacitors C1, C2. The capacitor C1 is coupled between the voltage amplifier AMP and the voltage stabilizing circuit 230 . The capacitor C2 is coupled between the voltage stabilizing circuit 230 and the ground terminal GND2. The filter 222 filters out the high frequency noise of the error voltage signal SC.

In addition, in order to avoid misoperation of the voltage dividing circuit 221 and the filter 222 , the error detection circuit 220 further includes a unidirectional diode DO2. The anode of the unidirectional diode DO2 is coupled to the voltage dividing circuit 221 and the filter 222 . The cathode of the one-way diode DO2 is coupled to the ground terminal GND2. In this embodiment, the second end of the output capacitor CO1 and the voltage stabilizing circuit 330 are coupled to the anode of the unidirectional diode DO2. In other words, the second terminal of the output capacitor CO1 and the voltage stabilizing circuit 330 are coupled to the ground terminal GND2 via the unidirectional diode DO2. However, the present invention is not limited thereto. In some embodiments, the second terminal of the output capacitor CO1 and the voltage stabilizing circuit 330 are directly connected to the ground terminal GND2.

In some embodiments, based on design requirements, the error detection circuit 220 may not include the voltage dividing circuit 221 and/or the filter 222 . In such embodiments, the unidirectional diode DO2 can be omitted.

In this embodiment, during the sampling time interval, when the voltage value of the error voltage signal SC is greater than the threshold value, the voltage stabilizing circuit 230 will gradually increase the voltage between the output terminal of the power converter and the ground terminal GND2 over time during the sampling time interval. capacitance value between. In other words, the voltage stabilizing circuit 230 will limit the fluctuation error of the output voltage VO within the sampling time interval.

The voltage stabilizing circuit 230 includes diodes DX1~DX3, capacitors CO2~CO4, transistors Q2~Q4, and delay circuits DL1, DL2. The anode error detection circuit 220 of the diode DX1 is coupled to. The anode of the diode DX1 receives the error voltage signal SC. The first end of the capacitor CO2 is coupled to the output end of the power converter 210 . The first end of the transistor Q2 is coupled to the second end of the capacitor CO2. The second terminal of the transistor Q2 is coupled to the ground terminal GND2. The control terminal of the transistor Q2 is coupled to the cathode of the diode DX1. In this embodiment, the combination of the diode DX1, the capacitor CO2 and the transistor Q2 may be the first branch circuit. In this embodiment, the second terminal of the transistor Q2 is coupled to the ground terminal GND2 through the unidirectional diode DO2. In some embodiments, the second terminal of the transistor Q2 can be directly connected to the ground terminal GND2.

The anode of the diode DX2 is coupled to the cathode of the diode DX1. The first end of the capacitor CO3 is coupled to the output end of the power converter 210 . The first end of the transistor Q3 is coupled to the second end of the capacitor CO3. The second terminal of the transistor Q3 is coupled to the ground terminal GND2. The input end of the delay circuit DL1 is coupled to the cathode of the diode DX2 to receive the error voltage signal SC. The output terminal of the delay circuit DL1 is coupled to the control terminal of the transistor Q3. The delay circuit DL1 delays the error voltage signal SC. In this embodiment, the combination of the diode DX2, the capacitor CO3, the transistor Q3 and the delay circuit DL1 may be the second branch circuit. In this embodiment, the second terminal of the transistor Q3 is coupled to the ground terminal GND2 via the unidirectional diode DO2. In some embodiments, the second terminal of the transistor Q3 can be directly connected to the ground terminal GND2.

The anode of the diode DX3 is coupled to the cathode of the diode DX2. The first end of the capacitor CO4 is coupled to the output end of the power converter 210 . The first end of the transistor Q4 is coupled to the second end of the capacitor CO4. The second terminal of the transistor Q4 is coupled to the ground terminal GND2. The input end of the delay circuit DL2 is coupled to the cathode of the diode DX3 to receive the error voltage signal SC. The output terminal of the delay circuit DL2 is coupled to the control terminal of the transistor Q4. The delay circuit DL2 delays the error voltage signal SC. In this embodiment, the combination of the diode DX3, the capacitor CO4, the transistor Q4 and the delay circuit DL2 may be the third branch circuit. In this embodiment, the second terminal of the transistor Q4 is coupled to the ground terminal GND2 through the unidirectional diode DO2. In some embodiments, the second terminal of the transistor Q4 can be directly connected to the ground terminal GND2.

It should be noted that the delay provided by the delay circuit DL2 is greater than the delay provided by the delay circuit DL1. The aforementioned thresholds are roughly equal to the critical voltages of the transistors Q2 - Q4 . Therefore, when the voltage value of the error voltage signal SC is greater than the threshold, the transistors Q2 - Q4 are sequentially turned on.

Based on design requirements, in some embodiments, the third branch circuit can be omitted. In other words, the voltage stabilizing circuit 230 includes diodes DX1 , DX2 , capacitors CO2 , CO3 , transistors Q2 , Q3 and a delay circuit DL1 . In some embodiments, branch circuits may be added.

The transistors Q2 to Q4 in this embodiment are respectively implemented as N-type field effect transistors in any form. The present invention is not limited to the implementation manners of the transistors Q2 - Q4 . In some embodiments, the transistors Q2 - Q4 are respectively implemented as NPN bipolar transistors.

Please refer to FIG. 3 and FIG. 4 at the same time. FIG. 4 is a schematic diagram showing the variation error of the output voltage is limited according to an embodiment of the present invention. In the sampling time interval, it is judged that the output voltage VO begins to have a large fluctuation error at the time point tp0. That is, the voltage value of the output voltage VO exceeds the range defined by the fluctuation upper limit value VH1 and the fluctuation lower limit value VL1. Therefore, the voltage value of the error voltage signal SC provided by the error detection circuit 220 is greater than the threshold voltage values of the transistors Q2 ˜ Q4 . Therefore, the transistor Q2 is turned on at the time point tp1 in the sampling time interval. When the transistor Q2 is turned on, the capacitor CO2 is coupled in parallel with the output capacitor CO1. Therefore, at the time point tp1, the capacitance between the output terminal of the power converter 210 and the ground GND2 increases from the first capacitance to the second capacitance. The variation error of the output voltage VO is limited between a variation upper limit VH1 and a variation lower limit VL1 .

Based on the delay of the error voltage signal SC by the delay circuit DL1, the transistor Q3 is turned on at the time point tp2 in the sampling time interval. When the transistors Q2, Q3 are turned on, the capacitors CO1, CO2 are coupled in parallel with the output capacitor CO1. Therefore, at the time point tp2, the capacitance between the output terminal of the power converter 210 and the ground terminal GND2 increases from the second capacitance value to the third capacitance value. The variation error of the output voltage VO is limited between a variation upper limit VH2 and a variation lower limit VL2.

Based on the delay of the error voltage signal SC by the delay circuit DL2, the transistor Q4 is turned on at the time point tp3 in the sampling time interval. When the transistors Q2 - Q4 are turned on, the capacitors CO2 - CO4 are coupled in parallel with the output capacitor CO1 . Therefore, at the time point tp3, the capacitance between the output terminal of the power converter 210 and the ground terminal GND2 increases from the third capacitance value to the fourth capacitance value. The variation error of the output voltage VO is limited between a variation upper limit VH3 and a variation lower limit VL3.

Please refer to FIG. 5 , which is a schematic diagram of a power supply device according to a third embodiment of the present invention. In this embodiment, the power supply device 300 includes a power converter 210 , an error detection circuit 220 and a voltage stabilizing circuit 330 . The implementation details of the power converter 210 and the error detection circuit 220 have been fully disclosed in the second embodiment, so they will not be repeated here. The voltage stabilizing circuit 330 includes the voltage stabilizing circuit 230 including diodes DX1 ˜ DX3 , resistors RX1 , capacitors CO2 ˜ CO4 , transistors Q2 ˜ Q4 , and delay circuits DL1 , DL2 . In this embodiment, the anode of the diode DX1 receives the error voltage signal SC. The first end of the capacitor CO2 is coupled to the output end of the power converter 210 . The first end of the transistor Q2 is coupled to the second end of the capacitor CO2. The second terminal of the transistor Q2 is coupled to the ground terminal GND2. The resistor RX1 is coupled between the control terminal of the transistor Q2 and the cathode of the diode DX1.

The coupling relationship of the diode DX2, the capacitor CO3, the transistor Q3 and the delay circuit DL1 has been fully disclosed in the second embodiment, so it will not be repeated here. In this embodiment, the delay circuit DL1 includes a delay capacitor CX2 and a delay resistor RX2. The delay capacitor CX2 and the delay resistor RX2 are coupled in series between the cathode of the diode DX2 and the control terminal of the transistor Q3. The first product of the capacitance of the delay capacitor CX2 and the resistance of the delay resistor RX2 is related to the delay time length of the delay circuit DL1.

The coupling relationship of the diode DX3, the capacitor CO4, the transistor Q4 and the delay circuit DL2 has been fully disclosed in the second embodiment, so it will not be repeated here. In this embodiment, the delay circuit DL2 includes a delay capacitor CX3 and a delay resistor RX3. The delay capacitor CX3 and the delay resistor RX3 are coupled in series between the cathode of the diode DX3 and the control terminal of the transistor Q4. The second product of the capacitance of the delay capacitor CX3 and the resistance of the delay resistor RX3 is related to the delay time length of the delay circuit DL2.

In this embodiment, the second product is greater than the first product. For example, the resistance value of the delay resistor RX3 is greater than the resistance value of the delay resistor RX2. The resistance value of the delay resistor RX2 is greater than that of the resistor RX1. The capacitance value of the delay capacitor CX3 is larger than the capacitance value of the delay capacitor CX2.

To sum up, the error detection circuit detects the variation error of the output voltage, and provides an error voltage signal according to the variation error. When the voltage value of the error voltage signal is greater than the threshold value, the voltage stabilizing circuit gradually increases the capacitance between the output terminal of the power converter and the ground terminal over time. In this way, the present invention can effectively reduce the fluctuation error of the output voltage, and avoid problems such as compensation feedback and EMI derived from the rapid limitation of the output voltage.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

100, 200, 300: power supply device 110, 210: power converter 120, 220: error detection circuit 130, 230, 330: regulator circuit 221: Voltage divider circuit 222: filter AMP: voltage amplifier BR: rectifier C1, C2, CO2~CO4: Capacitors CO1 output capacitor CV1~CV3: capacitance value DO1: output diode DO2: one-way diode DL1, DL2: delay circuit DX1~DX3: Diode EC: error amplifier EV: Variation Error GND1, GND2: ground terminal LM: Exciting inductor NP: Primary side winding NS: Secondary side winding Q1: Power switch Q2~Q4: Transistor R1, R2, RX1: Resistors SC: error voltage signal tp0~tp3: time point t: time TR: Transformer VH0~VH3: Change upper limit value VIN: input voltage VL0~VL3: change lower limit value VO: output voltage

Figure 1 is a waveform diagram of the output voltage. FIG. 2 is a schematic diagram of a power supply device according to a first embodiment of the present invention. FIG. 3 is a schematic diagram of a power supply device according to a second embodiment of the present invention. FIG. 4 is a schematic diagram illustrating that the fluctuation error of the output voltage is limited according to an embodiment of the present invention. FIG. 5 is a schematic diagram of a power supply device according to a third embodiment of the present invention.

100: Power supply device 110: Power converter 120: Error detection circuit 130: Regulator circuit CV1~CV3: capacitance value EV: Variation Error SC: error voltage signal VO: output voltage

Claims (10)

A power supply device, comprising: a power converter configured to provide an output voltage through an output terminal of the power converter; an error detection circuit, coupled to the power converter, configured to detect a variation error of the output voltage, and provide an error voltage signal according to the variation error, wherein the variation error is positively related to the error voltage signal the voltage value of ; and A voltage stabilizing circuit, coupled to the error detection circuit and the power converter, is configured to gradually increase the voltage between the output end of the power converter and a ground when the voltage value of the error voltage signal is greater than a threshold value over time. Capacitance value between terminals, thereby reducing the variation error. The power supply device as claimed in item 1, wherein the error detection circuit includes: an error amplifier configured to provide an error signal based on the varying error within a sampling time interval; and A voltage amplifier, coupled to the error amplifier, is configured to gain the error signal to generate the error voltage signal. The power supply device according to claim 2, wherein the error detection circuit further includes: a voltage dividing circuit, coupled to the voltage amplifier, configured to divide the voltage value of the error voltage signal; and A filter, coupled to the voltage amplifier, is configured to filter the error voltage signal. The power supply device as described in claim 1, wherein in a sampling time interval, when the voltage value of the error voltage signal is greater than the threshold value, the voltage stabilizing circuit gradually increases with time in the sampling time interval. The capacitance value between the output terminal of the device and the ground terminal. The power supply device as described in claim 1, wherein: When the voltage value of the error voltage signal is greater than the threshold value, the voltage stabilizing circuit connects a first output capacitor located between the output terminal of the power converter and the ground terminal at a first time point in the sampling time interval value is increased to a second output capacitance value, and at a second time point in the sampling time interval, the second output capacitance value is increased to a third output capacitance value, and The second point in time is behind the first point in time. The power supply device as described in claim 5, wherein the voltage stabilizing circuit includes: a first diode, the anode of the first diode receives the error voltage signal; a first capacitor, the first terminal of the first capacitor is coupled to the output terminal of the power converter; A first transistor, the first terminal of the first transistor is coupled to the second terminal of the first capacitor, the second terminal of the first transistor is coupled to the ground terminal, the control of the first transistor terminal coupled to the cathode of the first diode; a second diode, the anode of the second diode is coupled to the cathode of the first diode; a second capacitor, the first terminal of the second capacitor is coupled to the output terminal of the power converter; a second transistor, the first terminal of the second transistor is coupled to the second terminal of the second capacitor, and the second terminal of the second transistor is coupled to the ground terminal; and A first delay circuit, the input end of the first delay circuit is coupled to the cathode of the second diode to receive the error voltage signal, the output end of the first delay circuit is coupled to the control of the second transistor terminal configured to delay the error voltage signal. The power supply device as described in claim 6, wherein: The power converter includes an output capacitor, The output capacitor is coupled between the output terminal of the power converter and a ground terminal, The threshold is substantially equal to the threshold voltage value of the first transistor and the threshold voltage value of the second transistor, When the voltage value of the error voltage signal is greater than the threshold, the first transistor is turned on at the first time point, so that the first capacitor is coupled in parallel with the output capacitor, and The second transistor is turned on at the second time point, so that the second capacitor, the first capacitor and the output capacitor are coupled in parallel. The power supply device as claimed in item 6, wherein the first delay circuit includes: a delay capacitor; and A delay resistor is coupled in series with the delay capacitor between the cathode of the second diode and the control terminal of the second transistor. The power supply device as claimed in item 7, wherein the voltage stabilizing circuit further includes: a third diode, the anode of the third diode is coupled to the cathode of the second diode; a third capacitor, the first terminal of the third capacitor is coupled to the output terminal of the power converter; a third transistor, the first terminal of the third transistor is coupled to the second terminal of the third capacitor, and the second terminal of the third transistor is coupled to the ground terminal; and A second delay circuit, the input end of the first delay circuit is coupled to the cathode of the third diode to receive the error voltage signal, the output end of the second delay circuit is coupled to the control of the third transistor end, Wherein the third transistor is turned on at a third time point in the sampling time interval, so that the third capacitor, the second capacitor, the first capacitor and the output capacitor are coupled in parallel, Wherein the third time point is behind the second time point. The power supply device as claimed in claim 9, wherein the delay provided by the second delay circuit is greater than the delay provided by the first delay circuit.

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