TWI804272B - Three-dimensional memory device - Google Patents

Abstract

A three-dimensional memory device is provided. The three-dimensional memory device includes a substrate, a stacking structure, a vertical source structure, a vertical drain structure, and a vertical channel layer. The stacking structure is disposed on the substrate and includes a plurality of conductive layers and a plurality of insulating layer alternately stacked. The vertical source structure and the vertical drain structure are embedded in the stacking structure. The vertical source structure and the vertical drain structure respectively include single crystalline silicon and metal silicide. The vertical channel layer surrounds the vertical source structure and the vertical drain structure and is in contact with the vertical source structure and the vertical drain structure, in which the vertical channel layer includes single crystalline silicon.

Description

3D memory device

The invention relates to a three-dimensional memory element.

One of the great characteristics of non-volatile memory device design is that it can still maintain the integrity of the data state when the memory device loses or removes power. With the increase of various applications and the improvement of functions, the demand for memory components also tends to be smaller in size and larger in storage capacity. To meet these needs, designers are now turning to developing a three-dimensional memory device that includes a stack of multiple planes of memory cells.

However, as the critical dimension of the device shrinks to the limit of the general memory cell technology field, how to obtain a higher storage capacity in a smaller device size while taking into account the operational stability of the device has become an issue. Important issues facing the technical field. Therefore, an advanced three-dimensional memory structure is needed to solve the problems faced by the prior art.

An aspect of the present disclosure provides a three-dimensional memory device. The three-dimensional memory device includes a substrate, a stack structure, a vertical source structure, a vertical drain structure and a vertical channel layer. The stacked structure is located above the substrate and includes a plurality of conductive layers and a plurality of insulating layers stacked alternately. The vertical source structure and the vertical drain structure are buried in the stack structure, and respectively include single crystal silicon and metal silicide. The vertical channel layer surrounds and contacts the vertical source structure and the vertical drain structure.

According to some embodiments of the present disclosure, the vertical source structure and the vertical drain structure respectively include a bottom metal silicide layer, an inner metal silicide layer and a single crystal silicon layer, wherein the inner metal silicide layer and the single crystal silicon layer are located on the bottom metal silicide layer. on the silicide layer, and the single crystal silicon layer surrounds the inner metal silicide layer.

According to some embodiments of the present disclosure, the vertical source structure includes a bottom metal silicide layer, an outer metal silicide layer, an inner metal silicide layer, and a layer between the outer metal silicide layer and the inner metal silicide layer in the vertical source structure. The vertical drain structure includes a bottom metal silicide layer, an outer metal silicide layer, and a single crystal silicon layer between the outer metal silicide layer of the vertical drain structure and the vertical channel layer.

According to some embodiments of the present disclosure, the single crystal silicon has a doping concentration greater than about 10 ¹⁸ /cm ³ .

According to some embodiments of the present disclosure, the three-dimensional memory device further includes a bit line-connected vertical drain structure and a source line-connected vertical source structure.

According to another aspect of the present disclosure, a three-dimensional memory device is provided. The three-dimensional memory device includes a substrate, a plurality of stacked structures, a plurality of vertical source structures, a plurality of vertical drain structures, a plurality of annular channel layers and a plurality of slit structures. A plurality of stacked structures are located above the substrate, and each of the plurality of stacked structures includes a plurality of conductive layers and a plurality of insulating layers stacked alternately. A plurality of vertical source structures and a plurality of vertical drain structures are buried in a plurality of stacked structures, wherein the plurality of vertical source structures and the plurality of vertical drain structures respectively include single crystal silicon and metal silicide. A plurality of annular channel layers each surround a corresponding vertical source structure and a corresponding vertical drain structure, wherein the plurality of annular channel layers include single crystal silicon. The plurality of slit structures are located between the plurality of stacked structures to separate the plurality of stacked structures.

According to some embodiments of the present disclosure, the single crystal silicon has a doping concentration greater than about 10 ¹⁸ /cm ³ .

According to some embodiments of the present disclosure, each of the plurality of conductive layers includes a memory layer, a titanium nitride layer, and a tungsten layer.

According to some embodiments of the present disclosure, the three-dimensional memory device further includes a dielectric layer located between the corresponding vertical source structure and the corresponding vertical drain structure.

According to some embodiments of the present disclosure, the metal silicide includes CoSi, CoSi ₂ , NiSi or NiSi ₂ .

It is to be understood that both the foregoing general description and the following detailed description are examples and are intended to provide further explanation of the disclosure as claimed.

In order to make the description of the present disclosure more detailed and complete, the following provides an illustrative description of the implementation aspects and specific embodiments of the present disclosure, but this is not the only form for implementing or using the specific embodiments of the present disclosure. The various embodiments disclosed below can be combined or replaced with each other when beneficial, and other embodiments can also be added to one embodiment, without further description or illustration. In the following description, numerous specific details will be set forth in order to enable readers to fully understand the following embodiments. However, embodiments of the present disclosure may be practiced without these specific details.

Furthermore, relative spatial terms, such as "below", "below", "above", "above", etc., are for the convenience of describing the relative relationship between one element or feature and another element or feature, as shown in Fig. as shown in . The real meaning of these spatially relative terms includes other orientations. For example, when the diagram is turned upside down by 180 degrees, the relationship between one element and another may change from "below" and "below" to "above" and "above". In addition, the spatially relative descriptions used in this article should also be interpreted in the same way.

FIG. 1 to FIG. 16 are schematic diagrams illustrating various steps of manufacturing a three-dimensional memory device 100 according to an embodiment of the present invention. Please refer to Figure 1. A plurality of first insulating layers 110 and a plurality of second insulating layers 120 are alternately formed on the substrate 101 . The material of the first insulating layer 110 is different from that of the second insulating layer 120 . In some embodiments, the first insulating layer 110 includes oxide, such as silicon oxide. In some embodiments, the second insulating layer 120 includes nitride, such as silicon nitride. It should be understood that the number of the first insulating layer 110 and the second insulating layer 120 is not limited to that shown in FIG. 1 , and there may be more layers of the first insulating layer 110 and the second insulating layer 120 according to actual application.

Please refer to Figure 2. The first openings OP1 are formed in the plurality of first insulating layers 110 and the plurality of second insulating layers 120 . In some embodiments, the first opening OP1 passing through the plurality of first insulating layers 110 and the plurality of second insulating layers 120 is formed through an etching process, and the first opening OP1 stops at the bottommost first insulating layer 110 .

Please refer to Figure 3. A channel material layer 130 and a dielectric layer 140 are formed in the first opening OP1 shown in FIG. 2 . The channel material layer 130 is formed on the sidewall of the first opening OP1 and exposes the bottommost first insulating layer 110 , and then the dielectric layer 140 fills the remaining first opening OP1 . In some embodiments, the channel material layer 130 is an undoped amorphous silicon layer. In some embodiments, the channel material layer 130 has a thickness of about 5-20 nm. In some embodiments, the dielectric layer 140 includes oxide. In some embodiments, a charge trapping material (not shown) may be formed in the first opening OP1 before forming the channel material layer 130 . In some embodiments, the charge trapping material comprises an oxide-nitride (O-N) composite layer, such as an ONO composite layer. The channel material layer 130, the dielectric layer 140 and the charge trapping material may be formed by any suitable deposition method.

Please refer to Figure 4. A second opening OP2 is formed in the dielectric layer 140 . The second opening OP2 extending to the bottommost first insulating layer 110 may be formed by an etching process (such as a reactive ion etching process) to expose a portion of the channel material layer 130 and the bottommost first insulating layer 110 . This etching process has high selectivity without damaging the amorphous silicon of the channel material layer 130 .

Please refer to Figure 5. A semiconductor material layer 150 is formed in the second opening OP2 shown in FIG. 4 . In some embodiments, the semiconductor material layer 150 includes N-type amorphous silicon doped with arsenic (As) or phosphorus (P). In some embodiments, the doping concentration of the semiconductor material layer 150 is greater than about 10 ¹⁸ /cm ³ . The doping concentration is, for example, 10 ¹⁹ /cm ³ or 10 ²⁰ /cm ³ . Layer 150 of semiconductor material may be formed by any suitable deposition method.

Please refer to Figure 6. An insulating layer 112 is formed on the substrate 101 . The insulating layer 112 covers the upper surfaces of the uppermost first insulating layer 110 , the channel material layer 130 , the dielectric layer 140 and the semiconductor material layer 150 . In some embodiments, insulating layer 112 includes oxide. Insulating layer 112 may be formed by any suitable deposition method.

Please refer to Figure 7. A third opening OP3 is formed in the dielectric layer 140 . The third opening OP3 extending to the bottommost first insulating layer 110 may be formed by an etching process (such as a reactive ion etching process) to expose a portion of the channel material layer 130 and the bottommost first insulating layer 110 . This etching process has high selectivity without damaging the amorphous silicon of the channel material layer 130 .

Please refer to Figure 8. A semiconductor material layer 160 is formed in the third opening OP3. In some embodiments, the semiconductor material layer 160 includes N-type amorphous silicon undoped or doped with arsenic (As) or phosphorus (P). N-type amorphous silicon with high doping can form ohmic contacts and reduce resistance. In some embodiments, the doping concentration of the semiconductor material layer 160 is greater than about 10 ¹⁸ /cm ³ . In some embodiments, the semiconductor material layer 160 has a thickness of about 10-30 nm, such as about 20 nm. The semiconductor material layer 160 covering the channel material layer 130 can be used as a buffer layer in the subsequent crystallization process to form a channel layer with uniform single crystal silicon. Layer 160 of semiconductor material may be formed by any suitable deposition method.

Please refer to Figure 9. A metal silicide material layer 170 is formed on the semiconductor material layer 160 . In some embodiments, the metal silicide material layer 170 includes CoSi, NiSi, or the like. In some embodiments, forming the metal silicide material layer 170 includes forming a metal layer (such as Co or Ni) on the semiconductor material layer 160 , and then performing a first annealing process to form a metal silicide (such as CoSi or NiSi). In some embodiments, the metal layer has a thickness of about 5-10 nm. In some embodiments, the thickness of the metal layer (represented as a) is less than the sum of the thickness of the channel material layer 130 (represented as b) and the thickness of the semiconductor material layer 160 (represented as c), for example: b+c>1.9a . If the metal layer is too thick, the channel material layer 130 and the semiconductor material layer 160 will be consumed in the subsequent crystallization process. If the thickness of the metal layer is too thin, the subsequently formed channel layer will be discontinuous. In some embodiments, the first annealing process includes annealing at about 400-600 ^° C. for about 15-120 seconds, such as about 30-60 seconds.

Please refer to Figure 10A. A semiconductor material layer 180 is formed on the metal silicide material layer 170 to fill the remaining third opening OP3. In some embodiments, the semiconductor material layer 180 includes N-type amorphous silicon doped with arsenic (As) or phosphorus (P). In some embodiments, the doping concentration of the semiconductor material layer 180 is greater than about 10 ¹⁸ /cm ³ . In some embodiments, the doping concentration of the semiconductor material layer 180 may be the same as the doping concentration of the semiconductor material layers 150 , 160 . In some embodiments, the semiconductor material layer 180 has a thickness of about 5-30 nm, such as about 20 nm. The thickness of the semiconductor material layer 180 is greater than the thickness of the metal silicide material layer 170 . Layer 180 of semiconductor material may be formed by any suitable deposition method.

Figure 10B is a top view of the structure shown in Figure 10A. For clarity, the insulating layer 112 and the horizontal portions of the semiconductor material layers 160 , 180 and the metal silicide material layer 170 are not shown in FIG. 10B . Please refer to Figure 10B. The channel material layer 130 surrounds the dielectric layer 140 , the semiconductor material layer 150 and the semiconductor material layer 160 . The semiconductor material layer 150 is filled in the second opening OP2, the semiconductor material layer 160, the metal silicide material layer 170 and the semiconductor material layer 180 are filled in the third opening OP3, and the metal silicide material layer 170 and the semiconductor material layer 160 are sequentially Surround 180. In some embodiments, the channel material layer 130 may have an elliptical profile with a longitudinal axis extending along the first direction D1. In other embodiments, the channel material layer 130 may also have a circular profile. In some embodiments, the second opening OP2 and the third opening OP3 may respectively have an elliptical profile and have a longitudinal axis extending along the first direction D1 or the second direction D2. In other embodiments, the second opening OP2 and the third opening OP3 may respectively have circular profiles.

Please refer to Figures 11A and 11B. A crystallization process is performed to form the vertical channel layer 132 , the quasi-single crystal semiconductor layers 152 , 162 , 182 and the metal silicide layers 172 , 174 . In some embodiments, the vertical channel layer 132 is monocrystalline silicon. In some embodiments, the single crystal-like semiconductor layers 152 , 162 , 182 are single crystal silicon-like. In some embodiments, the quasi-single-crystal semiconductor layer 152 , 162 , 182 is N-type quasi-single-crystal silicon doped with arsenic (As) or phosphorus (P). In some embodiments, the quasi-single crystal semiconductor layers 152 , 162 , 182 have a uniform doping concentration, and the doping concentration is greater than about 10 ¹⁸ /cm ³ . In some embodiments, metal suicide layer 172 includes top metal suicide layer 172T, inner metal suicide layer 172I, and bottom metal suicide layer 172B, and metal suicide layer 174 includes inner metal suicide layer 174I and bottom metal suicide layer 174I. layer 174B. In some embodiments, the metal silicide layers 172 , 174 are made of the same material as the metal silicide material layer 170 .

In this paper, single crystalline-like means that most of the solid phase in this material is single crystal, and includes a small part of non-crystallized and/or polycrystalline. For example, quasi-single crystals include more than 95 volume percent single crystals, as well as amorphous and/or polycrystalline. In this context, quasi-monocrystalline silicon means that most of the solid phase in this material is monocrystalline silicon, and includes a small part of amorphous silicon and/or polycrystalline silicon that has not been completely monocrystalline. In one embodiment, in monocrystalline silicon, part of the crystal lattice of the monocrystalline silicon solid conforms to the lattice definition of the monocrystalline silicon solid. In one embodiment, the intra-grain defect density or grain boundary defect density of quasi-mono-silicon may be between that of single-crystal silicon and poly-silicon. In one embodiment, the defect density of quasi-single-crystal silicon is closer to that of single-crystal silicon phase, and the electrical conductivity is closer to that of single-crystal silicon. The conductivity of monocrystalline silicon is higher than that of polycrystalline silicon. In addition, during operation, the cell current of monocrystalline silicon is higher than that of polycrystalline silicon.

In some embodiments, the above-mentioned crystallization process may be a metal-assisted solid-phase crystallization (Metal-Assisted Solid-Phase Crystallization, MASPC) process. In some embodiments, the crystallization process includes annealing at about 450-550 ^° C for about 1-4 hours. In some embodiments, the execution time of the crystallization process is longer than the execution time of the first annealing process. During the crystallization process, the metal silicide material layer 170 (such as NiSi) shown in FIGS. The semiconductor layers 152 , 162 , 182 (such as monocrystalline silicon) grow along with the movement of the metal silicide material layer 170 . Specifically, during the crystallization process, the metal silicide continues to extend to the region of amorphous silicon, and converts the amorphous silicon into quasi-single crystal silicon where it passes. In some embodiments, a part of the metal silicide material layer 170 moves toward the inner semiconductor material layer 180, finally forming the inner metal silicide layer 172I at the center of the quasi-single crystal semiconductor layer 182, and a part of the metal silicide material layer The layer 170 moves along its outer semiconductor material layer 160 and channel material layer 130, and finally forms an inner metal silicide layer 174I at the center of the quasi-single crystal semiconductor layer 152, as shown in FIG. 11B.

FIG. 11C and FIG. 11D are a cross-sectional view and a top view after performing a crystallization process according to another embodiment of the present invention. The difference between Figures 11C and 11D and the structures shown in Figures 11A and 11B is that the metal silicide layer 172 includes a top metal silicide layer 172T, an inner metal silicide layer 172I, an outer metal silicide layer 172S and The bottom metal silicide layer 172B, and the metal silicide layer 174 includes an outer metal silicide layer 174S and a bottom metal silicide layer 174B.

For example, during the crystallization process, a part of the metal silicide material layer 170 shown in FIGS. 10A-10B moves toward the semiconductor material layer 180 and forms an inner metal silicide layer 172I on the surface of the single crystal semiconductor layer 182. At the center, a portion of the metal silicide material layer 170 moves toward the semiconductor material layer 160 and forms an outer metal silicide layer 172S at the interface with the dielectric layer 140 . In addition, another part of the metal silicide material layer 170 moves along the channel material layer 130 to form an outer metal silicide layer 174S at the interface between the quasi-single crystal semiconductor layer 152 and the dielectric layer 140 , as shown in FIG. 11D .

FIG. 12A and FIG. 12B are subsequent processes after the crystallization process shown in FIG. 11A and FIG. 11B is completed. Please refer to Figure 12A and Figure 12B. A second annealing process is performed to form metal silicide layers 172', 174'. In some embodiments, the metal silicide layers 172', 174' comprise _CoSi2 , _NiSi2, or the like. As shown in FIG. 12A, the metal silicide layer 172' includes a top metal silicide layer 172T', an inner metal silicide layer 1721', and a bottom metal silicide layer 172B', and the metal silicide layer 174' includes an inner metal silicide layer layer 174I' and bottom metal suicide layer 174B'. In some embodiments, the second annealing process includes annealing at about 600-800° C. for about 150-120 seconds, such as about 30-60 seconds. For example, the second annealing process can transform the metal silicide NiSi into NiSi ₂ to reduce the resistance. In some embodiments, the temperature of the second annealing process is higher than the temperature of the crystallization process and the first annealing process. In some embodiments, the second annealing process can be omitted.

Please refer to Figure 13. A planarization process is performed to remove the metal silicide layer 172' and the quasi-single crystal semiconductor layers 162, 182 on the upper surface of the insulating layer 112. At this time, the quasi-single crystal semiconductor layers 162, 182 and the metal silicide layer 172' form a vertical source structure SR, and the quasi-single crystal semiconductor layer 152 and the metal silicide layer 174' form a vertical drain structure DR. In some embodiments, the planarization process includes etch back, chemical-mechanical planarization (CMP), or other suitable methods.

Please refer to Figure 14. A capping layer 190 is formed on the insulating layer 112 . In some embodiments, capping layer 190 includes an insulating material, such as an oxide. Capping layer 190 may be formed by any suitable deposition method.

Please refer to Figure 15A and Figure 15B. A plurality of conductive layers 210 are formed between adjacent first insulating layers 110 . Specifically, each of the plurality of second insulating layers 120 may be replaced with a conductive layer 210 . The conductive layer 210 may be a single-layer or multi-layer structure. In some embodiments, the conductive layer 210 includes titanium nitride (TiN) and tungsten (W). In some embodiments, the conductive layer 210 further includes a memory layer and a barrier layer (not shown). For example, the conductive layer 210 may be a multilayer of memory layer (such as SiN or HFO _x ), barrier layer (such as oxide or high-k oxide), titanium nitride, and tungsten. Each conductive layer 210 can be used as a word line (or gate).

As shown in FIG. 15A and FIG. 15B , the three-dimensional memory device 100 includes a substrate 101 , a stack structure 200 , a vertical source structure SR, a vertical drain structure DR, and a vertical channel layer 132 . The stack structure 200 is located above the substrate 101 and includes a plurality of conductive layers 210 and a plurality of first insulating layers 110 stacked alternately.

The vertical source structure SR and the vertical drain structure DR are buried in the stack structure 200 , and the dielectric layer 140 is located between the vertical source structure SR and the vertical drain structure DR. The vertical source structure SR and the vertical drain structure DR respectively include single crystal silicon and metal silicide. In some embodiments, the vertical source structure SR includes a bottom metal silicide layer 172B', an inner metal silicide layer 172I', and single crystal-like semiconductor layers 162, 182, wherein the inner metal silicide layer 172I' and the single crystal semiconductor The layers 162, 182 are located on the bottom silicide layer 172B', and the quasi-single crystal semiconductor layer 162, 182 surrounds the inner silicide layer 172I'. In some embodiments, the vertical drain structure DR includes a bottom metal silicide layer 174B', an inner metal silicide layer 174I' and a quasi-single crystal semiconductor layer 152, wherein the inner metal silicide layer 174I' and the quasi-single crystal semiconductor layer 152 It is located on the bottom metal silicide layer 174B′, and the quasi-single crystal semiconductor layer 152 surrounds the inner metal silicide layer 174I′. In other embodiments, the vertical source structure SR may further include an outer metal silicide layer 172S (shown in FIG. 11C ), and the vertical drain structure DR includes an outer metal silicide layer 174S (shown in FIG. 11C ). The inner metal silicide layer 174I is not included.

The vertical channel layer 132 surrounds and contacts the vertical source structure SR and the vertical drain structure DR. The vertical channel layer 132 has a circular profile, as shown in FIG. 15B. In some embodiments, the vertical channel layer 132 includes monocrystalline silicon. A current path can be created between the vertical source structure SR and the vertical drain structure DR through the vertical channel layer 132, as indicated by the arrows in FIG. 15B. The vertical channel layer 132 made of single crystal silicon can improve the cell current and uniformity, thereby increasing the operation speed of the multilayer memory cell, and obtaining the three-dimensional memory device 100 with excellent electrical properties.

Please refer to Figure 16. The three-dimensional memory device 100 further includes source lines SL and bit lines BL. The source line SL and the bit line BL are formed on the cover layer 190 , and are electrically connected to the vertical source structure SR and the vertical drain structure DR through the source line contact structure 310 and the bit line contact structure 320 respectively.

Please refer to Figure 17. FIG. 17 is a top view of a three-dimensional memory array according to some embodiments of the present invention. For clarity, the insulating layer 112 , the cover layer 190 , the source line contact structure 310 , the bit line contact structure 320 , the source line SL and the bit line BL are not shown in FIG. 17 . As shown in FIG. 17 , the slit structure 400 separates adjacent stack structures 200 . Each stack structure 200 may include a plurality of ring-shaped vertical channel layers 132 surrounding a corresponding vertical source structure SR and a corresponding vertical drain structure DR. The materials and forming methods of the vertical source structure SR and the vertical drain structure DR can refer to FIG. 1 to FIG. 15B , and will not be repeated here.

As mentioned above, according to an embodiment of the present disclosure, a three-dimensional memory device is provided, which has a vertical source structure, a vertical drain structure, and a vertical channel layer surrounding the vertical source structure and the vertical drain structure. The vertical source structure, the vertical drain structure and the vertical channel layer may include monocrystalline silicon. The vertical source structure and the vertical drain structure also contain metal silicide, which can reduce the resistance value. A horizontal current path can be created between the vertical source structure and the vertical drain structure. In addition, the vertical channels made of single crystal silicon can improve cell current and uniformity, thereby increasing the operating speed of multilayer memory cells, and obtaining three-dimensional memory elements with excellent electrical properties.

While this disclosure has described details in terms of certain implementations, other implementations are possible. Therefore, the spirit and scope of the appended claims should not be limited to the implementations described herein.

Those skilled in the art will also understand that various modifications and variations to the present disclosure are possible without departing from the spirit and scope of the present disclosure. In light of the foregoing, this disclosure is intended to cover various modifications and variations in this disclosure that may fall within the scope of the subsequent claims.

100: Three-dimensional memory components 101: Substrate 110: the first insulating layer 112: insulation layer 120: second insulating layer 130: channel material layer 132: vertical channel layer 140: dielectric layer 150, 160, 180: Layers of semiconductor material 152, 162, 182: quasi-single crystal semiconductor layer 170: metal silicide material layer 172, 172’, 174, 174’: metal silicide layer 172B, 172B’, 174B, 174B’: bottom metal silicide layer 172I, 172I’, 174I, 174I’: inner metal silicide layer 172S, 174S: External metal silicide layer 172T, 172T’: top metal silicide layer 190: Overlay 200: stacked structure 210: conductive layer 310: Source line contact structure 320: bit line contact structure 400: slit structure D1: the first direction D2: Second direction BL: bit line DR: vertical drain structure OP1: first opening OP2: second opening OP3: the third opening SL: source line SR: vertical source structure

Aspects of the present disclosure are best understood from the following Detailed Description when read with the illustrations. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 is a cross-sectional view of various steps in the manufacturing process of a three-dimensional memory device according to some embodiments of the present invention. FIG. 2 is a cross-sectional view of various steps in the manufacturing process of a three-dimensional memory device according to some embodiments of the present invention. FIG. 3 is a cross-sectional view of various steps in the manufacturing process of a three-dimensional memory device according to some embodiments of the present invention. FIG. 4 is a cross-sectional view of various steps in the manufacturing process of a three-dimensional memory device according to some embodiments of the present invention. FIG. 5 is a cross-sectional view of various steps in the manufacturing process of a three-dimensional memory device according to some embodiments of the present invention. FIG. 6 is a cross-sectional view of various steps in the manufacturing process of a three-dimensional memory device according to some embodiments of the present invention. FIG. 7 is a cross-sectional view of various steps in the manufacturing process of a three-dimensional memory device according to some embodiments of the present invention. FIG. 8 is a cross-sectional view of various steps in the manufacturing process of a three-dimensional memory device according to some embodiments of the present invention. FIG. 9 is a cross-sectional view of various steps in the manufacturing process of a three-dimensional memory device according to some embodiments of the present invention. FIG. 10A is a cross-sectional view of various steps in the manufacturing process of a three-dimensional memory device according to some embodiments of the present invention. FIG. 10B is a top view of various steps in the manufacturing process of a three-dimensional memory device according to some embodiments of the present invention. FIG. 11A is a cross-sectional view of various steps in the manufacturing process of a three-dimensional memory device according to some embodiments of the present invention. FIG. 11B is a top view of various steps in the manufacturing process of a three-dimensional memory device according to some embodiments of the present invention. FIG. 11C is a cross-sectional view of various steps in the manufacturing process of a three-dimensional memory device according to some embodiments of the present invention. FIG. 11D is a top view of various steps in the manufacturing process of a three-dimensional memory device according to some embodiments of the present invention. FIG. 12A is a cross-sectional view of various steps in the manufacturing process of a three-dimensional memory device according to some embodiments of the present invention. FIG. 12B is a top view of various steps in the manufacturing process of a three-dimensional memory device according to some embodiments of the present invention. FIG. 13 is a cross-sectional view of various steps in the manufacturing process of a three-dimensional memory device according to some embodiments of the present invention. FIG. 14 is a cross-sectional view of various steps in the manufacturing process of a three-dimensional memory device according to some embodiments of the present invention. FIG. 15A is a cross-sectional view of various steps in the manufacturing process of a three-dimensional memory device according to some embodiments of the present invention. FIG. 15B is a top view of various steps in the manufacturing process of a three-dimensional memory device according to some embodiments of the present invention. FIG. 16 is a cross-sectional view of a three-dimensional memory device according to some embodiments of the present invention. FIG. 17 is a top view of a three-dimensional memory array according to some embodiments of the present invention.

Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

100: Three-dimensional memory components

101: Substrate

110: the first insulating layer

112: insulation layer

132: vertical channel layer

140: dielectric layer

152,162,182:Single crystal semiconductor layer

172B', 174B': bottom metal silicide layer

172I’, 174I’: inner metal silicide layer

190: Overlay

200: stacked structure

210: conductive layer

Claims (10)

A three-dimensional memory element, comprising: a substrate; a stacked structure located above the substrate, wherein the stacked structure includes a plurality of conductive layers and a plurality of insulating layers stacked alternately; a vertical source structure and a vertical drain structure embedded in the stack structure, wherein the vertical source structure and the vertical drain structure respectively comprise a monocrystalline silicon and a metal silicide; and A vertical channel layer surrounds the vertical source structure and the vertical drain structure and contacts the vertical source structure and the vertical drain structure, wherein the vertical channel layer includes single crystal silicon. The three-dimensional memory device as described in claim 1, wherein the vertical source structure and the vertical drain structure respectively include a bottom metal silicide layer, an inner metal silicide layer and a single crystal silicon layer, wherein the inner metal silicide layer The silicide layer and the single crystal silicon layer are located on the bottom metal silicide layer, and the single crystal silicon layer surrounds the inner metal silicide layer. The three-dimensional memory device as claimed in claim 1, wherein the vertical source structure includes a bottom metal silicide layer, an outer metal silicide layer, an inner metal silicide layer, and the outer metal layer in the vertical source structure a single crystal silicon layer between the silicide layer and the inner metal silicide layer, the vertical drain structure includes a bottom metal silicide layer, an outer metal silicide layer, and the outer metal silicide layer on the vertical drain structure A single crystal silicon layer between the silicide layer and the vertical channel layer. The three-dimensional memory device as claimed in claim 1, wherein the single crystal silicon has a doping concentration greater than about 10 ¹⁸ /cm ³ . The three-dimensional memory device according to claim 1, further comprising a bit line connected to the vertical drain structure and a source line connected to the vertical source structure. A three-dimensional memory element, comprising: a substrate; A plurality of stacked structures located above the substrate, wherein each of the plurality of stacked structures includes a plurality of conductive layers and a plurality of insulating layers stacked alternately; A plurality of vertical source structures and a plurality of vertical drain structures embedded in the plurality of stacked structures, wherein the plurality of vertical source structures and the plurality of vertical drain structures respectively include a single crystal silicon and a metal silicide ; a plurality of annular channel layers, each surrounding the corresponding vertical source structure and the corresponding vertical drain structure, wherein the plurality of annular channel layers comprise single crystal silicon; and A plurality of slit structures are located between the plurality of stacked structures to separate the plurality of stacked structures. The three-dimensional memory device as claimed in claim 1, wherein the single crystal silicon has a doping concentration greater than about 10 ¹⁸ /cm ³ . The three-dimensional memory device according to claim 6, wherein each of the plurality of conductive layers includes a memory layer, a titanium nitride layer, and a tungsten layer. The three-dimensional memory device as claimed in claim 6, further comprising a dielectric layer located between the corresponding vertical source structure and the corresponding vertical drain structure. The three-dimensional memory device according to claim 6, wherein the metal silicide comprises CoSi, CoSi ₂ , NiSi or NiSi ₂ .

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