TWI803294B - Semiconductor device structure having a profile modifier - Google Patents

Abstract

The present disclosure provides a semiconductor device structure. The semiconductor device structure includes a first metallization line, a second metallization line, a first isolation feature, a second isolation feature, a profile modifier, and a contact feature. The first metallization line and the second metallization line extend along a first direction. The first isolation feature and the second isolation feature are disposed between the first metallization line and the second metallization line. The first metallization line, the second metallization line, the first isolation feature and the second isolation feature define an aperture. The profile modifier is disposed within the aperture to modify a profile of the aperture in a plan view. The contact feature is disposed within the aperture.

Description

Semiconductor device structure with contour modifiers

This application claims priority to US Patent Application Nos. 17/665,722 and 17/666,037 (ie, the priority date is "February 7, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor device structure, in particular to a semiconductor device structure with contour modifiers.

With the rapid development of the electronic industry, integrated circuits (IC) have achieved high performance and miniaturization. Due to advances in materials and design techniques, current integrated circuits are smaller and more complex than previous generations.

Contacts are used to make connections within or between different features in a semiconductor structure. For example, a contact is used to connect one conductive feature to another conductive feature. In some cases, contact material filled openings may have voids formed thereby adversely affecting the electrical connection between the conductive features. Therefore, a new semiconductor device structure and method are needed to improve this problem.

The above "prior art" description is only to provide background technology, and does not acknowledge that the above "prior art" description discloses the subject of this disclosure, and does not constitute the prior art of this disclosure, and any description of the above "prior art" shall not form part of this case.

One aspect of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a first metallization line, a second metallization line, a first isolation feature, a second isolation feature, an outline modifier and a contact feature. The first metallization line and the second metallization line extend along a first direction. The first isolation feature and the second isolation feature are disposed between the first metallization line and the second metallization line. The first metallization line, the second metallization line, the first isolation feature, and the second isolation feature define an aperture. The profile modifier is disposed in the aperture to modify the profile of the aperture in a plan view. The contact feature is disposed within the aperture.

Another aspect of the present disclosure provides another semiconductor device structure. The semiconductor device structure includes a first metallization line, a second metallization line, a first isolation feature, a second isolation feature, an outline modifier and a contact feature. The first metallization line and the second metallization line extend along a first direction. The first isolation feature and the second isolation feature are disposed between the first metallization line and the second metallization line. The first metallization line, the second metallization line, the first isolation feature, and the second isolation feature define an aperture. The profile modifier is disposed within the aperture. The profile modifier includes a plurality of segments separated from each other. Each segment is located at a corner of the aperture. The contact feature is disposed within the aperture.

Another aspect of the disclosure provides a method for fabricating a semiconductor device structure. The preparation method includes: providing a substrate; forming a first metallization line and a second metallization line on the substrate, wherein the first metallization line and the second metallization line extend along a first direction; A first isolation feature and a second isolation feature are formed between the first metallization line and the second metallization line, wherein the first metallization line, the second metallization line, the first isolation feature and the The second isolation feature defines an aperture; forms an outline modifier to modify the outline of the aperture in plan view; and forms a contact feature within the aperture.

Embodiments of the present disclosure illustrate a semiconductor device structure with contour modifiers. In some embodiments, a contour modifier may be used to round the aperture to accommodate the contact feature so that the contact feature has a partially circular, partially elliptical, or partially elliptical profile in plan view. When the conductive material is filled into the circular apertures to form the contact features, no or less voids may be formed therein, thereby improving the fabrication yield of the semiconductor device structure.

The technical features and advantages of the present disclosure have been broadly summarized above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the disclosure defined by the appended claims.

Embodiments, or examples, of the present disclosure illustrated in the drawings will now be described in specific language. It should be understood that no limitation of the scope of the present disclosure is intended herein. Any changes or modifications to the described embodiments, and any further applications of the principles described herein, are considered to be within the ordinary skill of the art to which this disclosure pertains. Reference numerals may be repeated throughout the embodiments, but this does not mean that features of one embodiment are applicable to another embodiment, even if they share the same reference numerals.

It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections should not be limited by these terms. Instead, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the inventive concept.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concepts. As used herein, the singular forms "a", "an" and "the" are intended to include the plural unless the context clearly dictates otherwise. It should be further understood that when the words "comprise" and "comprising" are used in this specification, they point out the existence of the stated features, integers, steps, operations, elements or elements, but do not exclude the existence or addition of one or more other features, An integer, step, operation, element, component, or group thereof.

FIG. 1 is a top view illustrating the layout of a semiconductor device structure 100 according to some embodiments of the present disclosure.

In some embodiments, the semiconductor device structure 100 may include active devices and/or passive devices. Active components may include a memory chip (for example, a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, etc.), a power management chip (for example, a power management integrated circuit (PMIC) chip), a logic chip (e.g., system chip (SoC), central processing unit (CPU), graphics processing unit (GPU), application processor (AP), microcontroller, etc.), a radio frequency (RF) chip, a A sensor chip, a microelectromechanical systems (MEMS) chip, a signal processing chip (eg, a digital signal processing (DSP) chip), a front-end chip (eg, an analog front-end (AFE) chip) or other active components. Passive components may include a capacitor, a resistor, an inductor, a fuse or other passive components.

In some embodiments, the semiconductor device structure 100 may include a plurality of metallization lines 120-1, 120-2, and 120-3, a plurality of metallization lines 130-1, 130-2, 130-3, and 130-4, A plurality of isolation features 140-1, 140-2, 140-3, and 140-4, a plurality of contour modifiers 150, and a plurality of contact features 160-1, 160-2, 160-3, 160-4, 160 -5 and 160-6.

In some embodiments, the metallization lines 120-1, 120-2 and 120-3 may extend along the X direction. The metallization lines 120-1, 120-2, and 120-3 may be parallel to each other along the Y direction. The metallization lines 120-1, 120-2, and 120-3 may be spaced apart from each other. In some embodiments, each of the metallization lines 120-1, 120-2, and 120-3 can be used as a bit line, which can be used to connect, but is not limited to, gate structures (eg, bit line gate poles) and contacts (for example, bit line contacts).

In some embodiments, the semiconductor device structure 100 may include a plurality of spacers 122-1, 122-2, 124-1, 124-2, 126-1 and 126-2. Each spacer 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2 may be disposed on a sidewall of a metallization line (eg, 120-1, 120-2, and 120-3) . For example, the spacers 122-1 and 122-2 may be disposed on two opposite sidewalls of the metallization line 120-1. The spacers 122-2 and 124-1 may face each other. Each of the spacers 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2 may extend along the X direction. Each of the spacers 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2 may be parallel to each other along the Y direction. Each of the spacers 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2 may be spaced apart from each other. Each spacer 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2 can be used to connect metallization lines to contact features (eg, 160-1, 160-2, 160 -3, 160-4, 160-5 and 160-6) isolation.

In some embodiments, the metallization lines 130-1, 130-2, 130-3, and 130-4 may extend along the Y direction. The metallization lines 130-1, 130-2, 130-3, and 130-4 may be parallel to each other along the X direction. The metallization lines 130-1, 130-2, 130-3, and 130-4 may be spaced apart from each other. In some embodiments, each of the metallization lines 130-1, 130-2, 130-3, and 130-4 can be used as a word line, which can be used to connect, but is not limited to, gate structures (eg, word line gate) and contacts (eg, word line contacts).

In some embodiments, the isolation features 140-1, 140-2, 140-3, and 140-4 may be disposed on contact features (eg, 160-1, 160-2, 160-3, 160-4, 160-5 Or 160-6) on two opposite sides. In some embodiments, each isolation feature 140-1, 140-2, 140-3, and 140-4 may be located between two metallization lines in plan view. For example, isolation features 140-1 and 140-2 may be located between metallization lines 120-1 and 120-2.

In some embodiments, each of isolation features 140-1, 140-2, 140-3, and 140-4 may have a partially circular, partially elliptical, or partially elliptical profile in plan view. For example, two sidewalls of the isolation feature 140-1, extending from the metallization line 120-1 to the metallization line 120-2 (or extending from the spacer 122-2 to the spacer 124-1), may have a Arc shape. Each of the aforementioned side walls may have a raised surface in plan view.

In some embodiments, each of isolation features 140-1, 140-2, 140-3, and 140-4 can be aligned with metallization lines (eg, 130-1, 130-2, 130-3, and 130-4). Although not shown, it should be noted that a contact feature (eg, a wordline contact) may penetrate one of the isolation features 140-1, 140-2, 140-3, and 140-4 and may communicate with the corresponding Metallization lines 130-1, 130-2, 130-3 or 130-4 are electrically connected. In some embodiments, each isolation feature 140-1, 140-2, 140-3, and 140-4 may be in contact with a sidewall of a spacer of a metallization line. For example, isolation feature 140-1 may make contact with spacers 122-2 and 124-1.

In some embodiments, metallization lines (eg, 120-1, 120-2, and 120-3) and isolation features (eg, 140-1, 140-2, 140-3, and 140-4) may define an aperture (eg, R1). In some embodiments, spacers (such as 122-1, 122-2, 124-1, 124-2, 126-1, and 126- 2) The isolation features (such as 140-1, 140-2, 140-3 and 140-4) can define an aperture. For example, spacer 122-2 of metallization line 120-1, spacer 124-1 of metallization line 120-2, and isolation features 140-1 and 140-2 may define an aperture R1. In some embodiments, the two edges defined by the two sidewalls of the isolation features (eg, 140-1 and 140-2) may project toward each other in plan view.

In some embodiments, contour modifier 150 may be located within aperture R1. In some embodiments, contour modifiers 150 may be located at corners of aperture R1. In some embodiments, the profile of aperture R1 may be modified using a profile modifier 150 . In some embodiments, profile modifier 150 may be used to round the profile of aperture R1. In some embodiments, profile modifier 150 may be utilized to define aperture R2 (or a circular aperture) having a partially circular, partially elliptical, or partially elliptical profile. In some embodiments, aperture R2 may be defined by spacers (eg, 122 - 1 , 122 - 2 , 124 - 1 , 124 - 2 , 126 - 1 , and 126 - 2 ) of metallization lines and profile modifier 150 . In some embodiments, the contour modifier 150 may overlap the metallization lines (eg, 130-1 , 130-2, 130-3, and 130-4) along the Z direction.

In some embodiments, the contact features 160-1, 160-2, 160-3, 160-4, 160-5, and 160-6 (or cell contacts) may be aligned along the X direction. In some embodiments, each of the contact features 160-1, 160-2, 160-3, 160-4, 160-5, and 160-6 may be located between two metallization lines in plan view. For example, contact feature 160-1 may be located between metallization lines 120-1 and 120-2. In some embodiments, the contact features (eg, 160-1 and 160-2) can be separated from each other by isolation features (eg, 140-1). In some embodiments, each of contact features 160-1, 160-2, 160-3, 160-4, 160-5, and 160-6 may have a partial circle, partial ellipse, or partial ellipse in plan view shape outline. In some embodiments, each contact feature (160-1, 160-2, 160-3, 160-4, 160-5, and 160-6) may be associated with a spacer (eg, 122-1, 122-2, 124-1, 124-2, 126-1 and 126-2) are in contact with the sidewalls. In some embodiments, each contact feature ( 160 - 1 , 160 - 2 , 160 - 3 , 160 - 4 , 160 - 5 , and 160 - 6 ) may make contact with a sidewall of outline modifier 150 . In some embodiments, each contact feature (160-1, 160-2, 160-3, 160-4, 160-5, and 160-6) may be located within aperture R1 or R2. In some embodiments, the outline of each contact feature ( 160 - 1 , 160 - 2 , 160 - 3 , 160 - 4 , 160 - 5 , and 160 - 6 ) may be modified or defined by an outline modifier 150 .

FIG. 2 is a partial enlarged view illustrating some embodiments of the present disclosure, such as the region G of the semiconductor device structure 100 shown in FIG. 1 .

As shown in FIG. 2, the metallization line 120-1 may have a sidewall 120s1 on which a spacer 122-2 is disposed. The metallization line 120-2 may have sidewalls 120s2 on which the spacers 124-1 are disposed.

Isolation feature 140-1 has sidewall 140s1 that faces sidewall 140-2 of isolation feature 140-2. In some embodiments, the sidewalls 140s1 and 140s2 may protrude or protrude toward each other. In some embodiments, outline modifier 150 may include segments 152-1, 152-2, 152-3, and 152-4. In some embodiments, segments 152-1, 152-2, 152-3, and 152-4 may be separated from one another. In some embodiments, segments 152-1, 152-2, 152-3, and 152-4 may be located within aperture R1. In some embodiments, segments 152-1, 152-2, 152-3, and 152-4 may be located at corners (eg, E1) of aperture R1. For example, segment 152-1 may be located at a corner (eg, E1) defined by sidewall 122s1 of spacer 122-2 of metallization line 120-1 and sidewall 140s1 of isolation feature 140-1. In some embodiments, each of segments 152-1, 152-2, 152-3, and 152-4 may have slave gaps (eg, 122-1, 122-2, 124-1, 124-2, 126-1 and 126-2) extend sidewalls from sidewalls of isolation features such as 140-1, 140-2, 140-3, and 140-4. For example, segment 152-1 may have sidewall 152s1 extending from sidewall 122s1 of spacer 122-2 to sidewall 140s1 of isolation feature 140-1.

In some embodiments, segments 152-1, 152-2, 152-3, and 152-4 may taper along the Y direction. For example, segment 152-1 tapers in the negative Y direction, while segment 152-3 tapers in the positive Y direction. In some embodiments, each of segments 152-1, 152-2, 152-3, and 152-4 may taper progressively toward a corner (eg, E1) of aperture R1. In some embodiments, the sidewalls of the outline modifier 150 may be recessed relative to the contact features (eg, 160-1 , 160-2, 160-3, 160-4, 160-5, and 160-6). For example, sidewall 152s1 is recessed relative to the sidewall of contact feature 160-2.

In some embodiments, each segment (eg, 152-1) may have a width W1 along the X direction at the sidewall 122s1 of the spacer 122-2, and a width W1 along the X direction between the spacers 122-2 and 124-1. Width W2. Width W1 is greater than width W2. In some embodiments, a portion of the sidewall (eg, 122 s1 ) of the spacer 122 - 2 is exposed from the contour modifier 150 .

In some embodiments, a contact feature (eg, 160 - 2 ) may be surrounded by segments 152 - 1 , 152 - 2 , 152 - 3 , and 152 - 4 of outline modifier 150 .

In some embodiments, sidewalls of isolation features (eg, 140 - 1 , 140 - 2 , 140 - 3 , and 140 - 4 ) may protrude relative to outline modifier 150 . For example, sidewall 140s1 of isolation feature 140-1 may protrude relative to segment 152-1 or 152-3.

In some embodiments, the aperture R1 may have a width W3 along the X direction at the sidewall 122s2 of the spacer 124-1 (or the sidewall 122s1 of the spacer 122-2), between the spacers 122-2 and 122-3 along the The X direction has a width W4. Width W3 is greater than width W4.

3A , 3B and 3C are cross-sectional views, respectively illustrating the semiconductor device structure 100 along lines AA', BB' and CC' of some embodiments of the present disclosure, as shown in FIG. 1 .

As shown in FIG. 3A , the semiconductor device structure 100 may include a substrate 110 . Substrate 110 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The substrate 110 may include an elemental semiconductor, including silicon or germanium in single crystal form, polycrystalline form, or amorphous (amorphous) form; a compound semiconductor material, including silicon carbide, gallium arsenide, gallium phosphide, phosphide At least one of indium, indium arsenide, and indium antimonide; an alloy semiconductor material including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and GaInAsP; any other suitable material; or a combination thereof. In some embodiments, the alloyed semiconductor substrate may include a SiGe alloy having a graded Ge feature, wherein the composition of Si to Ge changes from a ratio at one location of the graded SiGe feature to another location. In another embodiment, a SiGe alloy is formed on a silicon substrate. In some embodiments, the SiGe alloy may be mechanically strained by another material in contact with the SiGe alloy. In some embodiments, the substrate 110 may have a multilayer structure, or the substrate 110 may include a multilayer compound semiconductor structure. In some embodiments, p-type and/or n-type dopants may be doped in the substrate 110 . In some embodiments, the p-type dopant includes boron (B), other Group III elements, or any combination thereof. In some embodiments, the n-type dopant includes arsenic (As), phosphorus (P), other group V elements, or any combination thereof.

Although not shown in FIG. 3A , it should be noted that the substrate 110 may include an isolation structure disposed therein. The isolation structure may include shallow trench isolation (STI), field oxide (FOX), area oxide on silicon (LOCOS) features, and/or other suitable isolation elements. The isolation structure may include dielectric materials such as silicon oxide, silicon nitride, silicon oxy-nitride, fluorine-doped silicate (FSG), low-k (dielectric constant) dielectric materials, combinations thereof, and/or or other suitable material. In some embodiments, the contact features 160 - 2 and 160 - 5 may be in contact with the silicon substrate (or active region) and the isolation structure of the substrate 110 at the same time.

Metallization line 120 - 2 may be disposed on or over substrate 110 and may be spaced apart from substrate 110 by a gate structure (eg, 170 ). The metallization line 120 - 2 may include a conductive material such as tungsten copper, aluminum, tantalum, tantalum nitride (TaN), titanium, titanium nitride (TiN), etc., and/or combinations thereof.

The semiconductor device structure 100 may include a gate structure 170 . The gate structure 170 may be disposed on the substrate 110 . The gate structure 170 may be disposed between the metallization line (eg, 120 - 2 ) and the substrate 110 . In some embodiments, a portion of the gate structure 170 may be located at a lower elevation than the upper surface of the substrate 110 . The gate structure 170 may include a gate dielectric layer and a gate electrode layer.

In some embodiments, the gate dielectric layer may include silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), or a combination thereof. In some embodiments, the gate dielectric layer may include a dielectric material, such as a high-K dielectric material. A high-K dielectric material may have a dielectric constant (k value) greater than 4. High-K dielectric materials may include hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), or other suitable materials. Other suitable materials are also contemplated for the present disclosure.

In some embodiments, the gate electrode layer may include a polysilicon layer. In some embodiments, the fabrication technology of the gate electrode layer may be a conductive material such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta) or other suitable materials. In some embodiments, the gate electrode layer may include a work function layer. The fabrication technology of the work function layer is a metal material, and the metal material may include a metal with N-work function or a metal with P-work function. N-work function metals include tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC ), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr) or combinations thereof. P-work function metals include titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru), or combinations thereof. Other suitable materials are also contemplated for the present disclosure. The gate electrode layer can be formed by low pressure chemical vapor deposition (LPCVD) and plasma enhanced CVD (PECVD).

A dielectric layer 182 may be disposed between the metallization line (eg, 120 - 1 or 120 - 3 ) and the substrate 110 . The dielectric layer 182 may include a dielectric material. For example, the dielectric layer 182 may include SiN, SiO2, silicon oxynitride (SiON), silicon carbide nitride (SiCN), silicon carbide (SiC), aluminum oxide (Al2O3), hafnium oxide (HfO2), or lanthanum oxide (La2O3) .

In some embodiments, the semiconductor device structure 100 may include a dielectric layer 184 . A dielectric layer 184 may be disposed on or over a metallization line (eg, 120-1, 120-2, or 120-3). The dielectric layer 184 may include a dielectric material. For example, the dielectric layer 184 may include SiN, SiO2, silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbide (SiC), aluminum oxide (Al2O3), hafnium oxide (HfO2) or lanthanum oxide (La2O3) .

Spacers (eg, 122 - 1 ) may be formed on the dielectric layer 182 , the metallization line 120 - 1 and the sidewalls of the dielectric layer 184 . Spacers (eg, 124 - 1 ) may be formed on the dielectric layer 184 , the metallization line 120 - 2 and the sidewalls of the gate structure 170 . In some embodiments, a portion of the spacer (eg, 124 - 1 ) may be lower than the upper surface of the substrate 110 . In some embodiments, spacers (eg, 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2) may include multiple layers. In some embodiments, the spacers (such as 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2) may include silicon oxide (SiOx), silicon nitride (SixNy), nitrogen Silicon oxide (SiON), or a combination thereof. In some embodiments, the spacers (eg, 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2) may include an air gap. For example, an air gap can be sandwiched between two silicon nitride layers.

Contact features (eg, 160 - 2 or 160 - 5 ) may be disposed on substrate 110 . In some embodiments, a portion of the contact feature (eg, 160 - 2 or 160 - 5 ) may be lower than the upper surface of the substrate 110 . In some embodiments, a contact feature (eg, 160-2 or 160-5) may make contact with a spacer of a metallization line. For example, contact feature 160-2 may be in contact with spacer 122-2 of metallization line 120-1 and spacer 124-1 of metallization line 120-2.

In some embodiments, the contact feature (eg, 160-2 or 160-5) can include a barrier layer (not shown) and a conductive layer (not shown) on the barrier layer. The barrier layer may include titanium, tantalum, titanium nitride, tantalum nitride, manganese nitride, or combinations thereof. The conductive layer may comprise metals such as tungsten (W), copper (Cu), Ru, Ir, Ni, Os, Rh, Al, Mo, Co, alloys thereof, combinations thereof, or any metallic material with suitable electrical resistance and gap filling capabilities . In some embodiments, the contact feature (eg, 160-2 or 160-5) can include a polysilicon layer.

Although not shown in FIG. 3A, it should be noted that another contact feature (e.g., a bitline contact) may penetrate dielectric layer 184 to electrically connect to metallization line 120-2, so that metallization line 120 -2 A power supply can be applied through the bit line contacts.

As shown in FIG. 3B , contour modifiers 150 may be disposed on substrate 110 between the spacers and the contact features. For example, segment 152-1 of outline modifier 150 may be located between spacer 122-2 and contact feature 160-2. That is, a portion of contact feature 160 - 2 may be spaced apart from spacer 122 - 2 by segment 152 - 1 of outline modifier 150 .

In some embodiments, the contour modifier 150 may include silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), or a combination thereof. In some embodiments, the material of the contour modifier 150 may be the same or similar to that of the outermost layer of the spacer. In some embodiments, a portion of the contact feature (eg, 160-2) may make contact with a sidewall (eg, 152s1) of the spacer (eg, 152-1).

As shown in FIG. 3C , the metallization line (eg, 130 - 2 ) may be separated from the gate structure 170 by a dielectric layer 186 . The metallization line 130 - 2 may include a conductive material such as tungsten copper, aluminum, tantalum, tantalum nitride (TaN), titanium, titanium nitride (TiN), etc., and/or combinations thereof. In some embodiments, the metallization lines (eg, 130 - 2 ) may be located lower than the upper surface of the substrate 110 .

The dielectric layer 186 may include silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), or a combination thereof.

An isolation feature (eg, 140-1) may be located between metallization lines (eg, 120-1 and 120-2). An isolation feature (eg, 140-1 ) may make contact with a sidewall (eg, 122s1 ) of a spacer (eg, 122-2 ). In some embodiments, as shown in FIGS. 3A and 3C , the elevation of the upper surface of the substrate 110 in contact with the isolation feature 140 - 1 may be higher than the elevation of the contact feature 160 - 2 .

In some embodiments, each of segments 152-1, 152-2, 152-3, and 152-4 of profile modifier 150 may be utilized to define aperture R2, which may have a partial circle, in plan view, Partial ellipse or part ellipse profile. When a conductive material is filled into the circular hole R2 to form a contact feature, no or less voids may be formed therein, thereby improving the manufacturing yield of the semiconductor device structure 100 . In a comparative example, conductive material is filled into an opening having a profile similar to aperture R1. As a result, voids may be created at the corners of the openings that negatively affect the electrical connection.

FIG. 4 is a schematic diagram illustrating a method 300 for fabricating a semiconductor device structure according to some embodiments of the present disclosure.

Fabrication method 300 begins at operation 310, where a substrate is provided. A plurality of first metallization lines (eg, word lines) can be formed in the substrate and extend along a first direction. A plurality of second metallization lines (eg, bit lines) may be formed on the substrate and extend along a second direction orthogonal to the first direction. A plurality of spacers may be formed on sidewalls of the second metallization line and extend along the second direction. A plurality of dielectric layers may be formed on the substrate between the spacers of the second metallization line.

The fabrication method 300 continues with operation 320, wherein an etching process is performed to remove a first portion of the dielectric layer. Therefore, a plurality of openings of the dielectric layer can be formed. Each opening of the dielectric layer has a partially circular, partially elliptical or partially elliptical profile. Each opening of the dielectric layer may overlap the first metallization line along a third direction orthogonal to the first direction and the second direction.

Fabrication method 300 continues with operation 330, where a plurality of isolation features may be formed to fill the openings in the dielectric layer. Each isolation feature has a partially circular, partially elliptical, or partially elliptical profile. Each isolation feature may overlap the first metallization line along a third direction that is orthogonal to the first direction and the second direction.

Fabrication method 300 continues with operation 340, wherein an etching process may be performed on a second portion of the dielectric layer. Therefore, a plurality of apertures are formed, and the upper surface of the substrate is exposed. Each aperture is defined by a second metallization line (or a spacer of the second metallization line) and an isolation feature, having a partially circular, partially elliptical, or partially elliptical profile. Each aperture may have corners defined by sidewalls of the isolation features and sidewalls of the spacers. Each corner of the aperture may taper toward the interface of the isolation feature and the spacer.

Fabrication method 300 continues with operation 350 where a profile modifying material may be formed to cover the top surface of the substrate, the sidewalls of the second metallization line (or the sidewalls of the spacers), and the sidewalls of the isolation features. The contour modifying material may be conformally disposed on the upper surface of the substrate, the sidewalls of the spacers, and the sidewalls of the isolation features. Contour modifiers can occupy the corners of holes.

Fabrication method 300 continues with operation 360, where an etching process may be performed to remove a portion of the profile modifying material, thereby exposing the upper surface of the substrate. The remaining profile modifying material forms a profile modifier to modify the profile of the aperture. Each profile modifier can have a plurality of segments located at corners defined by sidewalls of the second metallization line (or sidewalls of the spacers) and sidewalls of the isolation feature. Each segment of the profile modifier may extend from the sidewall of the second metallization line (or the sidewall of the spacer) to the sidewall of the isolation feature. Thus, apertures (or modified apertures) defined by spacers, profile modifiers, and/or isolation features may be circular, and may have a partially circular, partially elliptical, or partially elliptical profile.

Fabrication method 300 continues with operation 370 where a conductive material may be deposited to fill the circular aperture. Thus, a plurality of contact features can be formed within the circular aperture. Each contact feature may have a partially circular, partially elliptical, or partially elliptical profile.

The preparation method 300 is merely an example, and is not intended to limit the present disclosure beyond what is expressly mentioned in the claims. Additional operations may be provided before, during, or after each operation of manufacturing method 300, and some of the operations described may be replaced, eliminated, or moved for use in other embodiments of the method. In some embodiments, preparation method 300 may also include operations not depicted in FIG. 4 . In some embodiments, preparation method 300 may include one or more of the operations described in FIG. 4 .

Figure 5, Figure 5A, Figure 5B, Figure 5C, Figure 6, Figure 6A, Figure 6B, Figure 6C, Figure 7, Figure 7A, Figure 7B, Figure 7C, Figure 8, Figure 8A, Figure 8B, Figure 8C, Figure 9 , FIG. 9A, FIG. 9B, FIG. 9C, FIG. 10, FIG. 10A, FIG. 10B, FIG. 10C, FIG. 11, FIG. 11A, FIG. 11B and FIG. 11C illustrate various stages of the preparation of semiconductor device structure 100. Fig. 5A, Fig. 6A, Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A and Fig. 11A are respectively along the line AA' of Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10 and Fig. 11 Sectional view. Fig. 5B, Fig. 6B, Fig. 7B, Fig. 8B, Fig. 9B, Fig. 10B and Fig. 11B are respectively along Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10 and BB' line of Fig. 11 Sectional view. Fig. 5C, Fig. 6C, Fig. 7C, Fig. 8C, Fig. 9C, Fig. 10C and Fig. 11C are respectively along the line CC' of Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10 and Fig. 11 Sectional view.

Referring to FIGS. 5 , 5A, 5B, and 5C, a substrate 110 may be provided. A plurality of metallization lines 130-1, 130-2, 130-3, and 130-4 (eg, word lines) may be formed in the substrate 110 and extend along the Y direction. A gate structure 170 (eg, a bit gate) may be formed on the substrate 110 . A plurality of metallization lines 120-1, 120-2, and 120-3 (eg, bit lines) may be formed on the substrate 110 and extend along the X direction. Metallization lines 120 - 1 , 120 - 2 and 120 - 3 may be formed on respective gate structures 170 . A plurality of spacers 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2 may be formed on sidewalls of respective metallization lines (eg, 120-1, 120-2, and 120-3). superior. The spacers 122-1, 122-2, 124-1, 124-2, 126-1 and 126-2 may cover the sidewalls of the gate structure 170 and the metallization lines 120-1, 120-2 and 120-3. A dielectric layer 182 may be formed between the substrate 110 and the metallization line (eg, 120-1). Dielectric layer 184 may be formed on or over metallization lines (eg, 120-1, 120-2, and 120-3). A plurality of dielectric layers 188 may be formed on the substrate 110 . A dielectric layer 188 may be located between a respective pair of spacers 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2. The dielectric layer may include SiN, SiO2, silicon oxynitride (SiON), silicon carbide nitride (SiCN), silicon carbide (SiC), aluminum oxide (Al2O3), hafnium oxide (HfO2), or lanthanum oxide (La2O3). In some embodiments, the dielectric layer 188 may include silicon oxide. In some embodiments, each of the spacers 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2 may have a multilayer structure including silicon nitride, silicon oxide, or other suitable s material. In some embodiments, the fabrication technology of the outermost layer of the spacers 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2 is silicon nitride.

Referring to FIG. 6 , FIG. 6A , FIG. 6B and FIG. 6C , an etching process is performed. A portion of dielectric layer 188 is removed. Portions of dielectric layer 188 over metallization lines 130-1, 130-2, 130-3, and 130-4 may be removed. Therefore, a plurality of openings 188o may be formed. The upper surface of the substrate 110 may be exposed from the dielectric layer 180 . Each opening 188o of the dielectric layer 188 may have a partially circular, partially elliptical, or partially elliptical profile. The etching process may include wet etching, or dry etching.

Referring to FIG. 7 , FIG. 7A , FIG. 7B and FIG. 7C , a plurality of isolation features 140 - 1 , 140 - 2 , 140 - 3 and 140 - 4 may be formed to fill the opening 188 o of the dielectric layer 188 . Each isolation feature 140-1, 140-2, 140-3, and 140-4 has a partially circular, partially elliptical, or partially elliptical profile. Each isolation feature 140-1, 140-2, 140-3, and 140-4 may overlap a respective metallization line 130-1, 130-2, 130-3, or 130-4 along the Z direction. The isolation features 140-1, 140-2, 140-3, and 140-4 can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low pressure chemical vapor deposition (LPCVD) ) or other suitable process formation.

Referring to FIG. 8 , FIG. 8A , FIG. 8B and FIG. 8C , an etching process may be performed. The remaining dielectric layer 188 may be removed. Therefore, a plurality of apertures R1 are formed. Each aperture R1 consists of metallization lines (eg, 120-1, 120-2, and 120-3) (or spacers of metallization lines) and isolation features (eg, 140-1, 140-2, 140-3, and 140- 4) Definition. Each aperture R1 may have a corner formed by the sidewalls of the isolation features 140-1, 140-2, 140-3, and 140-4 and the spacers 122-1, 122-2, 124-1, 124-2, 126- 1 and 126-2 for sidewall definition. Each corner of aperture R1 can provide spacers (eg, 122-1, 122-2, 124-1, 124-2, 126-1 and 126-2) the interface gradually becomes thinner. The etching process may include wet etching, or dry etching.

Referring to FIG. 9, FIG. 9A, FIG. 9B and FIG. 9C, the contour modification material 150' can be formed to cover the upper surface of the substrate 110, the sidewalls of the spacers (such as 122-1, 122-2, 124-1, 124-2, 126-1 and 126-2) and the sidewalls of the isolation features (eg, 140-1, 140-2, 140-3 and 140-4). The contour modifying material 150' can be conformally disposed on the upper surface of the substrate 110, the sidewalls of the spacers (eg, 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2), and the isolation On the sidewalls of features such as 140-1, 140-2, 140-3, and 140-4. Contour-modifying material 150' may occupy the corners of aperture R1. In some embodiments, the contour modification material 150' can be formed by ALD process or other suitable processes.

Referring to FIG. 10 , FIG. 10A , FIG. 10B and FIG. 10C , an etching process may be performed to remove part of the contour modification material 150 ′. In some embodiments, the etching process may include, for example, a dry etching process.

The remaining contour modifying material 150' forms contour modifier 150 to modify the contour of aperture R1. Therefore, a circular aperture R2 can be formed. Each outline modifier 150 may have a plurality of segments 152-1, 152-2, 152-3, and 152-4, located at gaps (eg, 122-1, 122-2, 124-1, 124-2, 126 -1 and 126-2) and the corners of the sidewalls of the isolation features (eg, 140-1, 140-2, 140-3, and 140-4). Each segment 152-1, 152-2, 152-3, and 152-4 of the contour modifier 150 can be formed from a sidewall of the spacer (eg, 122-1, 122-2, 124-1, 124-2, 126- 1 and 126-2) extend to the sidewalls of the isolation features (eg, 140-1, 140-2, 140-3, and 140-4). Thus, spacers (such as 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2), contour modifiers 150, and/or isolation features (such as 140-1, 140-2 , 140-3 and 140-4) The circular aperture R2 defined may have a partially circular, partially elliptical or partially elliptical profile.

In some embodiments, a portion of the substrate 110 may be removed such that the upper surface of the substrate 110 may be recessed.

Referring to FIG. 11 , FIG. 11A , FIG. 11B and FIG. 11C , a conductive material may be deposited to fill the circular aperture R2 , thus forming the semiconductor device structure 100 . Accordingly, a plurality of contact features 160-1, 160-2, 160-3, 160-4, 160-5, and 160-6 may be formed. Each contact feature 160-1, 160-2, 160-3, 160-4, 160-5, and 160-6 may have a partially circular, partially elliptical, or partially elliptical profile.

When the conductive material is filled into the circular aperture R2, between the isolation features (such as 140-1, 140-2, 140-3 and 140-4) and spacers (such as 122-1, 122-2, 124-1, 124 - 2 , 126 - 1 and 126 - 2 ) have no or less voids formed on the corners of the sidewalls, so that the yield of the semiconductor device structure 100 can be improved. In a comparative example, no contour modifiers are formed. As a result, voids in the contact features may occur at the corners of the isolation features and spacers, adversely affecting the electrical connection.

One aspect of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a first metallization line, a second metallization line, a first isolation feature, a second isolation feature, an outline modifier and a contact feature. The first metallization line and the second metallization line extend along a first direction. The first isolation feature and the second isolation feature are disposed between the first metallization line and the second metallization line. The first metallization line, the second metallization line, the first isolation feature, and the second isolation feature define an aperture. The profile modifier is set in the aperture to modify the profile of the aperture in a plan view. The contact feature is disposed within the aperture.

Another aspect of the present disclosure provides another semiconductor device structure. The semiconductor device structure includes a first metallization line, a second metallization line, a first isolation feature, a second isolation feature, an outline modifier and a contact feature. The first metallization line and the second metallization line extend along a first direction. The first isolation feature and the second isolation feature are disposed between the first metallization line and the second metallization line. The first metallization line, the second metallization line, the first isolation feature, and the second isolation feature define an aperture. The profile modifier is disposed within the aperture. The profile modifier includes a plurality of segments separated from each other. Each segment is located at a corner of the aperture. The contact feature is disposed within the aperture.

Another aspect of the disclosure provides a method for fabricating a semiconductor device structure. The preparation method includes: providing a substrate; forming a first metallization line and a second metallization line on the substrate, wherein the first metallization line and the second metallization line extend along a first direction; A first isolation feature and a second isolation feature are formed between the first metallization line and the second metallization line, wherein the first metallization line, the second metallization line, the first isolation feature and the The second isolation feature defines an aperture; forms an outline modifier to modify the outline of the aperture in plan view; and forms a contact feature within the aperture.

Embodiments of the present disclosure illustrate a semiconductor device structure with contour modifiers. In some embodiments, a contour modifier may be used to round the aperture to accommodate the contact feature so that the contact feature has a partially circular, partially elliptical, or partially elliptical profile in plan view. When the conductive material is filled into the circular apertures to form the contact features, no or less voids may be formed therein, thereby improving the fabrication yield of the semiconductor device structure.

Although the present disclosure and its advantages have been described in detail, it should be understood that other changes, substitutions and substitutions can be made hereto without departing from the spirit and scope of the present disclosure as defined by the disclosed claims. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of the disclosure is not limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that they can use existing or future developed processes, machinery, manufacturing, A composition of matter, means, method, or step. Accordingly, such processes, machinery, manufacture, material composition, means, methods, or steps are included in the scope of the patent disclosure of this disclosure.

100:Semiconductor Component Structure 110: base 120-1: Metallized wire 120-2: Metallized wire 120-3: Metallized wire 120s1: side wall 120s2: side wall 122-1: spacer 122-2: spacer 122s1: side wall 124-1: spacer 124-2: spacer 126-1: spacer 126-2: spacer 130-1: Metallized wire 130-2: Metallized wire 130-3: Metallized wire 130-4: Metallized wire 140-1: Isolation Features 140-2: Isolation Features 140-3: Isolation Features 140-4: Isolation Features 140s1: side wall 140s2: side wall 150:Contour Modifier 150': Contouring material 152-1: Segmentation 152-2: Segmentation 152-3: Segmentation 152-4: Segmentation 152s1: side wall 160-1: Contact Features 160-2: Contact Features 160-3: Contact Features 160-4: Contact Features 160-5: Contact Features 160-6: Contact Features 170:Gate structure 182: dielectric layer 184: dielectric layer 186: dielectric layer 188: dielectric layer 188o: opening 300: Preparation method 310: Operation 320: operation 330: Operation 340: Operation 350: Operation 360: operation 370: Operation A-A': line B-B': line C-C': line E1: Corner G: area R1: aperture R2: Aperture W1: width W2: width W3: width W4: width W5: width X: direction Y: Direction Z: Direction

The disclosure content of the present application can be understood more comprehensively when referring to the embodiments and the patent scope of the application for combined consideration of the drawings, and the same reference numerals in the drawings refer to the same components. FIG. 1 is a top view illustrating the layout of a semiconductor device structure according to some embodiments of the present disclosure. FIG. 2 is a partially enlarged view illustrating a region G of the semiconductor device structure shown in FIG. 1 in some embodiments of the present disclosure. FIG. 3A is a cross-sectional view illustrating the structure of a semiconductor device along line AA' in FIG. 1 according to some embodiments of the present disclosure. FIG. 3B is a cross-sectional view illustrating the semiconductor device structure along line BB' in FIG. 1 according to some embodiments of the present disclosure. FIG. 3C is a cross-sectional view illustrating the semiconductor device structure along line CC' in FIG. 1 according to some embodiments of the present disclosure. FIG. 4 is a schematic diagram illustrating a method for fabricating a semiconductor device structure according to some embodiments of the present disclosure. 5, 5A, 5B, and 5C illustrate one or more stages of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. 6, 6A, 6B, and 6C illustrate one or more stages of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. 7, 7A, 7B, and 7C illustrate one or more stages of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. 8, 8A, 8B, and 8C illustrate one or more stages of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. 9 , 9A, 9B, and 9C illustrate one or more stages of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. FIGS. 10 , 10A, 10B, and 10C illustrate one or more stages of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. 11 , 11A, 11B, and 11C illustrate one or more stages of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

100:Semiconductor Component Structure

120-1: Metallized wire

120-2: Metallized wire

120-3: Metallized wire

122-1: spacer

122-2: spacer

124-1: spacer

124-2: spacer

126-1: spacer

126-2: spacer

130-1: Metallized wire

130-2: Metallized wire

130-3: Metallized wire

130-4: Metallized wire

140-1: Isolation Features

140-2: Isolation Features

140-3: Isolation features

140-4: Isolation Features

150:Contour Modifier

160-1: Contact Features

160-2: Contact Features

160-3: Contact Features

160-4: Contact Features

160-5: Contact Features

160-6: Contact Features

A-A': line

B-B': line

C-C': line

G: area

R1: aperture

R2: Aperture

X: direction

Y: Direction

Z: Direction

Claims (20)

A semiconductor device structure, comprising: a first metallization line and a second metallization line extending along a first direction; a first isolation feature and a second isolation feature arranged between the first metallization line and the second isolation feature Between the second metallization lines, wherein the first metallization line, the second metallization line, the first isolation feature, and the second isolation feature define an aperture; an outline modifier disposed within the aperture, to modify the contour of the aperture in plan view; and a contact feature disposed in the aperture. The semiconductor element structure as claimed in claim 1, wherein the contour modifier rounds the contour of the aperture in plan view. The semiconductor device structure of claim 1, wherein the outline modifier is located at a corner defined by the first metallization line and the first isolation feature. The semiconductor device structure as claimed in claim 1, wherein the profile modifier is disposed on a sidewall of the first metallization line. The semiconductor device structure of claim 1, wherein the contour modifier is disposed on a sidewall of the first isolation feature. The semiconductor device structure as claimed in claim 1, wherein the sidewalls of the first isolation feature and the sidewalls of the second isolation feature protrude from each other. The semiconductor device structure of claim 1, wherein the contour modifier has a sidewall recess relative to the contact feature. The semiconductor element structure according to claim 1, further comprising: a first spacer located on the sidewall of the first metallization line; and a second spacer located on the sidewall of the second metallization line, and The aperture is defined by the first spacer, the second spacer, the first isolation feature, and the second isolation feature. The semiconductor device structure as claimed in claim 8, wherein the contour modifier has a first width along the first direction at the sidewall of the first spacer, between the first spacer and the second spacer There is a second width along the first direction, and the first width is larger than the second width. The semiconductor device structure as claimed in item 8, wherein the aperture has a first width along the first direction at the sidewall of the first spacer, between the first spacer and the second spacer along the The first direction has a second width, and the first width is greater than the second width. The semiconductor device structure as claimed in claim 8, wherein part of the sidewall of the first spacer is exposed from the contour modifier. The semiconductor element structure as described in Claim 1, further comprising: a third metallization line and a fourth metallization line extending along a second direction different from the first direction; wherein the first isolation feature is along a first direction different from the first direction and the second direction Three directions overlap the third metallization line, and the second isolation feature overlaps the fourth metallization line along the third direction; wherein the third metallization line overlaps the outline modifier along the third direction . A semiconductor device structure, comprising: a first metallization line and a second metallization line extending along a first direction; a first isolation feature and a second isolation feature arranged between the first metallization line and the second isolation feature Between the second metallization lines, wherein the first metallization line, the second metallization line, the first isolation feature, and the second isolation feature define an aperture; an outline modifier disposed within the aperture, Wherein the outline modifier includes a plurality of mutually separated segments, wherein each segment is located at a corner of the aperture; and a contact feature is surrounded by the plurality of segments. The semiconductor device structure of claim 13, wherein the plurality of segments includes a first segment that tapers toward a corner defined by the first metallization line and the first isolation feature . The semiconductor device structure according to claim 13, wherein the contour modifier rounds the contour of the aperture in plan view. The semiconductor device structure as claimed in claim 13, wherein the sidewall of the first isolation feature and the sidewall of the second isolation feature (facing the sidewall of the first isolation feature) protrude from each other. The semiconductor device structure of claim 13, wherein the first isolation feature has a sidewall protrusion relative to the outline modifier. The semiconductor element structure as claimed in claim 13, further comprising: a first spacer located on the sidewall of the first metallization line; and a second spacer located on the sidewall of the second metallization line, and The aperture is defined by the first spacer, the second spacer, the first isolation feature, and the second isolation feature. The semiconductor device structure of claim 18, wherein the plurality of segments includes a first segment that tapers toward an interface between the first spacer and the first isolation feature. The semiconductor device structure as claimed in claim 18, wherein the contour modifier is in contact with a sidewall of the first spacer.

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