TW202333208A - Method for preparing a semiconductor device structure having a profile modifier - Google Patents

Abstract

The present disclosure provides a method for manufacturing a semiconductor device structure. The method includes forming a first metallization line and a second metallization line extending along a first direction; forming a first isolation feature and a second isolation feature between the first metallization line and the second metallization line, wherein the first metallization line, the second metallization line, the first isolation feature and the second isolation feature define an aperture; forming a profile modifier within the aperture, wherein the profile modifier comprises a plurality of segments spaced apart from each other, wherein each of the segments are located at corners of the aperture; and forming a contact feature surrounded by the plurality of segments.

Description

Preparation method of semiconductor device structure with contour modifier

This application claims priority to U.S. Patent Application Nos. 17/665,722 and 17/666,037 (that is, the priority date is "February 7, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a method of manufacturing a semiconductor device structure, and in particular to a method of manufacturing a semiconductor device structure having a profile modifier.

With the rapid development of the electronics industry, integrated circuits (ICs) have achieved high performance and miniaturization. Due to advances in materials and design technology, current integrated circuits are smaller and more complex than previous generations.

Contacts are used to make connections within or between different features in semiconductor structures. For example, contacts are used to connect one conductive feature to another conductive feature. In some cases, voids may form in the openings filled by the contact material, thereby adversely affecting the electrical connection between the conductive features. Therefore, a new semiconductor device structure and method are needed to improve this problem.

The above description of "prior art" is only to provide background technology, and does not admit that the above description of "prior art" reveals the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and any description of the above "prior art" None should form any part of this case.

One aspect of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a first metallization line, a second metallization line, a first isolation feature, a second isolation feature, a profile modifier and a contact feature. The first metallization line and the second metallization line extend along a first direction. The first isolation feature and the second isolation feature are disposed between the first metallization line and the second metallization line. The first metallization line, the second metallization line, the first isolation feature, and the second isolation feature define an aperture. The outline modifier is disposed within the aperture to modify the outline of the aperture in a plan view. The contact feature is disposed within the aperture.

Another aspect of the present disclosure provides another semiconductor device structure. The semiconductor device structure includes a first metallization line, a second metallization line, a first isolation feature, a second isolation feature, a profile modifier and a contact feature. The first metallization line and the second metallization line extend along a first direction. The first isolation feature and the second isolation feature are disposed between the first metallization line and the second metallization line. The first metallization line, the second metallization line, the first isolation feature, and the second isolation feature define an aperture. The profile modifier is set within the aperture. The outline modifier includes a plurality of mutually separated segments. Each segment is located at the corner of the aperture. The contact feature is disposed within the aperture.

Another aspect of the present disclosure provides a method of fabricating a semiconductor device structure. The preparation method includes: providing a substrate; forming a first metallization line and a second metallization line on the substrate, wherein the first metallization line and the second metallization line extend along a first direction; in A first isolation feature and a second isolation feature are formed between the first metallization line and the second metallization line, wherein the first metallization line, the second metallization line, the first isolation feature and the The second isolation feature defines an aperture; forms an outline modifier to modify the outline of the aperture in plan view; and forms a contact feature within the aperture.

Embodiments of the present disclosure illustrate a semiconductor device structure with profile modifiers. In some embodiments, a profile modifier may be utilized to round the aperture to accommodate the contact feature so that the contact feature has a partially circular, partially elliptical, or partially elliptical outline in plan view. When the conductive material is filled into the circular aperture to form the contact feature, no or less voids may be formed therein, thereby increasing the fabrication yield of the semiconductor device structure.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

Specific language will now be used to describe the embodiments, or examples, of the present disclosure illustrated in the drawings. It should be understood that no limitation on the scope of the present disclosure is intended. Any changes or modifications to the described embodiments, and any further applications of the principles described herein, are deemed to be commonly made by one of ordinary skill in the art to which this disclosure relates. Reference numbers may be repeated throughout the embodiments, but this does not imply that features of one embodiment apply to another embodiment even if they share the same reference number.

It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the inventive concept.

The terminology used herein is for describing particular embodiments only and is not intended to limit the concepts of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should be further understood that the words "include" and "include", when used in this specification, indicate the presence of stated features, integers, steps, operations, elements or components, but do not exclude the presence or addition of one or more other features, An integer, step, operation, element, component, or group thereof.

FIG. 1 is a top view illustrating the layout of a semiconductor device structure 100 according to some embodiments of the present disclosure.

In some embodiments, the semiconductor device structure 100 may include active devices and/or passive devices. Active components may include a memory chip (eg, a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, etc.), a power management chip (eg, a power management integrated circuit (PMIC) chip), a logic chip (e.g., system on chip (SoC), central processing unit (CPU), graphics processing unit (GPU), application processor (AP), microcontroller, etc.), a radio frequency (RF) chip, a A sensor chip, a microelectromechanical system (MEMS) chip, a signal processing chip (for example, a digital signal processing (DSP) chip), a front-end chip (for example, an analog front-end (AFE) chip) or other active components. Passive components may include a capacitor, a resistor, an inductor, a fuse or other passive components.

In some embodiments, the semiconductor device structure 100 may include a plurality of metallization lines 120-1, 120-2, and 120-3, a plurality of metallization lines 130-1, 130-2, 130-3, and 130-4, A plurality of isolation features 140-1, 140-2, 140-3 and 140-4, a plurality of outline modifiers 150, and a plurality of contact features 160-1, 160-2, 160-3, 160-4, 160 -5 and 160-6.

In some embodiments, metallization lines 120-1, 120-2, and 120-3 may extend along the X direction. The metallization lines 120-1, 120-2 and 120-3 may be parallel to each other along the Y direction. Metallization lines 120-1, 120-2, and 120-3 may be spaced apart from each other. In some embodiments, each of the metallization lines 120-1, 120-2, and 120-3 can be used as a bit line and can be used to connect, but is not limited to, a gate structure (eg, a bit line gate poles) and contacts (e.g., bit line contacts).

In some embodiments, the semiconductor device structure 100 may include a plurality of spacers 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2. Each spacer 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2 may be disposed on a sidewall of a metallization line (eg, 120-1, 120-2, and 120-3) . For example, spacers 122-1 and 122-2 may be disposed on two opposite sidewalls of metallization line 120-1. Spacers 122-2 and 124-1 may face each other. Each of the spacers 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2 may extend in the X direction. Each of the spacers 122-1, 122-2, 124-1, 124-2, 126-1 and 126-2 may be parallel to each other in the Y direction. Each of spacers 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2 may be spaced apart from each other. Each spacer 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2 may be used to connect metallized lines to contact features (e.g., 160-1, 160-2, 160 -3, 160-4, 160-5 and 160-6) isolation.

In some embodiments, metallization lines 130-1, 130-2, 130-3, and 130-4 may extend along the Y direction. The metallization lines 130-1, 130-2, 130-3 and 130-4 may be parallel to each other along the X direction. Metallization lines 130-1, 130-2, 130-3, and 130-4 may be spaced apart from each other. In some embodiments, each of the metallization lines 130-1, 130-2, 130-3 and 130-4 can be used as a word line and can be used to connect, but is not limited to, gate structures (eg, word line gate) and contacts (e.g., word line contacts).

In some embodiments, isolation features 140-1, 140-2, 140-3, and 140-4 may be disposed on contact features (e.g., 160-1, 160-2, 160-3, 160-4, 160-5 or 160-6) on two opposite sides. In some embodiments, each isolation feature 140-1, 140-2, 140-3, and 140-4 may be located between two metallization lines in plan view. For example, isolation features 140-1 and 140-2 may be located between metallization lines 120-1 and 120-2.

In some embodiments, each of isolation features 140-1, 140-2, 140-3, and 140-4 may have a partially circular, partially elliptical, or partially elliptical outline in plan view. For example, the two sidewalls of isolation feature 140-1, extending from metallization line 120-1 to metallization line 120-2 (or from spacer 122-2 to spacer 124-1), may have a Curved shape. Each of the side walls may have a raised surface in plan view.

In some embodiments, each of isolation features 140-1, 140-2, 140-3, and 140-4 may be aligned along the Z direction with metallization lines (eg, 130-1, 130-2, 130-3, and 130-4). Although not shown, it should be noted that a contact feature (eg, a word line contact) can penetrate one of the isolation features 140-1, 140-2, 140-3, and 140-4 and can interact with the corresponding Metalized lines 130-1, 130-2, 130-3 or 130-4 are electrically connected. In some embodiments, each isolation feature 140-1, 140-2, 140-3, and 140-4 may contact a sidewall of a spacer of a metallization line. For example, isolation feature 140-1 may be in contact with spacers 122-2 and 124-1.

In some embodiments, metallization lines (eg, 120-1, 120-2, and 120-3) and isolation features (eg, 140-1, 140-2, 140-3, and 140-4) may define an aperture (eg, R1). In some embodiments, spacers (eg, 122-1, 122-2, 124-1, 124-2, 126-1, and 126- 2) An aperture can be defined with isolation features (such as 140-1, 140-2, 140-3 and 140-4). For example, spacers 122-2 of metallization line 120-1, spacers 124-1 of metallization line 120-2, and isolation features 140-1 and 140-2 may define an aperture R1. In some embodiments, two edges defined by two side walls of an isolation feature (eg, 140-1 and 140-2) may bulge toward each other in plan view.

In some embodiments, profile modifier 150 may be located within aperture R1. In some embodiments, profile modifiers 150 may be located at the corners of aperture R1. In some embodiments, the profile modifier 150 may be used to modify the profile of the aperture R1. In some embodiments, profile modifier 150 may be used to round the profile of aperture R1. In some embodiments, the profile modifier 150 may be utilized to define an aperture R2 (or a circular aperture) having a partially circular, partially elliptical, or partially elliptical outline. In some embodiments, aperture R2 may be defined by metallized line spacers (eg, 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2) and profile modifier 150. In some embodiments, profile modifier 150 may overlap metallization lines (eg, 130-1, 130-2, 130-3, and 130-4) along the Z direction.

In some embodiments, contact features 160-1, 160-2, 160-3, 160-4, 160-5, and 160-6 (or cell contacts) may be aligned along the X direction. In some embodiments, each of contact features 160-1, 160-2, 160-3, 160-4, 160-5, and 160-6 may be located between two metallization lines in plan view. For example, contact feature 160-1 may be located between metallization lines 120-1 and 120-2. In some embodiments, contact features (eg, 160-1 and 160-2) may be spaced apart from each other by isolation features (eg, 140-1). In some embodiments, each of contact features 160-1, 160-2, 160-3, 160-4, 160-5, and 160-6 may be partially circular, partially elliptical, or partially elliptical in plan view shape outline. In some embodiments, each contact feature (160-1, 160-2, 160-3, 160-4, 160-5, and 160-6) may be associated with a spacer (eg, 122-1, 122-2, 124-1, 124-2, 126-1 and 126-2) are in contact with the side walls. In some embodiments, each contact feature (160-1, 160-2, 160-3, 160-4, 160-5, and 160-6) may contact the sidewall of profile modifier 150. In some embodiments, each contact feature (160-1, 160-2, 160-3, 160-4, 160-5, and 160-6) may be located within aperture R1 or R2. In some embodiments, the outline of each contact feature (160-1, 160-2, 160-3, 160-4, 160-5, and 160-6) may be modified or defined by outline modifier 150.

FIG. 2 is a partially enlarged view illustrating a region G of the semiconductor device structure 100 shown in FIG. 1 in some embodiments of the present disclosure.

As shown in FIG. 2, the metallization line 120-1 may have a sidewall 120s1 on which a spacer 122-2 is disposed. Metalized line 120-2 may have sidewalls 120s2 on which spacers 124-1 are disposed.

Isolation feature 140-1 has side wall 140s1 facing side wall 140-2 of isolation feature 140-2. In some embodiments, side walls 140s1 and 140s2 may bulge or protrude toward each other. In some embodiments, outline modifier 150 may include segments 152-1, 152-2, 152-3, and 152-4. In some embodiments, segments 152-1, 152-2, 152-3, and 152-4 may be separated from each other. In some embodiments, segments 152-1, 152-2, 152-3, and 152-4 may be located within aperture R1. In some embodiments, segments 152-1, 152-2, 152-3, and 152-4 may be located at corners (eg, E1) of aperture R1. For example, segment 152-1 may be located at a corner (eg, E1) defined by sidewall 122s1 of spacer 122-2 of metallization line 120-1 and sidewall 140s1 of isolation feature 140-1. In some embodiments, each of segments 152-1, 152-2, 152-3, and 152-4 may have slave spacers (eg, 122-1, 122-2, 124-1, 124-2, 126-1 and 126-2) and the side walls of the isolation features (eg, 140-1, 140-2, 140-3, and 140-4). For example, segment 152-1 may have sidewall 152s1 extending from sidewall 122s1 of spacer 122-2 to sidewall 140s1 of isolation feature 140-1.

In some embodiments, segments 152-1, 152-2, 152-3, and 152-4 may taper in the Y direction. For example, segment 152-1 tapers in the negative Y direction, while segment 152-3 tapers in the positive Y direction. In some embodiments, each of segments 152-1, 152-2, 152-3, and 152-4 may taper toward a corner (eg, E1) of aperture R1. In some embodiments, the sidewalls of profile modifier 150 may be recessed relative to contact features (eg, 160-1, 160-2, 160-3, 160-4, 160-5, and 160-6). For example, sidewall 152s1 is recessed relative to the sidewall of contact feature 160-2.

In some embodiments, each segment (eg, 152-1) may have a width W1 in the Width W2. Width W1 is greater than width W2. In some embodiments, a portion of the sidewall (eg, 122s1 ) of spacer 122 - 2 is exposed from profile modifier 150 .

In some embodiments, contact features (eg, 160 - 2 ) may be surrounded by segments 152 - 1 , 152 - 2 , 152 - 3 , and 152 - 4 of outline modifier 150 .

In some embodiments, sidewalls of isolation features (eg, 140-1, 140-2, 140-3, and 140-4) may be raised relative to profile modifier 150. For example, sidewall 140s1 of isolation feature 140-1 may be raised relative to segment 152-1 or 152-3.

In some embodiments, aperture R1 may have a width W3 along the The X direction has width W4. Width W3 is greater than width W4.

3A, 3B and 3C are cross-sectional views respectively illustrating the semiconductor device structure 100 along lines AA', BB' and CC' according to some embodiments of the present disclosure, as shown in FIG. 1 .

As shown in FIG. 3A , the semiconductor element structure 100 may include a substrate 110 . Substrate 110 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, or the like. The substrate 110 may include an elemental semiconductor, including silicon or germanium in a single crystal form, a polycrystalline form, or an amorphous form; a compound semiconductor material, including silicon carbide, gallium arsenide, gallium phosphide, or phosphide. At least one of indium, indium arsenide, and indium antimonide; an alloy semiconductor material, including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or a combination thereof. In some embodiments, the alloy semiconductor substrate may include a SiGe alloy having a gradient Ge feature, wherein the composition of Si to Ge changes from a ratio at one location to a ratio at another location of the gradient SiGe feature. In another embodiment, the SiGe alloy is formed on a silicon substrate. In some embodiments, the SiGe alloy can be mechanically strained by another material in contact with the SiGe alloy. In some embodiments, the substrate 110 may have a multi-layer structure, or the substrate 110 may include a multi-layer compound semiconductor structure. In some embodiments, p-type and/or n-type dopants may be doped into substrate 110 . In some embodiments, the p-type dopant includes boron (B), other Group III elements, or any combination thereof. In some embodiments, n-type dopants include arsenic (As), phosphorus (P), other Group V elements, or any combination thereof.

Although not shown in Figure 3A, it should be noted that the substrate 110 may include an isolation structure disposed therein. Isolation structures may include shallow trench isolation (STI), field oxide (FOX), local oxide on silicon (LOCOS) features, and/or other suitable isolation elements. The isolation structure may include dielectric materials such as silicon oxide, silicon nitride, silicon oxy-nitride, fluorosilicate (FSG), low-k (dielectric constant) dielectric materials, combinations thereof, and/or or other suitable materials. In some embodiments, contact features 160 - 2 and 160 - 5 may be in contact with both the silicon substrate (or active region) and the isolation structure of substrate 110 .

Metalization line 120 - 2 may be disposed on or over substrate 110 and may be spaced apart from substrate 110 by a gate structure (eg, 170 ). Metalized lines 120-2 may include conductive materials such as tungsten copper, aluminum, tantalum, tantalum nitride (TaN), titanium, titanium nitride (TiN), etc., and/or combinations thereof.

The semiconductor device structure 100 may include a gate structure 170 . The gate structure 170 may be disposed on the substrate 110 . Gate structure 170 may be disposed between metallization lines (eg, 120 - 2 ) and substrate 110 . In some embodiments, a portion of gate structure 170 may be located at a lower elevation than the upper surface of substrate 110 . The gate structure 170 may include a gate dielectric layer and a gate electrode layer.

In some embodiments, the gate dielectric layer may include silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), or combinations thereof. In some embodiments, the gate dielectric layer may include a dielectric material, such as a high-K dielectric material. High-K dielectric materials may have a dielectric constant (k value) greater than 4. High-K dielectric materials may include hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), or other suitable materials. Other suitable materials are contemplated by this disclosure.

In some embodiments, the gate electrode layer may include a polysilicon layer. In some embodiments, the gate electrode layer may be made of a conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta) or other suitable materials. In some embodiments, the gate electrode layer may include a work function layer. The manufacturing technology of the work function layer is a metal material, and the metal material may include an N-work function metal or a P-work function metal. N-work function metals include tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC ), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr) or combinations thereof. P-work function metals include titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru), or combinations thereof. Other suitable materials are contemplated by this disclosure. The gate electrode layer can be formed by low pressure chemical vapor deposition (LPCVD) and plasma enhanced CVD (PECVD).

Dielectric layer 182 may be disposed between metallization lines (eg, 120-1 or 120-3) and substrate 110. Dielectric layer 182 may include a dielectric material. For example, dielectric layer 182 may include SiN, SiO2, silicon oxynitride (SiON), silicon oxynitride (SiCN), silicon carbide (SiC), aluminum oxide (Al2O3), hafnium oxide (HfO2), or lanthanum oxide (La2O3) .

In some embodiments, semiconductor element structure 100 may include dielectric layer 184 . Dielectric layer 184 may be disposed on or over metallization lines (eg, 120-1, 120-2, or 120-3). Dielectric layer 184 may include a dielectric material. For example, dielectric layer 184 may include SiN, SiO2, silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbide (SiC), aluminum oxide (Al2O3), hafnium oxide (HfO2), or lanthanum oxide (La2O3) .

Spacers (eg, 122 - 1 ) may be formed on dielectric layer 182 , metallization lines 120 - 1 , and sidewalls of dielectric layer 184 . Spacers (eg, 124 - 1 ) may be formed on dielectric layer 184 , metallization lines 120 - 2 , and sidewalls of gate structure 170 . In some embodiments, a portion of the spacer (eg, 124 - 1 ) may be lower than the upper surface of the substrate 110 . In some embodiments, spacers (eg, 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2) may include multiple layers. In some embodiments, spacers (eg, 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2) may include silicon oxide (SiOx), silicon nitride (SixNy), nitrogen Silicon oxide (SiON), or combinations thereof. In some embodiments, spacers (eg, 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2) may include an air gap. For example, an air gap can be sandwiched between two silicon nitride layers.

Contact features (eg, 160-2 or 160-5) may be disposed on substrate 110. In some embodiments, a portion of the contact feature (eg, 160 - 2 or 160 - 5 ) may be lower than the upper surface of the substrate 110 . In some embodiments, a contact feature (eg, 160-2 or 160-5) may contact the spacer of the metallization line. For example, contact feature 160-2 may contact spacer 122-2 of metallization line 120-1 and spacer 124-1 of metallization line 120-2.

In some embodiments, contact features (eg, 160-2 or 160-5) may include a barrier layer (not shown) and a conductive layer (not shown) on the barrier layer. The barrier layer may include titanium, tantalum, titanium nitride, tantalum nitride, manganese nitride, or combinations thereof. The conductive layer may include metals such as tungsten (W), copper (Cu), Ru, Ir, Ni, Os, Rh, Al, Mo, Co, alloys thereof, combinations thereof, or any metal material with suitable resistance and gap filling capabilities. . In some embodiments, contact features (eg, 160-2 or 160-5) may include a polysilicon layer.

Although not shown in FIG. 3A , it should be noted that another contact feature (eg, a bit line contact) can penetrate the dielectric layer 184 to electrically connect with the metallization line 120 - 2 so that the metallization line 120 -2 A power supply can be applied through the bit line contacts.

As shown in FIG. 3B , profile modifiers 150 may be disposed on substrate 110 between spacers and contact features. For example, segment 152-1 of profile modifier 150 may be located between spacer 122-2 and contact feature 160-2. That is, a portion of contact feature 160-2 may be separated from spacer 122-2 by segment 152-1 of contour modifier 150.

In some embodiments, profile modifier 150 may include silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), or combinations thereof. In some embodiments, the profile modifier 150 may be made of the same or similar material as the outermost layer of the spacer. In some embodiments, a portion of the contact feature (eg, 160-2) may contact a sidewall (eg, 152s1) of the spacer (eg, 152-1).

As shown in FIG. 3C , metallization lines (eg, 130 - 2 ) may be separated from gate structure 170 by dielectric layer 186 . Metalized lines 130-2 may include conductive materials such as tungsten copper, aluminum, tantalum, tantalum nitride (TaN), titanium, titanium nitride (TiN), etc., and/or combinations thereof. In some embodiments, metallization lines (eg, 130 - 2 ) may be located lower than the upper surface of substrate 110 .

Dielectric layer 186 may include silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), or combinations thereof.

Isolation features (eg, 140-1) may be located between metallization lines (eg, 120-1 and 120-2). An isolation feature (eg, 140-1) may make contact with a sidewall (eg, 122s1) of a spacer (eg, 122-2). In some embodiments, as shown in FIGS. 3A and 3C , the upper surface of the substrate 110 may contact the isolation feature 140 - 1 at a higher level than the contact feature 160 - 2 .

In some embodiments, each of segments 152-1, 152-2, 152-3, and 152-4 of profile modifier 150 may be utilized to define aperture R2, which may have a partial circle in plan view, Partial elliptical or partial elliptical outline. When a conductive material is filled into the circular aperture R2 to form a contact feature, no or less voids may be formed therein, thereby improving the production yield of the semiconductor device structure 100 . In a comparative example, conductive material is filled into an opening with a profile similar to aperture R1. As a result, voids may be created at the corners of the opening that negatively affect electrical connections.

FIG. 4 is a schematic diagram illustrating a method 300 for manufacturing a semiconductor device structure according to some embodiments of the present disclosure.

The preparation method 300 begins with operation 310, where a substrate is provided. A plurality of first metallization lines (eg, word lines) may be formed in the substrate and extend along a first direction. A plurality of second metallization lines (eg, bit lines) may be formed on the substrate and extend along a second direction orthogonal to the first direction. A plurality of spacers may be formed on the sidewalls of the second metallization line and extend along the second direction. A plurality of dielectric layers may be formed on the substrate and located between the spacers of the second metallization line.

The method 300 continues with operation 320 where an etching process is performed to remove a first portion of the dielectric layer. Therefore, a plurality of openings of the dielectric layer can be formed. Each opening of the dielectric layer has a partially circular, partially elliptical or partially elliptical profile. Each opening of the dielectric layer may overlap the first metallization line along a third direction orthogonal to the first direction and the second direction.

The method 300 continues with operation 330 where a plurality of isolation features may be formed to fill openings in the dielectric layer. Each isolation feature has a partially circular, partially elliptical, or partially elliptical outline. Each isolation feature may overlap the first metallization line along a third direction orthogonal to the first direction and the second direction.

The method 300 continues with operation 340, where an etching process may be performed on a second portion of the dielectric layer. Therefore, a plurality of apertures are formed, and the upper surface of the substrate is exposed. Each aperture is defined by a second metallization line (or a spacer of a second metallization line) and an isolation feature, and has a partially circular, partially elliptical, or partially elliptical outline. Each aperture may have corners defined by the sidewalls of the isolation features and the sidewalls of the spacers. Each corner of the aperture may taper toward the interface of the isolation feature and the spacer.

The method 300 continues with operation 350 , where a profile modification material may be formed to cover the upper surface of the substrate, the sidewalls of the second metallization line (or the sidewalls of the spacers), and the sidewalls of the isolation features. The profile modifying material may be conformally disposed on the upper surface of the substrate, the sidewalls of the spacers, and the sidewalls of the isolation features. Contour material can occupy the corners of the hole.

The preparation method 300 continues with operation 360, where an etching process may be performed to remove a portion of the profile modification material, thereby exposing the upper surface of the substrate. The remaining contour modifying material forms a contour modifier to modify the contour of the aperture. Each profile modifier may have a plurality of segments located at the corners defined by the sidewalls of the second metallization line (or the sidewalls of the spacers) and the sidewalls of the isolation features. Each segment of the profile modifier may extend from a sidewall of the second metallization line (or a sidewall of the spacer) to a sidewall of the isolation feature. Thus, an aperture (or modified aperture) defined by spacers, profile modifiers, and/or isolation features may be circular and may have a partially circular, partially elliptical, or partially elliptical outline.

The method 300 continues with operation 370 where a conductive material may be deposited to fill the circular aperture. Therefore, a plurality of contact features can be formed within the circular aperture. Each contact feature may have a partially circular, partially elliptical, or partially elliptical outline.

The preparation method 300 is merely an example and is not intended to limit the disclosure beyond what is expressly mentioned in the patent application. Additional operations may be provided before, during, or after each operation of preparation method 300, and some of the operations described may be replaced, eliminated, or moved for other embodiments of the method. In some embodiments, the preparation method 300 may also include operations not depicted in FIG. 4 . In some embodiments, preparation method 300 may include one or more operations described in FIG. 4 .

Figure 5, Figure 5A, Figure 5B, Figure 5C, Figure 6, Figure 6A, Figure 6B, Figure 6C, Figure 7, Figure 7A, Figure 7B, Figure 7C, Figure 8, Figure 8A, Figure 8B, Figure 8C, Figure 9 , FIG. 9A, FIG. 9B, FIG. 9C, FIG. 10, FIG. 10A, FIG. 10B, FIG. 10C, FIG. 11, FIG. 11A, FIG. 11B and FIG. 11C illustrate various stages of preparation of the semiconductor device structure 100. Figure 5A, Figure 6A, Figure 7A, Figure 8A, Figure 9A, Figure 10A and Figure 11A are along the line AA' of Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10 and Figure 11 respectively. Sectional view. Figure 5B, Figure 6B, Figure 7B, Figure 8B, Figure 9B, Figure 10B and Figure 11B are along the BB' line of Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10 and Figure 11 respectively. Sectional view. Figure 5C, Figure 6C, Figure 7C, Figure 8C, Figure 9C, Figure 10C and Figure 11C are along the CC' line of Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10 and Figure 11 respectively. Sectional view.

Referring to Figures 5, 5A, 5B, and 5C, a substrate 110 may be provided. A plurality of metallization lines 130-1, 130-2, 130-3, and 130-4 (eg, word lines) may be formed in the substrate 110 and extend along the Y direction. Gate structure 170 (eg, bit gate) may be formed on substrate 110 . A plurality of metallization lines 120-1, 120-2, and 120-3 (eg, bit lines) may be formed on the substrate 110 and extend along the X direction. Metallization lines 120-1, 120-2, and 120-3 may be formed on respective gate structures 170. A plurality of spacers 122-1, 122-2, 124-1, 124-2, 126-1 and 126-2 may be formed on the sidewalls of respective metallization lines (eg 120-1, 120-2 and 120-3) superior. The spacers 122-1, 122-2, 124-1, 124-2, 126-1 and 126-2 may cover the sidewalls of the gate structure 170 and the metallization lines 120-1, 120-2 and 120-3. Dielectric layer 182 may be formed between substrate 110 and metallization lines (eg, 120-1). Dielectric layer 184 may be formed on or over metallization lines (eg, 120-1, 120-2, and 120-3). A plurality of dielectric layers 188 may be formed on the substrate 110 . Dielectric layer 188 may be located between a respective pair of spacers 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2. The dielectric layer may include SiN, SiO2, silicon oxynitride (SiON), silicon oxynitride (SiCN), silicon carbide (SiC), aluminum oxide (Al2O3), hafnium oxide (HfO2), or lanthanum oxide (La2O3). In some embodiments, dielectric layer 188 may include silicon oxide. In some embodiments, each of spacers 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2 may have a multi-layer structure including silicon nitride, silicon oxide, or other suitable s material. In some embodiments, the outermost layer of the spacers 122-1, 122-2, 124-1, 124-2, 126-1 and 126-2 is made of silicon nitride.

Referring to FIG. 6 , FIG. 6A , FIG. 6B and FIG. 6C , an etching process is performed. A portion of dielectric layer 188 is removed. Portions of dielectric layer 188 over metallization lines 130-1, 130-2, 130-3, and 130-4 may be removed. Therefore, a plurality of openings 188o can be formed. The upper surface of the substrate 110 may be exposed from the dielectric layer 180 . Each opening 188o of dielectric layer 188 may have a partially circular, partially elliptical, or partially elliptical outline. The etching process may include wet etching, or dry etching.

Referring to FIGS. 7, 7A, 7B, and 7C, a plurality of isolation features 140-1, 140-2, 140-3, and 140-4 may be formed to fill the opening 188o of the dielectric layer 188. Each isolation feature 140-1, 140-2, 140-3, and 140-4 has a partially circular, partially elliptical, or partially elliptical outline. Each isolation feature 140-1, 140-2, 140-3, and 140-4 may overlap with a respective metallization line 130-1, 130-2, 130-3, or 130-4 in the Z direction. Isolation features 140-1, 140-2, 140-3, and 140-4 can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low pressure chemical vapor deposition (LPCVD) ) or other suitable processes.

Referring to FIG. 8 , FIG. 8A , FIG. 8B and FIG. 8C , an etching process may be performed. The remaining dielectric layer 188 may be removed. Therefore, a plurality of apertures R1 are formed. Each aperture R1 consists of metallization lines (eg, 120-1, 120-2, and 120-3) (or spacers of metallization lines) and isolation features (eg, 140-1, 140-2, 140-3, and 140- 4) Definition. Each aperture R1 may have a corner consisting of sidewalls isolating features 140-1, 140-2, 140-3 and 140-4 from spacers 122-1, 122-2, 124-1, 124-2, 126- 1 and 126-2 sidewall definition. Each corner of aperture R1 can be connected to isolation features (e.g., 140-1, 140-2, 140-3, and 140-4) and spacers (e.g., 122-1, 122-2, 124-1, 124-2, 126-1 and 126-2) gradually become thinner. The etching process may include wet etching, or dry etching.

Referring to FIGS. 9, 9A, 9B, and 9C, the profile modification material 150' may be formed to cover the upper surface of the substrate 110, the sidewalls of the spacers (eg, 122-1, 122-2, 124-1, 124-2, 126-1 and 126-2) and sidewalls of isolation features (e.g., 140-1, 140-2, 140-3, and 140-4). Profile modifying material 150' may be conformally disposed on the upper surface of substrate 110, sidewalls of spacers (eg, 122-1, 122-2, 124-1, 124-2, 126-1, and 126-2), and isolation features (e.g., 140-1, 140-2, 140-3, and 140-4). Contour material 150' may occupy the corners of aperture R1. In some embodiments, the contour modification material 150' may be formed by an ALD process or other suitable processes.

Referring to FIG. 10 , FIG. 10A , FIG. 10B and FIG. 10C , an etching process may be performed to remove part of the profile modification material 150 ′. In some embodiments, the etching process may include, for example, a dry etching process.

The remaining profile modifying material 150' forms a profile modifier 150 to modify the profile of the aperture R1. Therefore, a circular aperture R2 can be formed. Each outline modifier 150 may have a plurality of segments 152-1, 152-2, 152-3 and 152-4, located in the spacer (for example, 122-1, 122-2, 124-1, 124-2, 126 -1 and 126-2) and the corners of the side walls of the isolation features (e.g., 140-1, 140-2, 140-3, and 140-4). Each segment 152-1, 152-2, 152-3, and 152-4 of the contour modifier 150 can be formed from a sidewall of the spacer (e.g., 122-1, 122-2, 124-1, 124-2, 126- 1 and 126-2) extending to the sidewalls of the isolation features (eg, 140-1, 140-2, 140-3, and 140-4). Therefore, by spacers (such as 122-1, 122-2, 124-1, 124-2, 126-1 and 126-2), outline modifiers 150 and/or isolation features (such as 140-1, 140-2 , 140-3 and 140-4), the circular aperture R2 defined may have a partially circular, partially elliptical or partially elliptical outline.

In some embodiments, a portion of the substrate 110 may be removed such that the upper surface of the substrate 110 may be recessed.

Referring to FIGS. 11 , 11A, 11B and 11C, a conductive material may be deposited to fill the circular aperture R2, thereby forming the semiconductor device structure 100. Accordingly, a plurality of contact features 160-1, 160-2, 160-3, 160-4, 160-5, and 160-6 may be formed. Each contact feature 160-1, 160-2, 160-3, 160-4, 160-5, and 160-6 may have a partially circular, partially elliptical, or partially elliptical outline.

When the conductive material is filled into the circular aperture R2, there is a gap between the isolation features (eg, 140-1, 140-2, 140-3, and 140-4) and the spacers (eg, 122-1, 122-2, 124-1, 124-2, 126-1 and 126-2), no or few gaps are formed at the corners of the side walls, so the yield of the semiconductor element structure 100 can be improved. In a comparative example, no contour modifiers are formed. Therefore, gaps in the contact features may be created at the corners of the isolation features and spacers, adversely affecting electrical connections.

One aspect of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a first metallization line, a second metallization line, a first isolation feature, a second isolation feature, a profile modifier and a contact feature. The first metallization line and the second metallization line extend along a first direction. The first isolation feature and the second isolation feature are disposed between the first metallization line and the second metallization line. The first metallization line, the second metallization line, the first isolation feature, and the second isolation feature define an aperture. The outline modifier is set within the aperture to modify the outline of the aperture in a plan view. The contact feature is disposed within the aperture.

Another aspect of the present disclosure provides another semiconductor device structure. The semiconductor device structure includes a first metallization line, a second metallization line, a first isolation feature, a second isolation feature, a profile modifier and a contact feature. The first metallization line and the second metallization line extend along a first direction. The first isolation feature and the second isolation feature are disposed between the first metallization line and the second metallization line. The first metallization line, the second metallization line, the first isolation feature, and the second isolation feature define an aperture. The profile modifier is set within the aperture. The outline modifier includes a plurality of mutually separated segments. Each segment is located at one corner of the aperture. The contact feature is disposed within the aperture.

Another aspect of the present disclosure provides a method of fabricating a semiconductor device structure. The preparation method includes: providing a substrate; forming a first metallization line and a second metallization line on the substrate, wherein the first metallization line and the second metallization line extend along a first direction; in A first isolation feature and a second isolation feature are formed between the first metallization line and the second metallization line, wherein the first metallization line, the second metallization line, the first isolation feature and the The second isolation feature defines an aperture; forms an outline modifier to modify the outline of the aperture in plan view; and forms a contact feature within the aperture.

Embodiments of the present disclosure illustrate a semiconductor device structure with profile modifiers. In some embodiments, a profile modifier may be utilized to round the aperture to accommodate the contact feature so that the contact feature has a partially circular, partially elliptical, or partially elliptical outline in plan view. When the conductive material is filled into the circular aperture to form the contact feature, no or less voids may be formed therein, thereby improving the fabrication yield of the semiconductor device structure.

Although the disclosure and its advantages have been described in detail, it should be understood that other changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the patent scope. For example, many of the processes described above may be implemented in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present disclosure is not limited to the specific embodiments of the process, machinery, manufacture, compositions of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure of this disclosure that they can use existing or future processes, machinery, manufacturing, etc. that have the same functions or achieve substantially the same results as the corresponding embodiments described herein in accordance with the present disclosure. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patent scope of the present disclosure.

100:Semiconductor component structure 110: Base 120-1:Metalized wire 120-2:Metalized wire 120-3:Metalized wire 120s1: side wall 120s2:Side wall 122-1: Gap 122-2: Gap 122s1:Side wall 124-1: Gap 124-2: Gap 126-1: Gap 126-2: Gap 130-1:Metalized wire 130-2:Metalized wire 130-3:Metalized wire 130-4:Metalized wire 140-1:Isolation Characteristics 140-2:Isolation Characteristics 140-3: Isolation Characteristics 140-4:Isolation Characteristics 140s1:Side wall 140s2:Side wall 150:Contour modifier 150':Contour modification material 152-1: Segmentation 152-2: Segmentation 152-3: Segmentation 152-4: Segmentation 152s1:Side wall 160-1:Contact Characteristics 160-2:Contact Characteristics 160-3:Contact Characteristics 160-4:Contact Characteristics 160-5:Contact Characteristics 160-6:Contact Characteristics 170: Gate structure 182:Dielectric layer 184:Dielectric layer 186:Dielectric layer 188:Dielectric layer 188o: Open your mouth 300:Preparation method 310: Operation 320: Operation 330: Operation 340: Operation 350: Operation 360:Operation 370:Operation A-A': line B-B': line C-C': line E1: corner G: area R1:Aperture R2:Aperture W1: Width W2: Width W3: Width W4: Width W5: Width X: direction Y: direction Z: direction

The disclosure content of this application can be more fully understood by referring to the embodiments and the patent scope combined with the drawings. The same element symbols in the drawings refer to the same elements. FIG. 1 is a top view illustrating the layout of a semiconductor device structure according to some embodiments of the present disclosure. FIG. 2 is a partially enlarged view illustrating a region G of the semiconductor device structure shown in FIG. 1 according to some embodiments of the present disclosure. FIG. 3A is a cross-sectional view illustrating the structure of a semiconductor device along line AA' in FIG. 1 according to some embodiments of the present disclosure. FIG. 3B is a cross-sectional view illustrating the structure of a semiconductor device along line BB' in FIG. 1 according to some embodiments of the present disclosure. FIG. 3C is a cross-sectional view illustrating the structure of a semiconductor device along line CC' in FIG. 1 according to some embodiments of the present disclosure. FIG. 4 is a schematic diagram illustrating a method of manufacturing a semiconductor device structure according to some embodiments of the present disclosure. 5, 5A, 5B, and 5C illustrate one or more stages of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. 6, 6A, 6B, and 6C illustrate one or more stages of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. 7, 7A, 7B, and 7C illustrate one or more stages of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. 8, 8A, 8B, and 8C illustrate one or more stages of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. 9, 9A, 9B, and 9C illustrate one or more stages of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. 10, 10A, 10B, and 10C illustrate one or more stages of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. 11, 11A, 11B, and 11C illustrate one or more stages of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

100:Semiconductor component structure

120-1:Metalized wire

120-2:Metalized wire

120-3:Metalized wire

122-1: Gap

122-2: Gap

124-1: Gap

124-2: Gap

126-1: Gap

126-2: Gap

130-1:Metalized wire

130-2:Metalized wire

130-3:Metalized wire

130-4:Metalized wire

140-1:Isolation Characteristics

140-2:Isolation Characteristics

140-3: Isolation Characteristics

140-4:Isolation Characteristics

150:Contour modifier

160-1:Contact Characteristics

160-2:Contact Characteristics

160-3:Contact Characteristics

160-4:Contact Characteristics

160-5:Contact Characteristics

160-6:Contact Characteristics

A-A': line

B-B':line

C-C':line

G: area

R1:Aperture

R2:Aperture

X: direction

Y: direction

Z: direction

Claims (20)

A method for preparing a semiconductor element structure, including: forming a first metallization line and a second metallization line extending along a first direction; A first isolation feature and a second isolation feature are formed between the first metallization line and the second metallization line, wherein the first metallization line, the second metallization line, the first isolation feature, and The second isolation feature defines an aperture; forming a profile modifier within the aperture, wherein the profile modifier includes a plurality of mutually spaced segments, wherein each segment is located at a corner of the aperture; and A contact feature surrounded by the plurality of segments is formed. The preparation method of claim 1, wherein the plurality of segments includes a first segment that tapers toward a corner defined by the first metallization line and the first isolation feature. The preparation method as claimed in claim 1, wherein the outline modifier makes the outline of the aperture rounded in plan view. The preparation method as claimed in claim 1, wherein the side wall of the first isolation feature and the side wall of the second isolation feature (side wall facing the first isolation feature) protrude from each other. The preparation method of claim 1, wherein the first isolation feature has a sidewall protrusion relative to the contour modifier. The preparation method as described in claim 1 further includes: forming a first spacer on the sidewall of the first metallization line; and A second spacer is formed on the sidewall of the second metallization line, and the aperture is defined by the first spacer, the second spacer, the first isolation feature, and the second isolation feature. The preparation method of claim 6, wherein the plurality of segments includes a first segment that tapers toward an interface between the first spacer and the first isolation feature. The preparation method as claimed in claim 6, wherein the profile modifier is in contact with the sidewall of the first spacer. The preparation method as claimed in claim 6, wherein part of the sidewall of the first spacer is exposed from the profile modifier. The preparation method of claim 6, wherein one of the plurality of segments of the profile modifier has a side wall extending from the side wall of the first spacer to the side wall of the first isolation feature. The preparation method as claimed in claim 1, wherein part of the sidewall of the first isolation feature is exposed from the profile modifier. A method for preparing a semiconductor element structure, including: provide a base; forming a first metallization line and a second metallization line on the substrate, wherein the first metallization line and the second metallization line extend along a first direction; A first isolation feature and a second isolation feature are formed between the first metallization line and the second metallization line, wherein the first metallization line, the second metallization line, the first isolation feature, and The second isolation feature defines an aperture; Form an outline modifier to modify the outline of the aperture in plan view; and A contact feature is formed within the aperture. The preparation method as described in claim 12 further includes: forming a dielectric layer between the first metallization line and the second metallization line; forming a first opening and a second opening defined by the dielectric layer; and An isolation material is filled to form a first isolation feature and a second isolation feature. The preparation method of claim 13, wherein each of the first opening and the second opening has a partially circular, partially elliptical or partially elliptical outline in plan view. The preparation method as described in claim 13 further includes: removing the dielectric layer between the first isolation feature and the second isolation feature to form the aperture; forming a contour-modifying material within the aperture; and A portion of the contour modifier is removed to form the contour modifier. The preparation method of claim 15, wherein the profile modification material is conformally formed on the sidewalls of the aperture and the upper surface of the substrate, and removing a portion of the profile modification material includes: removing the contour-modifying material from the upper surface of the substrate; and Remove part of the base. The preparation method of claim 16, wherein after removing the portion of the profile modification material, the profile modifier is located at a corner of the aperture, and the contact feature has a partial circle, a partial ellipse, or a partial ellipse in plan view. Partial oval silhouette. The preparation method as described in claim 12 further includes: forming a first spacer on the sidewall of the first metallization line; and forming a second spacer on the sidewall of the second metallization line; The aperture is defined by the first isolation feature, the second isolation feature, the first spacer, and the second spacer. The preparation method as claimed in claim 18, wherein forming the profile modifier to modify the profile of the aperture includes: forming a contour-modifying material within the aperture; and A portion of the profile modifier is removed to form the profile modifier, wherein the profile modifier has a sidewall extending from the first spacer to the first isolation feature. The preparation method as described in claim 18 further includes: A circular aperture is formed after forming the profile modifier, wherein the contour of the circular aperture is defined by at least the profile modifier, and the contact feature is formed within the circular aperture.