CN112750704A

CN112750704A - Method for forming semiconductor device structure

Info

Publication number: CN112750704A
Application number: CN202011187912.6A
Authority: CN
Inventors: 李东颖; 张开泰
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2019-10-30
Filing date: 2020-10-30
Publication date: 2021-05-04

Abstract

The present disclosure provides a method of forming a semiconductor device structure. The method includes providing a substrate, a first nanostructure, and a second nanostructure. The method includes forming an isolation layer on a substrate. The method includes forming a gate dielectric layer on the first nanostructure, the second nanostructure, the fin, and the isolation layer. The method includes forming a gate layer on the first portion. The method includes forming a spacer layer. The method includes removing the second portion of the gate dielectric layer and the first upper portion of the isolation layer to form a space between the fin and the spacer layer. The method includes forming a source/drain structure in the space and on the first nanostructure and the second nanostructure.

Description

Method for forming semiconductor device structure

Technical Field

Embodiments of the present invention relate to semiconductor device structures, and more particularly, to dual diamond shaped source/drain structures.

Background

The semiconductor integrated circuit industry has experienced rapid growth. Technological advances in integrated circuit materials and design have resulted in each generation of integrated circuits having smaller and more complex circuits than the previous generation. However, these advances also increase the complexity of processing and fabricating integrated circuits.

In the evolution of bulk circuits, the functional density (number of interconnect devices per chip area) generally increases as the geometries (the smallest features or lines resulting from the fabrication processes employed) shrink. The process of scaling down is generally advantageous in increasing throughput and reducing associated costs.

As the size of structures continues to shrink, the fabrication process becomes increasingly difficult. It is challenging to form smaller and reliable semiconductor devices.

Disclosure of Invention

It is an object of the present invention to provide a method for forming a semiconductor device structure to solve at least one of the above problems.

In some embodiments, methods of forming semiconductor device structures are provided. The method includes providing a substrate, a first nanostructure, and a second nanostructure. The substrate is provided with a base and a fin on the base, and the first nanostructure and the second nanostructure are sequentially stacked on the fin. The method includes forming an isolation layer on a substrate. The width of the first upper portion of the spacer layer increases toward the substrate. The method includes forming a gate dielectric layer on the first nanostructure, the second nanostructure, the fin, and the isolation layer. The gate dielectric layer has a first portion and a second portion. The method includes forming a gate layer on the first portion. The method includes forming a spacer layer on a first sidewall of the gate layer, a second sidewall of the first portion of the gate dielectric layer, and a third sidewall of the second portion of the gate dielectric layer over the first upper portion of the isolation layer. The method includes removing the second portion of the gate dielectric layer and the first upper portion of the isolation layer to form a space between the fin and the spacer layer. The method includes forming a source/drain structure in the space and on the first nanostructure and the second nanostructure.

In some embodiments, methods of forming semiconductor device structures are provided. The method includes providing a substrate, a first nanostructure, and a second nanostructure. The substrate is provided with a base and a fin on the base, and the first nanostructure and the second nanostructure are sequentially stacked on the fin. The method includes forming an isolation layer on a substrate. The method includes forming a gate layer to encapsulate the first nanostructure, the second nanostructure, and the fin. The method includes forming a spacer layer on a first sidewall of the gate layer and a second sidewall of the fin. The spacer layer has a sloped portion that is spaced a distance from the fin that increases toward the substrate. The method includes partially removing the isolation layer under the sloped portion of the spacer layer to form a space surrounded by the fin, the sloped portion, and the isolation layer. The method includes forming a source/drain structure that is partially in the space and partially surrounds the first nanostructure and the second nanostructure.

In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin on the base. The semiconductor device structure includes a gate structure that wraps around a top portion of the fin. The semiconductor device structure includes a first nanostructure on the fin and through the gate structure. The semiconductor device structure includes a source/drain structure on the fin. A source/drain structure is on one side of the gate structure and connected to the first nanostructure, the source/drain structure having an upper portion, a lower portion, and a neck portion between the upper portion and the lower portion, the upper portion being wider than the neck portion and the lower portion being wider than the neck portion.

Drawings

Fig. 1A-1H are perspective views of various stages in a process for forming a semiconductor device structure, in some embodiments.

FIG. 2A is a cross-sectional view of the semiconductor device structure taken along line I-I' of FIG. 1H, in some embodiments.

Fig. 2B is a cross-sectional view of the semiconductor device structure taken along line II-II' of fig. 1H in some embodiments.

Figures 3A and 3B are cross-sectional views of various stages of a process used to form semiconductor device structures, in some embodiments.

Fig. 4A-4C are perspective views of various stages in a process for forming a semiconductor device structure, in some embodiments.

Fig. 5A is a cross-sectional view of the semiconductor device structure taken along the cross-sectional line I-I' of fig. 4C in some embodiments.

Fig. 5B is a cross-sectional view of the semiconductor device structure taken along line II-II' of fig. 4C in some embodiments.

Fig. 6A and 6B are cross-sectional views of various stages of a process used to form a semiconductor device structure, in some embodiments.

Fig. 7A-7C are perspective views of various stages in a process for forming a semiconductor device structure, in some embodiments.

Fig. 8A is a cross-sectional view of the semiconductor device structure taken along the cross-sectional line I-I' of fig. 7C in some embodiments.

Fig. 8B is a cross-sectional view of the semiconductor device structure along the cross-sectional line II-II' of fig. 7C in some embodiments.

Fig. 9A and 9B are cross-sectional views of various stages of a process used to form a semiconductor device structure, in some embodiments.

Fig. 9B-1 is a cross-sectional view of a semiconductor device structure in some embodiments.

Fig. 9B-2 is a cross-sectional view of a semiconductor device structure in some embodiments.

Fig. 10 is a cross-sectional view of a semiconductor device structure in some embodiments.

Fig. 11 is a cross-sectional view of a semiconductor device structure, in some embodiments.

Fig. 12 is a cross-sectional view of a semiconductor device structure, in some embodiments.

The reference numbers are as follows:

d1, D144 distance

G is clearance

I-I ', II-II ', III-III ' cutting line

N inner spacer layer

N1, N2, N3, N4 medial spacers

P1, P2 part

R1, R2, R3, R4, R120,10: concave

S is space

S1,152,141b,162 side wall

T130, T132, T141, T142, T146 thickness

Maximum thickness of T182 and T184

W132, W144, W182, W184 width

110 base plate

112, substrate

114 fins

114a,136,141a,146a,164 upper surface

120 nanostructure Stack

121,122,123,124,125,126,127,128 nanostructure

130 insulating layer

132,142,184 upper side part

132a,144a oblique side wall

134,144,182 lower part

136a,182a,184a upper side surface

140 gate dielectric layer

146,174 horizontal part

150 gate layer

150a layer of gate material

160 mask layer

170 spacer layer

172 oblique portion

176 vertical part

178 groove

180 source/drain structure

182b,184b lower side surfaces

182B bottom

182c crystal plane surface

182d corner part

182e, bottom end

184c flat upper surface

184e tip

186 neck part

190 dielectric layer

192 contact hole

210 gate structure

212 gate dielectric layer

214 work function metal layer

216 grid layer

220 silicide layer

230 contact structure

300,600,900,1000,1100,1200 semiconductor device structure

1201 lower boundary surface

Detailed Description

The different embodiments or examples provided below may implement different configurations of the present invention. The specific components and arrangements are disclosed to simplify the present disclosure and not to limit the present disclosure. For example, the formation of a first element on a second element is described as including direct contact between the two elements, or the separation of additional elements other than direct contact between the two elements. Moreover, the same reference numbers may be repeated in various examples of the invention, and such repetition is for simplicity and clarity and does not imply that elements with the same reference numbers in different embodiments and/or arrangements have the same correspondence.

Furthermore, spatially relative terms such as "below," "lower," "above," "upper," or the like may be used for ease of description to refer to a relationship of one element to another in the figures. Spatially relative terms may be extended to elements used in other orientations than the orientation illustrated. The elements may also be rotated 90 or other angles, and thus directional terms are used only to describe directions in the drawings. It should be understood that additional steps may be provided before, during, and after the method, and that other embodiments of the method may replace or omit some of the described steps.

The present invention illustrates some embodiments. Additional steps may be provided before, during and/or after the stages described in these embodiments. Different embodiments may replace or omit some of the described stages. Additional structures may be added to the semiconductor device structure. Various embodiments may replace or omit some of the structures described below. Although some embodiments perform the steps in a particular order, the steps may be performed in other logical orders.

Those skilled in the art will understand that the term "substantially" or "about" in the specification, such as "substantially flat" or "substantially flush with. In some embodiments, adjectives may be substantially removed. The term "substantially" may include embodiments that are "all," "complete," or "all," where possible. The term "about" in combination with a particular distance or dimension should be construed as not excluding insignificant deviation from the specified distance or dimension. The terms "substantially" or "approximately" may vary in different technologies and within the deviations understood by those skilled in the art. For example, the term "substantially" or "approximately" may be greater than or equal to 90% of the value, such as greater than or equal to 95% of the value, particularly greater than or equal to 99% of the value, including greater than or equal to 100%, although embodiments of the invention are not limited thereto. Furthermore, terms such as "substantially parallel" or "substantially perpendicular" may be construed as not excluding minor deviations from a particular configuration, and may include deviations of up to 10 °. The phrase "substantially" does not exclude "completely," e.g., a composition that is "substantially free of Y" may be completely free of Y.

The method of patterning the all-around gate transistor structure may be any suitable method. For example, the structure may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. In general, double patterning or multiple patterning processes combine photolithography and self-aligned processes that produce a pattern pitch that is smaller than that obtained using a single direct photolithography process. For example, one embodiment forms a sacrificial layer on a substrate and patterns the sacrificial layer using a photolithography process. Spacers are formed along the patterned sacrificial layer sides using a self-aligned process. The sacrificial layer is then removed and the wrap-around gate structure may be patterned with the remaining spacers.

Fig. 1A-1H are perspective views of various stages in a process for forming a semiconductor device structure, in some embodiments. As some embodiments shown in fig. 1A, a substrate 110 is provided. In some embodiments, substrate 110 has a base 112 and fins 114 on base 112. For example, the substrate 110 includes a semiconductor substrate 110. The substrate 110 of a semiconductor includes, for example, a semiconductor wafer (such as a silicon wafer) or a portion of a semiconductor wafer.

In some embodiments, the composition of the substrate 110 is a semiconductor material including silicon or germanium in a single crystal, polycrystalline, or amorphous structure. In some other embodiments, the composition of the substrate 110 is a semiconductor compound (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium arsenide), a semiconductor alloy (e.g., silicon germanium or gallium arsenide phosphide), or a combination thereof. The substrate 110 may also comprise multiple layers of semiconductors, semiconductor-on-insulator (such as silicon-on-insulator or germanium-on-insulator), or combinations thereof.

In some embodiments, the substrate 110 is a device wafer including a variety of device units. In some embodiments, various device units are formed in and/or on the substrate 110. The devices are not shown for simplicity and clarity of the drawing. Examples of various device elements may include active devices, passive devices, other suitable elements, or a combination of the above. The active devices may include transistors or diodes (not shown) formed on the surface of the substrate 110. The passive devices may include resistors, capacitors, or other suitable passive devices.

For example, the transistor may be a metal oxide semiconductor field effect transistor, a complementary metal oxide semiconductor transistor, a bipolar junction transistor, a high voltage transistor, a high frequency transistor, a p-channel and/or n-channel field effect transistor, or the like. Various processes, such as front-end semiconductor fabrication processes, may be performed to form various device units. The front-end semiconductor fabrication process may include deposition, etching, implantation, photolithography, annealing, planarization, one or more other possible processes, or a combination thereof.

In some embodiments, isolation structures (not shown) are formed in the substrate 110. The isolation structures are used to define active regions and electrically isolate various device cells formed in and/or on the substrate 110 in the active regions. In some embodiments, the isolation structure comprises a shallow trench isolation structure, a local silicon oxide structure, other suitable isolation structures, or a combination thereof.

In some embodiments as shown in figure 1A, nanostructures 121,122,123,124,125,126,127, and 128 are sequentially stacked on fin 114. In some embodiments, nanostructures 121,122,123,124,125,126,127, and 128 comprise nanowires or nanoplatelets. In some embodiments, nanostructures 121,122,123,124,125,126,127, and 128 together form nanostructure stack 120.

In some embodiments, the composition of

nanostructures

121, 123, 125, and 127 are the same first material. In some embodiments, the first material is different from the material of the substrate 110. In some embodiments, the composition of the first material may be a semiconductor element material, including silicon or germanium in a single crystal, polycrystalline, or amorphous structure.

In some embodiments, the composition of the first material is a semiconductor compound (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or indium arsenide), a semiconductor alloy (e.g., silicon germanium or gallium arsenide phosphide), or a combination thereof.

In some embodiments, the composition of

nanostructures

122, 124, 126, and 128 may be the same second material. In some embodiments, the second material is different from the first material. In some embodiments, the second material is the same as the material of the substrate 110. In some embodiments, the composition of the second material may be a semiconductor element material, including silicon or germanium in a single crystal, polycrystalline, or amorphous structure.

In some embodiments, the composition of the second material is a semiconductor compound (such as silicon carbide, gallium arsenide, gallium phosphide, or indium arsenide), a semiconductor alloy (such as silicon germanium or gallium arsenide phosphide), or a combination of the above.

In some embodiments, as shown in FIG. 1A, an isolation layer 130 is formed on the substrate 112. In some embodiments, fins 114 are partially embedded in isolation layer 130. In some embodiments, isolation layer 130 surrounds fins 114.

In some embodiments, upper portion 132 of isolation layer 130 is adjacent to fin 114. In some embodiments, the width W132 of the upper portion 132 increases toward the base 112. In some embodiments, thickness T132 of upper portion 132 increases toward fin 114. In some embodiments, the upper portion 132 has a diagonal sidewall 132 a.

In some embodiments, the composition of the isolation layer 130 is an oxide such as silicon oxide. In some embodiments, the method of forming the isolation layer 130 includes depositing an isolation material layer (not shown) on the substrate 110, performing a planarization process on the isolation material layer, and performing an etch-back process on the isolation material layer. In some embodiments, the deposition process comprises a chemical vapor deposition process. In some embodiments, the planarization process includes a chemical mechanical polishing process. In some embodiments, thickness T132 of upper portion 132 increases toward fin 114 due to the difficulty in removing the layer of isolation material adjacent to fin 114.

In some embodiments, as illustrated in figure 1B, a gate dielectric layer 140 is formed on fin 114, nanostructure stack 120, and isolation layer 130. The composition of the gate dielectric layer 140 may be an oxide (e.g., silicon oxide) or another suitable insulating material. In some embodiments, the gate dielectric layer 140 may be formed by a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, a high density plasma chemical vapor deposition process, an organometallic chemical vapor deposition process, or a plasma-assisted chemical vapor deposition process.

In some embodiments, as shown in fig. 1C, a layer of gate material 150a is formed on the gate dielectric layer 140. The gate material layer 150a may include a single layer or a multi-layer structure. In some embodiments, the composition of the gate material layer 150a is polysilicon. The gate material layer 150a may be formed by a deposition process.

In some embodiments, the deposition process may include a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, a high density plasma chemical vapor deposition process, an organometallic chemical vapor deposition process, or a plasma assisted chemical vapor deposition process.

In some embodiments, as shown in fig. 1C, a mask layer 160 is formed on the gate material layer 150 a. In some embodiments, the mask layer 160 exposes a portion of the gate material layer 150 a. In some embodiments, the material of the mask layer 160 is different from the material of the gate material layer 150a and the gate dielectric layer 140. In some embodiments, the composition of the mask layer 160 is a nitride (e.g., silicon nitride) or an oxynitride (e.g., silicon oxynitride).

In some embodiments, as shown in fig. 1D, the portion of the gate material layer 150a exposed by the mask layer 160 is removed. In some embodiments, the remaining gate material layer 150a forms the gate layer 150. In some embodiments, the removal process forms the recess 10. In some embodiments, a gate dielectric layer 140 and a gate layer 150 surround each recess 10. In some embodiments, recesses 10 are located on both sides of fin 114. In some embodiments, the removal process includes a non-isotropic etch process, such as a dry etch process (e.g., a plasma etch process).

In some embodiments, as shown in fig. 1D, the gate dielectric layer 140, which was originally under the removed portion of the gate material layer 150a, is partially removed or thinned. In some embodiments, the removal process includes a non-isotropic etch process, such as a dry etch process (e.g., a plasma etch process).

In some embodiments, the gate dielectric layer 140 after the removal process has portions P1 and P2. In some embodiments, gate layer 150 is located on portion P1. In some embodiments, portion P2 has an upper portion 142, a lower portion 144, and a horizontal portion 146. In some embodiments, upper portion 142 covers nanostructure stack 120. In some embodiments, lower portion 144 covers fin 114 and upper portion 132 of isolation layer 130. In some embodiments, the horizontal portion 146 covers the underside portion 134 of the insulating layer 130. In some embodiments, the width W144 of the lower portion 144 increases toward the base 112. In some embodiments, the width W144 continuously increases toward the substrate 112. In some embodiments, the lower portion 144 has a diagonal sidewall 144 a.

In some embodiments, distance D144 between sloped sidewall 144a and fins 114 increases toward base 112. In some embodiments, distance D144 between sloped sidewall 144a and fins 114 continuously increases toward base 112.

In some embodiments, portion P1 is thicker than upper portion 142. Thus, in some embodiments, thickness T141 of portion P1 is thicker than thickness T142 of upper portion 142. In some embodiments, portion P1 is thicker than horizontal portion 146. Thus, in some embodiments, the thickness T141 is greater than the thickness T146 of the horizontal portion 146.

In some embodiments, as illustrated in fig. 1E, a spacer layer 170 is formed on sidewalls 162 of mask layer 160, on sidewalls 152 of gate layer 150, on sidewalls S1 of portion P1, on sloped sidewalls 144a of lower portion 144, and on upper surface 146a of horizontal portion 146. In some embodiments, the spacer layer 170 conformably covers the angled sidewalls 144 a.

In some embodiments, the spacer layer 170 has a diagonal portion 172, a horizontal portion 174, and a vertical portion 176. In some embodiments, the diagonal portion 172 covers the lower portion 144. In some embodiments, the horizontal portion 174 covers the horizontal portion 146.

In some embodiments, the vertical portion 176 covers the

sidewalls

162, 152 and S1. In some embodiments, the vertical portion 176 is thicker than the diagonal portion 172. In some embodiments, the diagonal portion 172 is thicker than the horizontal portion 174.

In some embodiments, the composition of the spacer layer 170 is an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide. In some embodiments, the spacer layer 170 is formed by depositing a spacer material layer (not shown) on the mask layer 160, the gate layer 150 and the gate dielectric layer 140, and performing an anisotropic etching process on the spacer material layer to partially remove the spacer material layer.

In some embodiments, the anisotropic etch process removes portions of the spacer material layer on the

upper surfaces

164 and 141a of the mask layer 160 and the gate dielectric layer 140, followed by upper portions of the spacer material layer on the

sidewalls

162 and 141b of the mask layer 160 and the gate dielectric layer 140. In some embodiments, after the anisotropic etching process, a spacer material layer remains on the

sidewalls

162 and 152 of the mask layer 160 and the gate layer 150, and on the bottom of the recess 10. In some embodiments, the etch rate of the layer of spacer material on the bottom will be less than the etch rate of the layer of spacer material on the upper portion of the sidewalls 141b, since the bottom of the recess 10 is difficult to reach by the etch unit of the anisotropic etch process (e.g., the etch plasma).

In some embodiments, as shown in fig. 1F, the upper portion 142 and the lower portion 144 of the gate dielectric layer 140 and a portion of the isolation layer 130 under the lower portion 144 are removed. In some embodiments, space S may be formed between sloped portion 172 and fins 114, and between isolation layer 130 and fins 114 after the removal process. In some embodiments, the removal process may include an etching process, such as a dry etching process and a chemical etching process. In some embodiments, the dry etch process comprises a non-isotropic etch process, such as a plasma etch process. In some embodiments, the chemical etching process comprises an isotropic etching process, such as a wet etching process or a vapor phase etching process.

In some embodiments, as illustrated in fig. 1E and 1F, an anisotropic etch process may be used to remove the upper portion 142 of the gate dielectric layer 140, and an isotropic etch process may be used to remove the lower portion 144 of the gate dielectric layer 140 and portions of the isolation layer 130. In some embodiments, the upper portion 142 of the gate dielectric layer 140 is removed using an anisotropic etch process, since the etch rate of the anisotropic etch process is greater than the etch rate of the isotropic etch process. The gap G between the sloped portion 172 of the spacer layer 170 and the nanostructure stack 120 is narrow, which may reduce the etch rate of the anisotropic etch process. The etchant of the isotropic etching process can easily pass through the gap G. Thus, in some embodiments, an isotropic etch process is used to remove the structures below the diagonal portion 172 (e.g., the lower portion 144 and the underlying isolation layer 130).

In some embodiments as illustrated in figure 1G, source/drain structure 180 is formed in space S and on fin 114 and nanostructure stack 120. In some embodiments, source/drain structure 180 directly contacts fin 114 and nanostructure stack 120. In some embodiments, fin 114 and nanostructure stack 120 pass through source/drain structure 180.

In some embodiments, the source/drain structure 180 has a diamond shape because the grown portion of the source/drain structure 180 is confined to the sloped portion 172 of the spacer layer 170. In some embodiments, each source/drain structure 180 has a lower portion 182, an upper portion 184, and a neck 186. In some embodiments, a neck 186 is connected between the upper portion 184 and the lower portion 182. In some embodiments, the upper portion 184 is located outside of any space S. In some embodiments, the upper portion 184 has a diamond shape.

In some embodiments, the lower portion 182 is located in the corresponding space S. In some embodiments, the lower portion 182 has a diamond shape. In some embodiments, the lower portion 182 is partially embedded in the isolation layer 130. In some embodiments, the upper portion 184 is wider than the neck 186. In some embodiments, the lower portion 182 is wider than the neck 186.

In some embodiments, the width W184 of the upper portion 184 tapers toward the neck 186. In some embodiments, the width W184 also tapers toward the top end 184e of the upper portion 184. In some embodiments, the width W182 of the lower portion 182 tapers toward the neck 186. In some embodiments, the width W182 also tapers toward the bottom end 182e of the lower portion 182.

In some embodiments, the upper portion 184 is wider than the lower portion 182. Thus, in some embodiments, the maximum width of the upper portion 184 is greater than the maximum width of the lower portion 182. In some embodiments, the upper portion 184 is thicker than the lower portion 182. Thus, in some embodiments, the maximum thickness T184 of the upper portion 184 is greater than the maximum thickness T182 of the lower portion 182.

In some embodiments, the source/drain structure 180 is comprised of a semiconductor material such as silicon germanium. The source/drain structure 180 may have a p-type doping such as a group IIIA element. The group IIIA element includes boron or another suitable material. In some other embodiments, the composition of the source/drain structure 180 is a semiconductor material such as silicon. The source/drain structure 180 may have n-type doping such as a group VA element. The group VA element includes phosphorus, antimony, or another suitable group VA material. In some embodiments, the source/drain structure 180 is formed using an epitaxial process.

FIG. 2A is a cross-sectional view of the semiconductor device structure taken along line I-I' of FIG. 1H, in some embodiments. Fig. 2B is a cross-sectional view of the semiconductor device structure taken along line II-II' of fig. 1H in some embodiments. FIG. 3A is a cross-sectional view of a semiconductor device structure taken along section III-III' of FIG. 1H, in some embodiments.

In some embodiments, a layer of dielectric material (not shown) is formed on the source/drain structures 180 and the spacer layer 170 of fig. 1G. In some embodiments, as shown in fig. 1H, the mask layer 160, an upper portion of the spacer layer 170, and an upper portion of the dielectric material layer are removed. In some embodiments, the remaining layer of dielectric material forms dielectric layer 190.

In some embodiments, as shown in fig. 1H, 2B and 3A, a dielectric layer 190 is disposed over the source/drain structures 180 and the spacer layer 170. In some embodiments, dielectric layer 190 comprises an oxide-containing material such as silicon oxide. In some embodiments, the removal process includes a planarization process such as a chemical mechanical polishing process.

In some embodiments, as shown in fig. 1H, portions P1 of gate layer 150 and gate dielectric layer 140 are removed to form trenches 178 in spacer layer 170. In some embodiments, the trench 178 exposes the nanostructure stack 120.

In some embodiments, as shown in fig. 1H and 2B, the

nanostructures

121, 123, 125 and 127 exposed by the trench 178 are removed. In some embodiments, as shown in fig. 2B, an inner spacer layer N is formed on end portions of the

nanostructures

121, 123, 125 and 127 adjacent to the trench 178.

In some embodiments, the composition of the inner spacer layer N is an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide. In some embodiments, the inner spacer layer N may be formed by performing an oxidation process on the end portions of the

nanostructures

121, 123, 125 and 127 through the trench 178. In some embodiments, the inner spacer layer N may be formed by a deposition process (e.g., an atomic layer deposition process) and an etching process.

In some embodiments, as shown in figure 1H, a gate structure 210 is formed in trench 178. In some embodiments shown in figure 2A, gate structure 210 wraps

nanostructures

122, 124, 126, and 128 and an upper portion of fin 114. In some embodiments, the gate structure 210 includes a gate dielectric layer 212, a work function metal layer 214, and a gate layer 216.

In some embodiments, the gate dielectric layer 212 conformally covers the inner sidewalls and the lower surface of the trench 178. The composition of the gate dielectric layer is a high dielectric constant material such as hafnium oxide, zirconium oxide, hafnium zirconium oxide, aluminum oxide, or another suitable dielectric material. In some embodiments, the term "high dielectric constant material" refers to a material having a dielectric constant greater than that of silicon oxide. The gate dielectric layer 212 may be formed using an atomic layer deposition process or another suitable process.

In some embodiments, the workfunction metal layer 214 is conformally formed on the gate dielectric layer 212. The composition of the work function metal layer 214 is titanium nitride, tantalum nitride, titanium silicon nitride, or another suitable conductive material. In some embodiments, the method of forming the work function metal layer 214 employs an atomic layer deposition process.

In some embodiments, the gate layer 216 is formed on the work function metal layer 214. The composition of the gate layer 216 may be tungsten, cobalt, aluminum, or another suitable conductive material. The gate layer 216 may be formed using an atomic layer deposition process or another suitable process.

Figures 3A and 3B are cross-sectional views of various stages of a process used to form semiconductor device structures, in some embodiments. In some embodiments, as shown in figure 3B, portions of the dielectric layer 190, the spacer layer 170, and the gate dielectric layer 140 adjacent to the source/drain structures 180 are removed to form contact holes 192.

In some embodiments, contact hole 192 passes through dielectric layer 190, spacer layer 170, and gate dielectric layer 140. In some embodiments, the contact hole 192 exposes the source/drain structure 180.

In some embodiments, upper portion 184 of source/drain structure 180 has an upper surface 184a and a lower surface 184 b. In some embodiments, upper portion 184 of source/drain structure 180 has an upper surface 184a and a lower surface 184 b. In some embodiments, lower portion 182 of source/drain structure 180 has an upper surface 182 a. In some embodiments, the contact holes 192 expose the

upper surfaces

182a and 184a and the lower surface 184 b. In some embodiments, the contact hole 192 may be formed using a dry etching process, such as a non-isotropic etching process (e.g., a plasma etching process).

In some embodiments, as illustrated in figure 3B, a silicide layer 220 is formed on the source/drain structures 180. In some embodiments, the silicide layer 220 conformally covers the source/drain structures 180. In some embodiments, silicide layer 220 covers all of the exterior surfaces of each source/drain structure 180, such as

upper side surfaces

182a and 184a and lower side surface 184 b.

In some embodiments, the composition of the silicide layer 220 may be a silicide material of a suitable metal material. Suitable metallic materials may include cobalt, nickel, platinum, titanium, ytterbium, molybdenum, erbium, or combinations thereof.

In some embodiments, as shown in fig. 3B, contact structures 230 are formed in contact holes 192. In some embodiments, the contact structure 230 directly contacts the silicide layer 220. In some embodiments, the contact structure 230 passes through the dielectric layer 190, the spacer layer 170, and the gate dielectric layer 140.

In some embodiments, each contact structure 230 encapsulates the silicide layer 220 and the corresponding source/drain structure 180. In some embodiments, each contact structure 230 wraps around the upper portion 184, the neck portion 186 and the lower portion 182 of the corresponding source/drain structure 180.

The contact structure 230 may be composed of a metal material (e.g., tungsten, aluminum, gold, silver, or a combination thereof), an alloy thereof, or another suitable conductive material. The contact structure 230 may be formed by physical vapor deposition, chemical vapor deposition, or another suitable process. In some embodiments, this step substantially forms the semiconductor device structure 300.

In some embodiments, the maximum width of source/drain structure 180 is reduced (as compared to a source/drain structure without a neck and having the same height) because source/drain structure 180 has neck 186. Thus, in some embodiments, forming the neck 186 may limit the maximum width of the source/drain structure 180 to avoid shorting between two adjacent source/drain structures 180.

In some embodiments, forming the neck 186 may also increase the surface area of the source/drain structure 180. Thus, in some embodiments, the contact area between the silicide layer 220 and the source/drain structure 180 and the contact area between the silicide layer 220 and the contact structure 230 may both be increased. As such, some embodiments may reduce the resistance between the contact structure 230 and the source/drain structure 180 to improve the performance of the semiconductor device structure 300.

Fig. 4A-4C are perspective views of various stages in a process for forming a semiconductor device structure, in some embodiments. In some embodiments, as shown in fig. 4A, after the step of fig. 1E, the spacer layer 170, the gate layer 150, the lower portion 144 of the gate dielectric layer 140, and a portion of the isolation layer 130 under the lower portion 144, the upper portion 142 of the gate dielectric layer 140 that is not covered, and end portions of the nanostructures 123,124,125,126,127, and 128 are removed.

In some embodiments, the removal process includes an etching process such as a dry etching process and a chemical etching process. In some embodiments, the dry etch process comprises an anisotropic etch process, such as a plasma etch process. In some embodiments, the chemical etching process comprises an isotropic etching process such as a wet etching process or a vapor phase etching process.

Specifically, as shown in fig. 1E and 4A, the method for removing the upper portion 142 of the gate dielectric layer 140 and the end portions of the nanostructures 123,124,125,126,127 and 128 not covered by the spacer layer 170 and the gate layer 150 may employ a dry etching process. In some embodiments, the lower portion 144 of the gate dielectric layer 140 and the underlying portion of the isolation layer 130 may be removed by a chemical etching process.

Some embodiments retain the central portions of fin 114,

nanostructures

121 and 122, and nanostructures 123,124,125,126,127, and 128 after the removal process. In some embodiments, the removal process forms a recess R120 in the nanostructure stack 120 and on both sides of the gate layer 150.

In some embodiments, as shown in fig. 4A,

nanostructures

123, 125, and 127 below spacer layer 170 are removed to form recesses R1, R2, and R3 in nanostructure stack 120. In some embodiments, the recess R1 is located between the

nanostructures

122 and 124. In some embodiments, the recess R2 is located between the

nanostructures

124 and 126. In some embodiments, the depression R3 is located between the

nanostructures

126 and 128.

In some embodiments as shown in FIG. 4A, inner spacers N1, N2, and N3 are formed in recesses R1, R2, and R3, respectively. In some embodiments, the composition of the inner spacers N1, N2, and N3 is an insulating material containing an oxide, such as silicon oxide.

In some embodiments, the composition of inner spacers N1, N2, and N3 is a nitride-containing insulating material, such as silicon nitride, silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. Silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. In some embodiments, the inner spacers N1, N2, and N3 may be formed by a deposition process (e.g., a cvd process or a pvd process) and an etching process.

In some embodiments, as illustrated in fig. 4B, a source/drain structure 180 is formed in the space S and the recess R120 of the nanostructure stack 120. In some embodiments, source/drain structure 180 directly contacts fin 114 and nanostructure stack 120. In some embodiments, fin 114 and

nanostructures

121 and 122 pass through source/drain structure 180.

Fig. 5A is a cross-sectional view of the semiconductor device structure taken along the cross-sectional line I-I' of fig. 4C in some embodiments. Fig. 5B is a cross-sectional view of the semiconductor device structure taken along line II-II' of fig. 4C in some embodiments. Fig. 6A is a cross-sectional view of a semiconductor device structure taken along the cross-sectional line III-III' of fig. 4C in some embodiments.

In some embodiments, a layer of dielectric material (not shown) is formed on the source/drain structures 180 and the spacer layer 170 of fig. 4B. In some embodiments, as shown in fig. 4C, the mask layer 160, an upper portion of the spacer layer 170, and an upper portion of the dielectric material layer are removed. In some embodiments, the remaining layer of dielectric material forms dielectric layer 190.

In some embodiments, as shown in fig. 4C, 5B and 6A, a dielectric layer 190 is located over the source/drain structures 180 and the spacer layer 170. In some embodiments, dielectric layer 190 comprises an oxide-containing material such as silicon oxide. In some embodiments, the removal process includes a planarization process such as a chemical mechanical polishing process.

In some embodiments, as shown in fig. 4C, portions P1 of gate layer 150 and gate dielectric layer 140 are removed to form trenches 178 in spacer layer 170. In some embodiments, the trench 178 exposes the nanostructure stack 120.

In some embodiments, as shown in fig. 4C and 5B, the

nanostructures

121, 123, 125 and 127 exposed by the trench 178 are removed. In some embodiments, as shown in fig. 4C, 5A and 5B, a gate structure 210 is formed in trench 178.

In some embodiments, gate structure 210 wraps

nanostructures

In some embodiments, the gate dielectric layer 212 conformally covers the inner sidewalls and the lower surface of the trench 178. In some embodiments, the workfunction metal layer 214 is conformally formed on the gate dielectric layer 212. In some embodiments, the gate layer 216 is formed on the work function metal layer 214.

Fig. 6A and 6B are cross-sectional views of various stages of a process used to form a semiconductor device structure, in some embodiments. In some embodiments, as shown in figure 6B, the dielectric layer 190, the spacer layer 170 and the gate dielectric layer 140 adjacent to the source/drain structure 180 are removed to form a contact hole 192.

In some embodiments, as illustrated in fig. 6B, a silicide layer 220 is formed on the source/drain structure 180. In some embodiments, the silicide layer 220 conformally covers the source/drain structures 180. In some embodiments, silicide layer 220 covers all of the exterior surfaces of each source/drain structure 180, such as

upper side surfaces

182a and 184a and lower side surface 184 b.

In some embodiments, as shown in fig. 6B, contact structures 230 are formed in contact holes 192. In some embodiments, the contact structure 230 directly contacts the silicide layer 220. In some embodiments, the contact structure 230 passes through the dielectric layer 190, the spacer layer 170, and the gate dielectric layer 140.

In some embodiments, each contact structure 230 encapsulates the silicide layer 220 and the corresponding source/drain structure 180. In some embodiments, each contact structure 230 wraps around the upper portion 184, the neck portion 186 and the lower portion 182 of the corresponding source/drain structure 180. In some embodiments, this step substantially forms the semiconductor device structure 600.

Fig. 7A-7C are perspective views of various stages in a process for forming a semiconductor device structure, in some embodiments. In some embodiments, as shown in fig. 7A, after the step of fig. 1E, the spacer layer 170 and the gate layer 150, and the lower portion 144 and a portion of the isolation layer 130 under the lower portion 144 of the gate dielectric layer 140, the uncovered upper portion 142 of the gate dielectric layer 140 and the end portions of the nanostructures 121,122,123,124,125,126,127 and 128 are removed. In some embodiments, the removal process forms a recess R120 in the nanostructure stack 120 and on both sides of the gate layer 150.

In some embodiments, the removal process includes an etching process such as a dry etching process and a chemical etching process. In some embodiments, the dry etch process comprises an anisotropic etch process, such as a plasma etch process. In some embodiments, the chemical etching process comprises an isotropic etching process, such as a wet etching process or a vapor phase etching process.

Specifically, the method for removing the upper portion 142 of the gate dielectric layer 140 and the end portions of the nanostructures 121,122,123,124,125,126,127 and 128, which are not covered by the spacer layer 170 and the gate layer 150, may employ a dry etching process. In some embodiments, the lower portion 144 of the gate dielectric layer 140 and the underlying portion of the isolation layer 130 may be removed by a chemical etching process.

In some embodiments, since the etch selectivity of the dry etch process of fig. 7B (between the gate dielectric layer 140 and the nanostructure stack 120) is less than the etch selectivity of the dry etch process of fig. 4A, the dry etch process of fig. 7B removes more nanostructures than the dry etch process of fig. 4A.

In some embodiments, as shown in fig. 7A, the

nanostructures

121, 123, 125 and 127 under the spacer layer 170 are removed to form recesses R4, R1, R2 and R3 in the nanostructure stack 120. In some embodiments, recess R4 is located between fin 114 and nanostructure 122.

In some embodiments, the recess R1 is located between the

nanostructures

122 and 124. In some embodiments, the recess R2 is located between the

nanostructures

124 and 126. In some embodiments, the depression R3 is located between the

nanostructures

126 and 128.

In some embodiments, as shown in fig. 7A, inner spacers N1, N2, N3, and N4 are formed in recesses R1, R2, R3, and R4, respectively. In some embodiments, the composition of the inner spacers N1, N2, N3, and N4 is an insulating material containing an oxide, such as silicon oxide.

In some other embodiments, the inner spacers N1, N2, N3, and N4 are composed of a nitride-containing insulating material, such as silicon nitride, silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. In some embodiments, the inner spacers N1, N2, N3, and N4 may be formed by a deposition process (e.g., a cvd process or a pvd process) and an etching process.

In some embodiments, as illustrated in fig. 7B, source/drain structures 180 are formed in the space S and in the recess R120 of the nanostructure stack 120. In some embodiments, source/drain structure 180 directly contacts fin 114 and nanostructure stack 120. In some embodiments, fin 114 passes through source/drain structure 180.

In some embodiments, fig. 8A is a cross-sectional view of the semiconductor device structure along section line I-I ' in fig. 7C, fig. 8B is a cross-sectional view of the semiconductor device structure along section line II-II ' in fig. 7C, and fig. 9A is a cross-sectional view of the semiconductor device structure along section line III-III ' in fig. 7C.

In some embodiments, a layer of dielectric material (not shown) is formed on the source/drain structures 180 and the spacer layer 170 of fig. 7B. In some embodiments, as shown in fig. 7C, the mask layer 160, an upper portion of the spacer layer 170, and an upper portion of the dielectric material layer are removed. And an upper portion of the dielectric material layer. In some embodiments, the remaining layer of dielectric material forms dielectric layer 190.

In some embodiments, as shown in figures 7C, 8B and 9A, a dielectric layer 190 is located over the source/drain structures 180 and the spacer layer 170. In some embodiments, dielectric layer 190 comprises an oxide-containing material such as silicon oxide. In some embodiments, the removal process includes a planarization process such as a chemical mechanical polishing process.

In some embodiments, as shown in fig. 7C, a portion P1 of gate dielectric layer 140 and gate layer 150 are removed to form trench 178 in spacer layer 170. In some embodiments, the trench 178 exposes the nanostructure stack 120.

In some embodiments, as shown in fig. 7C and 8B, the

nanostructures

121, 123, 125, and 127 exposed by the trench 178 are removed. As some embodiments shown in fig. 7C, 8A, and 8B, a gate structure 210 is formed in trench 178.

In some embodiments, gate structure 210 wraps

nanostructures

Figures 9A and 9B are cross-sectional views of various stages of a process used to form semiconductor device structures, in some embodiments. In some embodiments, as shown in fig. 9B, the gate dielectric layer 140, the spacer layer 170, and the dielectric layer 190 adjacent to the source/drain structures 180 are removed to form contact holes 192.

In some embodiments, the lower portion 182 of the source/drain structure 180 has an upper surface 182a, a lower surface 182b, and a crystal plane surface 182 c. In some embodiments, each crystal plane surface 182c is connected between a corresponding upper side surface 182a and a corresponding lower side surface 182 b. In some embodiments, the lower portion 182 adjacent to the crystal face surface 182c has a corner portion 182 d. In some embodiments, the crystal plane surface 182c of the corner portion 182d is substantially flush with the upper surface 136 of the isolation layer 130.

In some embodiments, as illustrated in fig. 9B, a silicide layer 220 is formed on the source/drain structure 180. In some embodiments, the silicide layer 220 conformally covers the source/drain structures 180. In some embodiments, the silicide layer 220 covers all of the outer surface of the source/drain structure 180.

In some embodiments, as shown in fig. 9B, contact structures 230 are formed in contact holes 192. In some embodiments, the contact structure 230 directly contacts the silicide layer 220. In some embodiments, the contact structure 230 passes through the dielectric layer 190, the spacer layer 170, and the gate dielectric layer 140.

In some embodiments, each contact structure 230 encapsulates the silicide layer 220 and the corresponding source/drain structure 180. In some embodiments, each contact structure 230 wraps around the upper portion 184, the neck portion 186 and the lower portion 182 of the corresponding source/drain structure 180. In some embodiments, this step substantially forms the semiconductor device structure 900.

In some embodiments, upper surface 114a of fin 114 is higher than upper surface 136 of isolation layer 130. If upper surface 114a is lower than upper surface 136, the surface area of fin 114 for epitaxial growth is too small, and the epitaxial time for growing lower portion 182 is too long. In some embodiments, as illustrated in fig. 9B, upper surface 114a is lower than neck 186 of source/drain structure 180. In some other embodiments, shown in FIG. 9B-1, the upper surface 114a is substantially flush with the neck 186. In other embodiments, shown in fig. 9B-2, the upper surface 114a is higher than the neck 186.

Fig. 10 is a cross-sectional view of a semiconductor device structure 1000 in some embodiments. In some embodiments, as illustrated in fig. 10, the semiconductor device structure 1000 is similar to the semiconductor device structure 900 of fig. 9B, with the difference that the contact holes 192 of the semiconductor device structure 1000 extend further into the isolation layer 130.

In some embodiments, the contact holes 192 expose all of the exterior surfaces of the corresponding source/drain structures 180, such as the upper and

lower surfaces

182a and 182b of the lower portion 182 and the upper and

lower surfaces

184a and 184b of the upper portion 184. In some embodiments, the upper surface 136a of the isolation layer 130 is substantially flush with the bottom 182B of the lower portion 182. A silicide layer 220 is formed on all of the outer surface of each source/drain structure 180.

In some embodiments, the contact holes 192 extend a distance D1 into the isolation layer 130. In some embodiments, the ratio between distance D1 and thickness T130 of isolation layer 130 is about 0.05 to about 0.4. If the ratio is greater than 0.4, the isolation layer 130 is too thin to electrically isolate the overlying contact structure 230 from the underlying substrate 112, which may cause a short between adjacent contact structures 230.

Figure 11 is a cross-sectional view of a semiconductor device structure 1100 in some embodiments. In some embodiments as illustrated in fig. 11, a semiconductor device structure 1100 is similar to the semiconductor device structure 1000 of fig. 10, except that the upper portion 184 of each source/drain structure 180 has a planar upper surface 184 c. In some embodiments, the flat upper surface 184c may be formed when the contact holes 192 are formed. Thus, in some embodiments, the sharp top of the upper side portion 184 is removed when the contact hole 192 is formed. In some embodiments, the contact hole 192 and the planar upper surface 184c may be formed using a dry etching process such as a non-isotropic etching process (e.g., a plasma etching process).

Fig. 12 is a cross-sectional view of a semiconductor device structure 1200 in some embodiments. In some embodiments, as illustrated in fig. 12, a semiconductor device structure 1200 is similar to the semiconductor device structure 1100 of fig. 11, except that the contact hole 192 exposes an upper portion 184 of the corresponding source/drain structure 180, but does not expose a lower portion 182 of the corresponding source/drain structure 180.

As such, the silicide layer 220 of some embodiments covers the upper portion 184 and does not cover the lower portion 182. In some embodiments, the contact structures 230 wrap around the corresponding upper side portions 184. In some embodiments, the contact structure 230 does not pass through the dielectric layer 190, the spacer layer 170, and the gate dielectric layer 140.

In some embodiments, the dielectric layer 190 under the contact structure 230 surrounds the lower portion 182. In some embodiments, the lower boundary surface 1201 between the contact structure 230 and the dielectric layer 190 may be above, below, or substantially flush with the neck 186 of the source/drain structure 180.

In some embodiments, the diagonal portion 172 of the spacer layer 170 conformably covers the upper surface 182a of the lower portion 182. In some embodiments, the diagonal portion 172 directly contacts the upper side surface 182 a. In some embodiments, the gate dielectric layer 140 directly contacts the crystal plane surface 182c of the lower portion 182.

The processes and materials used to form the

semiconductor device structures

1000,1100, and 1200 may be similar or identical to those described above for the semiconductor device structures 300,600, and 900.

In some embodiments, semiconductor device structures and methods of forming the same are provided. A method for forming a semiconductor device structure may include forming a slanted spacer layer in a source/drain region and on both sides of a fin, removing a structure under the slanted spacer layer to form a space between the fin and the slanted spacer layer, and forming a source/drain structure in and on the space to have a double diamond shape. The formation of the slanted spacer layer can limit the maximum width of the source/drain structures to prevent the adjacent two source/drain structures from being shorted. Since the surface area of the dual diamond-shaped source/drain structure is larger than that of the single diamond-shaped source/drain structure, the formation of the slanted spacer layer increases the surface area of the source/drain structure. The contact area between the silicide layer and the source/drain structure and the contact area between the silicide layer and the contact structure can be increased. Thus, the resistance between the contact structure and the source/drain structure can be reduced, thereby improving the performance of the semiconductor device structure.

In some embodiments, sequentially forming a gate dielectric layer and a gate layer on the first nanostructure, the second nanostructure, and the fin comprises: forming a gate dielectric layer on the fin, the first nanostructure, the second nanostructure, and the isolation layer; forming a gate material layer on the gate dielectric layer; and partially removing the gate material layer, and the gate dielectric layer under the removed gate material layer, wherein the remaining gate material layer forms a gate layer, the gate dielectric layer not covered by the gate layer forms a second portion, and the second portion on the first upper portion has a sloped sidewall.

In some embodiments, the second portion of the gate dielectric layer on the second nanostructure is thinner than the first portion of the gate dielectric layer.

In some embodiments, the method further comprises: after removing the second portion of the gate dielectric layer and the first upper portion of the isolation layer and before forming the source/drain structure in the space and over the first and second nanostructures, the isolation layer originally under the first upper portion is partially removed to enlarge the space.

In some embodiments, the method further comprises: forming a dielectric layer on the source/drain structure and the spacer layer after forming the source/drain structure in the space and on the first nanostructure and the second nanostructure; removing the gate layer and the first portion of the gate dielectric layer to form a trench in the spacer layer, wherein the trench exposes the first nanostructure and the second nanostructure; removing the first nanostructure exposed by the groove; and forming a gate structure in the trench, wherein the gate structure encapsulates the second nanostructure and the second upper portion of the fin.

In some embodiments, the method further comprises: after forming the grid structure in the groove, partially removing the spacer layer and the dielectric layer on the source/drain structure to form a contact hole in the dielectric layer and the spacer layer, wherein the contact hole exposes the source/drain structure; and forming a contact structure in the contact hole and on the source/drain structure.

In some embodiments, the contact structure wraps around the source/drain structure.

In some embodiments, the source/drain structure has a second upper portion, a lower portion, and a neck portion between the second upper portion and the lower portion, the second upper portion being wider than the neck portion, the lower portion being located in the space, and the second upper portion being located outside the space.

In some embodiments, the source/drain structure has an upper portion and a lower portion, the lower portion is in the space, the upper portion is on the space and the diagonal portion of the spacer layer, and the upper portion covers the first nanostructure and the second nanostructure.

In some embodiments, the lower portion has a diamond shape.

In some embodiments, the upper portion has a diamond shape.

In some embodiments, the method further comprises: forming a dielectric layer on the source/drain structure and the spacer layer; removing a portion of the dielectric layer and the oblique portion of the spacer layer to form a contact hole exposing the source/drain structure; and forming a contact structure in the contact hole.

In some embodiments, the first nanostructure further penetrates the source/drain structure.

In some embodiments, the semiconductor device structure further comprises: the second nanostructure passes through the source/drain structure and is located between the first nanostructure and the fin, wherein the second nanostructure directly contacts the first nanostructure and the fin.

In some embodiments, the upper portion is wider than the lower portion.

In some embodiments, the upper portion is thicker than the lower portion.

In some embodiments, the semiconductor device structure further comprises: an isolation layer on the substrate, wherein the fin portion is embedded in the isolation layer and a lower portion of the source/drain structure is partially embedded in the isolation layer.

In some embodiments, the semiconductor device structure further comprises: a silicide layer overlying the source/drain structure; and a contact structure covering the silicide layer and the source/drain structure.

The features of the above-described embodiments are helpful to those skilled in the art in understanding the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced above. It should also be understood by those skilled in the art that such equivalent substitutions may be made without departing from the spirit and scope of the present invention, and that changes, substitutions, or alterations may be made without departing from the spirit and scope of the present invention.

Claims

1. A method of forming a semiconductor device structure, comprising:

providing a substrate, a first nanostructure and a second nanostructure, wherein the substrate has a base and a fin on the base, and the first nanostructure and the second nanostructure are sequentially stacked on the fin;

forming an isolation layer on the substrate, wherein a width of a first upper portion of the isolation layer increases toward the substrate;

forming a gate dielectric layer on the first nanostructure, the second nanostructure, the fin, and the isolation layer, wherein the gate dielectric layer has a first portion and a second portion;

forming a gate layer on the first portion;

forming a spacer layer on a first sidewall of the gate layer, a second sidewall of the first portion of the gate dielectric layer, and a third sidewall of the second portion of the gate dielectric layer over the first upper portion of the isolation layer;

removing the second portion of the gate dielectric layer and the first upper portion of the isolation layer to form a space between the fin and the spacer layer; and

forming a source/drain structure in the space and on the first nanostructure and the second nanostructure.