TWI825786B - Semiconductor device with bit line contacts of different pitches - Google Patents

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate defining a plurality of trenches; and a plurality of bit line contacts disposed on the substrate, wherein at least one of the plurality of bit line contacts is disposed within one of the trenches defined by the substrate, wherein the plurality of trenches has a first row and a second row, and a pitch of the first row is different from a pitch of the second row.

Description

Semiconductor device with bit line contacts at different pitches

This application claims priority to U.S. Patent Application Nos. 17/725,551 and 17/726,004 (that is, the priority date is "April 21, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor device. In particular, it relates to a semiconductor device having a plurality of bit line contact points with different pitches.

With the rapid development of the electronics industry, integrated circuits (ICs) have achieved high performance and miniaturization. Technological advances in IC materials and design have produced several generations of ICs, each with smaller and more complex circuits.

Bit line contacts are used to establish connections in or between different features of a semiconductor structure. Bit line contacts may be formed in a trench defined by a substrate. The substrate may be chopped to form a trench in which the bit line contacts are formed. In some cases, the trench in one edge of a cell region may have only half an outline compared to the trench opposite a central region. However, such half-profile trenches can cause leakage between a bit line and a cell contact. Therefore, there is a need for a new semiconductor component and a method for improving these problems.

The above description of "prior art" only provides background technology, and does not admit that the above description of "prior art" reveals the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and any description of the above "prior art" does not constitute the prior art of the present disclosure. should not be used as any part of this case.

An embodiment of the present disclosure provides a method of manufacturing a semiconductor device. The preparation method includes providing a substrate including a plurality of active regions separated from each other. The preparation method also includes forming a plurality of mask structures on the substrate. The preparation method also includes forming a first protective layer to cover the first mask structures and the substrate. The first protective layer defines an area that exposes a portion of the first mask structures and the substrate, and from a top view, the area defined by the first protective layer has a zigzag edge. . In addition, the preparation method includes performing a first etching process to form a plurality of trenches defined by the substrate.

Another embodiment of the present disclosure provides a method of manufacturing a semiconductor device. The preparation method includes providing a substrate including a plurality of active regions separated from each other. The preparation method also includes forming a plurality of first mask structures on the substrate. The preparation method also includes forming a first protective layer to cover the first mask structures and the substrate. The first protective layer defines a first area that exposes the first mask structures and the substrate. Parts of the first mask structures are partially covered by the first protective layer. In addition, the preparation method includes performing a first etching process to remove the substrate exposed from the first mask structures and the first region to form a plurality of trenches.

Yet another embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate and a plurality of bit line contacts. The substrate defines a plurality of trenches. The plurality of bit line contact points are disposed on the substrate. At least one bit line contact is disposed within one of the trenches defined by the substrate. The plurality of trenches has a first row and a second row, and the first row A spacing of is different from a spacing of the second column.

Embodiments of the present disclosure illustrate a semiconductor device having multiple bit line contacts. In this embodiment, the insulating spacer adjacent the bit line contact may have an integral profile, thereby preventing an electrical short between the bit line and the capacitor contact or trench.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

100a: Semiconductor components

100b: Semiconductor components

110A:Unit area

110B: Surrounding area

112: Base

114:Insulation structure

116:Bit line contact point

116':Conductive layer

1161: column

1162: column

1163: OK

1164: OK

116a:Bit line contact point

118:Dielectric layer

120: Bit line stacking

120':Barrier layer

122:Bit line

122':Metalization layer

1221:Bit line

1222:Bit line

124:Dielectric layer

132: Mask structure

1321: column

1322: column

1323: column

132p1: part

134:Protective layer

134e:edge

134s1:Side

134s2:Side

136:Trench

1361: column

1362: column

1363: OK

1364: OK

138: Mask structure

140: Spacing adjustment structure

142:Protective layer

142s1:Side

142s2: Side

150: Insulation spacer

150a: Insulation spacer

152: Capacitor contact point

154:Stacked structure

156:Conductive layer

158:Trench

20:Active zone

200:Preparation method

202:Step

204:Step

206:Step

208:Step

21:Part

210: Step

212: Step

214: Step

216:Step

218:Step

22:Part

220:Step

D1: Direction

D2: Direction

P1: Etching process

P2: Etching process

R1:Region

R2:Region

T1: spacing

T2: Spacing

T3: spacing

T4: spacing

T5: Spacing

T6: spacing

T7: spacing

T8: Spacing

X: direction

Y: direction

A more complete understanding of the present disclosure can be obtained by referring to the detailed description and claimed claims. The present disclosure should also be understood to be associated with the drawing element numbering, which represents similar elements throughout the description.

FIG. 1A is a top view schematic diagram illustrating a semiconductor device according to some embodiments of the present disclosure.

FIG. 1B is a schematic cross-sectional view illustrating a cross-section along line AA' of the semiconductor device of FIG. 1A according to some embodiments of the present disclosure.

FIG. 2 is a schematic flowchart illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

FIG. 3A is a schematic diagram illustrating one or more stages of an example of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

FIG. 3B is a schematic cross-sectional view illustrating a cross-section along line A-A' of FIG. 3A according to some embodiments of the present disclosure.

FIG. 4A is a schematic diagram illustrating one or more stages of an example of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

FIG. 4B is a schematic cross-sectional view illustrating some embodiments of the present disclosure along the cross-section line A-A' of FIG. 4A.

FIG. 5A is a schematic diagram illustrating one or more stages of an example of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

FIG. 5B is a schematic cross-sectional view illustrating a cross-section along line A-A' of FIG. 5A according to some embodiments of the present disclosure.

FIG. 6A is a schematic diagram illustrating one or more stages of an example of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

FIG. 6B is a schematic cross-sectional view illustrating a cross-section along line A-A' of FIG. 6A according to some embodiments of the present disclosure.

FIG. 7A is a schematic diagram illustrating one or more stages of an example of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

FIG. 7B is a schematic cross-sectional view illustrating a cross-section along line A-A' of FIG. 7A according to some embodiments of the present disclosure.

FIG. 8A is a schematic diagram illustrating one or more stages of an example of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

8B is a schematic cross-sectional view illustrating some embodiments of the present disclosure along the cross-section line A-A' of FIG. 8A.

9A is a schematic diagram illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. One or more stages of an example.

FIG. 9B is a schematic cross-sectional view illustrating some embodiments of the present disclosure along the cross-section line A-A' of FIG. 9A.

FIG. 10A is a schematic diagram illustrating one or more stages of an example of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

FIG. 10B is a schematic cross-sectional view illustrating a cross-section along line A-A' of FIG. 10A according to some embodiments of the present disclosure.

FIG. 11A is a schematic diagram illustrating one or more stages of an example of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

11B is a schematic cross-sectional view illustrating a cross-section along line A-A' of FIG. 8A according to some embodiments of the present disclosure.

FIG. 12A is a schematic diagram illustrating one or more stages of an example of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

12B is a schematic cross-sectional view illustrating some embodiments of the present disclosure along the cross-section line A-A' of FIG. 8A.

FIG. 13 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure.

Specific language will now be used to describe the embodiments or examples of the present disclosure illustrated in the drawings. It should be understood that the scope of the present disclosure is not intended to be limited thereby. Any modifications or improvements to the described embodiments, as well as any further applications of the principles described in this document, are within the realm of ordinary skill in the art. Element numbers may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment apply to another embodiment even if they share the same element number.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, These elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, a "first element", "component", "region", "layer" or "section" discussed below may be referred to as a second device , component, region, layer or portion without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and/or "comprising" are used in this specification, these terms specify the stated features, integers, steps, operations, elements, and/or components. exists, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups of the above.

Please refer to FIGS. 1A and 1B . FIG. 1A is a top view schematic diagram illustrating the semiconductor device 100 a of some embodiments of the present disclosure. FIG. 1B is a cross-sectional schematic diagram illustrating the semiconductor device 100 a of some embodiments of the present disclosure along the sectional line A-. Section A'. It should be understood that some elements are omitted from Figure IB for the sake of brevity.

In some embodiments, the semiconductor device 100a may include a unit region 100A and a surrounding region 100B.

In some embodiments, the cell region 100A may be an area in which a memory device is formed. For example, the memory device may include a dynamic random access memory (DRAM) device, a one-time programmable (OTP) memory device, a static random access memory (SRAM) components or other suitable memory components. In some embodiments, a DRAM may include a transistor, a capacitor, and other components, for example. During a read operation, a word line may be asserted, turning on the transistor. The enabled transistor allows the voltage across the capacitor to be read by a sense amplifier via a bit line. During a write period, when the word line is asserted, the data written is provided on the bit line.

Surrounding area 100B may be an area used to form a logic device (eg, system on chip (SoC), central processing unit (CPU), graphics processing unit (GPU), application processor (AP), microprocessor, etc. ), a radio frequency (RF) component, a sensor component, a microelectromechanical system (MEMS) component, a signal processing component (such as a digital signal processing (DSP) component), a front-end component (such as an analog front-end (AFE) component) or other components.

Semiconductor device 100a may include a substrate 112. The substrate 112 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The substrate 112 may include an elemental semiconductor, including silicon or germanium in a single crystalline form, a polycrystalline form, or an amorphous form; a compound semiconductor material, including at least one of the following: silicon carbide, gallium arsenide, and gallium phosphide. , indium phosphide, indium arsenide and indium antimonide; an alloy semiconductor material, including at least one of the following: SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP; any other suitable material; or a combination thereof. In some embodiments, the alloy semiconductor substrate may be a SiGe alloy having a gradient Ge feature, wherein the composition of Si to Ge changes from one ratio at one location of the gradient SiGe feature to another ratio at another location of the gradient SiGe feature . In other embodiments, the SiGe alloy is formed on a silicon substrate. In some embodiments, a SiGe alloy can be mechanically strained by another material in contact with the SiGe alloy. In some embodiments, the substrate 112 may have a multi-layer structure, or the substrate 112 may include a multi-layer compound semiconductor structure.

In some embodiments, substrate 112 may include multiple active regions 20 . For example, the active area 20 can be used as a channel for electrical connection. In some embodiments, the active region 20 may be disposed within the cell region 100A of the semiconductor device 100a.

In some embodiments, semiconductor device 100a may include an insulating structure 114. In some embodiments, active regions 20 may be separated by the insulating structures 114 . In some embodiments, insulating structure 114 may be embedded in substrate 112 . In some embodiments, for example, the insulating structure 114 may include silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon nitride oxynitride (Si ₂ ON ₂ ), silicon oxynitride (Si ₂ N ₂ O) or other suitable materials.

In some embodiments, semiconductor device 100a may include a plurality of bit line contacts 116. In some embodiments, at least one bit line contact 116 may be disposed on the active region 20 of the substrate 112 . Bit line contacts 116 may include metals such as W, Cu, Ru, Ir, Ni, Os, Rh, Al, Mo, Co, alloys thereof, combinations thereof, or any metallic material with suitable resistance and gap filling capabilities. In some embodiments, at least one bit line contact 116 may be disposed within a trench 136 recessed from an upper surface of the substrate 112 .

In some embodiments, semiconductor device 100a may include a dielectric layer 118. Dielectric layer 118 may be disposed on substrate 112 . In some embodiments, dielectric layer 118 may cover a portion of insulating structure 114 . In some embodiments, dielectric layer 118 may be used to define trench 136 . In some embodiments, for example, dielectric layer 118 may include silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (Si ₂ ON ₂ ), silicon oxynitride (Si ₂ N ₂ O), a high dielectric constant material, or a combination thereof. Examples of the high-k material include a dielectric material having a dielectric constant higher than silicon dioxide, or a dielectric material having a dielectric constant higher than about 3.9. In some embodiments, the dielectric layer 118 may include at least one metal element, such as HfO ₂ , HSO (silicon doped hafnium oxide), La ₂ O ₃ , LaAlO ₃ , ZrO ₂ , ZrSiO ₄ , Al ₂ O ₃ or combinations thereof .

In some embodiments, at least one active region 20 may have a portion that does not overlap the dielectric layer 118 in a top view.

In some embodiments, semiconductor device 100a may include a plurality of bit line stacks 120. In some embodiments, at least bit line stack 120 may extend along the X direction. In some embodiments, a portion of the bit line stack 120 may be disposed on the bit line contact 116 . In some embodiments, a portion of the bitline stack 120 may contact the bitline contact 116 . In some embodiments, a portion of the bit line stack 120 may be electrically connected to the bit line contacts 116 . In some embodiments, a portion of the bit line stack 120 may be disposed on the dielectric layer 118 . In some embodiments, a portion of the bit line stack 120 may contact the dielectric layer 118 . In some embodiments, a portion of the bit line stack 120 may be electrically isolated from the bit line contacts 116 . Bit line stack 120 may include titanium, tantalum, titanium nitride, tantalum nitride, manganese nitride, or combinations thereof.

In some embodiments, semiconductor device 100a may include a plurality of bit lines 122. In some embodiments, at least one bit line 122 may extend along an X direction. In some embodiments, at least one bit line 122 may be disposed on bit line stack 120 . In some embodiments, a portion of the bit lines 122 may be disposed on the bit line stack 116 . In some embodiments, a portion of the bit lines 122 may be electrically connected to the bit line contacts 116 . In some embodiments, a portion of the bit lines 122 may be disposed on the dielectric layer 118 . In some embodiments, a portion of the bit lines 122 may be electrically isolated from the bit line contacts 116 . Bit lines 122 may include metals such as W, Cu, Ru, Ir, Ni, Os, Rh, Al, Mo, Co, alloys thereof, or combinations thereof.

In some embodiments, semiconductor device 100a may include multiple dielectric layers 124. In some embodiments, at least one dielectric layer 124 may extend along the X direction. In some embodiments, at least one dielectric layer 124 may be disposed on bit line 122 . In some embodiments, for example, dielectric layer 124 may include silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (Si ₂ ON ₂ ), silicon oxynitride (Si ₂ N ₂ O), a high dielectric constant material, or a combination thereof. Examples of the high-k material include a dielectric material having a dielectric constant higher than silicon dioxide, or a dielectric material having a dielectric constant higher than about 3.9. In some embodiments, the dielectric layer 124 may include at least one metal element, such as HfO ₂ , HSO (silicon doped hafnium oxide), La ₂ O ₃ , LaAlO ₃ , ZrO ₂ , ZrSiO ₄ , Al ₂ O ₃ or combinations thereof .

In some embodiments, the semiconductor device 100a may further include a plurality of word lines (not shown). At least one character line may extend along the Y direction. The word lines may be generally perpendicular to the bit lines 122 .

As shown in FIG. 1B , trenches 136 may be recessed from the upper surface of substrate 112 . In some embodiments, a portion of insulating structure 114 may be exposed from trench 136 . In some embodiments, trench 136 may be surrounded by dielectric layer 118 . Although FIG. 1A illustrates trench 136 as having a boundary concave surface relative to dielectric layer 118, trench 136 may have other contours, such as circular, elliptical, or other suitable contours in other embodiments.

As shown in FIG. 1A , the trenches 136 may have one column 1361 and one column 1362 . In some embodiments, a pitch T1 of the rows 1361 of trenches 136 may be different from a pitch T2 of the rows 1362 of trenches 136 . In some embodiments, the pitch T1 of the rows 1361 of trenches 136 may exceed the pitch T2 of the rows 1362 of trenches 136 . In some embodiments, pitch T1 may be approximately twice the pitch T2. In some embodiments, column 1361 of trenches 136 may be the outermost column. In some embodiments, the row 1361 of trenches 136 may be the uppermost row (or lowermost row) from a top view within a cell region 110A.

In some embodiments, the trenches 136 may have a row 1363 and a row 1364 . In some embodiments, a pitch T3 of the rows 1363 of trenches 136 may be different from a pitch T4 of the rows 1364 of trenches 136 . In some embodiments, the pitch T3 of the rows 1363 of trenches 136 may exceed the pitch T4 of the rows 1364 of trenches 136 . In some embodiments, pitch T3 may be approximately twice the pitch T4. In some embodiments, row 1363 of trenches 136 may be the outermost row. In some embodiments, the row 1363 of trenches 136 may be the leftmost row (or rightmost row) from a top view within a cell region 111A.

As shown in FIG. 1A , the bit line contact points 116 may have a column 1161 and a column 1162 . In some embodiments, a pitch T5 of the rows 1161 of bit line contact points 116 may be different from a pitch T6 of the rows 1162 of the bit line contact points 116 . In some embodiments, the pitch T5 of the columns 1161 of the bit line contact points 116 may exceed the pitch T6 of the columns 1162 of the bit line contact points 116 . In some embodiments, pitch T5 may be approximately twice the pitch T6. In some embodiments, the column 1161 of bit line contacts 116 may be the outermost column. In some embodiments, the column 1161 of bit line contact points 116 may be the topmost column (or bottommost column) from a top view within a cell region 110A.

In some embodiments, the bit line contacts 116 may have a row 1163 and a row 1164 . In some embodiments, a pitch T7 of the rows 1163 of bit line contact points 116 may be different from a pitch T8 of the row 1164 of the bit line contact points 116 . In some embodiments, the pitch T7 of the rows 1163 of bit line contact points 116 may exceed the pitch T8 of the row 1164 of the bit line contact points 116 . In some embodiments, pitch T7 may be approximately twice the pitch T8. In some embodiments, the row 1163 of bitline contact points 116 may be the outermost row. In some embodiments, the row 1163 of bit line contacts 116 may be the leftmost row (or the rightmost row) from a top view of a cell region 110A.

In this embodiment, the trenches 136 in the outermost column (or row) may have the same overall profile as an inner row. For example, the profile of trenches 136 in column 1361 may be substantially the same as the profile of column 1362 . In this embodiment, the spacing of the trenches 136 in the outermost row (eg, 1361) is different from the spacing of the trenches 136 in one of the inner rows of the trenches 136 (eg, 1362). In a comparative semiconductor element, the trenches in the outermost column (or row) may have only half the outline compared to the trenches in an inner column. As a result, the side wall of the bit line contact in the outermost column (or row) may not have an insulating spacer, resulting in leakage between the bit line and a capacitor contact. In this embodiment, since the trenches 136 of the outermost column (or row) have an overall profile, insulating spacers can be formed on both sides of the bit line contact point, thereby preventing the bit line 122 from contacting the capacitor. An electrical short circuit between points of contact.

FIG. 2 is a schematic flowchart illustrating a method 200 for manufacturing a semiconductor device according to some embodiments of the present disclosure.

The preparation method 200 begins with step 202, which is providing a substrate. The substrate may include multiple active regions. The plurality of active regions can be separated by an insulating structure. A first dielectric layer can be formed on the substrate. The first dielectric layer can cover the active region and the insulating structures.

The preparation method 200 continues with step 204, in which a plurality of first mask structures may be formed. The first mask structures may be staggered. The first mask structures may have a first column, a second column and a third column. At least one first mask structure in the first column can be aligned with a corresponding structure in the third column. The first mask structures in the first column and the second mask structures in the second column may be interleaved. At least one active region may have a first portion that does not vertically overlap the first mask structures. From a top view, the first portion of the first active area may be surrounded by the first mask structures. At least one active area may have a second portion vertically overlapping the first mask structures. At least one active zone can match two of them The first mask structures overlap vertically.

The preparation method 200 continues with step 206, which may form a first protective layer. The first protective layer can be used to define a first region for etching by a subsequent first etching. The first protective layer may cover a portion of the first mask structures. The first protective layer may include a photosensitive material. A portion of the first mask structures may be partially covered by the first protective layer. The portion of the first mask structures may be partially exposed by the first mask structures. The first protective layer may cover a portion of the substrate. Viewed from a top view, the first protective layer may have a zigzag edge. The edge of the first protective layer does not intersect the first portion of the active area.

The first protective layer may have a first side and a second side, the first side extending along a first direction, the second side extending along a second direction, and the second direction is different from the First direction. The first direction may be inclined relative to the X direction. The first direction may be inclined relative to the Y direction. The second direction may be inclined relative to the X direction. The second direction may be inclined relative to the Y direction. The first side of the first protective layer is generally perpendicular to the second side of the first protective layer. The first side of the first protective layer may not intersect the first portion of the active area. The second side of the first protective layer may not intersect the first portion of the active area. The first side of the first protective layer may span two or more first mask structures in different columns. The second side of the first protective layer may span two or more first mask structures in different columns.

Furthermore, the semiconductor device may include a plurality of word lines embedded in the substrate. At least one character line may be substantially parallel to the Y direction. From a top view, the first side of the first protective layer may be tilted relative to the word line. Viewed from a top view, the second side of the first protective layer may be inclined relative to the word line.

The manufacturing method 200 continues with step 208, which is to perform a first etching process. The first dielectric layer exposed by the first protective layer and exposed by the first mask structures can be removed. The substrate exposed by the first protective layer and exposed by the first mask structures can be removed.

A portion of the insulating structure can be removed. Parts of these active zones may be removed. A portion of the first dielectric layer may remain on the substrate. Multiple trenches can be formed. The manufacturing technology of the plurality of trenches may include the first etching processes. The trenches may be recessed from the substrate. The trenches may be recessed from the first dielectric layer. At least one trench may be defined by the first dielectric layer, the substrate, and the insulating structure.

After the first etching process, the first mask structures can be removed. After the first etching process, the first protective layer can be removed. A portion of the first dielectric layer may be removed through a chemical mechanical polishing process.

The trenches may have a first row and a second row. A pitch of the first row of trenches may be different from a pitch of the second row of trenches. The pitch of the first row of trenches may exceed the pitch of the second row of trenches. The first row of the trenches may be the outermost row. The pitch of the first row of trenches may be approximately twice the pitch of the second row of trenches. From a top view, the first row of the trenches may be the uppermost row (or lowermost row).

The trenches may have a first row and a second row. A pitch of the first row of trenches may be different from a pitch of the second row of trenches. The pitch of the first row of trenches may exceed the pitch of the second row of trenches. The pitch of the first row of trenches may be approximately twice the pitch of the second row of trenches. The first row of the trenches may be the outermost row. From a top view, the first row of the trenches may be the leftmost row (or the rightmost row).

The preparation method 200 continues with step 210, which may form a conductive layer. The conductive layer can fill the trenches. The conductive layer may be surrounded by the first dielectric layer.

The preparation method 200 continues with step 212 of forming a barrier layer, a metallization layer and a second dielectric layer. The barrier layer can cover the substrate. The barrier layer can cover the first dielectric layer. The metallization layer can be configured to form a plurality of bit lines. The metallization layer can cover the barrier layer. The second dielectric layer can cover the metallization layer.

The manufacturing method 200 continues with step 214, which is to form a plurality of second mask structures and a pitch adjustment structure. The second mask structures may cover the second dielectric layer. A portion of the metallization layer may be exposed from the second mask structures. A portion of the barrier layer may be exposed from the second mask structures. A portion of the second dielectric layer may be exposed from the second mask structures. A portion of the conductive layer may not vertically overlap the second mask structures.

The spacing adjustment structure may be conformally formed on the second mask structures. The spacing adjustment structure can be used to reduce the gap defined by the second mask structures. A portion of the spacing adjustment structure may be disposed between a plurality of openings defined by the second shield structures.

The preparation method 200 continues with step 216, which may form a second protective layer. The second protective layer can be used to define a second region for etching by subsequently performing a second etching process. The second area may be rectangular or square. A portion of the substrate may be exposed through the second protective layer. A portion of the second mask structures may be exposed through the second protective layer. A portion of the spacing adjustment structure may be exposed through the second protective layer.

The second protective layer may include a first side and a second side, the second side being substantially perpendicular to the first side. The first side of the first protective layer may be inclined relative to the first side of the second protective layer. The first side of the first protective layer may be inclined relative to the second side of the second protective layer. The second side of the first protective layer may be inclined relative to the first side of the second protective layer. This section The second side of a protective layer may be inclined relative to the second side of the second protective layer.

The manufacturing method 200 continues with step 218, which is to perform a second etching process. The second dielectric layer exposed by the second protective layer and exposed by the second mask structures can be removed. The metallization layer exposed by the second protective layer and exposed by the second mask structures can be removed, thereby forming a plurality of bit lines extending along the X direction. The barrier layer exposed by the second protective layer and exposed by the second mask structures can be removed, thereby forming a plurality of bit line stacks extending along the X direction.

After the second etching process, the second protective layer can be removed. After the second etching process, the second mask structures can be removed. After the second etching process, the pitch adjustment layer can be removed. A portion of the conductive layer may be exposed by the stack of bit lines. The portion of the conductive layer may be exposed through the bit lines. The portion of the conductive layer may be exposed through the second conductive layer. A portion of the bit lines may be disposed on the conductive layer. A portion of the bit lines may be disposed on the first conductive layer. A portion of the bit lines may be disposed on the insulating structure.

The method 200 continues with step 220 of removing a portion of the conductive layer, thereby producing a semiconductor device.

In some embodiments, the portion of the conductive layer exposed by the bit lines may be removed, thereby forming a plurality of bit line contacts. At least one bit line contact can be formed within the trench defined by the substrate. At least one bit line contact can be connected via the bit line. In some embodiments, the bit line contacts may have a first column and a second column. In some embodiments, the first column of bit line contacts may be connected by a bit line. In some embodiments, the second column of bit line contacts may be connected by a second bit line. A pitch of the first row of bit line contact points may be different from the bit line contact Click a spacing of the second column. In some embodiments, the pitch of the first column of bit line contacts may exceed the spacing of the second column of bit line contacts. The pitch of the first row of equal bit line contacts may be approximately twice the pitch of the second row of equal bit line contacts. In some embodiments, the first column of the bit line contacts may be the outermost column. In some embodiments, the first column of the bit line contacts may be the uppermost column (or the lowermost column) from a top view within a cell region of the semiconductor device.

In some embodiments, the bit line contacts may have a first row and a second row. A pitch of the first row of bit line contact points may be different from a pitch of the second row of bit line contact points. In some embodiments, the pitch of the first row of bit line contact points may exceed the pitch of the second row of bit line contact points. The spacing of the first row of equal bit line contacts may be approximately twice the spacing of the second row of equal bit line contacts. In some embodiments, the first row of bitline contact points may be the outermost row. In some embodiments, the first row of bit line contacts may be the leftmost row (or rightmost row) from a top view within a cell region of the semiconductor device.

In this embodiment, the first protective layer having a specific profile, such as a zigzag shape, is used to define an area on which an etching is performed. By using the aforementioned first protective layer, the trench in the outermost column (or row) can have an overall profile compared to an inner trench, thereby avoiding contact with the capacitor at the bit line An electrical short circuit between points.

The preparation method 200 is only an example and is not intended to limit the present disclosure beyond the scope explicitly stated in the patent application. Additional steps may be provided before, during, or after each step of the preparation method 200, and some of the steps described may be replaced, eliminated, or reordered for additional embodiments of the preparation method. In some embodiments, the preparation method 200 may include further steps not shown in FIG. 2 . In some embodiments, preparation methods 200 may include one or more steps illustrated in FIG. 2 .

3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, and 12A illustrate one or more exemplary methods for manufacturing semiconductor devices according to some embodiments of the present disclosure. stage; and Figures 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B and 12B are along the lines of Figures 3A, 4A, 5A, 6A and 7A respectively. , Figure 8A, Figure 9A, Figure 10A, Figure 11A and Figure 12A are cross-sectional views of AA'. It should be understood that some elements are omitted from FIGS. 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, and 12A for the sake of brevity.

Referring to FIG. 3A and FIG. 3B , a substrate 112 is provided. In some embodiments, substrate 112 may include multiple active regions 20 . In some embodiments, active regions 20 may be separated by an insulating structure 114 . A dielectric layer 118 may be formed on the substrate 112 . In some embodiments, the substrate 112 may cover the active region 20 and the insulating structures 114 . In some embodiments, multiple word lines (not shown) may be formed within the substrate 112 . At least one character line may extend along the Y direction. In some embodiments, the word lines are tilted relative to a long axis of at least one active region 20 . The semiconductor device may include a unit region 110A and a surrounding region 110B.

Referring to FIGS. 4A and 4B , multiple mask structures 132 can be formed. In some embodiments, the manufacturing technology of the mask structures may include chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low pressure chemical vapor deposition (LPCVD), or other suitable process. In some embodiments, the mask structures 132 may be circular or other suitable shapes when viewed from a top view.

In some embodiments, the mask structures 132 may be staggered. In some embodiments, the mask structures 132 may have multiple columns 1321, 1322, and 1323. Column 1322 may be disposed between columns 1321 and 1323. At least one mask structure 132 in column 1321 may be aligned in column 1321 A corresponding structure in 1323. In some embodiments, the mask structures 132 in column 1321 and the mask structures 132 in column 1322 may be interleaved.

At least one active area 20 may have a portion that does not vertically overlap the mask structures 132 . In some embodiments, the portion of active area 20 may be surrounded by the mask structures 132 from a top view. At least one active area 20 may have a portion 22 that vertically overlaps the mask structures 132 . At least one active area 20 may vertically overlap two or more mask structures 132 .

Referring to FIG. 5A and FIG. 5B , a protective layer 134 can be formed. In some embodiments, the protective layer 134 can be used to define a region R1 for sequential etching. In some embodiments, the protective layer 134 may cover a portion of the mask structures 132 . In some embodiments, the protective layer 134 may include a photosensitive material.

In some embodiments, a portion 132p1 of the mask structures 132 may be partially covered by the mask structures 132. In some embodiments, the portions 132p1 of the mask structures 132 may be partially exposed by the protective layer 134. In some embodiments, protective layer 134 may cover a portion of substrate 112 .

In some embodiments, the protective layer 134 may have an edge 134e. In one embodiment, edge 134e may have a zigzag shape when viewed from a top view. In some embodiments, edge 134e of protective layer 134 may not intersect portion 21 of active region 20 from a top view.

In some embodiments, the protective layer 134 may have one side 134s1 and a side 134s2. The side 134s1 extends along a direction D1 and the side 134s2 extends along a direction D2, and the direction D2 is different from the direction D1. In some embodiments, direction D1 may be tilted relative to the X direction. In some embodiments, direction D1 may be tilted relative to the Y direction. In some embodiments , direction D2 may be inclined relative to the X direction. In some embodiments, direction D2 may be tilted relative to the Y direction. In some embodiments, a plurality of word lines (not shown) are formed in the substrate 112 . The character line can extend along the Y direction. In some embodiments, the side 134s1 of the protective layer 134 may be inclined relative to the word line. In some embodiments, the side 134s2 of the protective layer 134 may be tilted relative to the word line.

In some embodiments, the side 134s1 of the protective layer 134 may be substantially perpendicular to the side 134s2 of the protective layer 134 . In some embodiments, the side 134s1 of the protective layer 134 may not intersect the portion 21 of the active region 20 from a top view. In some embodiments, the side 134s2 of the protective layer 134 may not intersect the portion 22 of the active region 20 when viewed from a top view. In some embodiments, from a top view, the side 134s1 of the protective layer 134 may span two or more mask structures 132 in different columns. In some embodiments, from a top view, the side 134s2 of the protective layer 134 may span two or more mask structures 132 in different columns.

Please refer to FIG. 6A and FIG. 6B to perform an etching process P1. The etching process P1 may include a dry etching, a wet etching or other suitable processes. In some embodiments, dielectric layer 118 exposed by protective layer 134 and exposed by mask structure 132 may be removed. In some embodiments, the substrate 112 exposed by the protective layer 134 and exposed by the mask structures 132 may be removed. In some embodiments, portions of the insulating structures 114 may be removed.

In some embodiments, a portion of the active areas 20 may be removed. In some embodiments, a portion of dielectric layer 118 may remain on substrate 112 .

In some embodiments, multiple trenches 136 may be formed. In some embodiments, the fabrication technology of the plurality of trenches 136 may include an etching process P1. In some embodiments, the trenches 136 may be recessed from the substrate 112 . In some embodiments, the trenches 136 may be recessed from the dielectric layer 118 . At least one trench 136 can be formed by the dielectric layer 118, the substrate 112, and the insulating structures. 114 defined.

In some embodiments, the mask structures 132 may be removed after the etching process P1. In some embodiments, the protective layer 134 may be removed after the etching process P1. In some embodiments, dielectric layer 118 may be removed through a chemical mechanical polishing process.

In some embodiments, the trenches 136 may have columns 1361 and 1362. In some embodiments, a pitch T1 of the rows 1361 of trenches 136 may be different from a pitch T2 of the rows 1362 of trenches 136 . In some embodiments, the pitch T1 of the rows 1361 of trenches 136 may exceed the pitch T2 of the rows 1362 of trenches 136 . In some embodiments, pitch T1 may be approximately twice the pitch T2. In some embodiments, the column 1361 of trenches 136 may be the outermost column within cell region 110A. In some embodiments, the row 1361 of trenches 136 may be the uppermost row (or lowermost row) from a top view.

In some embodiments, the trenches 136 may have rows 1363 and 1364. In some embodiments, a pitch T3 of the rows 1363 of trenches 136 may be different from a pitch T4 of the rows 1364 of trenches 136 . In some embodiments, the pitch T3 of the rows 1363 of trenches 136 may exceed the pitch T4 of the rows 1364 of trenches 136 . In some embodiments, pitch T3 may be approximately twice the pitch T4. In some embodiments, row 1363 of trenches 136 may be the outermost row within cell region 110A. In some embodiments, row 1363 of trenches 136 may be the leftmost row (or rightmost row) from a top view.

Referring to Figures 7A and 7B, a conductive layer 116' can be formed. In some embodiments, conductive layer 116' may fill trenches 136. In some embodiments, conductive layer 116' may be surrounded by dielectric layer 118. In some embodiments, the manufacturing technology of the conductive layer 116' may include CVD, ALD, PVD, LPCVD or other suitable processes.

Referring to FIG. 8A and FIG. 8B, a barrier layer 120' and a metallization layer may be formed. 122' and a dielectric layer 124. The manufacturing technology of the barrier layer 120' may include CVD, ALD, PVD, LPCVD or other suitable processes. The manufacturing technology of the metallization layer 122' may include CVD, ALD, PVD, LPCVD or other suitable processes. The manufacturing technology of the dielectric layer 124 may include CVD, ALD, PVD, LPCVD or other suitable processes.

In some embodiments, barrier layer 120' may cover substrate 112. In some embodiments, barrier layer 120' may cover dielectric layer 118.

In some embodiments, metallization layer 122' may be configured to form a plurality of bit lines 122. In some embodiments, metallization layer 122' may cover barrier layer 120'.

In some embodiments, dielectric layer 124 may cover metallization layer 122'.

Referring to FIGS. 9A and 9B , a plurality of mask structures 138 and a pitch adjustment structure 140 can be formed. In some embodiments, the mask structures 138 may cover the dielectric layer 124 .

In some embodiments, a portion of the conductive layer 116' may not vertically overlap the mask structures 138. In some embodiments, pitch adjustment structures 140 may be conformally formed on the mask structures 138 . In some embodiments, spacing adjustment structures 140 may be used to reduce the gap defined by the mask structures 138 . In some embodiments, a portion of the spacing adjustment structure 140 may be disposed between openings defined by the mask structures 138 .

Referring to FIG. 10A and FIG. 10B , a protective layer 142 may be formed. In some embodiments, the protective layer 142 may be used to define a region R2 for subsequent etching. In some embodiments, region R2 may be rectangular or square.

In some embodiments, a portion of substrate 112 is exposed through protective layer 142 . In some embodiments, a portion of the mask structures 138 may be exposed through the protective layer 142 . In some embodiments, the pitch adjustment structure 140 may be exposed through the protective layer 142 .

In some embodiments, the protective layer 142 may include one side 142s1 and one side Side 142s2, and side 142s2 is generally perpendicular to side 142s1. In some embodiments, the side 134s1 of the protective layer 134 (as shown in FIG. 5A ) may be inclined relative to the side 142s1 of the protective layer 142 . In some embodiments, the side 134s1 of the protective layer 134 may be inclined relative to the side 142s2 of the protective layer 142. In some embodiments, the side 134s2 of the protective layer 134 may be inclined relative to the side 142s1 of the protective layer 142. In some embodiments, the side 134s2 of the protective layer 134 may be inclined relative to the side 142s2 of the protective layer 142.

Please refer to FIG. 11A and FIG. 11B to perform an etching process P2. The etching process P2 may include a dry etching, a wet etching or other suitable etching processes. In some embodiments, dielectric layer 124 exposed by protective layer 142 and exposed by mask structures 138 may be removed.

In some embodiments, the metallization layer 122 ′ exposed through the protective layer 142 and exposed through the mask structures 138 may be removed, thereby forming a plurality of bit lines 122 . At least one bit line 122 may extend along the X direction.

In some embodiments, the barrier layer 120 ′ exposed through the protective layer 142 and exposed through the mask structures 138 may be removed, thereby forming a plurality of bit line stacks 120 . At least one bit line stack 120 may extend along the X direction.

In some embodiments, after the etching process P2, the protective layer 142 may be removed. In some embodiments, the mask structures 138 may be removed after the etching process P2. In some embodiments, after the etching process P2, the pitch adjustment structure can be removed.

In some embodiments, a portion of the conductive layer 116' may be exposed through the bit line stack 120. In some embodiments, the portion of conductive layer 116' may be exposed through the bit lines 122. In some embodiments, this portion of conductive layer 116' may be exposed by dielectric layer 124.

In some embodiments, a portion of the bit lines 122 may be disposed on the conductive layer 116'. In some embodiments, a portion of the bit line stack 120 may be disposed on the conductive layer 116'. In some embodiments, a portion of the bit lines 122 may be disposed on the insulating structures 114 .

Referring to FIGS. 12A and 12B , a portion of the conductive layer 116 ′ is removed, thereby forming a plurality of bit line contact points 116 . As a result, a semiconductor element 100a can be produced.

In some embodiments, the portion of conductive layer 116' exposed by the bit lines 122 may be removed. In some embodiments, the portion of conductive layer 116' exposed by dielectric layer 118 may be removed.

At least one bit line contact 116 may be connected by a corresponding bit line 122 . In some embodiments, the bitline contacts 116 may have columns 1161 and 1162 . In some embodiments, the bit line contacts 116 in column 1161 may be connected by a bit line 1221 . In some embodiments, the bit line contacts 116 in column 1162 may be connected by bit lines 1222 .

In some embodiments, a pitch T5 of the rows 1161 of bit line contact points 116 may be different from a pitch T6 of the rows 1162 of the bit line contact points 116 . In some embodiments, the pitch T5 of the columns 1161 of the bit line contact points 116 may exceed the pitch T6 of the columns 1162 of the bit line contact points 116 . In some embodiments, pitch T5 may be approximately twice the pitch T6. In some embodiments, the column 1161 of bit line contacts 116 may be the outermost column within the cell region 110A. In some embodiments, the column 1161 of equal bit line contacts 116 may be the uppermost column (or lowermost column) from a top view.

In some embodiments, the bit line contacts 116 may have rows 1163 and 1164. In some embodiments, a spacing T7 of the rows 1163 of bit line contact points 116 may not be A spacing T8 corresponding to the row 1164 of the bit line contact points 116 . In some embodiments, the pitch T7 of the rows 1163 of bit line contact points 116 may exceed the pitch T8 of the row 1164 of the bit line contact points 116 . In some embodiments, pitch T7 may be approximately twice the pitch T8. In some embodiments, the row 1163 of bit line contacts 116 may be the outermost row within cell region 110A. In some embodiments, the row 1163 of equal bit line contact points 116 may be the leftmost row (or rightmost row) from a top view.

In this embodiment, a protective layer 132 having a specific profile, such as a zigzag shape, is used to define a region R1, and an etching process P1 is performed on the region R1. By using the aforementioned protective layer, the trench in the outermost column (or row) can have an overall profile compared to an inner trench. As a result, a plurality of insulating spacers (as shown in FIG. 13 ) may be formed on both sides of the bit line contacts 116 in the outermost column (or row), thereby preventing contact with the capacitor at the bit line 122 An electrical short circuit between points (shown in Figure 13).

FIG. 13 is a schematic cross-sectional view illustrating a semiconductor device 100b according to some embodiments of the present disclosure. Semiconductor device 100b is similar to semiconductor device 100a, except that semiconductor device 100b may also include an insulating spacer 150, a capacitor contact 152, a stack structure 154, a conductive layer 156, and a trench 158. The fabrication technique of the semiconductor device 100b may include performing a plurality of processes, such as deposition, etching, lithography, or other suitable processes on the semiconductor device 100a.

In some embodiments, insulating spacers 152 may be disposed on the sidewalls of bit line contacts 116 , on bit line stack 120 , on bit lines 122 , and on dielectric layer 124 . In some embodiments, bit line contacts 116 and capacitor contacts 152 are separated by insulating spacers 150 .

In some embodiments, bit line stack 120 and capacitor contact 152 may be separated by insulating spacers 150 . In some embodiments, bit line 122 is in contact with the capacitor Points 152 may be separated by insulating spacers 150 .

In some embodiments, for example, the insulating spacer 152 may include silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (Si ₂ ON ₂ ), silicon oxynitride (Si ₂ N ₂ O), a high dielectric constant material, or a combination thereof. Examples of the high-k material include a dielectric material having a dielectric constant higher than silicon dioxide, or a dielectric material having a dielectric constant higher than about 3.9. In some embodiments, the insulating spacer 150 may include at least one metal element, such as HfO ₂ , HSO (silicon doped hafnium oxide), La ₂ O ₃ , LaAlO ₃ , ZrO ₂ , ZrSiO ₄ , Al ₂ O ₃ or combinations thereof .

In some embodiments, capacitor contacts 152 may be disposed on substrate 112 . In some embodiments, capacitor contacts 152 may be disposed between the insulating spacers 150 . In some embodiments, a portion of capacitor contact 152 may be disposed within the trench defined by substrate 112 . In some embodiments, capacitor contacts 152 may include metals such as W, Cu, Ru, Ir, Ni, Os, Rh, Al, Mo, Co, alloys thereof, combinations thereof, or materials with suitable resistance and gap filling capabilities. Any metal material.

In some embodiments, stack structure 154 may be disposed on capacitor contacts 152 . In some embodiments, the stacked structure 154 may include a multi-layer structure. In some embodiments, for example, stack structure 154 may include a metal silicide layer (eg, _CoSix ), a metal nitride layer (eg, TiN), and other suitable layers.

In some embodiments, conductive layer 156 may be disposed on stack structure 154 . For example, conductive layer 156 may be used to connect multiple capacitor structures (not shown) and capacitor contacts 152 . In some embodiments, conductive layer 156 may cover insulating spacers 150 and dielectric layer 124 . In some embodiments, conductive layer 156 may include a metal such as W, Cu, Ru, Ir, Ni, Os, Rh, Al, Mo, Co, alloys thereof, or combinations thereof.

In some embodiments, the trench 158 may be disposed at a boundary between the cell region 110A and the surrounding region 110B. For example, trench 158 may be used to protect surrounding area 100B from defects. The trench 158 may span the cell region 110A and the surrounding region 110B. The material of trench 158 may be the same as the material of conductive layer 156 .

In this embodiment, the grooves in the outermost column (or row) may have the same overall profile as an inner groove. In a comparative semiconductor device, the trench in the outermost column (or row) may have only half an outline compared to an inner trench, resulting in the bit line contact having only one side of the insulating gap formed thereon son. The other side of the bit line contact can be adjacent to the active region of the substrate. As a result, leakage from the bit line to the trench via the bit line stack, the bit line contact, the active region of the substrate, and the capacitor contact may occur. In this embodiment, since the trenches 136 in the outermost column (or row) have an overall profile, a plurality of insulating spacers (eg, 150a) can be formed on both sides of the bit line contact 116a, and the bit line contact 116a can be formed on both sides. The element line contact point 116a is located in the trench 136 of the outermost column (or row). Therefore, current leakage between bit lines 122 and capacitor contacts 152 can be avoided.

An embodiment of the present disclosure provides a method of manufacturing a semiconductor device. The preparation method includes providing a substrate including a plurality of active regions separated from each other. The preparation method also includes forming a plurality of mask structures on the substrate. The preparation method also includes forming a first protective layer to cover the first mask structures and the substrate. The first protective layer defines an area that exposes a portion of the first mask structures and the substrate, and from a top view, the area defined by the first protective layer has a zigzag edge. . In addition, the preparation method includes performing a first etching process to form a plurality of trenches defined by the substrate.

Another embodiment of the present disclosure provides a method of manufacturing a semiconductor device. The preparation method includes providing a substrate including a plurality of active regions separated from each other. The preparation The method also includes forming a plurality of first mask structures on the substrate. The preparation method also includes forming a first protective layer to cover the first mask structures and the substrate. The first protective layer defines a first area that exposes the first mask structures and the substrate. Parts of the first mask structures are partially covered by the first protective layer. In addition, the preparation method includes performing a first etching process to remove the substrate exposed from the first mask structures and the first region to form a plurality of trenches.

Yet another embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate and a plurality of bit line contacts. The substrate defines a plurality of trenches. The plurality of bit line contact points are disposed on the substrate. At least one bit line contact is disposed within one of the trenches defined by the substrate. The plurality of trenches has a first row and a second row, and a pitch of the first row is different from a pitch of the second row.

Embodiments of the present disclosure illustrate a semiconductor device having multiple bit line contacts. In this embodiment, the insulating spacer adjacent the bit line contact may have an integral profile, thereby preventing an electrical short between the bit line and the capacitor contact or trench.

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the claimed claims. For example, many of the processes described above may be implemented in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art will understand from the disclosure of this disclosure that existing or future developed devices that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used in accordance with the present disclosure. process, machinery, manufacture, material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patent scope of this application.

100a: Semiconductor components 110A:Unit area 110B: Surrounding area 112: Base 114:Insulation structure 116:Bit line contact point 1161: column 1162: column 1163: OK 1164: OK 118:Dielectric layer 122:Bit line 136:Trench 1361: column 1362: column 1363: OK 1364: OK 20:Active zone T1: Spacing T2: Spacing T3: Spacing T4: spacing T5: Spacing T6: Spacing T7: spacing T8: Spacing X: direction Y: direction

Claims (6)

A semiconductor element including: a substrate defining a plurality of trenches; and a plurality of bit line contacts disposed on the substrate, wherein at least one bit line contact is disposed in one of the trenches defined by the substrate in, wherein the plurality of trenches have a first row and a second row, and a pitch of the first row is different from a pitch of the second row; wherein the trenches include a first row and a first row. Two rows, and a pitch of the first row of the trenches is different from a pitch of the second row of the trenches. The semiconductor device of claim 1, wherein the first column is the outermost column of the plurality of trenches, and the pitch of the first column is greater than the pitch of the second column. The semiconductor device of claim 2, wherein the first row is an outermost row of the trenches, and the pitch of the first row is greater than the pitch of the second row. The semiconductor device according to claim 1, further comprising: a first element line disposed on the plurality of bit line contact points in the first column of the plurality of trenches, wherein the first element line lines connecting the plurality of bit line contacts in the first column of the plurality of trenches; and a second bit line disposed on the plurality of bit lines in the second column of the plurality of trenches on the bit line contact point, wherein the second bit line is connected to the bit line in the second column of the plurality of trenches Multiple bit line contacts. The semiconductor device of claim 1, wherein the bit line contact points include a first column and a second column, and a pitch of the first column of the bit line contact points is different from that of the bit line contact points. A spacing of the second column between element line contact points. The semiconductor device of claim 1, wherein the bit line contact points include a first row and a second row, and a pitch of the first row of bit line contact points is different from that of the bit line contact points. A spacing of the second row from the element line contact point.