TWI833296B - Memory device having word line with protrusion - Google Patents

Abstract

The present disclosure provides a memory device. The memory device includes a substrate, a dielectric layer, a first metallization layer, a first channel layer, a second metallization layer, and a second channel layer. The dielectric layer is disposed on the substrate. The first metallization layer is disposed within the dielectric layer and extends along a first direction. The first channel layer is surrounded by the first metallization layer. The second metallization layer is disposed within the dielectric layer and extends along the first direction. The second channel layer is surrounded by the second metallization layer. The first metallization layer includes a first protruding portion protruding toward the second metallization layer.

Description

Memory device with protruding word lines

This application claims priority to U.S. Patent Application Nos. 17/824,011 and 17/824,507 (that is, the priority date is "May 25, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a memory device, and in particular to a memory device with protruding word lines.

With the rapid development of the electronics industry, the development of integrated circuits (ICs) has achieved high performance and miniaturization. Advances in integrated circuit materials and design technology have produced several generations of integrated circuits, each generation smaller and more complex than the previous generation.

A dynamic random access memory (DRAM) device is a type of random access memory that stores each bit of data in a separate capacitor within an integrated circuit. Typically, DRAM is arranged in a square array, with a capacitor and transistor per cell. Vertical transistors for 4F ² DRAM cells have been developed, where F represents the minimum feature width or critical dimension (CD) of the lithography. However, as the spacing between word lines continues to shrink recently, DRAM manufacturers are facing huge challenges in reducing the area of memory cells. For example, bit line channels can easily come into contact with word lines, inducing short circuits due to overlay errors in the lithography process.

The above description of "prior art" is only to provide background technology and does not acknowledge the above The "prior art" description in this article discloses the subject matter of the present disclosure and does not constitute the prior art of the present disclosure, and any description of the "prior art" above shall not be regarded as any part of this case.

One aspect of the present disclosure provides a memory device. The memory device includes a substrate, a dielectric layer, a first metallization layer, a first channel layer, a second metallization layer and a second channel layer. The dielectric layer is disposed on the substrate. The first metallization layer is disposed in the dielectric layer and extends along a first direction. The first channel layer is surrounded by the first metallization layer. The second metallization layer is disposed in the dielectric layer and extends along the first direction. The second channel layer is surrounded by the second metallization layer. The first metallization layer includes a first protrusion protruding toward the second metallization layer.

Another aspect of the present disclosure provides another memory device. The memory device includes a bottom substrate, a first bottom unit, a top substrate, a first top unit and a common bit line. The first bottom unit includes a first bottom capacitor disposed in the bottom substrate. The first bottom unit also includes a first bottom character line disposed on the bottom substrate and extending along a first direction. The first bottom cell further includes a first bottom channel layer surrounded by the first bottom word line. The first top unit includes a first top capacitor disposed in the top substrate. The first top unit also includes a first top word line disposed on the top substrate and extending along the first direction. The first top cell further includes a first top channel layer surrounded by the first top word line. The common bit line is disposed between the first bottom unit and the first top unit and extends along a second direction substantially perpendicular to the first direction.

Another aspect of the present disclosure provides a method of manufacturing a memory device. The preparation method includes providing a substrate. The preparation method also includes forming a conductive layer on the substrate. The preparation method further includes patterning the conductive layer to form a pattern extending along a first direction. A first metallization layer and a second metallization layer. The first metallization layer has a first protrusion protruding toward the second metallization layer. In addition, the preparation method also includes forming a first channel layer in the first metallization layer, and forming a second channel layer in the second metallization layer.

In some embodiments, the first top word line is formed between the first top capacitor and the common bit line.

In some embodiments, the first top word line is formed between the first top capacitor and the first bottom word line.

In some embodiments, forming the first top word line includes forming a protrusion protruding toward the second top word line.

In some embodiments, the manufacturing method further includes forming a second bottom unit, which includes: forming a second bottom character line on the bottom substrate and extending along the first direction; and forming a second bottom character line on the bottom substrate. A second bottom channel layer surrounded by element lines; wherein the first bottom word line includes a protrusion protruding toward the second bottom word line.

In some embodiments, the second bottom word line includes a protrusion protruding toward the first bottom word line.

In some embodiments, the protruding portions of the first bottom word line and the protruding portions of the second bottom word line are staggered along the second direction.

In some embodiments, the first bottom channel layer and the second bottom channel layer are staggered along the second direction.

In some embodiments, the first top word line has a protrusion.

In some embodiments, the protrusion of the first bottom word line overlaps the protrusion of the first top word line along a third direction that is substantially perpendicular to the first direction and the protrusion of the first top word line. Second direction.

In some embodiments, the first top channel layer overlaps the protrusion of the first top word line along the second direction.

In some embodiments, the preparation method further includes: forming a second top unit, which includes: forming a second top character line on the top substrate and extending along the first direction; and forming a second top unit by the second top unit. A second top channel layer surrounded by word lines; wherein the second top word line includes a protrusion protruding toward the first top word line.

In some embodiments, the first top word line has a first sidewall and a second sidewall opposite to the first sidewall. The second sidewall faces the second top word line, and the first sidewall is connected to the first sidewall. A first distance between the first top channel layers is different from a second distance between the second sidewall and the first top channel layer.

In some embodiments, the second top word line has a third sidewall and a fourth sidewall, the third sidewall faces the first top word line, and there is a gap between the third sidewall and the second top channel layer. A third distance is different from a fourth distance between the fourth side wall and the second top channel layer.

Embodiments of the present disclosure provide a memory device. The memory device may include word lines having protrusions. The protrusion can make the overlay error of the word line pattern relatively large to form an opening (in which a channel layer is formed), which can prevent electrical leakage between the word line and the channel layer.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. The technical field to which this disclosure belongs Those with ordinary knowledge should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

100:Memory components

102: Base

104-1: Gate dielectric

104-2: Gate dielectric

106-1: Channel layer

106-2: Channel layer

108-1:Capacitor

108-2:Capacitor

110: Dielectric layer

112: Dielectric layer

114: Dielectric layer

116:Conductive layer

116-1:Metallized layer

116-1p:Protrusion

116-2:Metallized layer

116-2p:Protrusion

116-r1: Opening

116r2-1: Opening

116r2-2: Opening

116s1:Side wall

116s2:Side wall

116s3:Side wall

116s4:Side wall

118:Contact plug

118-1:Contact plug

118-2:Contact plug

120-1:Metallized layer

120-2:Metallized layer

140-1:Unit

140-2:Unit

150: Dielectric layer

200:Memory components

202:Base

204-1: Gate dielectric

204-2: Gate dielectric

206-1: Channel layer

206-2: Channel layer

208-1:Capacitor

208-2:Capacitor

212: Dielectric layer

216-1:Metallized layer

216-1p:Protrusion

216-2:Metallized layer

216-2p:Protrusion

216s1:Side wall

216s2:Side wall

216s3:Side wall

216s4:Side wall

218-1: Contact plug

218-2: Contact plug

240-1:Unit

240-2:Unit

300:Preparation method

302: Operation

304: Operation

306: Operation

308: Operation

310: Operation

312: Operation

314: Operation

A-A': line

B-B':line

D1: distance

D2: distance

D3: distance

D4: distance

D5: distance

D6: distance

D7: distance

D8: distance

D9: distance

D10: distance

D11: distance

D12: distance

X: axis

Y: axis

Z: axis

The disclosure content of this application can be more fully understood by referring to the embodiments and the patent scope combined with the drawings. The same element symbols in the drawings refer to the same elements.

FIG. 1A is a top view illustrating a memory device according to some embodiments of the present disclosure.

FIG. 1B is a cross-sectional view along line AA' of the memory device of FIG. 1A illustrating some embodiments of the present disclosure.

FIG. 2A is a top view illustrating a memory device according to some embodiments of the present disclosure.

FIG. 2B illustrates a cross-sectional view of the memory device of FIG. 2A along line BB′ according to some embodiments of the present disclosure.

FIG. 3 is a flow chart illustrating a method of manufacturing a memory device according to some embodiments of the present disclosure.

FIG. 4A illustrates one or more stages of a method of manufacturing a memory device according to some embodiments of the present disclosure.

4B is a cross-sectional view along line AA' of FIG. 4A illustrating some embodiments of the present disclosure.

FIG. 5A illustrates one or more stages of a method of manufacturing a memory device according to some embodiments of the present disclosure.

Figure 5B is a cross-sectional view along line AA' of Figure 5A illustrating some embodiments of the present disclosure.

FIG. 6A illustrates one or more stages of a method of manufacturing a memory device according to some embodiments of the present disclosure.

6B is a cross-sectional view along line AA' of FIG. 6A illustrating some embodiments of the present disclosure.

FIG. 7A illustrates one or more stages of a method of manufacturing a memory device according to some embodiments of the present disclosure.

7B is a cross-sectional view along line AA' of FIG. 7A illustrating some embodiments of the present disclosure.

FIG. 8A illustrates one or more stages of a method of manufacturing a memory device according to some embodiments of the present disclosure.

8B is a cross-sectional view along line AA' of FIG. 8A illustrating some embodiments of the present disclosure.

FIG. 9A illustrates one or more stages of a method of manufacturing a memory device according to some embodiments of the present disclosure.

9B is a cross-sectional view along line AA' of FIG. 9A illustrating some embodiments of the present disclosure.

Specific language will now be used to describe the embodiments, or examples, of the present disclosure illustrated in the drawings. It should be understood that there is no intention to limit the scope of the present disclosure. Any changes or modifications to the described embodiments, and any further applications of the principles described herein, are deemed to be commonly made by one of ordinary skill in the art to which this disclosure relates. Reference numbers may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment apply to another embodiment, even if they share the same reference number.

It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers or sections, these elements, elements, regions, layers or sections are not limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the inventive concept.

The terminology used herein is for describing particular embodiments only and is not intended to limit the concepts of the invention. As used herein, the singular forms "a", "an" and "the" also include the plural forms unless the context clearly dictates otherwise. It should be further understood that the term "package" "Contain" and "include", when used in this specification, indicate the presence of stated features, integers, steps, operations, elements or components, but do not exclude the presence or addition of one or more other features, integers, steps, An operation, element, component, or group thereof.

FIG. 1A is a top view illustrating a memory device 100 according to some embodiments of the present disclosure.

In some embodiments, the memory device 100 may include a cell region in which the memory device is formed, such as the structure shown in FIGS. 1A and 1B . Memory devices may include, for example, dynamic random access memory (DRAM) devices, one-time programming (OTP) memory devices, static random access memory (SRAM) devices, or other suitable memory devices. In some embodiments, DRAM may include, for example, transistors, capacitors, and other components.

During read operations, the word lines can be enabled to turn on the transistors. The enabled transistor allows the voltage on the capacitor to be read by the sense amplifier through the bit line. During a write operation, when the word line is enabled, the data to be written is available on the bit line.

In some embodiments, memory element 100 may include peripheral areas (not shown) used to form logic elements (eg, system on chip (SoC), central processing unit (CPU), graphics processing unit (GPU), application processor (AP, microcontroller, etc.), radio frequency (RF) components, sensor components, microelectromechanical systems (MEMS) components, signal processing components (e.g., digital signal processing (DSP) components), front-end components (e.g., analog front-end (AFE) components) or other components.

As shown in FIG. 1A , the memory device 100 may include a substrate 102, a plurality of metallization layers 116-1 and 116-2, a plurality of metallization layers 120-1 and 120-2, and a plurality of gate dielectrics 104- 1 and 104-2, a plurality of channel layers 106-1 and 106-2, and a dielectric layer 112.

The substrate 102 may be a semiconductor substrate, such as a bulk semiconductor, an insulating Semiconductor on bulk (SOI) substrate, or similar substrate. The substrate 102 may include elemental semiconductors, including silicon or germanium in single crystal form, polycrystalline form, or amorphous form, composite semiconductor materials, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, At least one of indium arsenide and indium antimonide, the alloy semiconductor material includes at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and GaInAsP, any other suitable material, or a combination thereof. In some embodiments, the alloy semiconductor substrate may include a SiGe alloy with gradient Ge features, where the composition of Si and Ge changes from one ratio to another with the location of the features. In another embodiment, a SiGe alloy is formed on a silicon substrate. In some embodiments, the silicon germanium alloy can be mechanically stretched by another material in contact with the silicon germanium alloy. In some embodiments, the substrate 102 may have a multi-layer structure, or the substrate 102 may include a multi-layer compound semiconductor structure.

Substrate 102 may have a plurality of doped regions (not shown) therein. In some embodiments, p-type and/or n-type dopants may be doped into substrate 102 . In some embodiments, the p-type dopant includes boron (B), other Group III elements, or any combination thereof. In some embodiments, n-type dopants include arsenic (As), phosphorus (P), other Group V elements, or any combination thereof.

Each of metallization layers 116-1 and 116-2 may extend along the Y-axis. Each of metallization layers 116-1 and 116-2 may be parallel. In some embodiments, each of metallization layers 116-1 and 116-2 may be physically separated. Metallization layers 116-1 and 116-2 may include conductive materials such as tungsten (W), copper (Cu), aluminum (Al), tantalum (Ta), molybdenum (Mo), tantalum nitride (TaN), titanium, Titanium nitride (TiN), etc., and/or combinations thereof. In some embodiments, metallization layers 116-1 and 116-2 may be referred to as word lines.

The metallization layer 116-1 may include a sidewall 116s1 and an opposite sidewall 116s2. Sidewalls 116s2 of metallization layer 116-1 may face metallization layer 116-2. In some practical In embodiments, metallization layer 116-1 may have protrusions 116-1p. In some embodiments, protrusions 116-1p of metallization layer 116-1 may face metallization layer 116-2. In some embodiments, sidewalls 116s2 of metallization layer 116-1 may protrude toward metallization layer 116-2, thus defining protrusions 116-1p.

The metallization layer 116-2 may include a sidewall 116s3 and a sidewall 116s4 opposite the sidewall 116s3. Sidewalls 116s3 of metallization layer 116-2 may face metallization layer 116-1. In some embodiments, metallization layer 116-2 may have protrusions 116-2p. In some embodiments, protrusions 116-2p of metallization layer 116-2 may face metallization layer 116-1. In some embodiments, sidewalls 116s3 of metallization layer 116-2 may protrude toward metallization layer 116-1, thus defining protrusions 116-2p.

In some embodiments, the protruding portions 116-1p of the metallization layer 116-1 and the protruding portions 116-2p of the metallization layer 116-2 may be staggered. In some embodiments, protrusions 116-1p of metallization layer 116-1 are staggered along the X-axis with protrusions 116-2p of metallization layer 116-2. In some embodiments, protrusions 116-1p of metallization layer 116-1 may not overlap protrusions 116-2p of metallization layer 116-2 along the X-axis. In other embodiments, the protrusion 116-1p of the metallization layer 116-1 may partially overlap the protrusion 116-2p of the metallization layer 116-2 along the X-axis. In some embodiments, protrusions 116-1p and/or 116-2p may have a semicircular or semielliptical outline when viewed from above. However, the contents of this disclosure are not intended to be limiting.

Metallization layers 120-1 and 120-2 may be disposed on metallization layers 116-1 and 116-2. Each metallization layer 120-1 and 120-2 may extend along the X-axis. Each of metallization layers 120-1 and 120-2 may be parallel. Each metallization layer 120-1 and 120-2 may be physically separated. In some embodiments, metallization layers 120-1 and 120-2 may be located at a higher level than metallization layers 116-1 and 116-2. Metallization layers 120-1 and 120-2 may include conductive materials such as tungsten, Copper, aluminum, tantalum, tantalum nitride, titanium, titanium nitride, etc., and/or combinations thereof. In some embodiments, metallization layers 120-1 and 120-2 may be referred to as bit lines.

In some embodiments, gate dielectrics 104-1 and 104-2 may be disposed on sidewalls of word lines (eg, 116-1 and 116-2) (not shown in the figure). In some embodiments, gate dielectric 104-1 may be embedded in metallization layer 116-1. In some embodiments, gate dielectric 104-2 may be embedded in metallization layer 116-2. In some embodiments, gate dielectric 104-1 may be surrounded by metallization layer 116-1. In some embodiments, gate dielectric 104-2 may be surrounded by metallization layer 116-2. In some embodiments, each of gate dielectrics 104-1 and 104-2 may overlap metallization layer 120-1 or 120-2 along the Z-axis.

In some embodiments, gate dielectrics 104-1 and 104-2 may include silicon oxide ( _SiOx ), silicon nitride ( _{SixNy )} , silicon oxynitride (SiON), or combinations thereof. In some embodiments, the gate dielectric layer may include a dielectric material, such as a high-k dielectric material. High-k dielectric materials may have a dielectric constant (k value) greater than 4. High dielectric materials may include hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), lanthanum oxide (La ₂ O ₃ ), yttrium oxide (Y ₂ O ₃ ), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ) or other suitable materials. Other suitable materials are also contemplated for this disclosure. In some embodiments, gate dielectrics 104-1 and 104-2 may include rings having circular, oval, oval, or other contours.

In some embodiments, each of the channel layers 106-1 and 106-2 may be disposed on the sidewalls of the gate dielectric 104-1 or 104-2 (not labeled in the figure). In some embodiments, each of channel layers 106-1 and 106-2 may be embedded in gate dielectric 104-1 or 104-2. In some embodiments, channel layers 106-1 and 106-2 may each be surrounded by gate dielectric 104-1 or 104-2. In some embodiments, each of channel layers 106-1 and 106-2 may be in contact with gate dielectric 104-1 or 104-2. In some embodiments, channel layer 106-1 and Each of 106-2 may overlap along the Z-axis with metallization layer 120-1 or 120-2. In some embodiments, each of the channel layers 106-1 and 106-2 may be completely surrounded by the gate dielectric 104-1 or 104-2 when viewed from a top view.

In some embodiments, each of the channel layers 106-1 and 106-2 may be disposed on the sidewalls of the metallization layer 116-1 or 116-2 (not labeled in the figure). In some embodiments, each of channel layers 106-1 and 106-2 may be embedded in metallization layer 116-1 or 116-2. In some embodiments, each of channel layers 106-1 and 106-2 may be surrounded by metallization layer 116-1 or 116-2.

In some embodiments, channel layers 106-1 and 106-2 may be staggered. In some embodiments, channel layer 106-1 may be staggered with channel layer 106-2 along the X-axis. In some embodiments, channel layer 106-1 may overlap protrusions 116-1p of metallization layer 116-1 along the X-axis. In some embodiments, channel layer 106-2 may overlap along the X-axis with protrusions 116-2p of metallization layer 116-2.

There may be a distance D1 between the sidewall 116s1 of the metallization layer 116-1 and the channel layer 106-1 along the X-axis. There may be a distance D2 between the sidewall 116s2 of the metallization layer 116-1 and the channel layer 106-1 along the X-axis. In some embodiments, distance D1 may be different from distance D2. In some embodiments, distance D2 may be greater than distance D1.

There may be a distance D3 between the sidewall 116s3 of the metallization layer 116-2 and the channel layer 106-2 along the X-axis. There may be a distance D4 between the metallization layer 116-2 and the sidewall 116s4 of the channel layer 106-2 along the X-axis. In some embodiments, distance D3 may be different from distance D4. In some embodiments, distance D3 may be greater than distance D4.

In some embodiments, sidewalls 116s1 of metallization layer 116-1 may have relatively straight edges. In some embodiments, sidewalls 116s4 of metallization layer 116-2 may have relatively straight edge. There may be a distance D5 between the metallization layer 116-1s of the metallization layer 116-1 and the sidewall 116s4 of the metallization layer 116-2 along the X-axis. In some embodiments, distance D5 may be substantially uniform or constant along the Y-axis.

There may be a distance D6 between the sidewall 116s2 of the metallization layer 116-1 and the sidewall 116s3 of the metallization layer 116-2 along the X-axis. In some embodiments, distance D6 may vary along the Y-axis.

The material of the channel layers 106-1 and 106-2 may include amorphous semiconductor, polycrystalline semiconductor and/or metal oxide. Semiconductors may include, but are not limited to, germanium (Ge), silicon (Si), tin (Sn), and antimony (Sb). Metal oxides may include but are not limited to: indium oxide; tin oxide; zinc oxide; dual-component metal oxides, such as In-Zn-based oxides, Sn-Zn-based oxides, Al-Zn-based oxides, Zn-Mg-based oxide, Sn-Mg-based oxide, In-Mg-based oxide or In-Ga-based oxide. Three-component metal oxides, such as In-Ga-Zn-based oxide (also expressed as IGZO), In-Al-Zn-based oxide, In-Sn-based oxide (also expressed as ITO), In-Sn-Zn-based Oxide, Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn-based oxide, In-La-Zn-based oxide, In- Ce-Zn based oxide, In-Pr-Zn based oxide, In-Nd-Zn based oxide, In-Sm-Zn based oxide, In-Eu-Zn based oxide, In-Gd-Zn based oxide Material, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb -Zn-based oxide or In-Lu-Zn-based oxide; and four-component metal oxides, such as In-Sn-Ga-Zn-based oxide, In-Hf-Ga-Zn-based oxide, In-Al-Ga -Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide or In-Hf-Al-Zn-based oxide, but the present disclosure is not limited thereto.

In some embodiments, the dielectric layer 112 may be disposed on the sidewalls of the metallization layer 116-1 or 116-2 (not labeled in the figure). In some embodiments, dielectric layer 112 may be provided Between metallization layers 116-1 and 116-2. In some embodiments, each gate dielectric 104-1 and 104-2 may be physically separated from dielectric layer 112. In some embodiments, each of gate dielectrics 104-1 and 104-2 may be physically separated from dielectric layer 112 by metallization layer 116-1 or 116-2.

In some embodiments, each of channel layers 106-1 or 106-2 may be physically separated from dielectric layer 112. In some embodiments, channel layer 106-1 or 106-2 may be physically separated from dielectric layer 112 by gate dielectrics 104-1 and 104-2 and metallization layer 116-1 or 116-2 .

The dielectric layer 112 may include silicon oxide (SiO _x ), silicon nitride ( _Six N _y ), silicon oxynitride (SiON), or other suitable materials. In some embodiments, the material of dielectric layer 112 may be different from the material of gate dielectrics 104-1 and 104-2. In some embodiments, dielectric layer 112 may be made of the same material as gate dielectrics 104-1 and 104-2, but with different qualities or film densities.

FIG. 1B is a cross-sectional view along line AA' of the memory device 100 of FIG. 1A illustrating some embodiments of the present disclosure.

As shown in FIG. 1B , the memory device 100 may also include a plurality of capacitors 108 - 1 and 108 - 2 , a dielectric layer 110 , a dielectric layer 114 and a contact plug 118 .

In some embodiments, capacitor 108-1 may be electrically connected to metallization layer 120-1 through contact plug 118 and channel layer 106-1. In some embodiments, capacitor 108-2 may be electrically connected to metallization layer 120-2 through contact plug 118 and channel layer 106-2.

In some embodiments, capacitors 108-1 and 108-2 may be embedded in substrate 102. In some embodiments, each of capacitors 108-1 and 108-2 may include a first electrode, a capacitor dielectric, and a second electrode (not labeled). In some embodiments , each of capacitors 108-1 and 108-2 may have a circular, elliptical, elliptical or similar profile when viewed from above. In some embodiments, the capacitor dielectric may surround the first electrode. In some embodiments, the second electrode may surround the first electrode. In some embodiments, the second electrode may surround the capacitor dielectric. In some embodiments, a capacitor dielectric may be disposed between the first electrode and the second electrode.

The first electrode and/or the second electrode may include semiconductor material or conductive material. The semiconductor material may include polycrystalline silicon or other suitable materials. Conductive materials may include tungsten, copper, aluminum, tantalum, or other suitable materials.

The capacitor dielectric may include a dielectric material such as silicon oxide, tungsten oxide, zirconium oxide, copper oxide, aluminum oxide, hafnium oxide, or similar materials.

In some embodiments, contact plug 118 may be disposed between capacitor 108-1 and channel layer 106-1. Contact plug 118 may include a semiconductor material or a conductive material.

The dielectric layer 110 may be disposed on the substrate 102 . The dielectric layer 110 may include silicon oxide (SiO _x ), silicon nitride ( _Six N _y ), silicon oxynitride (SiON), phosphosilicate glass (PSG), boron phosphosilicate glass (BPSG), Low-k dielectric materials (k<4) or other suitable materials. The dielectric layer 110 may also be referred to as an underlying dielectric.

Dielectric layer 114 may be disposed on metallization layers 116-1 and 116-2. The dielectric layer 114 may include silicon oxide (SiO _x ), silicon nitride ( _Six N _y ), silicon oxynitride (SiON), phosphosilicate glass (PSG), boron phosphosilicate glass (BPSG), Low-k dielectric materials (k<4) or other suitable materials. In some embodiments, metallization layers 120-1 and 120-2 may be disposed on dielectric layer 114. The dielectric layer 114 may also be referred to as an upper dielectric.

In some embodiments, each of gate dielectrics 104-1 and 104-2 may penetrate dielectric layer 114. In some embodiments, each of gate dielectrics 104-1 and 104-2 One can penetrate the dielectric layer 110 . In some embodiments, each gate dielectric 104-1 and 104-2 may penetrate metallization layer 116-1 or 116-2.

In some embodiments, each of channel layers 106-1 and 106-2 may penetrate dielectric layer 114. In some embodiments, each of channel layers 106-1 and 106-2 may penetrate dielectric layer 110. In some embodiments, each of channel layers 106-1 and 106-2 may penetrate metallization layer 116-1 or 116-2.

In some embodiments, word lines (eg, metallization layer 116-1 or 116-2), gate dielectric 104-1 or 104-2, and channel layer 106-1 or 106-2 may be included in electrical circuits. in the crystal. During a read operation, a word line (eg, metallization layer 116-1 or 116-2) may be activated, turning on a transistor, which may be formed in the surrounding area. The enabled transistor allows the voltage on the capacitor (eg, capacitor 108-1 or capacitor 108-2) to be read by the sense amplifier through the bit line (eg, metallization layer 120-1 or 120-2). During a write operation, when the word line (eg, metallization layer 116-1 or 116-2) is enabled, data to be written may be provided to the bit line (eg, metallization layer 120-1 or 120-2 ).

In this embodiment, the metallization layer 116-1 may have protrusions 116-1p, and the channel layer 106-1 may be partially surrounded by the protrusions 116-1p. The protrusion 116-1p may allow a relatively large overlay error during patterning of the metallization layer 116-1, which may prevent interference between the metallization layer 116-1 and the channel layer 106-1. Leakage.

In this embodiment, the protrusion 116-1p of the metallization layer 116-1 may face the metallization layer 116-2, and the protrusion 116-2p of the metallization layer 116-2 may face the metallization layer 116-1 , thus reducing the size of the memory device 100 .

2A and 2B illustrate a memory device 200 according to some embodiments of the present disclosure, wherein FIG. 2A is a top view, and FIG. 2B is a cross-sectional view along line BB′ of FIG. 2A. It should be noted that in order to For the sake of brevity, some elements or features have been omitted from Figure 2A. The memory device 200 is similar to the memory device 100 shown in FIGS. 1A and 1B , with the following differences.

As shown in FIG. 2A, the memory device 200 may include a substrate 202, a plurality of metallization layers 216-1 and 216-2, a plurality of gate dielectrics 204-1 and 204-2, and a plurality of channel layers 206-1. and 206-2, and dielectric layer 212.

Each of metallization layers 216-1 and 216-2 may extend along the Y-axis. Each of metallization layers 216-1 and 216-2 may be parallel. In some embodiments, each of metallization layers 216-1 and 216-2 may be physically separated. The materials of metallization layer 216-1 and metallization layer 216-2 may be the same as or similar to the material of metallization layer 116-1. In some embodiments, metallization layers 216-1 and 216-2 may be referred to as top word lines. In some embodiments, metallization layers 116-1 and 116-2 (shown in Figure 2B) may be referred to as bottom word lines.

In some embodiments, the material of substrate 202 may be the same as or similar to the material of substrate 102 . In some embodiments, substrate 202 may also be referred to as the top substrate. In some embodiments, substrate 102 (shown in Figure 2B) may also be referred to as the bottom substrate.

The metallization layer 216-1 may include a sidewall 216s1 and an opposite sidewall 216s2. Sidewalls 216s2 of metallization layer 216-1 may face metallization layer 216-2. In some embodiments, metallization layer 216-1 may have protrusions 216-1p. In some embodiments, protrusions 216-1p of metallization layer 216-1 may face metallization layer 216-2. In some embodiments, sidewall 216s2 of metallization layer 216-1 may protrude toward metallization layer 216-2, thus defining protrusion 216-1p.

The metallization layer 216-2 may include a sidewall 216s3 and an opposite sidewall 216s4. Sidewalls 216s3 of metallization layer 216-2 may face metallization layer 216-1. In some embodiments, metallization layer 216-2 may have protrusions 216-2p. In some embodiments, the metallization The protrusion 216-2p of layer 216-2 may face the metallization layer 216-1. In some embodiments, sidewalls 216s3 of metallization layer 216-2 may protrude toward metallization layer 216-1, thus defining protrusions 216-2p.

In some embodiments, the protruding portion 216-1p of the metallization layer 216-1 and the protruding portion 216-2p of the metallization layer 216-2 may be staggered. In some embodiments, protrusions 216-1p of metallization layer 216-1 may be staggered along the X-axis with protrusions 216-2p of metallization layer 216-2. In some embodiments, protrusions 216-1p of metallization layer 216-1 may not overlap protrusions 216-2p of metallization layer 216-2 along the X-axis. In other embodiments, the protrusion 216-1p of the metallization layer 216-1 may partially overlap the protrusion 216-2p of the metallization layer 216-2 along the X-axis. In some embodiments, protrusions 216-1p and/or 216-2p may have a semicircular or semielliptical outline when viewed from above. However, the contents of this disclosure are not intended to be limiting.

In some embodiments, metallization layer 216-1 may be disposed on metallization layer 120-1. In some embodiments, metallization layer 216-2 may be disposed on metallization layer 120-2. In some embodiments, each of metallization layers 216-1 and 216-2 may be located at a higher level than metallization layers 120-1 and 120-2.

In some embodiments, gate dielectrics 204-1 and 204-2 may be disposed on the sidewalls of the word lines (not labeled in the figure). In some embodiments, gate dielectric 204-1 may be embedded in metallization layer 216-1. In some embodiments, gate dielectric 204-2 may be embedded in metallization layer 216-2. In some embodiments, gate dielectric 204-1 may be surrounded by metallization layer 216-1. In some embodiments, gate dielectric 204-2 may be surrounded by metallization layer 216-2. In some embodiments, each of gate dielectrics 204-1 and 204-2 may overlap metallization layer 120-1 or 120-2 along the Z-axis.

In some embodiments, the materials of gate dielectrics 204-1 and 204-2 may be The gate dielectric 104-1 is made of the same or similar material. In some embodiments, gate dielectrics 204-1 and 204-2 may be referred to as top gate dielectric layers, while gate dielectrics 104-1 and 104-2 (shown in Figure 2B Can be called the bottom gate dielectric layer.

In some embodiments, each of the channel layers 206-1 and 206-2 may be disposed on the sidewalls of the gate dielectric 204-1 or 204-2 (not labeled in the figure). In some embodiments, each of channel layers 206-1 and 206-2 may be embedded in gate dielectric 204-1 or 204-2. In some embodiments, channel layers 206-1 and 206-2 may each be surrounded by gate dielectric 204-1 or 204-2. In some embodiments, each of channel layers 206-1 and 206-2 may be in contact with gate dielectric 204-1 or 204-2.

In some embodiments, each of the channel layers 206-1 and 206-2 may be disposed on the sidewalls of the metallization layer 216-1 or 216-2 (not labeled in the figure). In some embodiments, each of channel layers 206-1 and 206-2 may be embedded in metallization layer 216-1 or 216-2. In some embodiments, each of channel layers 206-1 and 206-2 may be surrounded by metallization layer 216-1 or 216-2.

In some embodiments, the material of channel layers 206-1 and 206-2 may be the same or similar to the material of channel layer 106-1. In some embodiments, channel layers 206-1 and 206-2 may be referred to as top channel layers, while channel layers 106-1 and 106-2 (shown in Figure 2B) may be referred to as bottom channel layers.

In some embodiments, channel layers 206-1 and 206-2 may be staggered. In some embodiments, channel layer 206-1 may be staggered with channel layer 206-2 along the X-axis. In some embodiments, channel layer 206-1 may not overlap channel layer 206-2 along the X-axis. In some embodiments, channel layer 206-1 may overlap protrusion 216-1p along the X-axis. In some embodiments, channel layer 206-2 may overlap protrusion 216-2p along the X-axis.

In some embodiments, each of channel layers 206-1 and 206-2 may overlap along the Z-axis with metallization layer 120-1 or 120-2. In some embodiments, each of channel layers 206-1 and 206-2 may be completely surrounded by gate dielectric 204-1 or 204-2 when viewed from a top view.

There may be a distance D7 between the sidewall 216s1 of the metallization layer 216-1 and the channel layer 206-1 along the X-axis. There may be a distance D8 between the sidewall 216s2 of the metallization layer 216-1 and the channel layer 206-1 along the X-axis. In some embodiments, distance D7 may be different from distance D8. In some embodiments, distance D8 may be greater than distance D7.

There may be a distance D9 between the sidewall 216s3 of the metallization layer 216-2 and the channel layer 206-2 along the X-axis. There may be a distance D10 between the sidewall 216s4 of the metallization layer 216-2 and the channel layer 206-2 along the X-axis. In some embodiments, distance D9 may be different from distance D10. In some embodiments, distance D9 may be greater than distance D10.

In some embodiments, sidewalls 216s1 of metallization layer 216-1 may have relatively straight edges. In some embodiments, sidewalls 216s4 of metallization layer 216-2 may have relatively straight edges. There may be a distance D11 along the X-axis between the metallization layer 216-1s of the metallization layer 216-1 and the sidewall 216s4 of the metallization layer 216-2. In some embodiments, distance D11 may be substantially uniform or constant along the Y-axis.

There may be a distance D12 between the sidewall 216s2 of the metallization layer 216-1 and the sidewall 216s3 of the metallization layer 216-2 along the X-axis. In some embodiments, distance D12 may vary along the Y-axis.

In some embodiments, the dielectric layer 212 may be disposed on the sidewalls of the metallization layer 216-1 or 216-2. In some embodiments, dielectric layer 212 may be disposed between metallization layers 216-1 and 216-2. In some embodiments, each of gate dielectrics 204-1 and 204-2 may be physically separated from dielectric layer 212. In some embodiments, gate dielectric 204-1 and Each of 204-2 may be physically separated from dielectric layer 212 by metallization layer 216-1 or 216-2. In some embodiments, the material of dielectric layer 212 may be the same as or similar to the material of dielectric layer 112 .

In some embodiments, each of channel layer 206-1 or 206-2 may be physically separated from dielectric layer 212. In some embodiments, channel layer 206-1 or 206-2 may be physically separated from dielectric layer 212 by gate dielectrics 204-1 and 204-2 and metallization layer 216-1 or 216-2. .

As shown in Figure 2B, memory element 200 may include cells 140-1, 140-2, 240-1, and 240-2. Each of the units 240-1 and 240-2 may be located at a higher level than the units 140-1 and 140-2. In some embodiments, each unit 140-1 and 140-2 may also be referred to as a bottom unit. In some embodiments, each of units 240-1 and 240-2 may also be referred to as a top-on unit.

Cell 140-1 may include capacitor 108-1, channel layer 106-1, metallization layer 116-1, contact plug 118-1, and metallization layer 120-1.

Cell 140-2 may include capacitor 108-2, channel layer 106-2, metallization layer 116-2, contact plug 118-2, and metallization layer 120-2.

Cell 240-1 may include capacitor 208-1, channel layer 206-1, metallization layer 216-1, contact plug 218-1, and metallization layer 120-1.

Cell 240-2 may include capacitor 208-2, channel layer 206-2, metallization layer 216-2, contact plug 218-2, and metallization layer 120-2.

In some embodiments, protrusions 216-1p of metallization layer 216-1 may partially or completely overlap along the Z-axis with protrusions 116-1p of metallization layer 116-1. In some embodiments, protrusion 216-2p of metallization layer 216-2 may be aligned with protrusion 116-2 of metallization layer 116-2 along the Z-axis. 2p partially or fully overlapped.

In some embodiments, metallization layers 120-1 and 120-2 may be disposed within dielectric layer 150. In some embodiments, metallization layer 120-1 may be disposed between cells 140-1 and 240-1. In some embodiments, metallization layer 120-1 may be disposed between channel layers 106-1 and 206-1.

In some embodiments, metallization layer 120-1 may be disposed between channel layers 106-1 and 206-1. In some embodiments, metallization layer 120-1 may be disposed between metallization layers 116-1 and 216-1. In some embodiments, metallization layer 120-1 may be disposed between capacitors 108-1 and 208-1. In some embodiments, metallization layer 120-1 may be disposed between channel layer 106-1 and capacitor 208-1. In some embodiments, metallization layer 120-1 may serve as a common bit line for cells 140-1 and 240-1. In some embodiments, metallization layer 120-2 may serve as a common bit line for cells 140-2 and 240-2.

In this embodiment, metallization layer 120-1 may serve as a common bit line. Therefore, the size of the memory device 200 can be reduced. Additionally, the capacitance of memory element 200 can be increased.

FIG. 3 is a flowchart illustrating a method 300 for manufacturing a memory device according to some embodiments of the present disclosure.

The preparation method 300 begins with operation 302, where a substrate may be provided. In some embodiments, a first capacitor and a second capacitor may be formed within the substrate. In some embodiments, a contact plug may be formed in the substrate and on the first capacitor and the second capacitor. In some embodiments, a first dielectric layer may be formed on the substrate. In some embodiments, a conductive layer may be formed on the first dielectric layer. In some embodiments, a second dielectric layer may be formed on the conductive layer.

The preparation method 300 continues with operation 304, in which a certain patterning process may be performed to remove a portion of the first dielectric layer, the second dielectric layer and the conductive layer. Therefore, a first word line and a second word line are formed. A plurality of openings may be formed to expose an upper surface of the substrate.

In some embodiments, the conductive layer can be patterned to form a first protrusion of the first word line. In some embodiments, the conductive layer may be patterned to form a second protrusion of a second word line. In some embodiments, the first protrusion may face the second word line. In some embodiments, the second protrusion may face the first word line.

The method 300 continues with operation 306, where a third dielectric layer may be formed to fill the opening.

The method 300 continues with operation 308, where the second dielectric layer, the first and second word lines, and a portion of the first dielectric layer may be removed. An opening may be formed in the first word line. An opening may be formed in the second word line.

The manufacturing method 300 continues with operation 310, where a first gate dielectric and a first channel layer may be formed in the opening of the first word line. The second gate dielectric and the second channel layer may be formed within the opening of the second word line.

The manufacturing method 300 continues with operation 312, in which a first bit line and a second bit line may be formed on the first channel layer and the second channel layer respectively, thereby forming a memory device.

The preparation method 300 is merely an example and is not intended to limit the disclosure beyond what is expressly mentioned in the patent application. Additional operations may be provided before, during, or after each operation of preparation method 300, and some of the operations described may be replaced, eliminated, or reordered for other embodiments of the method. In some embodiments, preparation methods 300 may include further operations not depicted in FIG. 3 . In some embodiments, preparation method 300 may include one or more operations described in FIG. 3 .

4A to 9A and 4B to 9B illustrate one or more stages of a memory device manufacturing method according to some embodiments of the present disclosure, wherein FIGS. 4A to 9A are top views, and FIGS. 4B to 9B are respectively FIGS. 4A to 9B. Figure 9A is a cross-sectional view along line AA'. It should be noted that, for the sake of brevity, some elements are illustrated in the section view but not in the top view.

As shown in Figures 4A and 4B, a substrate 102 may be provided. In some embodiments, capacitors 108-1 and 108-2 may be formed within substrate 102. In some embodiments, contact plugs 118 may be formed within substrate 102 and on capacitors 108-1 and 108-2. In some embodiments, dielectric layer 110 may be formed on substrate 102 . In some embodiments, conductive layer 116 may be formed on dielectric layer 110 . In some embodiments, dielectric layer 114 may be formed on conductive layer 116 . The fabrication technology of dielectric layer 110 and dielectric layer 114 may include chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low pressure chemical vapor deposition (LPCVD), or other suitable processes. process. The manufacturing technology of the conductive layer 116 may include sputtering, PVD or other suitable processes.

As shown in FIGS. 5A and 5B , a patterning process may be performed to remove portions of the dielectric layer 110 , the dielectric layer 114 and the conductive layer 116 . Therefore, metallization layers 116-1 and 116-2 are formed. A plurality of openings 116 - r1 may be formed to expose the upper surface of the substrate 102 . The patterning process may include lithography, etching, or other suitable processes. The lithography process may include photoresist coating (eg, spin coating), soft bake, mask alignment, exposure, post-exposure bake, photoresist development, rinsing, and drying (eg, hard bake). The etching process may include, for example, dry or wet etching.

In some embodiments, conductive layer 116 may be patterned to form protrusions 116-1p of metallization layer 116-1. In some embodiments, conductive layer 116 may be patterned to shape Forming the protruding portion 116-2p of the metallization layer 116-2. In some embodiments, protrusion 116-1p may face metallization layer 116-2. In some embodiments, protrusion 116-2p may face metallization layer 116-1.

As shown in FIGS. 6A and 6B , a dielectric layer 112 may be formed to fill the opening 116 - r1 . The manufacturing technology of the dielectric layer 112 may include CVD, ALD, PVD, LPCVD or other suitable processes.

As shown in FIGS. 7A and 7B , dielectric layer 114 , metallization layers 116 - 1 and 116 - 2 and a portion of dielectric layer 110 may be removed. Openings 116r2-1 of metallization layer 116-1 may be formed. Openings 116r2-2 of metallization layer 116-2 may be formed. In some embodiments, openings 116r2-1 and 116r2-2 may be staggered. In some embodiments, opening 116r2-1 may not overlap opening 116r2-2 along the X-axis. In other embodiments, opening 116r2-1 may partially overlap opening 116r2-2 along the X-axis.

As shown in FIGS. 8A and 8B , the gate dielectric 104-1 and the channel layer 106-1 may be formed in the opening 116r2-1. Gate dielectric 104-2 and channel layer 106-2 may be formed within opening 116r2-2. The manufacturing technology of the gate dielectrics 104-1 and 104-2 and the channel layers 106-1 and 106-2 may include CVD, ALD, PVD, LPCVD or other suitable processes.

As shown in FIGS. 9A and 9B , metallization layers 120 - 1 and 120 - 2 may be formed on the dielectric layer 112 , thereby forming the memory device 100 . The manufacturing technology of the metallization layers 120-1 and 120-2 may include sputtering, PVD or other suitable processes.

In this embodiment, the word lines (eg 116-1 and/or 116-2) have a protruding portion (eg 116-1p and 116-2P). When the word lines are patterned to form openings (eg, 116r2-1 and/or 116r2-2) of their inner channel layers (eg, 106-1 and/or 106-2), the protrusions may allow for relatively large overlaps. setting error. Therefore, leakage between word lines and channel layers can be prevented.

One aspect of the present disclosure provides a memory device. The memory device includes a substrate, a dielectric layer, a first metallization layer, a first channel layer, a second metallization layer and a second channel layer. The dielectric layer is disposed on the substrate. The first metallization layer is disposed in the dielectric layer and extends along a first direction. The first channel layer is surrounded by the first metallization layer. The second metallization layer is disposed in the dielectric layer and extends along the first direction. The second channel layer is surrounded by the second metallization layer. The first metallization layer includes a first protrusion protruding toward the second metallization layer.

Another aspect of the present disclosure provides another memory device. The memory device includes a bottom substrate, a first bottom unit, a top substrate, a first top unit and a common bit line. The first bottom unit includes a first bottom capacitor disposed in the bottom substrate. The first bottom unit also includes a first bottom character line disposed on the bottom substrate and extending along a first direction. The first bottom cell further includes a first bottom channel layer surrounded by the first bottom word line. The first top unit includes a first top capacitor disposed within the top substrate. The first top unit also includes a first top word line disposed on the top substrate and extending along the first direction. The first top cell further includes a first top channel layer surrounded by the first top word line. The common bit line is disposed between the first bottom unit and the first top unit and extends along a second direction substantially perpendicular to the first direction.

Another aspect of the present disclosure provides a method of manufacturing a memory device. The preparation method includes providing a substrate. The preparation method also includes forming a conductive layer on the substrate. The preparation method further includes patterning the conductive layer to form a first metallization layer and a second metallization layer extending along a first direction. The first metallization layer has a first protrusion protruding toward the second metallization layer. In addition, the preparation method also includes forming a first channel layer in the first metallization layer, and forming a second channel layer in the second metallization layer.

Embodiments of the present disclosure provide a memory device. The memory device may include word lines having protrusions. The protrusion can make the overlay error of the word line pattern relatively large to form an opening (in which a channel layer is formed), which can prevent electrical leakage between the word line and the channel layer.

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as claimed. For example, many of the processes described above may be implemented in different ways and may be substituted for many of the processes described above with other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art will understand from the disclosure of this disclosure that existing or future developed processes, machines, manufacturing, etc. can be used in accordance with the disclosure to have the same function or achieve substantially the same results as the corresponding embodiments described herein. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patentable scope of this application.

100:Memory components 102: Base 104-1: Gate dielectric 104-2: Gate dielectric 106-1: Channel layer 106-2: Channel layer 112: Dielectric layer 116-1:Metallized layer 116-1p:Protrusion 116-2:Metallized layer 116-2p:Protrusion 116s1:Side wall 116s2:Side wall 116s3:Side wall 116s4:Side wall 120-1:Metallized layer 120-2:Metallized layer A-A': line D1: distance D2: distance D3: distance D4: distance D5: distance D6: distance X: axis Y: axis Z: axis

Claims (14)

A memory element includes: a bottom substrate; a first bottom unit including: a first bottom capacitor arranged in the bottom substrate; a first bottom word line arranged on the bottom substrate and along a first extending in one direction; and a first bottom channel layer surrounded by the first bottom word line; a top substrate; a first top unit including: a first top capacitor disposed in the top substrate; a first top substrate A top word line is disposed on the top substrate and extends along the first direction; and a first top channel layer is surrounded by the first top word line; a common bit line is disposed on the first extending between the bottom unit and the first top unit and along a second direction substantially perpendicular to the first direction, wherein the first bottom channel layer and the first top channel layer extend along a direction perpendicular to the bottom substrate The upper surface overlaps the common bit line in one direction. The memory device of claim 1, wherein the first top word line is disposed between the first top capacitor and the common bit line. The memory device of claim 1, wherein the first top word line is disposed between the first top capacitor and the first bottom word line. The memory device of claim 1, wherein the first top word line includes a protrusion protruding toward a second top word line. The memory device of claim 4, further comprising: a second bottom unit including: a second bottom word line disposed on the bottom substrate and extending along the first direction; and a second bottom channel layer, surrounded by the second bottom word line; wherein the first bottom word line includes a protrusion protruding toward the second bottom word line. The memory device of claim 5, wherein the second bottom word line includes a protrusion protruding toward the first bottom word line. The memory device of claim 5, wherein the protruding portions of the first bottom word line and the protruding portions of the second bottom word line are staggered along a second direction. The memory device of claim 5, wherein the first bottom channel layer and the second bottom channel layer are staggered along the second direction. The memory device of claim 5, wherein the first top word line has a protrusion. The memory device of claim 9, wherein the protruding portion of the first bottom word line overlaps the protruding portion of the first top word line along a third direction, and the third direction is substantially perpendicular to the first direction and the second direction. The memory device of claim 9, wherein the first top channel layer overlaps the protrusion of the first top word line along the second direction. The memory device of claim 9, further comprising: a second top unit including: a second top word line disposed on the top substrate and extending along the first direction; and a second top channel layer, surrounded by the second top word line; wherein the second top word line includes a protrusion protruding toward the first top word line. The memory device of claim 12, wherein the first top word line has a first side wall and a second side wall opposite to the first side wall, and the second side wall faces the second top word line, And a first distance between the first side wall and the first top channel layer is different from a second distance between the second side wall and the first top channel layer. The memory device of claim 13, wherein the second top word line has a third side wall and a fourth side wall, the third side wall faces the first top word line, and the third side wall is connected to the third side wall. A third distance between the two top channel layers is different from a fourth distance between the fourth sidewall and the second top channel layer.