TWI800734B - 用於人工神經網路中之類比神經記憶體的測試電路及方法 - Google Patents

用於人工神經網路中之類比神經記憶體的測試電路及方法 Download PDF

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TWI800734B
TWI800734B TW109119122A TW109119122A TWI800734B TW I800734 B TWI800734 B TW I800734B TW 109119122 A TW109119122 A TW 109119122A TW 109119122 A TW109119122 A TW 109119122A TW I800734 B TWI800734 B TW I800734B
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methods
testing circuitry
analog
memory
neural network
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TW109119122A
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TW202105399A (zh
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曉萬 陳
順 武
史蒂芬 Ｔ 鄭
史丹利 洪
英 李
史蒂芬 利姆克
雅 阮
維平 蒂瓦里
恩漢 杜
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美商超捷公司
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0688—Non-volatile semiconductor memory arrays
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/048—Activation functions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1204—Bit line control
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G11C2029/2602—Concurrent test
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5006—Current

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Biophysics (AREA)
  • Molecular Biology (AREA)
  • General Health & Medical Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Evolutionary Computation (AREA)
  • Data Mining & Analysis (AREA)
  • Computational Linguistics (AREA)
  • Software Systems (AREA)
  • Artificial Intelligence (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Neurology (AREA)
  • Computer Hardware Design (AREA)
  • Human Computer Interaction (AREA)
  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)
  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
TW109119122A 2019-07-19 2020-06-08 用於人工神經網路中之類比神經記憶體的測試電路及方法 TWI800734B (zh)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US201962876515P 2019-07-19 2019-07-19
US62/876,515 2019-07-19
US16/569,611 2019-09-12
US16/569,611 US11393546B2 (en) 2019-07-19 2019-09-12 Testing circuitry and methods for analog neural memory in artificial neural network
PCT/US2019/068201 WO2021015812A1 (en) 2019-07-19 2019-12-21 Testing circuitry and methods for analog neural memory in artificial neural network
WOPCT/US19/68201 2019-12-21

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TW202105399A TW202105399A (zh) 2021-02-01
TWI800734B true TWI800734B (zh) 2023-05-01

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TW109119122A TWI800734B (zh) 2019-07-19 2020-06-08 用於人工神經網路中之類比神經記憶體的測試電路及方法

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US (2) US11393546B2 (zh)
EP (1) EP4000069A1 (zh)
JP (2) JP2022540723A (zh)
KR (2) KR20220016505A (zh)
CN (1) CN114127854A (zh)
TW (2) TW202326740A (zh)
WO (1) WO2021015812A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11449741B2 (en) * 2019-07-19 2022-09-20 Silicon Storage Technology, Inc. Testing circuitry and methods for analog neural memory in artificial neural network
US20210350217A1 (en) * 2020-05-10 2021-11-11 Silicon Storage Technology, Inc. Analog neural memory array in artificial neural network with source line pulldown mechanism
CN113761793B (zh) * 2021-08-16 2024-02-27 固德威技术股份有限公司 逆变器输出阻抗检测装置及方法、逆变器运行控制方法
US20240087622A1 (en) * 2022-09-08 2024-03-14 Micron Technology, Inc. Model Inversion in Integrated Circuit Devices having Analog Inference Capability
US12100455B2 (en) * 2022-09-08 2024-09-24 Micron Technology, Inc. Weight calibration check for integrated circuit devices having analog inference capability

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130028021A1 (en) * 2011-07-28 2013-01-31 Eran Sharon Simultaneous Sensing of Multiple Wordlines and Detection of NAND Failures
US20130301335A1 (en) * 2012-05-08 2013-11-14 Adrian E. Ong Architecture, system and method for testing resistive type memory
US20190205729A1 (en) * 2018-01-03 2019-07-04 Silicon Storage Technology, Inc. Programmable Neuron For Analog Non-Volatile Memory In Deep Learning Artificial Neural Network

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5029130A (en) 1990-01-22 1991-07-02 Silicon Storage Technology, Inc. Single transistor non-valatile electrically alterable semiconductor memory device
KR960009033B1 (en) * 1991-07-17 1996-07-10 Toshiba Kk Semiconductor memory
FR2690751B1 (fr) 1992-04-30 1994-06-17 Sgs Thomson Microelectronics Procede et circuit de detection de fuites de courant dans une ligne de bit.
US6452837B2 (en) * 1999-12-27 2002-09-17 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory and threshold voltage control method therefor
JP4131902B2 (ja) * 1999-12-27 2008-08-13 株式会社東芝 不揮発性半導体メモリおよびそのスレシホールド電圧制御方法
US6768685B1 (en) 2001-11-16 2004-07-27 Mtrix Semiconductor, Inc. Integrated circuit memory array with fast test mode utilizing multiple word line selection and method therefor
US6850438B2 (en) 2002-07-05 2005-02-01 Aplus Flash Technology, Inc. Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations
US6747310B2 (en) 2002-10-07 2004-06-08 Actrans System Inc. Flash memory cells with separated self-aligned select and erase gates, and process of fabrication
US7177183B2 (en) * 2003-09-30 2007-02-13 Sandisk 3D Llc Multiple twin cell non-volatile memory array and logic block structure and method therefor
US7050344B1 (en) 2004-11-04 2006-05-23 Promos Technologies Inc. Failure test method for split gate flash memory
US7652929B2 (en) 2007-09-17 2010-01-26 Sandisk Corporation Non-volatile memory and method for biasing adjacent word line for verify during programming
US9070481B1 (en) 2014-05-30 2015-06-30 Sandisk Technologies Inc. Internal current measurement for age measurements
US9449694B2 (en) 2014-09-04 2016-09-20 Sandisk Technologies Llc Non-volatile memory with multi-word line select for defect detection operations
US10310734B2 (en) 2014-12-27 2019-06-04 Intel Corporation Tier mode for access operations to 3D memory
KR102444604B1 (ko) 2016-02-02 2022-09-21 에스케이하이닉스 주식회사 데이터 저장 장치 및 그것의 동작 방법
US11308383B2 (en) 2016-05-17 2022-04-19 Silicon Storage Technology, Inc. Deep learning neural network classifier using non-volatile memory array
JP6249504B1 (ja) * 2016-08-24 2017-12-20 ウィンボンド エレクトロニクス コーポレーション 半導体記憶装置
US10403357B2 (en) * 2017-09-18 2019-09-03 Nxp Usa, Inc. Resistive non-volatile memory and a method for sensing a memory cell in a resistive non-volatile memory
US10748630B2 (en) 2017-11-29 2020-08-18 Silicon Storage Technology, Inc. High precision and highly efficient tuning mechanisms and algorithms for analog neuromorphic memory in artificial neural networks
CN111199767B (zh) 2018-11-16 2022-08-16 力旺电子股份有限公司 非易失性存储器良率提升的设计及测试方法
US10991430B2 (en) * 2018-12-19 2021-04-27 Ememory Technology Inc. Non-volatile memory cell compliant to a near memory computation system
US11487464B2 (en) * 2019-07-03 2022-11-01 Micron Technology, Inc. Neural network memory

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130028021A1 (en) * 2011-07-28 2013-01-31 Eran Sharon Simultaneous Sensing of Multiple Wordlines and Detection of NAND Failures
US20130301335A1 (en) * 2012-05-08 2013-11-14 Adrian E. Ong Architecture, system and method for testing resistive type memory
US20190205729A1 (en) * 2018-01-03 2019-07-04 Silicon Storage Technology, Inc. Programmable Neuron For Analog Non-Volatile Memory In Deep Learning Artificial Neural Network

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TW202105399A (zh) 2021-02-01
JP2022540723A (ja) 2022-09-16
WO2021015812A1 (en) 2021-01-28
US11393546B2 (en) 2022-07-19
US11783904B2 (en) 2023-10-10
JP2024123058A (ja) 2024-09-10
TW202326740A (zh) 2023-07-01
CN114127854A (zh) 2022-03-01
KR20240135678A (ko) 2024-09-11
EP4000069A1 (en) 2022-05-25
US20210020255A1 (en) 2021-01-21
KR20220016505A (ko) 2022-02-09
US20220319619A1 (en) 2022-10-06

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