TWI799739B - 積體電路及操作積體電路之系統的方法 - Google Patents

積體電路及操作積體電路之系統的方法 Download PDF

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Publication number
TWI799739B
TWI799739B TW109133717A TW109133717A TWI799739B TW I799739 B TWI799739 B TW I799739B TW 109133717 A TW109133717 A TW 109133717A TW 109133717 A TW109133717 A TW 109133717A TW I799739 B TWI799739 B TW I799739B
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TW
Taiwan
Prior art keywords
integrated circuit
operating
circuit system
operating integrated
integrated
Prior art date
Application number
TW109133717A
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English (en)
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TW202147072A (zh
Inventor
黃開麒
劉祈麟
馬偉翔
謝尚志
Original Assignee
台灣積體電路製造股份有限公司
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Publication of TW202147072A publication Critical patent/TW202147072A/zh
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Publication of TWI799739B publication Critical patent/TWI799739B/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30141—Implementation provisions of register files, e.g. ports
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
TW109133717A 2020-06-12 2020-09-28 積體電路及操作積體電路之系統的方法 TWI799739B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/900,514 US11422819B2 (en) 2020-06-12 2020-06-12 Power efficient multi-bit storage system
US16/900,514 2020-06-12

Publications (2)

Publication Number Publication Date
TW202147072A TW202147072A (zh) 2021-12-16
TWI799739B true TWI799739B (zh) 2023-04-21

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW109133717A TWI799739B (zh) 2020-06-12 2020-09-28 積體電路及操作積體電路之系統的方法

Country Status (3)

Country Link
US (2) US11422819B2 (zh)
CN (1) CN113268941A (zh)
TW (1) TWI799739B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230179206A1 (en) * 2021-12-07 2023-06-08 Mediatek Inc. Clock gating cells

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080301594A1 (en) * 2007-05-29 2008-12-04 Magma Design Automation, Inc. Method For Optimized Automatic Clock Gating
US7782108B2 (en) * 2005-11-25 2010-08-24 Infineon Technologies Ag Flip-flop device and method for storing and outputting a data value
US20140225655A1 (en) * 2013-02-14 2014-08-14 Qualcomm Incorporated Clock-gated synchronizer
US20150022252A1 (en) * 2013-07-22 2015-01-22 Nordic Semiconductor Asa Digital circuits
US20160049937A1 (en) * 2014-08-15 2016-02-18 Qiang Tong Activity correlation based optimal clustering for clock gating for ultra-low power vlsi

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8046651B2 (en) * 2008-04-02 2011-10-25 Texas Instruments Incorporated Compare circuit receiving scan register and inverted clock flip-flop data

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7782108B2 (en) * 2005-11-25 2010-08-24 Infineon Technologies Ag Flip-flop device and method for storing and outputting a data value
US20080301594A1 (en) * 2007-05-29 2008-12-04 Magma Design Automation, Inc. Method For Optimized Automatic Clock Gating
US20140225655A1 (en) * 2013-02-14 2014-08-14 Qualcomm Incorporated Clock-gated synchronizer
US20150022252A1 (en) * 2013-07-22 2015-01-22 Nordic Semiconductor Asa Digital circuits
US20160049937A1 (en) * 2014-08-15 2016-02-18 Qiang Tong Activity correlation based optimal clustering for clock gating for ultra-low power vlsi

Also Published As

Publication number Publication date
US20210389952A1 (en) 2021-12-16
US20220334842A1 (en) 2022-10-20
CN113268941A (zh) 2021-08-17
US11422819B2 (en) 2022-08-23
TW202147072A (zh) 2021-12-16

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