TWI799588B - 積和運算裝置、積和運算電路、積和運算系統及積和運算方法 - Google Patents

積和運算裝置、積和運算電路、積和運算系統及積和運算方法 Download PDF

Info

Publication number
TWI799588B
TWI799588B TW108117978A TW108117978A TWI799588B TW I799588 B TWI799588 B TW I799588B TW 108117978 A TW108117978 A TW 108117978A TW 108117978 A TW108117978 A TW 108117978A TW I799588 B TWI799588 B TW I799588B
Authority
TW
Taiwan
Prior art keywords
sum operation
product sum
product
circuit
operation device
Prior art date
Application number
TW108117978A
Other languages
English (en)
Other versions
TW202006611A (zh
Inventor
森江隆
山口正登志
岩元剛毅
田向権
Original Assignee
日商索尼股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商索尼股份有限公司 filed Critical 日商索尼股份有限公司
Publication of TW202006611A publication Critical patent/TW202006611A/zh
Application granted granted Critical
Publication of TWI799588B publication Critical patent/TWI799588B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/049—Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/16—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division
    • G06G7/161—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division with pulse modulation, e.g. modulation of amplitude, width, frequency, phase or form
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/18—Arrangements for performing computing operations, e.g. operational amplifiers for integration or differentiation; for forming integrals
    • G06G7/184—Arrangements for performing computing operations, e.g. operational amplifiers for integration or differentiation; for forming integrals using capacitive elements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/048—Activation functions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01728—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/0806—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using charge transfer devices (DTC, CCD)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4814—Non-logic devices, e.g. operational amplifiers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Biophysics (AREA)
  • Software Systems (AREA)
  • Computational Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Computer Hardware Design (AREA)
  • Artificial Intelligence (AREA)
  • Computational Linguistics (AREA)
  • Molecular Biology (AREA)
  • Data Mining & Analysis (AREA)
  • Evolutionary Computation (AREA)
  • General Health & Medical Sciences (AREA)
  • Neurology (AREA)
  • Power Engineering (AREA)
  • Complex Calculations (AREA)
  • Amplifiers (AREA)
  • Analogue/Digital Conversion (AREA)
  • Logic Circuits (AREA)
TW108117978A 2018-07-13 2019-05-24 積和運算裝置、積和運算電路、積和運算系統及積和運算方法 TWI799588B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018133750 2018-07-13
JP2018-133750 2018-07-13

Publications (2)

Publication Number Publication Date
TW202006611A TW202006611A (zh) 2020-02-01
TWI799588B true TWI799588B (zh) 2023-04-21

Family

ID=69141673

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108117978A TWI799588B (zh) 2018-07-13 2019-05-24 積和運算裝置、積和運算電路、積和運算系統及積和運算方法

Country Status (6)

Country Link
US (1) US12008338B2 (zh)
EP (1) EP3822843B1 (zh)
JP (1) JP7283477B2 (zh)
CN (1) CN112384927B (zh)
TW (1) TWI799588B (zh)
WO (1) WO2020013069A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210374507A1 (en) * 2020-06-02 2021-12-02 University Of Louisiana At Lafayette Method for Pulse-Based Convolution for Near-Sensor Processing
KR20230039668A (ko) * 2020-07-17 2023-03-21 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 전자 기기
US20230049032A1 (en) * 2021-08-02 2023-02-16 Silicon Storage Technology, Inc. Output circuitry for analog neural memory in a deep learning artificial neural network
JPWO2023032158A1 (zh) * 2021-09-03 2023-03-09
US20230386566A1 (en) * 2022-05-25 2023-11-30 Stmicroelectronics International N.V. Bit line voltage clamping read circuit for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (sram)
US20230410892A1 (en) * 2022-05-25 2023-12-21 Stmicroelectronics International N.V. Bit line read current mirroring circuit for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (sram)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07141313A (ja) * 1993-11-18 1995-06-02 Fujitsu Ltd 神経回路素子
JP2010061428A (ja) * 2008-09-04 2010-03-18 Yazaki Corp 掛算回路
US20180101359A1 (en) * 2016-10-12 2018-04-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and system using the same
US20180181708A1 (en) * 2013-01-17 2018-06-28 Edico Genome Corporation Bioinformatics systems, apparatuses, and methods executed on an integrated circuit processing platform

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4272967B2 (ja) * 2003-10-16 2009-06-03 キヤノン株式会社 演算回路およびその動作制御方法
JP4620944B2 (ja) * 2003-10-16 2011-01-26 キヤノン株式会社 積和演算回路及びその方法
JP6501146B2 (ja) * 2014-03-18 2019-04-17 パナソニックＩｐマネジメント株式会社 ニューラルネットワーク回路およびその学習方法
CN109923550B (zh) * 2016-08-19 2022-11-15 索尼公司 乘数累加器
US9779355B1 (en) * 2016-09-15 2017-10-03 International Business Machines Corporation Back propagation gates and storage capacitor for neural networks
US11315009B2 (en) * 2017-03-03 2022-04-26 Hewlett Packard Enterprise Development Lp Analog multiplier-accumulators

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07141313A (ja) * 1993-11-18 1995-06-02 Fujitsu Ltd 神経回路素子
JP2010061428A (ja) * 2008-09-04 2010-03-18 Yazaki Corp 掛算回路
US20180181708A1 (en) * 2013-01-17 2018-06-28 Edico Genome Corporation Bioinformatics systems, apparatuses, and methods executed on an integrated circuit processing platform
US20180101359A1 (en) * 2016-10-12 2018-04-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and system using the same

Also Published As

Publication number Publication date
EP3822843A4 (en) 2021-09-01
CN112384927B (zh) 2024-09-13
US20210294573A1 (en) 2021-09-23
JPWO2020013069A1 (ja) 2021-08-02
CN112384927A (zh) 2021-02-19
WO2020013069A1 (ja) 2020-01-16
EP3822843B1 (en) 2024-10-16
JP7283477B2 (ja) 2023-05-30
EP3822843A1 (en) 2021-05-19
TW202006611A (zh) 2020-02-01
US12008338B2 (en) 2024-06-11

Similar Documents

Publication Publication Date Title
ZA201903714B (en) Blockchain-based commodity claim method and apparatus, and electronic device
TWI799588B (zh) 積和運算裝置、積和運算電路、積和運算系統及積和運算方法
DK3812900T3 (da) Systemer, fremgangsmåder og apparater til heterogen beregning
EP3544260A4 (en) METHOD AND DEVICE FOR SERVICE DESIGN AND SERVER
DK3374163T3 (da) Additivfremstillingsanordning, system og fremgangsmåde
KR102528125B9 (ko) 정보 처리 방법, 장치 및 기기
HK1247508A1 (zh) 一種終端設備的搜網顯示的方法、裝置和終端設備
BR112016022190A2 (pt) método e aparelho de processamento de informações de humor, e dispositivo de terminal
DK3671565T3 (da) Fisketælleenhed, fisketællesystem, og fisketællefremgangsmåde
ZA201806954B (en) Electronic device, information processing apparatus, and information processing method
IL264266A (en) A lithographic device, a lithographic projection device and a method of manufacturing a device
KR102419581B9 (ko) 표면 상의 악취를 감소시키는 장치 및 방법
EP3438891A4 (en) INFORMATION PROCESSING DEVICE AND METHOD AND INFORMATION PROVIDING METHOD
FI3570582T3 (fi) Entiteetin konfigurointimenetelmä, -laite ja -järjestelmä sekä cu-u
EP3591868A4 (en) INFORMATION PROCESSING METHOD, APPARATUS, AND DEVICE
TWI800761B (zh) 對準裝置、對準方法、成膜裝置及成膜方法
DE112017007742T8 (de) Informationsverarbeitungsvorrichtung, Informationsbereitstellungsverfahren undInformationsbereitstellungssystem
GB201918897D0 (en) Information provision device, information provision method and program
EP3581950A4 (en) DETECTION CIRCUIT, METHOD AND DEVICE
EP3438888A4 (en) INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND INFORMATION PROVIDING METHOD
DK3687238T3 (da) Databehandlingsfremgangsmåde og -terminalanordning
TWI800521B (zh) 基板處理方法、記憶媒體及基板處理系統
JP2019149641A5 (ja) 監視システム、監視方法及び監視プログラム
JP2018122228A5 (ja) 塗布装置、情報処理装置、情報処理方法、プログラム
ES2981285T3 (es) Aparato de comunicación, método y programa informático