TWI799498B - Method for forming multilayer wiring, device for forming multilayer wiring, and storage medium - Google Patents

Method for forming multilayer wiring, device for forming multilayer wiring, and storage medium Download PDF

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Publication number
TWI799498B
TWI799498B TW108102198A TW108102198A TWI799498B TW I799498 B TWI799498 B TW I799498B TW 108102198 A TW108102198 A TW 108102198A TW 108102198 A TW108102198 A TW 108102198A TW I799498 B TWI799498 B TW I799498B
Authority
TW
Taiwan
Prior art keywords
multilayer wiring
forming multilayer
storage medium
forming
wiring
Prior art date
Application number
TW108102198A
Other languages
Chinese (zh)
Other versions
TW201935586A (en
Inventor
岩下光秋
田中崇
Original Assignee
日商東京威力科創股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商東京威力科創股份有限公司 filed Critical 日商東京威力科創股份有限公司
Publication of TW201935586A publication Critical patent/TW201935586A/en
Application granted granted Critical
Publication of TWI799498B publication Critical patent/TWI799498B/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
TW108102198A 2018-02-05 2019-01-21 Method for forming multilayer wiring, device for forming multilayer wiring, and storage medium TWI799498B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018018473 2018-02-05
JP2018-018473 2018-02-05

Publications (2)

Publication Number Publication Date
TW201935586A TW201935586A (en) 2019-09-01
TWI799498B true TWI799498B (en) 2023-04-21

Family

ID=67479249

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108102198A TWI799498B (en) 2018-02-05 2019-01-21 Method for forming multilayer wiring, device for forming multilayer wiring, and storage medium

Country Status (3)

Country Link
JP (1) JP6910480B2 (en)
TW (1) TWI799498B (en)
WO (1) WO2019151023A1 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07122644A (en) * 1993-10-26 1995-05-12 Nec Corp Semiconductor device and fabrication thereof
JP2000150647A (en) * 1998-11-11 2000-05-30 Sony Corp Wiring structure and its manufacture
JP2002285343A (en) * 2000-12-11 2002-10-03 Ebara Corp Electroless plating apparatus
JP2006303062A (en) * 2005-04-19 2006-11-02 Sony Corp Manufacturing method of semiconductor device
JP2016156039A (en) * 2015-02-23 2016-09-01 東京エレクトロン株式会社 Semiconductor device, plating treatment method, plating treatment system and storage medium

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4945865B2 (en) * 2001-08-27 2012-06-06 ソニー株式会社 Multilayer wiring structure or electrode extraction structure, electric circuit device, and manufacturing method thereof
US7005379B2 (en) * 2004-04-08 2006-02-28 Micron Technology, Inc. Semiconductor processing methods for forming electrical contacts
JP6404174B2 (en) * 2015-04-16 2018-10-10 東京エレクトロン株式会社 Plating processing method, storage medium, and plating processing system

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07122644A (en) * 1993-10-26 1995-05-12 Nec Corp Semiconductor device and fabrication thereof
JP2000150647A (en) * 1998-11-11 2000-05-30 Sony Corp Wiring structure and its manufacture
JP2002285343A (en) * 2000-12-11 2002-10-03 Ebara Corp Electroless plating apparatus
JP2006303062A (en) * 2005-04-19 2006-11-02 Sony Corp Manufacturing method of semiconductor device
JP2016156039A (en) * 2015-02-23 2016-09-01 東京エレクトロン株式会社 Semiconductor device, plating treatment method, plating treatment system and storage medium

Also Published As

Publication number Publication date
JP6910480B2 (en) 2021-07-28
WO2019151023A1 (en) 2019-08-08
JPWO2019151023A1 (en) 2021-01-28
TW201935586A (en) 2019-09-01

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