JP4945865B2 - Multilayer wiring structure or electrode extraction structure, electric circuit device, and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multilayer wiring structure or an electrode lead-out structure, an electric circuit device, and a manufacturing method thereof.
[0002]
[Prior art]
Conventionally, as a method of manufacturing an electric circuit device, circuit elements (for example, semiconductor chips) are separated by dicing from a wafer, the separated circuit elements are transferred from a dicing sheet to a chip tray, and further, the circuit elements are removed from the chip tray. A method of picking up by vacuum suction and wiring after mounting or connecting to a substrate is known.
[0003]
This method is generally performed in, for example, a semiconductor package manufacturing process.
[0004]
[Course to Invention]
The present applicant has already proposed an image display device having an effective and preferable multilayer wiring structure and electrode lead-out structure, a manufacturing method thereof, and the like in Japanese Patent Application No. 2001-144452.
[0005]
The multilayer wiring structure, the electrode lead-out structure, the image display device, the manufacturing method thereof and the like according to the invention of the prior application are as exemplified below.
[0006]
This circuit element is, for example, a circuit element having a tapered tip portion, and includes a light emitting element having a structure as shown in FIG. 18A is a cross-sectional view of the light-emitting element, and FIG. 18B is a plan view thereof.
[0007]
This light-emitting element is a GaN-based light-emitting diode, for example, a light-emitting element in which a crystal is grown on a sapphire substrate (not shown). Such a GaN-based light emitting diode element causes laser ablation by laser irradiation that passes through the substrate, and the film is peeled off at the interface between the sapphire substrate and the GaN-based crystal growth layer as GaN is decomposed. It has a feature that it can be easily separated.
[0008]
According to this structure, the hexagonal pyramid-shaped n-type GaN: Si layer 22 selectively formed on the underlying growth layer 21 made of a GaN-based semiconductor layer is formed. An insulating film (not shown) is present on the underlying growth layer 21, and the hexagonal pyramid-shaped GaN: Si layer 22 is formed by a MOCVD (metal organic chemical vapor deposition) method or the like in the opening of the insulating film.
[0009]
This GaN: Si layer 22 is a pyramidal growth layer covered with an S plane (1-101 plane) when the main surface of a sapphire substrate used during growth is a C plane, and is doped with silicon. Area. The inclined S-plane portion of the GaN: Si layer 22 functions as a double heterostructure cladding.
[0010]
Next, an InGaN layer 23 which is an active layer is formed so as to cover the inclined S surface of the GaN: Si layer 22, and a magnesium-doped p-type GaN: Mg layer 24 is formed outside the InGaN layer 23. . The magnesium-doped GaN: Mg layer 24 also functions as a cladding.
[0011]
Further, a p-electrode 25 and an n-electrode 26 are formed on such a light emitting diode element 52. The p-electrode 25 is formed on the magnesium-doped GaN layer 24, and is formed by vapor deposition of a metal material such as Ni / Pt / Au or Ni (Pd) / Pt / Au.
[0012]
The n-electrode 26 is formed by vapor deposition of a metal material such as Ti / Al / Pt / Au in a portion where an insulating film (not shown) is opened. When the n electrode 26 is taken out from the back side of the base growth layer 21, it is not necessary to form the n electrode 26 on the surface side of the base growth layer 21.
[0013]
The GaN-based light-emitting diode element 52 having such a structure is an element capable of emitting blue light. In particular, the GaN-based light-emitting diode element 52 can be peeled off from the sapphire substrate relatively easily by laser ablation, and selectively irradiates a laser beam. To achieve selective peeling.
[0014]
The GaN-based light-emitting diode element 52 may have a structure in which an active layer is formed in a flat plate shape or a belt shape, or may have a pyramid structure in which a C surface is formed at an upper end portion. Further, other nitrides or compound semiconductors may be used.
[0015]
Next, the resin chip 54 used as a display element will be described.
[0016]
As shown in FIGS. 19 and 20, the resin chip 54 has a substantially flat plate shape, and its main surface has a substantially square shape. The shape of the resin chip 54 is a shape formed by solidifying the resin 53. Specifically, the resin layer 53 is formed by coating the entire surface of the light emitting diode elements 52 so as to substantially wrap each of the light emitting diode elements 52 with uncured resin. And after hardening this, it obtains by cut | disconnecting the edge part by a dicing etc.
[0017]
Electrode pads 56 and 57 are formed on the surface side of the resin layer 53 in which the substantially flat light emitting diode element 52 is embedded. As a method for forming the electrode pads 56 and 57, for example, a conductive layer such as a metal layer or a polycrystalline silicon layer, which is a material of the electrode pads 56 and 57, is formed on the entire surface, and a required electrode shape is formed by a photolithography technique or the like. It is formed by patterning. The electrode pads 56 and 57 are formed so as to be respectively connected to the p-electrode 25 and the n-electrode 26 of the element 52 which is a light-emitting diode element. For this purpose, a via hole or the like is formed in the resin layer 53. .
[0018]
The reason why the positions of the electrode pads 56 and 57 are shifted in plan view is to prevent the electrode pads 56 and 57 from overlapping when making contact from the upper side when the final wiring is formed. The shape of the electrode pads 56 and 57 is not limited to a square, and may be other shapes.
[0019]
By constructing such a resin chip 54, the periphery of the light emitting diode element 52 is covered with the resin 53 and flattened, the electrode pads 56 and 57 can be formed with high accuracy, and a wider area than the light emitting diode element 52 is formed. Further, the electrode pads 56 and 57 can be extended to facilitate handling when the transfer in the next transfer process is performed by an adsorption device or the like.
[0020]
Further, as will be described later, since the final wiring is performed after the transfer process, the wiring defect is prevented by performing the wiring using the electrode pads 56 and 57 having a relatively large size.
[0021]
Next, with reference to FIGS. 6 to 17, an electrode lead-out structure, a multilayer wiring structure, an image display device, a manufacturing method thereof, and the like shown in FIG. 18 will be described.
[0022]
As shown in FIG. 6, the first release layer 64 and the resin layer 53 are formed in close contact with each other on the upper surface of the first temporary holding member 51.
[0023]
Examples of the material of the first temporary holding member 51 that is in close contact with the resin layer 53 through the first release layer 64 include a polymer sheet and the like. As the material of the release layer 64, fluorine coat, silicone resin, water-soluble adhesive (for example, polyvinyl alcohol: PVA), polyimide, or the like can be used.
[0024]
Further, as the resin layer 53 on the first temporary holding member 51, a layer made of any one of an ultraviolet (UV) curable resin, a thermosetting resin, and a thermoplastic resin can be used. As an example, a polymer sheet or the like can be used as the first temporary holding member 51, and after forming a polyimide film as the first release layer 64, a UV curable resin can be applied as the resin layer 53.
[0025]
Then, the portion other than the portion where the light emitting diode element 52 is embedded (transferred) on the resin layer 53 is cured by irradiation with laser light. And the part which does not irradiate laser light other than this is made into the soft part 82 which embeds the light emitting diode element 52 at a later step.
[0026]
As shown in FIG. 7, on the main surface of the first substrate 50 such as sapphire, a plurality of light emitting diode elements 52 are formed in a matrix by the crystal growth described above.
[0027]
As the constituent material of the first substrate 50, a material having a high transmittance of the wavelength of the laser light irradiated to the light emitting diode element 52, such as a sapphire substrate, is used. Further, although the p electrode and the n electrode have already been formed in the light emitting diode element 52, the final wiring has not been made yet, and a separation groove 62g for separating the light emitting diode elements 52 is formed. The individual light emitting diode elements 52 are in a state where they can be separated.
[0028]
The groove 62g is formed by, for example, reactive ion etching. Then, the first substrate 50 is opposed to the first temporary holding member 51 to transfer the light emitting diode element 52 to the resin layer 52 as shown in FIG.
[0029]
At the time of this transfer, as shown in FIG. 7, a predetermined light emitting diode element 52 to be transferred is irradiated with laser light from the back surface of the first substrate 50, and the predetermined light emitting diode element 52 to be transferred is applied to the first substrate 50. Is peeled off using laser ablation. The GaN-based light-emitting diode element 52 is decomposed into metal Ga and nitrogen by laser ablation at the interface with the first substrate 50, which is a sapphire substrate, and can be peeled off relatively easily.
[0030]
As the laser light to be irradiated, an excimer laser, a harmonic YAG laser, or the like is used. Then, by the peeling action using this laser ablation, the predetermined light emitting diode element 52 to be transferred is separated at the interface between the GaN layer as the underlayer and the first substrate 50, and as shown in FIG. Transfer is performed by piercing a part of the p-electrode into the soft portion 82 of the layer 53.
[0031]
For the light-emitting diode elements 52 other than the predetermined light-emitting diode element 52 transferred to the soft portion 82 of the resin layer 53, the portion of the resin layer 53 that is in contact with the light-emitting diode element 52 is already laser light in the previous step. Therefore, it is not transferred to the resin layer 53 only by contact, and remains attached to the first substrate 50.
[0032]
Then, as shown in FIG. 8, the state after the transfer is such that the interval between the transferred light-emitting diode elements 52 is farther than when the light-emitting diode elements 52 are arranged on the first substrate 50. It will be arranged above.
[0033]
That is, the interval between the light emitting diode elements 52 is expanded in the X direction, and at the same time, the interval between the light emitting diode elements 52 is also expanded in the Y direction perpendicular to the X direction.
[0034]
Next, as shown in FIG. 9, the light-emitting diode element 52 held so as to partially pierce the p-electrode on the soft portion 82 of the resin layer 53 is pressed by the pressing means 84, and the softness of the resin layer 53 is It is further pressed against the part 82 and buried.
[0035]
Thus, as shown in FIG. 10, the light emitting diode element 52 is substantially embedded and held in the resin layer 53 of the first temporary holding member 51. Then, the back surface of the light emitting diode element 52 is surely removed and cleaned so that the resin 53 or the like existing between the light emitting diode element 52 and the first substrate 50 does not remain.
[0036]
Next, as shown in FIG. 11, the first temporary holding member 51 is peeled off from the resin layer 53 in which the light emitting diode element 52 is buried by laser light irradiation of the first peeling layer 64, and then the light emitting diode The back surface side of the resin layer 53 in which the element 52 is embedded is brought into close contact with the second temporary holding member 67 via the second release layer 60 and transferred.
[0037]
In FIG. 12, the light-emitting diode element 52 is transferred from the first temporary holding member 51 to the second temporary holding member 67 through the second release layer 60, and then the anode electrode (p electrode) is irradiated by laser light irradiation. ) Side and cathode electrode (n electrode) side, via holes 70 are formed, anode side electrode pads 56 and cathode side electrode pads 57 are formed, and then a part of resin layer 53 is diced to obtain individual resins. The state of the chip 54 is shown.
[0038]
By this dicing process, the cured resin layer 53 for each light-emitting diode element 52 is divided into a resin chip 54 corresponding to each light-emitting diode element 52. Here, the dicing process is performed by dicing using a mechanical means or laser dicing using a laser beam.
[0039]
The cut width by dicing depends on the size of the light-emitting diode element 52 (resin chip 54) covered with the resin layer 53 in the pixel of the image display device. For example, a narrow cut having a width of 20 μm or less is necessary. In some cases, it is necessary to perform processing with a laser using the above laser beam. At this time, an excimer laser, a harmonic YAG laser, a carbon dioxide gas laser, or the like can be used as the laser beam.
[0040]
As a result of this dicing, an element isolation groove 71 is formed, and the light emitting diode element 52 is divided into elements to form the resin chip 54. In order to separate the light emitting diode elements 52 in a matrix form, the element separation groove 71 is composed of a plurality of parallel lines extending in the vertical and horizontal directions as a pattern in plan view. Note that the surface of the second temporary holding member 67 faces the bottom of the element isolation groove 71. As an example, the second temporary holding member 67 is a dicing sheet in which a UV adhesive material is applied to a plastic substrate, and a material whose adhesive strength decreases when irradiated with ultraviolet rays (UV) can be used. .
[0041]
In the above transfer, for example, excimer laser light is irradiated from the back surface of the first temporary holding member 51 on which the first release layer 64 is formed, as shown in FIG. Thereby, for example, in the case where polyimide is formed as the first release layer 64, it is peeled off by ablation of polyimide. Thereafter, the resin layer 53 in which each light emitting diode element 52 is embedded is transferred to the second temporary holding member 67 side.
[0042]
Further, as an example of the process for forming the anode and cathode electrode pads 56 and 57, the surface of the resin layer 53 is etched with oxygen plasma until the p electrode and the n electrode of the light emitting diode element 52 are exposed. Form. For forming the via hole 70, an excimer laser, a harmonic YAG laser, a carbon dioxide laser, or the like can be used. The electrode pads 56 and 57 on the anode and cathode sides are made of Cu.
[0043]
Next, as shown in FIG. 13, the resin chip 54 in which the light emitting diode element 52 is embedded is peeled from the second temporary holding member 67 by using an adsorption device 73 as mechanical means. At this time, the second release layer 60 made of, for example, a fluorine coat, a silicone resin, a water-soluble adhesive (for example, PVA), polyimide, or the like is formed on the second temporary holding member 67. For example, YAG third harmonic laser light is irradiated from the back surface of the second temporary holding member 67 on which such a release layer 60 is formed. Thereby, for example, when the second release layer 60 is formed of polyimide, peeling occurs due to polyimide ablation between the polyimide layer and the interface of the second temporary holding member 67, and each light emitting diode element 52. The resin chip 54 embedded with can be easily peeled off from the second temporary holding member 67 by mechanical means such as the suction device 73 described above.
[0044]
FIG. 13 is a view showing a state where the resin chip 54 in which the light emitting diode elements 52 arranged on the second temporary holding member 67 are embedded is picked up by the suction device 73 as the mechanical means. .
[0045]
The suction holes 75 of the suction device 73 at this time are opened in a matrix at the pixel pitch of the image display device so that a large number of resin chips 54 embedded in the light-emitting diode elements 52 can be sucked together. .
[0046]
As the member of the suction hole 75, for example, a member produced by Ni electroforming or a member obtained by etching a metal plate 72 such as stainless steel (SUS) is used. An adsorption chamber 74 is formed in the back of the adsorption hole 75 of the metal plate 72. By controlling the adsorption chamber 74 to a negative pressure, the resin chip 54 in which the light emitting diode element 52 is embedded can be adsorbed.
[0047]
The light emitting diode element 52 is covered with a resin 53 at this stage, and the upper surface thereof is substantially flattened. For this reason, selective adsorption by the adsorption device 73 can be easily advanced.
[0048]
Next, FIG. 14 shows a process of fixing (bonding) the resin chip 54 in which the light emitting diode element 52 is embedded to the second substrate 55.
[0049]
When the resin chip 54 is fixed to the second substrate 55, since the adhesive layer 76 is previously applied on the second substrate 55, the adhesive layer 76 on the lower surface of the light emitting diode element 52 is selectively used. The resin chip 54 in which the light emitting diode element 52 is embedded can be fixed and arranged on the second substrate 55 by being cured. After this fixing, the adsorption chamber 74 portion of the adsorption device 73 is in a high pressure state, and the coupled state by adsorption between the adsorption device 73 and the resin chip 54 in which the light emitting diode element 52 is embedded is released.
[0050]
At this time, a beam 93 that gives energy for curing the resin of the adhesive layer 76 is irradiated from the back surface of the second substrate 55. For example, when a UV curable adhesive is used, it is performed by a UV irradiation apparatus. When a thermosetting adhesive is used, only the lower surface of the resin chip 54 in which the light emitting diode element 52 is embedded is cured by a laser. When a thermoplastic adhesive is used, the adhesive 76 is melted by laser irradiation for adhesion.
[0051]
An electrode layer 77 which is a wiring substrate that also functions as a shadow mask is provided on the second substrate 55, and a black chrome layer 78 is formed on the surface of the electrode layer 77 on the screen side. As a result, the contrast of the image is improved, the energy absorption rate in the black chrome layer 78 is increased, and the adhesive layer 76 can be hardened quickly by the selectively irradiated beam 93.
[0052]
Next, in FIG. 15, the light emitting diode elements 52R, 52G, and 52B of three colors of R (red), G (green), and B (blue) are arranged on the second substrate 55 and covered with the insulating layer 79. Shows the state.
[0053]
When the suction device 73 is used to mount the second substrate 55 at a position corresponding to each color, a pixel composed of three colors can be formed with the pixel pitch kept constant. In addition, as a material of the insulating layer 79, a transparent epoxy adhesive, a UV curable adhesive, polyimide, or the like can be used.
[0054]
In FIG. 15, the red light-emitting diode element 52R has a structure that does not have a hexagonal pyramid GaN layer, and is different in shape from the other light-emitting diode elements 52G and 52B. 52R, 52G, and 52B are already covered with the resin 53 as the resin chip 54, and the same handling can be realized because the shapes are the same regardless of the structure as the element.
[0055]
Next, as shown in FIG. 16, the electrode pads 57 and anode electrode pads 56 of the light emitting diode elements 52R, 52G, and 52B of three colors R, G, and B, and electrode layers on the second substrate 55 Corresponding to 77 and the like, via holes 70 ′ that are openings for electrically connecting these are formed, and wiring 86 is formed as shown in FIG. 17. The via hole 70 ′ is formed using, for example, a laser beam.
[0056]
The via hole 70 ′ formed at this time increases the area of the electrode pad 57 of each of the R, G, and B light emitting diode elements 52 R, 52 G, and 52 B and the electrode pad 56 on the anode side. The shape of the via hole 70 ′ corresponding to the electrode pad 56 can be increased, and the position accuracy of the via hole 70 ′ can be formed with coarser accuracy than the via hole directly formed in each light emitting diode element 52.
[0057]
After the wiring 86 is formed, a protective layer (not shown) is formed on the wiring to complete the panel of the image display device.
[0058]
As this protective layer, a material such as a transparent epoxy adhesive can be used in the same manner as the insulating layer 79 in FIG. This protective layer is cured by heating to completely cover the wiring. Thereafter, a driver IC is connected to the wiring at the end of the panel to produce a drive panel.
[0059]
Next, FIG. 21 shows an example in which a plurality of types of light emitting (diode) elements having different emission colors are collectively transferred onto a glass substrate 11 (corresponding to 55 described above) on which wiring is formed.
[0060]
On the glass substrate 11, the first wiring layer 12 and the second wiring layer 13 connected to the electrode layer 77 are formed orthogonal to each other, and the wiring layers 12 and 13 are connected to each other. The red light emitting diode element 52R, the green light emitting diode element 52G, and the blue light emitting diode element 52B are arranged in a matrix. The light emitting diode elements are alternately arranged in a matrix on the second substrate through the process as described above.
[0061]
Here, the glass substrate 11 is used as the substrate of the image display device, and the light emitting diode element is transferred thereon, but a polymer sheet or the like can also be used as the substrate to be transferred. It is also possible to use the second temporary holding member 67 as it is as a substrate. For example, when a polymer sheet is used as a substrate of an image display device, it is possible to realize an image display device that is flexible, lightweight, and difficult to break.
[0062]
[Problems to be solved by the invention]
Conventionally, a process of forming and forming a laser via (referred to as a connection hole formed by laser light, hereinafter simply referred to as a connection hole) on a printed circuit board (wiring board) or the like on which an insulating layer is formed, and this connection In the process of forming the wiring and the like around the hole, the electrode pad or the wiring under the insulating layer is made of a Cu layer, and the thickness of the Cu layer is generally 10 μm or more. Less susceptible to damage, CO on the electrode pad or wiring₂The connection hole can be processed and formed using laser light having a short wavelength and high output, such as a laser and a harmonic YAG laser.
[0063]
Then, after the connection hole is formed, the connection hole is filled with an electrolytic Cu plating layer or the like by an electrolytic plating method or the like, and then the wiring is formed.
[0064]
However, recently, when a Cu layer is formed as a wiring on a wiring board, there is a demand for reducing the thickness. This is because when the Cu wiring formed on the wiring substrate is patterned by the photoetching technique, the wiring is easily processed.
[0065]
In particular, when the thickness of the Cu layer such as the electrode pad or the wiring on the wiring substrate on which the insulating layer is formed is reduced to 1 μm, the effect becomes large, and the accuracy of the photoetching process is improved.
[0066]
However, in the case of manufacturing the image display device shown in FIGS. 6 to 17, the electrode 77 made of a Cu layer formed on the glass substrate of the wiring board, the electrode made of the Cu layer formed on the wiring, the resin chip 54, or the like. When the thickness of the pads 56, 57, etc. is about 1 μm, when the laser beam for forming the connection hole 70 ′ is overshot (over-irradiated) in the insulating layer 79 thereon, an electrode pad made of a Cu layer, Holes may be formed in the wiring or the like, causing failure such as disconnection.
[0067]
This is because the electrode pad made of a Cu layer, wiring, and the like have a high heat absorption rate, so that the heat generated by laser light irradiation is easily absorbed and processed.
[0068]
Therefore, when laser vias (connection holes) are formed on the insulating layer 79 using an excimer laser, a harmonic YAG laser, or the like, the material of the electrode pads and electrode layers in the insulating layer is not Cu but aluminum (Al). Then, due to the characteristics of aluminum (Al), which has a low heat absorption rate when irradiated with laser light, it is difficult to laser process electrode pads, wiring, etc., making it easy to process connection holes with high-power, short-wavelength lasers. become.
[0069]
However, when a Cu plating layer is formed in the connection hole for embedding the formed laser via (connection hole), the connection between the Cu plating layer and the Al layer is improved before the Cu plating. It is necessary to apply a pretreatment (acid treatment) to the surface of the Al layer, but the Al layer is attacked by this pretreatment (acid treatment), and it is difficult to form a Cu plating layer on the Al layer. .
[0070]
The present invention has been made in view of the above situation, and the object thereof is a multilayer wiring structure or an electrode lead-out structure that can satisfactorily connect these even when a Cu layer is formed on an Al layer. An electrical circuit device and a manufacturing method thereof are provided.
[0071]
[Means for Solving the Problems]
That is, in the present invention, an insulating layer is formed on an aluminum-based first conductive layer such as Al,
A connection hole is formed in the insulating layer on the first conductive layer,
A nickel-based second conductive layer such as Ni is formed in the connection hole,
A third conductive layer such as Cu is formed on the second conductive layer;
The present invention relates to a multilayer wiring structure or an electrode lead-out structure and a manufacturing method thereof.
[0072]
In the present invention, an insulating layer is formed on an aluminum-based first conductive layer such as Al that is connected to a circuit element or / and that forms a lower wiring.
A connection hole is formed in the insulating layer on the first conductive layer,
A nickel-based second conductive layer such as Ni is formed in the connection hole,
A third conductive layer such as Cu is formed on the second conductive layer;
The circuit element is connected to the wiring substrate by the third conductive layer;
The present invention relates to an electric circuit device and a manufacturing method thereof.
[0073]
According to the present invention, since the first conductive layer is formed of an aluminum-based material, the first conductive layer has durability against damage caused when the connection hole is formed, so that the damage to the first conductive layer is reduced. The durability can be maintained even if the first conductive layer is thinned.
[0074]
In addition, since the nickel-based second conductive layer is formed between the first conductive layer and the third conductive layer, the connection between the first conductive layer and the third conductive layer becomes possible. The acid treatment of the first conductive layer becomes unnecessary, and the connection with the third conductive layer becomes good with the first conductive layer protected by the second conductive layer.
[0075]
Furthermore, since the nickel-based second conductive layer is formed in the connection hole, the depth of the connection hole is reduced, so that the third conductive layer provided thereon is not disconnected and the reliability is increased.
[0076]
DETAILED DESCRIPTION OF THE INVENTION
In the present invention, the first conductive layer is preferably a lower wiring, an electrode pad or an electrode.
[0077]
In order to flatten the surface of the insulating layer, it is preferable that the connection hole on the first conductive layer connected to the circuit element is filled up to the height of the surface of the insulating layer with the second conductive layer.
[0078]
Further, it is desirable that the connection hole on the first conductive layer formed in the wiring substrate to which the circuit element is connected and fixed is buried with the second conductive layer so as to be shallower than the surface height of the insulating layer.
[0079]
In order to flatten the surface of the insulating layer, it is preferable that the connection hole on the first conductive layer connected to the circuit element is filled up to the height of the surface of the insulating layer with the second conductive layer.
[0080]
Also, the connection hole on the first conductive layer formed in the wiring substrate to which the circuit element is connected and fixed is buried by the second conductive layer so as to be shallower than the surface height of the insulating layer, and further on the second conductive layer. It is desirable to embed the fourth conductive layer up to the height of the surface of the insulating layer.
[0081]
The circuit element is preferably connected to the wiring board by the third conductive layer.
[0082]
Further, it is desirable that the connection hole is formed on the insulating layer by laser beam irradiation.
[0083]
The second conductive layer is preferably formed by an electroless plating method.
[0084]
The third conductive layer and / or the fourth conductive layer is preferably formed by a physical film forming method or a plating method of a conductive material.
[0085]
The circuit element is preferably a light emitting element.
[0086]
It is desirable to constitute an image display device or a light source device.
[0087]
Next, a preferred embodiment of the present invention will be specifically described with reference to the drawings.
[0088]
First embodiment
1 and 2 show a first embodiment of the present invention.
[0089]
In the present embodiment, the process is the same as that described above except that aluminum (Al) is used as the material of the electrode pad 56, the electrode pad 57, and the electrode layer 77 connected to the light emitting diode element 52. First, the steps from FIG. 6 to FIG. 16 are performed in the same manner.
[0090]
Thereafter, as shown in FIG. 1, a via hole 70 'is formed in the insulating layer 79 by laser light so that a part of the electrode pad 56 made of Al, the electrode pad 57, and the electrode layer 77 is exposed. Further, an electroless Ni plating process for depositing and depositing Ni in the via hole 70 ′ is performed to form an electroless Ni plating layer 81 in the via hole 70 ′. The Ni plating layer 81 is formed so as to completely fill the via hole 70 ′ on the resin chip 54 in which the light emitting diode element 52 is embedded, and is formed halfway through the via hole 70 ′ on the electrode layer 77 of the wiring board.
[0091]
Here, the reason why Al is used as the material of the electrode pad 56, the electrode pad 57, and the electrode layer 77 is that the Al is a material having a low laser absorptivity with respect to laser light. Even when a laser beam is irradiated when forming a via hole 70 ′ that is a connection hole on the electrode layer 77, the electrode pad 56 made of Al, the electrode pad 57, the electrode layer 77, and the like are deformed by heating due to the laser beam irradiation. This is because it is difficult to cause such problems.
[0092]
The reason why the electroless Ni plating layer 81 is formed on the electrode pad 56, the electrode pad 57, and the electrode layer 77 made of Al is as follows. For example, when the wiring 86 which is a Cu layer is applied directly to these by electroplating or the like, a pretreatment using an acid must be performed on the Al layer in order to improve the connectivity between the Cu layer and the Al layer. However, when this pretreatment with acid is performed, the Al layer is corroded. For this reason, both the Cu and Al metals have good connectivity between the Al layer and the Cu layer so that the Al layer and the Cu layer are not in direct contact with each other without the pretreatment with the acid. This is because by forming the electroless Ni plating layer 81, the connectivity and conductivity between the Al layer and the Cu layer thereon can be secured.
[0093]
The formation of the electroless Ni plating layer 81 proceeds by the following mechanism.
[0094]
For example, when hypophosphite is added to the electroless plating solution as a reducing agent, the following reaction occurs when Ni is deposited.
Ni²⁺+ H₂PO₂ ^-+ H₂O → Ni + H₂PO_Three ^-+ 2H⁺
H₂PO₂ ^-+ H₂O → H₂PO_Three ^-+ H₂
[0095]
In this case, the electroless Ni plating process on the electrode pad 56, the electrode pad 57, and the electrode layer 77 made of Al is performed after performing a zincate process as a pre-process.
[0096]
In this zincate treatment, Zn particles are first deposited on the Al surface by a substitution reaction between Al and Zn in an alkaline solution containing Zn ions, and then Zn and Ni undergo a substitution reaction during the reduction reaction described above. Ni precipitates. Thereafter, the precipitated Ni becomes a catalytic starting point (seed), and the reduction precipitation reaction by hypophosphite ions proceeds.
[0097]
Through these steps, the electroless Ni plating layer 81 is deposited only on the exposed portion where the electrode pad 56, the electrode pad 57, and the electrode layer 77 made of Al are exposed to the via hole 70 'as shown in FIG. grow up.
[0098]
Here, in the via hole 70 ′ on the electrode pad 56 and the electrode pad 57, the height at which the electroless Ni plating layer 81 is grown and formed is the same as the surface of the insulating layer 79, thereby The surface is relatively flattened, and in the next wiring process, the level difference between the buried surface of the via hole 70 ′ and the surface of the insulating layer 79 is eliminated (on the electrode pads 56 and 57) or reduced (on the electrode layer 77). The wiring 86 shown in FIG. 2 can be formed relatively easily.
[0099]
That is, as shown in FIG. 1, the depth of the via hole 70 'on the electrode pad 56 and the electrode pad 57 of the resin chip 54 is different from the depth of the via hole 70' on the electrode layer 77 on the wiring board. An electroless Ni plating layer 81 is formed in the via hole 70 ′ on the electrode layer 77 on the wiring substrate in accordance with the depth of the via hole 70 ′ on the electrode pad 57 and the electrode pad 57.
[0100]
Next, as shown in FIG. 2, the electroless Ni plating layer 81 embedded in the upper portion of the insulating layer 79, the electrode pad 56 and the via hole 70 ′ provided on the electrode pad 57, and the via hole 70 on the electrode layer 77. Cu is deposited on the electroless Ni plating layer 81 and the like deposited on by a physical film forming method such as sputtering, and this is patterned by photolithography to form a Cu wiring 86.
[0101]
As described above, in the present embodiment, the electrode pads 54 and 56 as the first conductive layer and the electrode layer 77 are formed of aluminum, and thus the via hole 70 ′ is formed in the insulating layer 79 thereon by laser light irradiation. In this case, since the laser beam has durability (low heat absorption rate), the damage associated with the formation of the laser via is eliminated, and the durability can be maintained even if the aluminum layer is made as thin as 1 μm.
[0102]
Further, by forming the electroless nickel plating layer 81 on these aluminum layers, the connection between the aluminum layers 54, 56, 77 and the Cu layer 86 is sufficient, and the acid treatment of the first conductive layer is performed at this connection. It becomes unnecessary.
[0103]
Furthermore, the formation of the electroless nickel plating layer 81 in the via hole 70 'eliminates or reduces the depth of the via hole. Therefore, the Cu layer 86 can be reliably formed on the via hole without disconnection. it can.
[0104]
That is, the surface of the insulating layer 79 is flattened by the presence of the electroless Ni plating layer 81, or the depth of the via hole 70 'becomes shallow and the level difference is reduced, so that the workability and adherence of the wiring 86 are good. Thus, no disconnection occurs.
[0105]
In addition, the presence of the electroless Ni plating layer 81 can relieve stress generated in the wiring 86 and the like due to the thermal expansion of the metal, so that disconnection does not occur and the resistance of the wiring can be reduced. If the Cu layer 86 is directly formed by sputtering or the like without providing the electroless Ni plating layer 81, the stress increases due to thermal expansion depending on the thickness, and disconnection is likely to occur.
[0106]
Further, since electrolytic plating is not performed for filling the via hole 70 ′, wiring necessary for forming the electrolytic plating layer need not be formed. The formation of the electroless Ni plating layer 81 makes it easy to control the depth of the via hole.
[0107]
When forming connection holes (vias) by irradiating with laser light, when processing with laser light such as high-power, short-wavelength UV-YAG and excimer lasers to reduce the size, they are formed with laser light. The size of the via hole and the electrode on the bottom surface of the via hole is required to be finely patterned, and the thickness of the electrode is also thinner, but in any case, the present embodiment can be effectively adapted. Become.
[0108]
This embodiment can be applied not only to a circuit device for a display element but also to a general electric circuit board.
[0109]
That is, this embodiment can be applied not only to a display device such as a display but also to a printed board or a flexible board.
[0110]
Second embodiment
3 to 5 show a second embodiment of the present invention.
[0111]
In the present embodiment, the above-described steps (steps from FIG. 6 to FIG. 16) are performed except that aluminum (Al) is used as the material of the electrode pad 56, the electrode pad 57, and the electrode layer 77 formed in the light emitting diode element 52. 3), via holes 70 'for connecting the electrode pads 56, the electrode pads 57, and the electrode layers 77 made of Al are formed by laser light, as shown in FIG. The electroless Ni plating layer 81 is grown and formed.
[0112]
Through these steps, the electroless Ni plating layer 81 is formed and grown in the via hole 70 ′ on the electrode pad 56, the electrode pad 57, and the electrode layer 77 made of Al. The electroless Ni plating layer 81 in the via hole 70 ′ formed for connection between the electrode pad 56 and the electrode pad 57 is formed and grown up to the same height as the surface of the insulating layer 79, so that the surface of the insulating layer 79 is formed. When planarized, in the next wiring process, there is almost no step on the surface of the insulating layer 79, and wiring formation becomes easy.
[0113]
In this case, as in the first embodiment described above, the depth of the via hole 70 ′ on the electrode pad 56 and the electrode pad 57 of the resin chip 54 and the depth of the via hole 70 ′ on the electrode layer 77 of the wiring board are determined. Although different, as shown in FIG. 3, the electroless Ni plating layer 81 is formed on the electrode layer 77 on the wiring board in accordance with the depth (height) of the electrode pad 56 and the electrode pad 57.
[0114]
Next, as shown in FIG. 4, the resin chip 54 (electrode pads 56, 57) is covered with a mask material (not shown), and palladium or the like is formed in the recesses on the electrode layer 77 in which the electroless Ni plating layer 81 is embedded to some extent. After performing the surface treatment by the above, by performing electroless Ni plating again, the fourth conductive layer 80 is formed up to the surface of the insulating layer 79 to completely fill the via hole 70 ′. Instead of the Ni plating, the Cu electroplating layer 80 may be formed by an electrolytic plating method using the electroless Ni plating layer 81 as an electrode.
[0115]
Thereafter, if the mask material is removed, the height of the plating layer 81 on the electrode pad 56 and the electrode pad 57 and the height of the plating layer 80 on the electrode layer 77 can be made equal to the surface height of the insulating layer 79. Therefore, the wiring layer 86 can be formed in a predetermined pattern with high accuracy by the photolithography technique. In this case, it may be desirable to polish the surface of the insulating layer 79 by, for example, chemical mechanical polishing (CMP). This is because the base can be planarized by such polishing. This is because the wiring layer 86 is easier to form.
[0116]
That is, as described above, the electroless Ni plating layer 81 is embedded on the electrode pad 56 and the electrode pad 57 of the resin chip 54, and the embedded surface is selectively masked with a photoresist, and then the electrode layer 77 is formed. A conductive layer 80 is formed on the electroless Ni plating layer 81 in the via hole 70 ', and a Cu layer is deposited by sputtering or the like and patterned to form a Cu wiring 86, as shown in FIG.
[0117]
Also in the present embodiment, as in the first embodiment described above, the electrode pads 56 and 57 and the electrode layer 77 as the first conductive layer are formed of aluminum, and therefore damage caused when the via hole 70 'is formed. Even in the case of thinning, durability against the above can be maintained.
[0118]
In addition, due to the presence of the electroless nickel plating layers 81 and 80 as the second conductive layer, sufficient connection between the aluminum layers 56, 57, and 77 and the Cu wiring 86 as the third conductive layer thereon is acid-treated. This is also possible without the need for heat, and it is possible to further suppress thermal stress during wiring formation and further prevent disconnection.
[0119]
Further, since the electroless nickel plating layer 81 is formed in the via hole 70 ′ and the conductive layer 80 is further buried thereon, the surface of the insulating layer 79 after removing the mask material is only on the resin chip 54. In addition, since the conductive layer 77 is planarized, the wiring layer 86 can be formed on the conductive layer 77 more reliably without disconnection.
[0120]
Further, when the Cu layer 80 is formed by electrolytic Cu plating, the electroless Ni plating layer 81 already formed in the via hole 70 ′ can play the role of an electrode necessary for electroplating, so that the electrolysis can be performed separately. It is not necessary to form a dedicated electrode for Cu plating.
[0121]
In addition, in the present embodiment, the same operations and effects as described in the first embodiment are produced.
[0122]
The embodiment of the present invention described above can be further modified based on the technical idea of the present invention.
[0123]
For example, in the above-described embodiment, the laser via and the electroless Ni plating thereon are applied to the pixel portion including the light emitting diode element 52. However, the present invention is similarly applied to the peripheral drive circuit. it can.
[0124]
Further, the electrode lead-out structure of the above embodiment may be applied to connection of upper and lower wirings in a multilayer wiring structure.
[0125]
The above embodiment relates to a light emitting diode element, but can be applied to other arbitrary elements. For example, a semiconductor laser element, a liquid crystal control element, a photoelectric conversion element, and a piezoelectric element. The present invention can be applied to an electric circuit device such as a thin film transistor element, a thin film diode element, a resistance element, a switching element, a minute magnetic element, a minute optical element, and a light emitting display device including these.
[0126]
The material of each of the electrode pads 56 and 57 and the electrode layer 77 is Al alone, but an Al alloy such as Al-Si may be used, and the material of the electroless Ni plating layer 81 is Ni simple. In addition, Ni alloy may be used, and the material of the wiring 86 may be not only Cu alone but also Cu alloy, and other conductive materials.
[0127]
Further, the structure of the resin chip, particularly the electrode extraction structure, the type of laser light, the irradiation amount, the irradiation time, the irradiation position, etc. at each step may be arbitrarily changed as long as there are predetermined effects.
[0128]
[Effects of the invention]
In the present invention, as described above, since the first conductive layer is formed of an aluminum-based material, the conductive layer has durability against damage caused when the connection hole is formed, and thus the damage to the first conductive layer is reduced. In addition, durability can be maintained even if the first conductive layer is thinned.
[0129]
In addition, since the nickel-based second conductive layer is formed between the first conductive layer and the third conductive layer, the connection between the first conductive layer and the third conductive layer becomes possible. The acid treatment of the first conductive layer becomes unnecessary, and the connection with the third conductive layer becomes good with the first conductive layer protected by the second conductive layer.
[0130]
Furthermore, since the nickel-based second conductive layer is formed in the connection hole, the depth of the connection hole is reduced, so that the third conductive layer provided thereon is not disconnected and the reliability is increased.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a process of embedding an electroless Ni plating layer in a via hole in a first embodiment of the present invention.
FIG. 2 is a cross-sectional view of a process for forming a wiring in the same.
FIG. 3 is a cross-sectional view of a process of embedding an electroless Ni plating layer in a via hole in the second embodiment of the present invention.
FIG. 4 is a cross-sectional view of the process of further embedding a plating layer in the via hole.
FIG. 5 is a cross-sectional view of a step of forming a wiring in the same.
FIG. 6 is a cross-sectional view of a process of irradiating a resin layer with laser light in the prior invention.
FIG. 7 is a cross-sectional view of a process for transferring a light emitting diode element to a resin layer.
FIG. 8 is a cross-sectional view showing a state where the light emitting diode element is transferred to a resin layer.
FIG. 9 is a cross-sectional view of the process of embedding the light-emitting diode element in the resin layer.
FIG. 10 is a cross-sectional view of the light emitting diode element embedded in a resin layer.
FIG. 11 is a cross-sectional view of a process for further transferring a resin layer in which a light emitting diode element is embedded by irradiating a laser beam.
FIG. 12 is a cross-sectional view of the process of separating the transferred resin layer after forming the electrode pad.
FIG. 13 is a sectional view of a process of picking up a resin chip.
FIG. 14 is a cross-sectional view of a process of bonding a resin chip to a printed circuit board.
FIG. 15 is a cross-sectional view of an image display device covered with an insulating layer.
FIG. 16 is a sectional view showing a state where a via hole is formed.
FIG. 17 is a cross-sectional view of a state where wiring is formed.
FIG. 18 is a cross-sectional view and a plan view of the light-emitting diode element.
FIG. 19 is a perspective view of the resin chip.
FIG. 20 is a plan view of the resin chip.
FIG. 21 is a plan view of a part of an image display device using light emitting diode elements of the same three colors.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... Glass substrate, 12 ... 1st wiring layer, 13 ... 2nd wiring, 21 ... Underlayer growth layer,
22 ... GaN: Si layer, 23 ... InGaN layer, 24 ... GaN: Mg layer,
25 ... p electrode, 26 ... n electrode, 50 ... first substrate, 51 ... first temporary holding member,
52 ... Light emitting diode element, 52R ... Red light emitting diode element,
52G ... Green light emitting diode element, 52B ... Blue light emitting diode element,
53 ... Resin layer, 54 ... Resin chip, 55 ... Second substrate, 56, 57 ... Electrode pad,
60 ... second release layer, 62g ... groove, 64 ... first release layer,
67 ... second temporary holding member, 70, 70 '... via hole, 71 ... element isolation groove,
72 ... Metal plate, 73 ... Adsorption device, 74 ... Adsorption chamber, 75 ... Adsorption hole,
76 ... Adhesive layer, 77 ... Electrode layer, 78 ... Black chrome layer, 79 ... Insulating layer,
80 ... plating layer, 81 ... electroless Ni plating layer, 82 ... soft part,
84 ... Pressure means, 86 ... wiring, 93 ... beam

Claims (13)

A circuit element including an aluminum-based first electrode and a second electrode is embedded in a resin layer and connected to the first electrode and the second electrode formed so as to be connected to the first electrode. A surface of the flat resin chip formed with the second electrode pads formed on the surface side facing the surface side is fixed to the wiring substrate on which the aluminum-based third electrode is formed. And the process of
A second step of covering the resin chip fixed to the wiring board with an insulating layer;
The first opening, the second opening, and the third opening are respectively formed so that a part of each of the first electrode pad, the second electrode pad, and the third electrode is exposed. Forming the insulating layer, wherein the first opening and the second opening have the same depth, and the third opening
A third step in which the depth of the opening is deeper than the depth of the first opening and the second opening;
A nickel-based first conductive material on each surface of the first electrode pad in the first opening and the second electrode pad in the second opening to the same height (H) as the surface of the insulating layer. Forming a layer on the surface of the third electrode in the third opening, in the first opening and in the second opening.
A fourth step of forming the nickel-based first conductive layer having the same thickness as the first conductive layer formed in the mouth ;
A fifth step comprising the following step A or step B for forming a conductive layer,
In the step A, the surface of the first conductive layer, the surface of the insulating layer formed on the respective surfaces of the first electrode pad, the second electrode pad, and the third electrode, the surface of the insulating layer, and the third opening A conductive material is deposited on each of the inner wall surfaces of the portion and patterned to form a first conductive layer formed on the surface of the third electrode and a first electrode formed on the surface of the second electrode pad. Forming a third conductive layer for connecting the first conductive layer,
In the step B, a surface of the first conductive layer formed on each surface of the first electrode pad in the first opening and the second electrode pad in the second opening is covered with a mask material. ,
After forming the second conductive layer up to the surface of the insulating layer on the surface of the first conductive layer formed inside the front third opening, the surface of the first conductive layer and the insulating layer The first conductive layer is formed on the second conductive layer and the second electrode pad surface by depositing a conductive material and patterning the second conductive layer and the second conductive layer. Forming a third conductive layer connecting the conductive layer of
A manufacturing method of a multilayer wiring structure or an electrode lead-out structure.   2. The multilayer wiring structure or electrode lead-out structure according to claim 1, wherein the first opening, the second opening, and the third opening are formed on the insulating layer by laser light irradiation. Method.   The method for manufacturing a multilayer wiring structure or an electrode lead-out structure according to claim 1, wherein the first conductive layer is formed by an electroless plating method.   The manufacturing method of the multilayer wiring structure or electrode extraction structure of Claim 1 which forms the said 2nd conductive layer or / and the said 3rd conductive layer by the physical film-forming method or plating method of a conductive material.   The manufacturing method of the multilayer wiring structure or electrode extraction structure of Claim 1 which uses the said circuit element as a light emitting element.   The manufacturing method of the multilayer wiring structure or electrode extraction structure of Claim 1 which the said 2nd conductive layer consists of a nickel-type plating layer or copper plating layer which consists of an electroless plating layer.   The manufacturing method of the multilayer wiring structure or electrode extraction structure of Claim 1 with which a said 3rd conductive layer consists of a copper wiring layer.   The manufacturing method of an electric circuit apparatus based on the manufacturing method of the multilayer wiring structure or electrode extraction structure of any one of Claims 1-7.   The method for manufacturing an electric circuit device according to claim 8, wherein the image display device or the light source device is manufactured. A first electrode pad formed so that a circuit element including an aluminum-based first electrode and a second electrode is embedded in a resin layer and connected to the first electrode;
The surface of the flat resin chip formed on the surface side of the second electrode pad formed so as to be connected to the electrode is fixed to the surface side, and an aluminum-based third electrode is formed. Wiring board,
An insulating layer covering the resin chip fixed to the wiring board;
Openings formed in the insulating layer so as to expose portions of the first electrode pad, the second electrode pad, and the third electrode, respectively, and having the same depth An opening and a second opening, and a third opening deeper than the first and second openings,
A nickel-based first layer formed on each surface of the first electrode pad in the first opening and the second electrode pad in the second opening to the same height (H) as the surface of the insulating layer .
1 conductive layer and the surface of the third electrode in the third opening, in the first opening and in the front
Serial formed with the same thickness as the second said first conductive layer formed in the opening, and the first conductive layer of the nickel-based,
A conductive layer comprising the following conductive layer A or conductive layer B;
The conductive layer A includes a surface of the first conductive layer formed on each surface of the first electrode pad, the second electrode pad, and the third electrode, a surface of the insulating layer, A conductive material is deposited on the inner wall surface of the third opening and patterned to form the first conductive layer formed on the surface of the third electrode and the surface of the second electrode pad. A third conductive layer connecting the formed first conductive layer;
The conductive layer B is formed by masking a surface of the first conductive layer formed on each surface of the first electrode pad in the first opening and the second electrode pad in the second opening. A surface of the first conductive layer formed inside the third opening, a surface of the second conductive layer formed up to the surface of the insulating layer, and a surface of the first conductive layer And a first conductive layer formed on the surface of the second conductive layer and the second electrode pad by depositing a conductive material on the surface of the insulating layer and patterning it. A third conductive layer connecting
Multi-layer wiring structure or electrode extraction structure.   The multilayer wiring structure or electrode lead-out structure according to claim 10, wherein the circuit element is a light emitting element.   An electric circuit device having the multilayer wiring structure or the electrode lead-out structure according to any one of claims 10 and 11.   The electric circuit device according to claim 12, constituting an image display device or a light source device.

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