TWI799410B - Integrated circuit - Google Patents

Integrated circuit Download PDF

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Publication number
TWI799410B
TWI799410B TW107112412A TW107112412A TWI799410B TW I799410 B TWI799410 B TW I799410B TW 107112412 A TW107112412 A TW 107112412A TW 107112412 A TW107112412 A TW 107112412A TW I799410 B TWI799410 B TW I799410B
Authority
TW
Taiwan
Prior art keywords
integrated circuit
integrated
circuit
Prior art date
Application number
TW107112412A
Other languages
Chinese (zh)
Other versions
TW201842599A (en
Inventor
李在鵬
都楨湖
宋泰中
李昇映
鄭鐘勳
柳志秀
Original Assignee
南韓商三星電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 南韓商三星電子股份有限公司 filed Critical 南韓商三星電子股份有限公司
Publication of TW201842599A publication Critical patent/TW201842599A/en
Application granted granted Critical
Publication of TWI799410B publication Critical patent/TWI799410B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
TW107112412A 2017-04-11 2018-04-11 Integrated circuit TWI799410B (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
??10-2017-0046929 2017-04-11
KR20170046929 2017-04-11
KR10-2017-0046929 2017-04-11
KR10-2017-0113950 2017-09-06
KR1020170113950A KR102475281B1 (en) 2017-04-11 2017-09-06 Standard cell and integrated circuit including the same
??10-2017-0113950 2017-09-06

Publications (2)

Publication Number Publication Date
TW201842599A TW201842599A (en) 2018-12-01
TWI799410B true TWI799410B (en) 2023-04-21

Family

ID=64101927

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107112412A TWI799410B (en) 2017-04-11 2018-04-11 Integrated circuit

Country Status (2)

Country Link
KR (1) KR102475281B1 (en)
TW (1) TWI799410B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102157355B1 (en) 2019-04-23 2020-09-18 삼성전자 주식회사 Integrated circuit including standard cells, method and computing system for fabricating the same
CN111244064A (en) * 2020-01-19 2020-06-05 比特大陆科技有限公司 Semiconductor chip, semiconductor device, and data processing apparatus

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5933725A (en) * 1998-05-27 1999-08-03 Vanguard International Semiconductor Corporation Word line resistance reduction method and design for high density memory with relaxed metal pitch
TW200807685A (en) * 2006-07-28 2008-02-01 Mediatek Inc Filler capacitor with a multiple cell height
US20140252650A1 (en) * 2013-03-08 2014-09-11 Kabushiki Kaisha Toshiba Semiconductor integrated circuit
US20150214154A1 (en) * 2014-01-24 2015-07-30 Renesas Electronics Corporation Semiconductor Device and IO-Cell

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4837870B2 (en) 2002-11-05 2011-12-14 株式会社リコー Layout design method for semiconductor integrated circuit
KR20120127252A (en) * 2011-05-13 2012-11-21 에이알엠 리미티드 Integrated circuit, method of generating a layout of an integrated circuit using standard cells, and a standard cell library providing such standard cells
US9653393B2 (en) * 2013-12-12 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method and layout of an integrated circuit
KR101697343B1 (en) * 2014-08-22 2017-01-18 삼성전자주식회사 Method of designing layout of integrated circuit and method of manufacturing the integrated circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5933725A (en) * 1998-05-27 1999-08-03 Vanguard International Semiconductor Corporation Word line resistance reduction method and design for high density memory with relaxed metal pitch
TW200807685A (en) * 2006-07-28 2008-02-01 Mediatek Inc Filler capacitor with a multiple cell height
US20140252650A1 (en) * 2013-03-08 2014-09-11 Kabushiki Kaisha Toshiba Semiconductor integrated circuit
US20150214154A1 (en) * 2014-01-24 2015-07-30 Renesas Electronics Corporation Semiconductor Device and IO-Cell

Also Published As

Publication number Publication date
KR20180114812A (en) 2018-10-19
KR102475281B1 (en) 2022-12-08
TW201842599A (en) 2018-12-01

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