KR20180114812A - Standard cell and integrated circuit including the same - Google Patents

Abstract

According to an exemplary embodiment of the present disclosure, an integrated circuit including a plurality of standard cells to provide high degree of freedom of design may comprise: a power rail formed by using a plurality of conductive layers at the boundaries of the standard cells for providing power to the standard cells and extending in a first horizontal direction; and at least one signal line passing the power rail in a second horizontal direction orthogonal to the first horizontal direction to transfer an input signal or an output signal of the standard cells and formed at one of the conductive layers. The power rail may include a conductive line formed at the conductive layer in which at least one signal line is formed and extending in the first horizontal direction insulated with at least one signal line.

Description

[0001] STANDARD CELL AND INTEGRATED CIRCUIT INCLUDING THE SAME [0002]

Technical aspects of the present disclosure relate to integrated circuits, and more particularly, to integrated circuits including standard cells and methods of manufacturing the same.

As the semiconductor process is miniaturized, the pattern included in the integrated circuit may have a reduced width and / or thickness, which may increase the effect of IR drop on the pattern. The transition of the signal due to the IR drop may be delayed, and as a result, the performance of the integrated circuit may deteriorate. Increasing the width of the pattern to mitigate the IR drop or using overlapping patterns may be considered, but these approaches can reduce the space efficiency of the integrated circuit and allow only limited use of the structure in the integrated circuit have.

The technical idea of the present disclosure relates to an integrated circuit including a standard cell, which provides a standard cell that eliminates the IR drop and provides a high degree of design freedom, an integrated circuit comprising the same, and a method of manufacturing the integrated circuit.

In order to achieve the above object, an integrated circuit including a plurality of standard cells according to one aspect of the technical idea of the present disclosure includes a plurality of standard cells, A power rail including first and second conductive lines extending in parallel and extending in a first horizontal direction and electrically connected to each other and a second power line extending between the first and second conductive lines to transmit an input signal or an output signal of the standard cell And at least one third conductive line extending in a second horizontal direction perpendicular to the first horizontal direction.

An integrated circuit including a plurality of standard cells according to an aspect of the technical idea of the present disclosure includes first and second integrated circuits arranged in a first horizontal direction and having the same length in a second horizontal direction orthogonal to the first horizontal direction, 2 standard cell, first and second standard cells extending in a first horizontal direction and spaced apart from each other in a vertical direction at the boundaries of the first and second standard cells in order to supply power to the first and second standard cells, A power rail comprising a conductive line and at least one electrical conductor extending between the first and second standard cells for passing an input signal or an output signal of the first standard cell and extending in a second horizontal direction, 3 conductive line, the power rail extending in the first horizontal direction at the boundary of the second standard cell and electrically connected to the first and second conductive lines and being identical to the third conductive line It may include a fourth conductive line formed on the conductive layer.

An integrated circuit including a plurality of standard cells according to an aspect of the technical idea of the present disclosure is formed using a plurality of conductive layers at a boundary of a plurality of standard cells to supply power to a plurality of standard cells, A power rail extending in the first horizontal direction and a power rail extending in the second horizontal direction orthogonal to the first horizontal direction for conveying an input signal or an output signal of the standard cell, And the power rail may include a first horizontally extending conductive line formed in the conductive layer on which the at least one signal line is formed and insulated from the at least one signal line.

According to an exemplary embodiment of the present disclosure, an integrated circuit can have efficiently routed patterns while having a relaxed IR drop.

In addition, according to an exemplary embodiment of the present disclosure, problems due to micronized semiconductor processes due to relaxed IR drop and efficiently routed patterns can be solved.

In addition, the integrated circuit can have improved performance due to the relaxed IR drop and efficiently routed patterns.

The effects obtainable in the exemplary embodiments of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned can be obtained from the following description of the exemplary embodiments of the present disclosure, And can be clearly understood and understood by those skilled in the art to which the embodiments belong. That is, unintended effects of implementing the exemplary embodiments of the present disclosure may also be derived from those of ordinary skill in the art from the exemplary embodiments of the present disclosure.

The drawings attached hereto are not to scale for convenience of illustration and may be exaggerated or reduced in size.
1 is a diagram illustrating a portion of an integrated circuit according to an exemplary embodiment of the present disclosure;
Figures 2a and 2b are illustrations of examples of cross sections of an integrated circuit cut parallel to the Z-axis direction along line X1-X1 'of Figure 1 in accordance with exemplary embodiments of the present disclosure.
Figures 3A-3C show examples of power rails according to comparative examples.
4 is a diagram illustrating a portion of an integrated circuit in accordance with an exemplary embodiment of the present disclosure;
Figures 5A and 5B are views showing a standard cell according to an exemplary embodiment of the present disclosure;
Figures 6A and 6B are views showing a standard cell according to an exemplary embodiment of the present disclosure;
7 is a diagram illustrating a portion of an integrated circuit in accordance with an exemplary embodiment of the present disclosure;
8A-8C are diagrams illustrating power rails in accordance with exemplary embodiments of the present disclosure.
Figures 9A-9C are illustrations of examples of structures for electrically interconnecting conductive lines of different layers according to an exemplary embodiment of the present disclosure.
10A and 10B are views showing power rails according to an exemplary embodiment of the present disclosure;
11 is a flow diagram illustrating a method of fabricating an integrated circuit including a plurality of standard cells in accordance with an exemplary embodiment of the present disclosure;
Figure 12 is a block diagram illustrating a system-on-chip SoC in accordance with an exemplary embodiment of the present disclosure.
13 is a block diagram illustrating a computing system including a memory for storing a program in accordance with an exemplary embodiment of the present disclosure.

1 is a view of a portion of an integrated circuit 10 in accordance with an exemplary embodiment of the present disclosure, and FIGS. 2A and 2B are cross-sectional views along line X1-X1 'of FIG. 1 in accordance with exemplary embodiments of the present disclosure Are views showing examples of cross sections of the integrated circuit 10 cut in parallel to the Z-axis direction. For ease of illustration, Figures 1, 2A, and 2B show only some of the layers included in the integrated circuit 10. The drawings herein may show some of the layers formed by a back end of line (BEOL) process, except for layers formed by a font end of line (FEOL) process. Further, in this specification, a plane made up of the X-axis and the Y-axis can be referred to as a horizontal plane, and a component arranged in a + Z direction relative to other components can be referred to as being on another component, A component arranged in a relatively-Z direction may be referred to as being under another component.

Referring to Figures 1, 2A, and 2B, the integrated circuit 10 may include standard cells C11 and C12, as shown by the thick dotted lines. A standard cell is a unit of a layout included in the integrated circuit 10, and the integrated circuit 10 may include a large number of various standard cells. The standard cells may have a structure conforming to a predetermined standard. For example, as shown in FIG. 1, the standard cells C11 and C12 may have a constant height, that is, a length Y10 in the Y-axis direction, and may extend in parallel in the X- And may have a boundary overlapping with a pair of extended power rails PR11 and PR12. Although the standard cells C11 and C12 in FIG. 1 are shown as including the patterns of the M1 to M3 layers, the standard cells C11 and C12 include patterns of the M1 layer or patterns of the M1 layer to the M2 layer You may. For example, the structure of the standard cells C11 and C12 defined by the standard cell library may be defined from the substrate to the M1 layer or M2 layer, and some patterns of the M2 layer and the pattern of the M3 layer may be defined as standard cells C11 , C12) may be those determined in the routing step after the placement of the standard cells C11 and C12 in the course of designing.

Standard cells C11 and C12 may include patterns for movement of signals. For example, the first standard cell C11 may include a pattern in which an internal signal generated in the first standard cell C11 moves, and the input and output signals of the first standard cell C11 may be Moving patterns, i.e., input pins and output pins. In the integrated circuit 10 of FIG. 1, the input and output pins of the first standard cell C11 may be patterns formed in the M2 layer. The input pin and the output pin of the first standard cell C11 may be electrically connected to the outside of the first standard cell C11, for example, the output pin and the input pin of another standard cell, respectively. In order to electrically connect the input pin and / or the output pin of the first standard cell C11 to the outside of the first standard cell C11, patterns passing through the boundary of the first standard cell C11 may be required . For example, as shown in FIG. 1, patterns of the M3 layer connected to the input pin and / or the output pin of the first standard cell C11 formed in the M2 layer and the output pins and vias, respectively, (C11). 1, the input pins and / or the output pins of the first standard cell C11 formed on the M2 layer are extended to allow the patterns of the M2 layer to pass through the first standard cell C11 in the Y axis direction You may. As described later, the operation of connecting the input pins and the output pins of the standard cells C11 and C12 (that is, the task of generating patterns or signal routing) includes power rails PR11, PR12). ≪ / RTI >

The power rails PR11 and PR12 for supplying power to the standard cells C11 and C12 can be arranged in the integrated circuit 10 at an interval equal to the height Y10 of the standard cell, Y10), that is, in the X-axis direction. In some embodiments, a positive supply voltage (e.g., VDD) may be applied to the first power rail PR11 and a negative supply voltage (e.g., VSS) may be applied to the second power rail PR12 . On the other hand, in some embodiments, a negative supply voltage (e.g., VSS) may be applied to the first power rail PR11 and a positive supply voltage (e.g., VDD) may be applied to the second power rail PR12 . In the following exemplary embodiments of the present disclosure, it is described that the positive supply voltage VDD is applied to the first power rail PR11 and the negative supply voltage VSS is applied to the second power rail PR12, It is to be understood that the technical idea of the disclosure is not limited thereto. Elements such as transistors formed in the standard cells C11 and C12 can receive current from the first power rail PR11 and draw current to the second power rail PR12.

As the semiconductor process is miniaturized, the width and / or thickness (i.e., the Z-direction length) of the patterns included in the integrated circuit can be reduced, and the size of the standard cells can also be reduced. Thus, the effect of the IR drop occurring in the pattern can be significant, and in particular the IR drop occurring in the power rails supplied to the standard cells of the integrated circuit will delay the transition of the signals, thereby degrading the resulting performance of the integrated circuit It can be a major cause. As one of the methods for mitigating such an IR drop, the power rails PR11 and PR12 may include overlapping patterns. For example, as shown in FIG. 1, the first power rail PR11 includes electrically conductive lines L11 and L31 extending parallel to each other in the X-axis direction, and electrically conductive lines L11 and L31 electrically And the second power rail PR12 may include vias for connecting the conductive lines L12 and L32 and the conductive lines L12 and L32 that extend parallel to each other in the X axis direction Lt; / RTI > As shown in FIG. 1, the conductive lines L11 and L12 may be formed in the M1 layer, and the conductive lines L31 and L32 may be formed in the M3 layer.

As shown in FIG. 1, the power rails PR11 and PR12 may partially include the patterns of the M2 layer extending in the X-axis direction, that is, the conductive lines L21 and L22. Accordingly, in the sections where the conductive lines L21 and L22 of the M2 layer are formed in the power rails PR11 and PR12, the mitigating effect of the IR drop can be enhanced. In addition, a space where the patterns of the M2 layer are not formed in the power rails PR11 and PR12 can be used for signal routing of the standard cells C11 and C12. 1, the input pin and / or the output pin of the first standard cell C11 extend in the Y-axis direction to connect the first power rail PR11 and / or the second power rail PR12 L22 of the M2 layer included in the power rails PR11 and PR12 may be formed in the power lines PR11 and PR12 and the conductive lines L23 and L24 may be formed in the power lines PR11 and PR12, (I.e., the length in the Y-axis direction) may be equal to or greater than the width (i.e., the length in the X-axis direction) of the conductive lines L23, L24, and L25 for signal routing. Accordingly, the integrated circuit 10 can achieve not only the relaxation of the IR drop, but also the freedom of signal routing. Details of the structure of the power rails PR11 and PR12 will be described later with reference to Figs. 2A and 2B showing examples of cross sections of the second power rail PR12, and the first power rail PR11 is also a second It will be understood that it may have the same or similar structure as the examples of the power rail PR12.

Referring to FIG. 2A, the second power rail PR12 may include conductive lines L12 and L32 extending parallel to each other in the X-axis direction and formed in the M1 layer and the M3 layer, respectively, And a conductive line L22 formed in the M2 layer extending in the X-axis direction in one of the divided regions R22. The second power rail PR12 includes a plurality of vias V11, V12, V13, V21, V22 and V23 for electrically interconnecting the conductive lines L12, L22 and L32 in the region R22 . A region R21 where the pattern of the M2 layer is not formed in the second power rail PR12 is electrically connected to the conductive lines L23, L24 and L25 through which the input signal and / or the output signal of the first standard cell C11 move And the conductive lines L23, L24 and L25 can pass through the second power rail PR12 in the Y axis direction. Thus, the region R21 of the second power rail PR12 can be used for signal routing while the region R22 of the second power rail PR12 can be used for IR drop mitigation. The area R21 of the second power rail PR12 is provided for a standard cell having a relatively large number of input pins and output pins While the region R22 of the second power rail PR12 may be provided for a standard cell (e.g., C12) in which the electrical characteristics of the output signal are relatively important.

Referring to FIG. 2B, the vias included in the region R22 of the second power rail PR12 in some embodiments may have a bar shape. For example, vias V11 ', V12', V13 ', V21', V22 ', and V23' for electrically interconnecting the conductive lines L12, L22, and L32, Shaped bar shape extending in the X-axis direction, and can be referred to as bar-type vias. That is, the length X20b in the X axis direction of the vias V11 'and V21' in FIG. 2B may be larger than the length X20a in the X axis direction of the vias V11 and V21 in FIG. 2A . Due to the bar shaped vias V11 'and V21', the resistance values between the conductive lines L12, L22 and L32 of FIG. 2B can be reduced and the IR drop can be further mitigated. Although FIG. 2B shows an example in which all the vias V11 ', V12', V13 ', V21', V22 ', V23' of the second power rail PR12 have a bar shape, It will be understood that it may have a shape. Further, the vias included in the second power rail PR12, without being limited to the name of the bar shape, may have any shape that increases the amount of the plug filling the via to reduce the via resistance, for example, Section.

Figures 3A-3C show examples of power rails according to comparative examples. As described above with reference to Figures 1, 2A, and 2B, the power rails in accordance with the exemplary embodiments of the present disclosure may include conductive lines formed in the M1 and M3 layers, respectively, And may partially include a conductive line formed in the M2 layer.

Referring to FIG. 3A, the power rail PR30a according to the comparative example may include conductive lines L01a and L02a that are respectively formed in the M1 layer and the M3 layer and extend in parallel with each other in the X axis direction, And vias for electrically interconnecting the lines L01a and L02a. Due to the conductive line L02a, in order to electrically connect the input pin and / or the output pin formed in the M2 layer of the standard cell adjacent to the power rail PR30a to the outside of the standard cell, the M3 layer or the upper conductive layer May be required, and signal routing congestion may occur accordingly. In some cases, the pattern formed in the M2 layer in the standard cell due to the semiconductor process for fabricating the integrated circuit can be limited to be formed in a direction parallel to the gate line (e.g., the Y-axis direction in Fig. 1) , This restriction can add to signal routing congestion. Further, in some cases, the pattern formed on the M2 layer due to the semiconductor process may have a width (i.e., a length in the Y-axis direction in Fig. 3A) and / or a thickness The length in the axial direction) may be small. As described above, the power rail PR30a including the conductive line L01a of the M1 layer and the conductive line L02a of the M2 layer may not only cause signal routing congestion, but also mitigate the effect of reducing the IR drop.

Referring to FIG. 3B, the power rail PR30b according to the comparative example may include a conductive line L01b formed in the M1 layer and extending in the X-axis direction. The conductive lines formed in the M2 layer in which the signal of the standard cell moves can extend across the power rail PR30b in the Y axis direction. Thus, in the example of FIG. 3B, the degree of freedom of signal routing can be ensured while the influence of the IR drop generated in the power rail PR30b can be increased by supplying power to standard cells only through the conductive line L01b.

Referring to FIG. 3C, the power rail PR30c according to the comparative example includes conductive lines L01c, L02c, and L03c that are formed respectively in the M1 layer, the M2 layer, and the M3 layer and extend in parallel with each other in the X axis direction And may include vias for electrically interconnecting the conductive lines L01c, L02c, L03c. The power rail PR30c of FIGS. 3A and 3C can have a relaxed IR drop than the power rails PR30a and PR30b of FIGS. 3A and 3B, but the use of the M3 layer as well as the M2 layer for signal routing is limited Signal routing congestion can be increased.

As described above with reference to Figures 1, 2A, and 2B, other power rails in the exemplary embodiments of the present disclosure may include conductive lines formed in the M1 and M3 layers, respectively, and extending parallel to each other , And a conductive line formed in the M2 layer. As will be described below with reference to the drawings, the power rail can remove the conductive lines formed in the M2 layer in the region adjacent to the standard cell where signal routing is important, and the IR drop can be formed in the M2 layer And may include a conductive line. Thus, the IR drop in the power rail can be mitigated while the degree of signal routing freedom is ensured.

4 is a diagram illustrating a portion of an integrated circuit 40 in accordance with an exemplary embodiment of the present disclosure.

4, the integrated circuit 40 may include a plurality of power rails PR41 to PR44 extending parallel to each other in the X-axis direction, and disposed between the plurality of power rails PR41 to PR44 A plurality of standard cells C41 to C49 may be included. Each of the plurality of standard cells C41 to C49 may include at least one active region extending in the X-axis direction and at least one gate line extending in the Y-axis direction. For example, as shown in FIG. 4, the standard cell C41 may include active regions AC1 and AC2 extending in the X-axis direction, and a gate line GL1 extending in the Y- And may include a plurality of gate lines. In some embodiments, active areas AC1 and AC2 may comprise a semiconductor such as Si or Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs, or InP, and may include a conductive region, A well, and an impurity-doped structure. The gate lines may comprise a work-function metal-containing layer and a gap-fill metal film. For example, the work function metal-containing layer may include at least one metal of Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd, The metal film may be composed of a W film or an Al film. In some embodiments, the gate lines may comprise a laminated structure of TiAlC / TiN / W, a laminated structure of TiN / TaN / TiAlC / TiN / W, or a laminated structure of TiN / TaN / TiN / TiAlC / have.

Each of the power rails PR41 to PR44 shown in Fig. 4 includes a plurality of power lines PR41 to PR44, which are respectively formed in the M1 layer and the M3 layer and extend in parallel with each other in the X axis direction, as described above with reference to Figs. 1, 2A, Lt; / RTI > In FIG. 4, the power rails PR41 to PR44 may include a conductive line formed in the M2 layer in the portion where the pattern of the M2 layer is drawn on the power rails PR41 to PR44.

Referring to FIG. 4, in some embodiments, the power rails PR41 to PR44 may include a conductive line formed in the M2 layer with respect to the boundary of the standard cell. For example, as shown in FIG. 4, the first and second power rails PR41 and PR42 may each include conductive lines of the M2 layer overlapping the boundary of the standard cell C43. Similarly, the second and third power rails PR42 and PR43 may each include conductive lines of the M2 layer overlapping the boundaries of the standard cells C44 and C45, and the third and fourth power rails PR43 , PR44 may include the conductive lines of the M2 layer overlapping the boundary of the standard cell C49, respectively. Further, the conductive lines of the M2 layer may be continuous in the standard cells adjacent to each other in the X-axis direction, such as the standard cells C44 and C45. The regions where the conductive lines of the M2 layer are not arranged in the power rails PR41 to PR44 may be used for the patterns of the M2 layer for signal routing of the standard cells C41 to C49.

As illustrated in FIGS. 5A, 5B, 6A and 6B, in some embodiments, the standard cells may have a boundary overlapped with a conductive line formed in the M2 layer of the power rails PR41 to PR44, It can be classified into the first group and the second group which is not. For example, in FIG. 4, the standard cells C43, C44, C45, and C49 may belong to a first group having a boundary overlapped with a conductive line formed in the M2 layer in the adjacent power rail, while the standard cells C41, , C46, C47, and C48 may belong to a second group that is not forced to have a boundary overlapped with a conductive line formed in the M2 layer in adjacent power rails.

The first group may be supplied to the transistors included in the first group of standard cells due to the relatively good performance, e.g., the fast rise / fall time of the output signal or a short propagation delay, Lt; RTI ID = 0.0 > current. ≪ / RTI > For example, standard cells C43, C44, C45, and C49 may include signal buffers, clock buffers, inverters, etc. in some embodiments, and in some embodiments, the timing critical path of integrated circuit 40 As shown in FIG.

The second group may have a structure that causes signal routing, such as a relatively large number of input and output pins. For example, standard cells C43, C44, C45, C49 may include AOI22, etc., which in some embodiments have a larger number of input pins relative to the area of the standard cell, and in some embodiments, May not include standard cells that are not included in the timing critical path of the base station 40.

5A and 5B are diagrams illustrating a standard cell C50 according to an exemplary embodiment of the present disclosure. Specifically, FIGS. 5A and 5B show the standard cell C50 as the inverter and the layout around it, and show some layers of the layout, respectively.

The standard cell C50 can be sensitive to the IR drop generated in the power rails PR51 and PR52 as inverters. For example, the output signal of the inverter may be required to have a fast rise / fall time so that the output power of the power rails PR51 and PR52 adjacent to the standard cell C50, as shown in Figures 5A and 5B, The regions can be reinforced with conductive lines formed in the M2 layer. Accordingly, the power rails PR51 and PR52 may include conductive lines respectively formed in the M1 layer, the M2 layer, and the M3 layer and extending in the X-axis direction, and include vias for electrically interconnecting the conductive lines can do.

5A, the standard cell C50 includes an input pin P51 and an output pin P52 formed in the M2 layer to which the input signal A is applied and the output signal Y is output. . 5A, the input pin P51 and the output pin P52 are connected to the conductive line of the M2 layer included in the power rail PR51 by a predetermined distance Y51 due to the semiconductor process or the design rule And can be spaced apart from each other by a constant distance X51. In some embodiments, the distance Y51 in the Y-axis direction may be greater than the distance X51 in the X-axis direction.

Referring to FIG. 5B, a plurality of conductive lines L51 to L55 may be disposed on the M3 layer on the standard cell C50 and extending in parallel with each other in the X-axis direction. At least some of the plurality of conductive lines L51 to L55 may be used to route the input signal A and the output signal Y of the standard cell C50. 5B, the input pin P51 and / or the output pin P52 are connected to at least one of the conductive lines L51 to L55 of the M3 layer by placing the via V2 in at least one of the points indicated by ' And can be electrically connected to one. As the length of the input pin P51 and the output pin P52 in the Y-axis direction is limited due to the conductive line of the M2 layer included in the power rails PR51 and PR52 as described above with reference to Fig. 5A, The points at which the via V2 can be placed in the standard cell C50 can be relatively limited (i.e., while the points marked with " * " in the conductive lines L51 and L55 of the M3 layer are omitted) By reinforcing the rails PR51 and PR52 by the conductive lines of the M2 layer, the standard cell C50 can provide good performance due to the relaxed IR drop.

Figures 6A and 6B are views showing a standard cell (C60) according to an exemplary embodiment of the present disclosure. Specifically, Figs. 6A and 6B show a standard cell C60 with AOI22 and a layout around it, and show some layers of the layout, respectively.

The standard cell C60 may have a relatively large number of input signals A0, A1, B0, B1 as AOI22. Accordingly, the conductive lines formed in the M2 layer in the regions of the power rails PR61 and PR62 adjacent to the standard cell C60 can be omitted, as shown in Figs. 6A and 6B. Accordingly, the power rails PR61 and PR62 may include conductive lines respectively formed in the M1 layer and the M3 layer and extending in the X-axis direction.

Referring to FIG. 6A, the standard cell C60 receives input signals A0, A1, B0 and B1, input pins P61 to P64 formed on the M2 layer and an output signal Y, And formed output pin P65. 6A, the input pins P61 to P64 and the output pin P65 are connected to the boundary of the standard cell C60 due to the omission of the conductive line of the M2 layer in the power rails PR61 and PR62, Axis direction to a position close to the Y-axis direction.

Referring to FIG. 6B, similarly to FIG. 5B, a plurality of conductive lines L61 to L65 may be disposed in the M3 layer on the standard cell C60 and extending in parallel to each other in the X-axis direction. At least some of the plurality of conductive lines L61 to L65 may be used to route the input signals A0, A1, B0, B1 and the output signal Y of the standard cell C60. 6B, the input pins P61 to P64 and / or the output pin P65 are electrically connected to the conductive lines L61 to L65 of the M3 layer by arranging the vias V2 in at least one of the points indicated by ' As shown in FIG. The input pins P61 to P64 and the output pin P65 are connected to the conductive lines of the M3 layer due to the conductive lines of the M2 layer omitted from the power rails PR61 and PR62 as described above with reference to Fig. L61 to L65 extend to the vicinity of the boundary of the standard cell C60 in the Y-axis direction orthogonal to the X-axis direction in which the vias V2 can be extended relatively. Further, the input pins P61 to P64 and the output pin P65 extend in the Y-axis direction across the power rails PR61 and PR62, as described above with reference to Figs. 1, 2A and 2B, The signals A0, A1, B0, B1 and the output signal Y may be routed to the outside of the standard cell C60. Accordingly, routing congestion for the input signals A0, A1, B0, B1 and the output signal Y of the standard cell C60 may not be induced.

7 is a diagram illustrating a portion of an integrated circuit 70 in accordance with an exemplary embodiment of the present disclosure. 7, the integrated circuit 70 may include a plurality of power rails PR71 to PR74 extending parallel to each other in the X-axis direction, and a plurality of power rails PR71 to PR74 And a plurality of standard cells C71 to C79 arranged in a plurality of standard cells. As described above with reference to Figs. 1, 2A, and 2B, each of the power rails PR71 to PR74 in Fig. 7 includes a plurality of power lines PR71 to PR74, which are respectively formed in the M1 layer and the M3 layer and extend parallel to each other in the X- Lt; / RTI > Similar to Fig. 4, for convenience of illustration, Fig. 7 shows only the M2 layer in the power rail.

Referring to FIG. 7, in some embodiments, the power rails PR71 to PR74 extend from a pattern (or a conductive line) of the M2 layer extending in the Y axis direction in the standard cell to M2 Layer < / RTI > 7, the power rail PR71 includes a pattern L71 extending in the Y axis direction from the standard cell C72 and a pattern L71 extending in the X axis direction at a distance X71 from the standard cell C72, And a conductive line L72 of the M2 layer extended to the upper side. Thus, as shown in Fig. 7, the challenge to be formed in the M2 layer of the power rails PR71 to PR74 in the regions excluding the region where the patterns of the M2 layer for routing the signals of the standard cells C71 to C79 are formed The lines can be extended. That is, since the conductive lines formed in the M2 layer of the power rails PR71 to PR74 after the signal routing are extended, the power rails PR71 to PR74 can be strengthened, and the IR drop can be mitigated.

In some embodiments, the conductive lines formed in the M2 layer of the power rails PR71 to PR74 may have a minimum area. For example, as shown in Fig. 7, the power rail PR71 includes the conductive lines L72 and L73 of the M2 layer which are not less than the length X72 in the X axis direction, while the lengths X72 ) ≪ / RTI > may be omitted. That is, the conductive lines formed in the M2 layer of the power rail PR71 between the patterns L71 and L74 of the M2 layer extending in the Y-axis direction can be omitted.

Figures 8A-8C show power rails PR80a, PR80b, PR80c in accordance with the exemplary embodiments of the present disclosure. 8A to 8C, the power rails PR80a, PR80b and PR80c are connected to the conductive layers adjacent to the semiconductor elements (for example, transistors), for example, the conductors formed on the upper wiring layer D1 of the M1- Line. ≪ / RTI > Although the examples in which the upper wiring layer D1 is located on the M1 layer to the M4 layer are shown in the following drawings, the lower wiring layer D1 is formed on the lower conductive layers or more conductive layers, for example, the M1 layer to the M8 layer It will be appreciated that it may be located.

8A, the power rail PR80a may include a conductive line L81a formed in the M1 layer and extending in the X axis direction, a conductive line L85a formed in the D1 layer and extending in the X axis direction, . ≪ / RTI > The conductive lines L81a and L85a may be electrically interconnected through the patterns of the plurality of vias and the conductive layer. As shown in Fig. 8A, the D1 layer as the upper wiring layer may have a thicker thickness (i.e., a length in the Z-axis direction) than the M1 to M4 layers and / or may be made of a material having a high conductivity . Accordingly, the IR drop of the power rail PR80a can be alleviated due to the relatively low resistance value in the X-axis direction of the conductive line L85a. In addition, the power rail PR80a can provide the M2 layer to the M4 layer for signal routing, and the freedom of signal routing can also be improved accordingly.

8B, the power rail PR80b may include conductive lines L81b and L83b respectively formed in the M1 layer and the M2 layer and extending in the X axis direction. The power rail PR80b may be formed in the D1 layer, And an extended conductive line L85b. The conductive lines L81b, L83b, and L85b may be electrically interconnected through the patterns of the plurality of vias and conductive layers. The IR drop of the power rail PR80b can be alleviated due to the conductive line L83b formed in the M3 layer as well as the conductive line L85b having the thick thickness. Further, the power rail PR80b can provide the M2 layer and the M4 layer for signal routing, thereby assuring the freedom of signal routing.

Referring to FIG. 8C, the power rail PR80c may include a conductive line L85c formed in the D1 layer and extending in the X-axis direction. The conductive line L85c can supply power to lower semiconductor elements through patterns of a plurality of vias and conductive layers. The IR drop can be mitigated due to the conductive line L85b having a thick thickness while the power rail PR80c can provide the M1 layer to the M4 layer for signal routing so that the degree of freedom in signal routing can be improved .

Figures 9A-9C are illustrations of examples of structures for electrically interconnecting conductive lines of different layers according to an exemplary embodiment of the present disclosure. As shown in FIGS. 9A-9C, a plurality of vias disposed in parallel in the same layer may be used to reduce the resistance between the conductive lines of different layers, and this structure is referred to herein as a via pillar ). ≪ / RTI > For example, the exemplary structures depicted in FIGS. 9A-9C may provide paths through which input signals, output signals, and / or internal signals travel in a standard cell, and may include conductive lines of power rails extending in different layers Lt; / RTI > Hereinafter, the repetition of the description of Figs. 9A to 9C will be omitted.

Referring to FIG. 9A, the via filler VP90 may include conductive lines L91 and L95 formed in the M1 layer and the M5 layer, respectively, and extending in the X-axis direction. Two vias V16 and V17 may be arranged on the conductive line L91 of the M1 layer and two vias V16 and V17 may be arranged to electrically interconnect the conductive lines L91 and L95, Two conductive lines L92a and L92b which are formed on the M2 layer and extend in parallel to each other in the Y axis direction can be disposed. Four vias V26 to V29 can be disposed on the two conductive lines L92a and L92b and are formed in the M3 layer on the four vias V36 to V39 and are parallel to each other in the X- Two extending conductive lines L93a and L93b may be disposed. Four vias V36 to V39 may be disposed on the two conductive lines L93a and L93b and may be formed in the M4 layer on the four vias V36 to V39 and parallel to each other in the Y axis direction Two extending conductive lines L94a and L94b may be disposed. Two vias V46 and V47 may be disposed on the two conductive lines L94a and L94b and a conductive line L95 formed on the M5 layer may be disposed on the two vias V46 and V47 . By arranging the plurality of vias in the same layer in this way, the resistance value between the conductive line L91 of the M1 layer and the conductive line L95 of the M5 layer can be reduced, and the electric power is supplied through the conductive line L91 of the M1 layer The receiving semiconductor device may experience a relaxed IR drop.

9A, similar to the via filler VP90 of FIG. 9A, the via filler VP90 'includes conductive lines L91' and L95 'formed respectively in the M1 layer and the M5 layer and extending in the X- . ≪ / RTI > Different from the conductive line L91 'formed in the M1 layer connected via the contacts and / or vias (e.g., V0) to the semiconductor devices included in the standard cell and including patterns for signal routing, (L95 ') may have a relatively wide width, i.e., a length in the Y-axis direction. Thus, as shown in Fig. 9B, four vias V46 'to V49' may be arranged on the patterns L94a 'and L94b' of the M4 layer.

9A and 9B, similar to the via fillers VP90 and VP90 'of FIGS. 9A and 9B, the via filler VP90 "is formed of conductive lines formed in the M1 layer and the D1 layer, respectively, (L91 ", L95 "). The conductive lines formed in each of the M2 layer to the M4 layer in the via fillers VP90 and VP90 'of Figs. 9A and 9B, Conductive lines formed in each of the M2 layer to the M4 layer in the via filler VP90 "may be merged into one pattern L92, L93, and L94.

Although the via fillers VP90, VP90 ', VP90 "in Figs. 9A to 9C are shown as including conductive lines formed in the M1 layer and the M5 layer respectively and extending in parallel to each other in the X axis direction, It is to be understood that the structures shown in Figs. 9A to 9C can also be applied to a conductive line formed in the M3 layer and extending along the conductive lines of the M1 layer and the M5 layer in the X-axis direction. The via fillers (VP90, VP90 ', VP90 ") shown in FIG. 9C are only examples, and different examples, such as a structure in which more than four vias are arranged in the same layer, ) ≪ / RTI > type of vias may be disposed on the same layer, or the like.

10A and 10B are views showing power rails PR100a and PR100b according to an exemplary embodiment of the present disclosure. 10A and 10B, the power rails PR100a and PR100b include conductive lines L110, L111, L150 and L151 respectively formed in the M1 layer and the D1 layer and extending in the X axis direction And may include a plurality of vias for electrically interconnecting the conductive lines L110, L111 of the M1 layer and the conductive lines L150, L151 of the D1 layer.

Referring to FIG. 10A, the power rail L150 includes conductive lines L1 to L4 of M2 to M4 layers connected to a plurality of vias for electrically interconnecting the conductive lines L110 and L150 extending in the X- , L130, L140). 10A, the conductive lines L120, L130, and L140 may extend in the X-axis direction to enhance the electrical connection between the conductive lines L110 and L150 of the M1 layer and the D1 layer.

Referring to FIG. 10B, the power rail L150 may include vias spaced in the Y-axis direction in the same layer for electrically interconnecting the conductive lines L111 and L151 extending in the X-axis direction, And M2 through M4 layers connected to the vias and extending in the Y axis direction. For example, as shown in FIG. 10B, the conductive lines L121, L122 and L123 of the M2 layer may extend in the Y-axis direction and may be arranged on the conductive lines L121 to L123 in the Y- A plurality of spaced vias may be disposed. The conductive lines L131 and L132 of the M3 layer may extend in the X axis direction while the conductive lines L141, L142 and L143 of the M4 layer are electrically connected to the conductive lines L121, L122 and L123 of the M2 layer Axis direction as shown in Fig.

The power rail PR100b of FIG. 10B has a structure extended in the Y axis direction to electrically connect the conductive lines L111 and L151 of the M1 layer and the D1 layer, as compared with the power rail PR100a of FIG. 10A While providing space for signal routing. That is, the regions R11a to R14a shown in FIG. 10A may be limited to be used for the pattern for routing signals due to the conductive lines L120 and L140 formed in the M2 layer and the M4 layer, The regions R11b to R14b shown in Figs. 10A and 10B can be used for a pattern for routing signals due to the conductive lines L121 to L123, L141 to L143 extending in the Y-axis direction of the M2 layer and the M4 layer . For example, in the case where the conductive lines L121, L122 and L123 extending in the Y-axis direction in the M2 layer are arranged at equal intervals or more in FIG. 10B, the regions R11b and R12b are connected to the M2 layer Axis direction and extend in the Y-axis direction.

The power rails PR100a and PR100b shown in Figs. 10A and 10B are only examples. For example, the power rails PR100a and PR100b in Figs. 10A and 10B include three vias spaced apart from each other in the X-axis direction in the same layer or three pairs of vias spaced from each other in the Y-axis direction, It will be appreciated that the power rails in accordance with the exemplary embodiments of the disclosure may include fewer or greater numbers of vias and / or conductive lines than those shown in Figs. 10A and 10B.

11 is a flow diagram illustrating a method of fabricating an integrated circuit including a plurality of standard cells in accordance with an exemplary embodiment of the present disclosure;

The standard cell library D50 may include information on a plurality of standard cells, for example, function information, characteristic information, layout information, and the like. As shown in FIG. 7, the first group information D51 and the second group information D51 Information D52. The first group information D51 may include information on standard cells having a boundary overlapped with a conductive line formed in the M2 layer in adjacent power rails, as described above with reference to Figs. 5A and 5B, The second group information D52 includes information on standard cells that are not forced to have a boundary overlapped with a conductive line formed in the M2 layer in adjacent power rails, as described above with reference to Figs. 6A and 6B .

Referring to FIG. 11, in step S100, a logic synthesis operation for generating netlist data D20 from RTL data D10 may be performed. For example, a semiconductor design tool (e.g., a logic synthesis tool) refers to a standard cell library D50 from RTL data D10 written as HDL (Hardware Description Language) such as VHDL (VHSIC Hardware Description Language) It is possible to generate netlist data D20 including a bitstream or a netlist. As described above, information about standard cells (i.e., D52) providing information about standard cells (i.e., D51) and enhanced routing freedom is reduced by standard cell library D50 by strengthening adjacent power rails, And standard cells can be included in the integrated circuit by referring to such information in the logic synthesis process.

In step S200, placement and routing (P & R) operations for generating the layout data D30 from the netlist data D20 may be performed. As shown in FIG. 11, the placement and routing step S200 may include a plurality of steps S210, S220, S230.

In step S210, an operation of placing standard cells can be performed. For example, a semiconductor design tool (e.g., a P & R tool) may reference a standard cell library D50 from netlist data D20 to locate a plurality of standard cells. As described above, standard cells can have predetermined heights, so that a semiconductor design tool can place standard cells on a grid that intersects with a predetermined length. The power rails may extend in one direction overlapping the grid, and may be arranged at regular intervals.

In step S220, operations to create interconnections may be performed. The interconnections may electrically connect the output pins and input pins of the standard cell and may include, for example, at least one via and at least one conductive pattern. By creating interconnections, standard cells can be routed and the M2 layer can be used to route in some areas of the power rails. Further, as described above with reference to Fig. 7, after the routing of the signal is completed, the conductive lines of the M2 layer included in the power rail are extended, so that the IR drop in the power rail can be further mitigated.

In step S230, an operation of generating the layout data D30 may be performed. The layout data D30 may have a format such as GDSII, for example, and may include geometric information of standard cells and interconnections.

In step S300, an operation of manufacturing a mask may be performed. For example, patterns formed in a plurality of layers may be defined according to the layout data D30, and at least one mask (or photomask) for forming patterns of each of the plurality of layers may be fabricated.

In step S400, an operation of fabricating the integrated circuit may be performed. For example, an integrated circuit can be fabricated by patterning a plurality of layers using at least one mask fabricated in step S300. As shown in FIG. 11, step S400 may include steps S410 and S420.

In step S410, a front-end-of-line (FEOL) process may be performed. FEOL can refer to a process of forming individual elements such as transistors, capacitors, resistors, and the like on a substrate in an integrated circuit manufacturing process. For example, the FEOL may include planarizing and cleaning the wafer, forming a trench, forming a well, forming a gate line, forming a source and a drain, Forming a drain, and the like.

In step S420, a back-end-of-line (BEOL) process may be performed. BEOL can refer to the process of interconnecting discrete components, such as transistors, capacitors, resistors, etc., in an integrated circuit fabrication process. For example, the BEOL can be formed by silicidating the gate, source and drain regions, adding a dielectric, planarizing, forming holes, adding metal layers, forming vias, passivation layer may be formed. The integrated circuit may then be packaged in a semiconductor package and used as a component in various applications. By the BEOL process (S420), power rails and patterns for routing signals according to the exemplary embodiment of the present disclosure can be formed.

12 is a block diagram illustrating a system-on-chip (SoC) 120 in accordance with an exemplary embodiment of the present disclosure. The SoC 120 may be a semiconductor device, including an integrated circuit according to the exemplary embodiment of the present disclosure. The SoC 120 implements complex functional blocks, such as intellectual property (IP), that perform various functions on a single chip, and standard cells and power rails in accordance with the exemplary embodiment Functional blocks, so that the SoC 120 with improved performance due to the relaxed IR drop and efficiently routed patterns can be achieved.

12, the SoC 120 includes a modem 122, a display controller 123, a memory 124, an external memory controller 125, a central processing unit (CPU) 126, a transaction unit 127, A PMIC 128 and a graphics processing unit (GPU) 129, and each functional block of the SoC 120 can communicate with one another via the system bus 121. [

The CPU 126 which can control the operation of the SoC 120 can control the operation of the other functional blocks 122, 123, 124, 125, 127, 128, The modem 122 may demodulate a signal received from the outside of the SoC 120 or may modulate a signal generated in the SoC 120 and transmit the modulated signal to the outside. The external memory controller 125 may control the operation of sending and receiving data from the external memory device connected to the SoC 120. [ For example, programs and / or data stored in the external memory device may be provided to the CPU 126 or the GPU 129 under the control of the external memory controller 125. GPU 129 may execute program instructions related to graphics processing. The GPU 129 may receive graphic data through the external memory controller 125 and may transmit graphics data processed by the GPU 129 to the outside of the SoC 120 through the external memory controller 125. The transaction unit 127 may monitor the data transaction of each functional block and the PMIC 128 may control the power supplied to each functional block under the control of the transaction unit 127. [ The display controller 123 can transmit data generated inside the SoC 120 to the display by controlling a display (or a display device) outside the SoC 120. [

The memory 124 may be a nonvolatile memory such as a non-volatile memory such as an electrically erasable programmable read-only memory (EEPROM), a flash memory, a PRAM (Phase Change Random Access Memory), a RRAM ), Nano Floating Gate Memory (NFGM), Polymer Random Access Memory (PoRAM), Magnetic Random Access Memory (MRAM), and Ferroelectric Random Access Memory (FRAM) , A static random access memory (SRAM), a mobile DRAM, a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power DDR SDRAM, a graphic DDR SDRAM, and a Rambus Dynamic Random Access Memory (RDRAM) .

FIG. 13 is a block diagram illustrating a computing system 130 that includes a memory for storing a program in accordance with an exemplary embodiment of the present disclosure. At least some of the steps involved in a method of manufacturing an integrated circuit (e.g., the method illustrated in FIG. 11) according to an exemplary embodiment of the present disclosure may be performed in the computing system 130.

Computing system 130 may be a fixed computing system, such as a desktop computer, a workstation, a server, or the like, or a portable computing system, such as a laptop computer. 13, the computing system 130 includes a processor 131, input / output devices 132, a network interface 133, a random access memory (RAM) 134, a read only memory (ROM) 135 And a storage device 136. The processor 131, the input / output devices 132, the network interface 133, the RAM 134, the ROM 135 and the storage 136 may be connected to the bus 137, Communication can be performed.

The processor 131 may be referred to as a processing unit and may include any instruction set such as a microprocessor, an application processor (DSP), a digital signal processor (DSP), a graphics processing unit (GPU) IA-32 (Intel Architecture-32), 64-bit extensions IA-32, x86-64, PowerPC, Sparc, MIPS, ARM, IA-64, etc.). For example, processor 131 may access memory, i. E. RAM 134 or ROM 135, via bus 137 and execute instructions stored in RAM 134 or ROM 135. [

The RAM 134 may store a program 200 or at least a portion thereof for manufacturing an integrated circuit according to an exemplary embodiment of the present disclosure and the program 200 may cause the processor 131 to generate an integrated circuit To perform at least some of the steps included in the method. In other words, the program 200 may include a plurality of instructions executable by the processor 131, and the plurality of instructions contained in the program 200 may cause the processor 131 to perform, for example, Synthesis operation and / or place and route (P & R) operation of step S200.

The storage device 136 may not lose stored data even if power supplied to the computing system 130 is interrupted. For example, the storage device 136 may comprise a non-volatile memory device and may include a storage medium such as a magnetic tape, optical disk, or magnetic disk. In addition, the storage device 136 may be removable from the computing system 130. The storage device 136 may store the program 200 in accordance with the illustrative embodiment of the present disclosure and may store the program 200 from the storage device 136 prior to being executed by the processor 131 At least a portion of it may be loaded into the RAM 134. Alternatively, the storage device 136 may store a file written in a programming language, and a program 200 or at least a portion thereof generated by a compiler or the like from a file may be loaded into the RAM 134. [ 13, the storage device 136 may store the database 251 and the database 251 may include information necessary to design the integrated circuit, such as the standard cell library D50 of FIG. 7 can do.

The storage device 136 may store data to be processed by the processor 131 or data processed by the processor 131. [ That is, the processor 131 may generate data by processing the data stored in the storage device 136 according to the program 200, and may store the generated data in the storage device 136. [ For example, the storage device 136 may store RTL data D10, netlist data D20, and / or layout data D30.

The input / output devices 132 may include input devices such as a keyboard, pointing device, and the like, and may include output devices such as a display device, a printer, and the like. For example, the user may trigger the execution of the program 200 by the processor 131 via the input / output devices 132, or may execute the RTL data D10 and / or the netlist data D20 of FIG. And the layout data D30 in Fig. 11 can be confirmed.

The network interface 133 may provide access to a network external to the computing system 130. For example, a network may include multiple computing systems and communication links, and the communication links may include wired links, optical links, wireless links, or any other type of links.

As described above, exemplary embodiments have been disclosed in the drawings and specification. Although the embodiments have been described herein with reference to specific terms, it should be understood that they have been used only for the purpose of describing the technical idea of the present disclosure and not for limiting the scope of the present disclosure as defined in the claims . Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. Accordingly, the true scope of protection of the present disclosure should be determined by the technical idea of the appended claims.

Claims (20)

An integrated circuit comprising a plurality of standard cells,
A power rail including first and second electrically conductive lines extending in a first horizontal direction and spaced apart from each other in a vertical direction on the boundary of the plurality of standard cells to supply power to the plurality of standard cells, ; And
And at least one third conductive line extending between the first and second conductive lines and extending in a second horizontal direction orthogonal to the first horizontal direction for conveying an input signal or an output signal of a standard cell integrated circuit. The method according to claim 1,
The power rail further includes at least one fourth conductive line electrically connected to the first and second conductive lines and extending in the first horizontal direction and formed in the same conductive layer as the at least one third conductive line . The method of claim 2,
The power rail includes:
At least one first via electrically connecting the first conductive line and the at least one fourth conductive line; And
Further comprising at least one second via electrically connecting said second conductive line and said at least one fourth conductive line. The method of claim 3,
Wherein at least one of the at least one first via and the at least one second via has a bar shape extending in the first horizontal direction. The method of claim 2,
Wherein the at least one fourth conductive line extends in the first horizontal direction from the plurality of third conductive lines to a point spaced a predetermined distance from the plurality of third conductive lines. . The method of claim 5,
Wherein the at least one fourth conductive line has a length in the first horizontal direction that is longer than a predetermined length. The method of claim 2,
Wherein the width of the fourth conductive line is equal to or greater than the width of the at least one third conductive line. The method of claim 2,
Wherein the at least one fourth conductive line completely overlaps the first horizontal boundaries of first standard cells having the same FEOL structure among the plurality of standard cells. The method of claim 8,
Wherein the first standard cells have a propagation delay shorter than other standard cells providing the same functionality. The method according to claim 1,
First and second signal lines formed to be spaced apart from each other in the vertical direction in different conductive layers;
Fourth and fifth conductive lines extending between the first and second signal lines in the second or first horizontal direction so as to be spaced apart from each other in the first or second horizontal direction;
At least one first upper via disposed on the fourth conductive line; And
Further comprising at least one second upper via disposed on the fifth conductive line,
Wherein the first and second signal lines are electrically connected through the fourth and fifth conductive lines, the at least one first upper via, and the at least one second upper via. The method according to claim 1,
First and second signal lines formed to be spaced apart from each other in the vertical direction in different conductive layers;
Fourth and fifth conductive lines extending in the first horizontal direction and spaced apart from each other in the second horizontal direction between the first and second signal lines;
At least one first sub-via disposed under the fourth conductive line; And
Further comprising at least one second lower via disposed under the fifth conductive line,
Wherein the first and second conductive lines are electrically connected through the fourth and fifth conductive lines, the at least one first sub-via, and the at least one second sub-via. The method according to claim 1,
Wherein the power rail comprises at least two fourth conductive lines electrically connected to the first and second conductive lines and extending in the second horizontal direction and formed in the same conductive layer as the at least one third conductive line Including,
Wherein the at least one third conductive line comprises a conductive material disposed between the at least two fourth conductive lines. The method according to claim 1,
Wherein each of the plurality of standard cells comprises:
At least one active region extending in the first horizontal direction; And
And at least one gate line extending in the second horizontal direction. The method according to claim 1,
Wherein the first and second conductive lines are applied with a positive supply voltage or a negative supply voltage of the integrated circuit. First and second standard cells arranged in a first horizontal direction and having the same length in a second horizontal direction orthogonal to the first horizontal direction;
The first and second standard cells being electrically connected to each other in a first horizontal direction and spaced apart from each other in a vertical direction on a boundary of the first and second standard cells in order to supply power to the first and second standard cells, A power rail including a conductive line; And
At least one third conductive line extending between the first and second standard cells and extending in the second horizontal direction to transmit an input signal or an output signal of the first standard cell, Including,
The power rail includes a fourth conductive line extending in the first horizontal direction on the boundary of the second standard cell and electrically connected to the first and second conductive lines and formed in the same conductive layer as the third conductive line ≪ / RTI > In claim 15,
Wherein the fourth conductive line extends in the first horizontal direction at a boundary of the first standard cell from a point spaced a predetermined distance from the at least one third conductive line. In claim 15,
The power rail includes:
At least one first via electrically connecting the first and fourth conductive lines; And
And at least one second via for electrically connecting said second and fourth conductive lines. An integrated circuit comprising a plurality of standard cells,
A power rail formed using a plurality of conductive layers on a boundary of the plurality of standard cells and extending in a first horizontal direction to supply power to the plurality of standard cells; And
At least one signal line passing through the power rail in a second horizontal direction orthogonal to the first horizontal direction and formed in one of the plurality of conductive layers, for transmitting an input signal or an output signal of a standard cell, / RTI >
Wherein the power rail comprises a first horizontal extending conductive line formed in the conductive layer on which the at least one signal line is formed and insulated from the at least one signal line. 19. The method of claim 18,
Wherein the power rail further comprises first and second conductive lines each formed in two different ones of the plurality of conductive layers and extending parallel to each other in the first horizontal direction,
Wherein the at least one signal line is formed in the conductive layer between the two conductive layers. 19. The method of claim 18,
The power rail includes:
A plurality of conductive lines formed in the plurality of conductive layers and extending parallel to each other in the first horizontal direction; And
Further comprising vias electrically connecting the plurality of conductive lines,
Wherein at least one of the vias has a bar shape extending in the first horizontal direction.

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