TW201842599A - Integrated circuit - Google Patents

Abstract

An integrated circuit including: a power rail including first and second conductive lines spaced apart from each other in a vertical direction, wherein the first and second conductive lines extend in parallel to each other in a first horizontal direction, and are electrically connected to each other, to supply power to a first standard cell, wherein the first and second conductive lines are disposed at a boundary of the first standard cell; and a third conductive line between the first and second conductive lines and extending in a second horizontal direction orthogonal to the first horizontal direction, to transfer an input signal or an output signal of the first standard cell.

Description

Integrated circuit

SUMMARY OF THE INVENTION The present invention relates to an integrated circuit, and more particularly to an integrated circuit including a standard cell and a method of fabricating the integrated circuit.

As the semiconductor process is miniaturized, the patterns included in the integrated circuit may have a reduced width and/or thickness. Such reduced width and/or thickness may increase the likelihood of a voltage drop (or IR drop) on the pattern. The resistance drop can cause the signal to decay as it passes through the pattern. Therefore, the transition of the signal may be delayed, and the performance of the integrated circuit may deteriorate.

According to an exemplary embodiment of the inventive concept, an integrated circuit is provided, the integrated circuit including: a power rail including a first conductive line and a second conductive line spaced apart from each other in a vertical direction, wherein the a conductive line and the second conductive line extend parallel to each other in a first horizontal direction and are electrically connected to each other to supply power to the first standard cell, wherein the first conductive line and the second conductive line Provided at a boundary of the first standard cell; and a third conductive line between the first conductive line and the second conductive line and at a second level orthogonal to the first horizontal direction Extending in direction to transmit an input signal or an output signal of the first standard cell.

According to an exemplary embodiment of the inventive concept, an integrated circuit is provided, the integrated circuit including: a first standard cell and a second standard cell arranged in a first horizontal direction; and a power rail, including in a vertical a first conductive line and a second conductive line spaced apart from each other in a direction, wherein the first conductive line and the second conductive line extend in parallel in the first horizontal direction and are electrically connected to each other to The first standard cell and the second standard cell supply power, wherein the first conductive line and the second conductive line are disposed in the first standard cell and the second standard cell a boundary of each of; and a third conductive line extending between the first conductive line and the second conductive line and extending in a second horizontal direction orthogonal to the first horizontal direction for transmission An input signal or an output signal of the first standard cell, wherein the power rail further includes a fourth conductive line extending in the first horizontal direction on the boundary of the second standard cell, Wherein the fourth conductive line is electrically connected to the A first conductive line and the second conductive line and the third conductive line is formed in the same layer.

According to an exemplary embodiment of the inventive concept, an integrated circuit is provided, the integrated circuit including: a power rail including a plurality of conductive lines on a boundary of a plurality of standard cells, wherein the conductive lines are a plurality of conductive layers are formed and extend parallel to each other in a first horizontal direction to supply power to the plurality of standard cells; and a signal line in a second horizontal direction orthogonal to the first horizontal direction Passing through the power rail, wherein the signal line is formed in one of the plurality of conductive layers to transmit an input signal or an output signal of at least one of the plurality of standard cells, wherein The power rail includes a first conductive line formed in the conductive layer in which the signal line is formed, wherein the first conductive line extends in the first horizontal direction and Insulated from the signal line.

FIG. 1 is a diagram of a portion of an integrated circuit 10 in accordance with an exemplary embodiment of the inventive concept. 2A and 2B are cross-sectional views of the integrated circuit 10 cut along the line X1-X1' shown in FIG. 1 in parallel with the Z-axis direction, according to an exemplary embodiment of the inventive concept. For convenience of explanation, FIGS. 1, 2A, and 2B show only some of the layers included in the integrated circuit 10. For example, Figures 1, 2A, and 2B illustrate some of the layers formed by a back end of line (BEOL) process. Hereinafter, a plane formed by the X-axis and the Y-axis may be referred to as a horizontal plane; an element placed in the Z-direction may be regarded as below or above other elements such as in the Z direction.

Referring to Figures 1, 2A, and 2B, integrated circuit 10 can include standard cells C11 and C12 as indicated by dashed lines. The standard cell is a unit of the layout included in the integrated circuit 10. The integrated circuit 10 can include a plurality of various standard cells. The standard cell may have a structure conforming to a predetermined specification. For example, as shown in FIG. 1, the standard cells C11 and C12 may have a specific height (in other words, a length Y10 in the Y-axis direction), and may have a boundary overlapping with a pair of power rails PR11 and PR12. The pair of power supply rails PR11 and PR12 are spaced apart from each other in the Y-axis direction and extend in parallel in the X-axis direction. Although the standard cells C11 and C12 include patterns of the M1 layer to the M3 layer, the standard cells C11 and C12 may include a pattern of only the M1 layer or a pattern of only the M1 layer and the M2 layer. For example, the structure of the standard cells C11 and C12 defined by the standard cell library can be defined from the substrate to the M1 layer or the M2 layer, and the standard cells can be placed in the design process of the standard cells C11 and C12. After C11 and C12, some patterns of the M2 layer and the pattern of the M3 layer are determined in the routing operation.

Standard cells C11 and C12 may include a pattern along which the signal is moved. For example, the first standard cell C11 may include a pattern in which the internal signal generated in the first standard cell C11 is moved, and may include the input signal and the output signal of the first standard cell C11 being respectively included therein. Moving patterns (for example, input pins and output pins). In the integrated circuit 10 shown in FIG. 1, the input pin and the output pin of the first standard cell C11 may be a pattern formed on the M2 layer. The input pin and the output pin of the first standard cell C11 are electrically connected to the outside of the first standard cell C11. For example, the input pin of the first standard cell C11 can be electrically connected to the output pin of another standard cell, and the output pin of the first standard cell C11 can be electrically connected to another standard cell. Input pin. To electrically connect the input pins and/or output pins of the first standard cell C11 to the outside of the first standard cell C11, a pattern passing through the boundary of the first standard cell C11 may be used. For example, as shown in FIG. 1, the pattern of the M3 layer connected to the input pin and/or the output pin of the first standard cell C11 formed on the M2 layer via the via hole can be worn in the X-axis direction. Passes the boundary of the first standard cell C11. In addition, as shown in FIG. 1, the input pins and/or output pins of the first standard cell C11 formed on the M2 layer may be extended such that the pattern of the M2 layer can pass the first standard in the Y-axis direction. Cell C11. As will be explained later, the operation of connecting the input and output pins of the standard cells C11 and C12 (for example, the task of generating a pattern or signal routing) may be subject to a power rail PR11 having a structure for mitigating the resistance potential drop and The impact of PR12.

The power rails PR11 and PR12 for supplying power to the standard cells C11 and C12 may be arranged in the integrated circuit 10 at intervals equal to the height Y10 of the standard cells C11 and C12, and may be in the same manner as the standard cells C11 and C12. The height Y10 extends in the vertical direction (in other words, in the X-axis direction). In an exemplary embodiment of the inventive concept, the first power rail PR11 may be applied with a positive supply voltage (eg, VDD) and the second power rail PR12 may be applied with a negative supply voltage (eg, VSS). In an alternative embodiment, the first power rail PR11 may be applied with a negative supply voltage (eg, VSS) and the second power rail PR12 may be applied with a positive supply voltage (eg, VDD). In the following description, the first power supply rail PR11 is applied with the positive supply voltage VDD and the second power supply rail PR12 is applied with the negative supply voltage VSS, but the inventive concept is not limited thereto. Elements (eg, transistors) formed in standard cells C11 and C12 may receive current from the first power rail PR11 and introduce current into the second power rail PR12.

As the semiconductor process is miniaturized, the width and/or thickness of the pattern included in the integrated circuit (for example, the length in the Z direction) may be reduced, and the size of the standard cell may also be reduced. Therefore, the voltage drop (or resistance potential drop) effect on the pattern may increase. For example, a potential drop occurring in a power rail connected to such a standard cell may cause a delay in signal transition and thus degrade the performance of the integrated circuit. In a method of mitigating the resistance potential drop, the power rails PR11 and PR12 may have a redundant pattern. For example, as shown in FIG. 1, the first power rails PR11 include conductive lines L11 and L31 extending in parallel with each other in the X-axis direction, and through holes for electrically connecting the conductive lines L11 and L31 to each other. . The second power rails PR12 may also include conductive lines L12 and L32 extending in parallel with each other in the X-axis direction, and through holes for electrically connecting the conductive lines L12 and L32 to each other. As shown in FIG. 1, conductive lines L11 and L12 may be formed in the M1 layer, and conductive lines L31 and L32 may be formed in the M3 layer.

As shown in FIG. 1, the power rails PR11 and PR12 may partially include a pattern of the M2 layer extending in the X-axis direction (in other words, the conductive lines L21 and L22). Therefore, in the section in which the conductive lines L21 and L22 of the M2 layer are formed in the power supply rails PR11 and PR12, the resistance potential drop can be further alleviated. In addition, a space in which the pattern of the M2 layer is not formed in the power rails PR11 and PR12 can be used for signal routing. For example, as shown in FIG. 1, the input pins and/or output pins of the first standard cell C11 may extend in the Y-axis direction such that the first power rails PR11 and/or the The conductive lines L23, L24, and L25 of the two power rails PR12. In an exemplary embodiment of the inventive concept, the widths (for example, the length in the Y-axis direction) of the conductive lines L21 and L22 of the M2 layer included in the power rails PR11 and PR12 may be equal to or greater than the conductivity for signal routing. The width of the lines L23, L24, and L25 (for example, the length in the X-axis direction). Therefore, the integrated circuit 10 can not only reduce the resistance potential drop, but also obtain a degree of freedom commensurate with the signal routing. The structure of the power rails PR11 and PR12 will be explained in detail later with reference to FIGS. 2A and 2B which are cross-sectional views of the second power rail PR12. It should be understood that the first power rail PR11 may also have the same or similar structure as that of the second power rail PR12.

Referring to FIG. 2A, in the region R22, the second power rails PR12 may include conductive lines L12 and L32 extending in parallel with each other in the X-axis direction and formed in the M1 layer and the M3 layer, respectively, and formed in the M2 layer and A conductive line L22 extending in the X-axis direction. The second power rail PR12 may also include a plurality of through holes V11, V12, V13, V21, V22, and V23 for electrically interconnecting the conductive lines L12, L22, and L32 in the region R22. The region 21 in which the pattern of the M2 layer is not formed in the second power rail PR12 may be a space for the conductive lines L23, L24, and L25. In other words, the input signal and/or output signal of the first standard cell C11 can be moved via the conductive lines L23, L24, and L25 in the region R21. The conductive lines L23, L24, and L25 may pass through the second power rails PR12 in the Y-axis direction. Therefore, the region R21 of the second power rail PR12 can be used for signal routing, and the region R22 of the second power rail PR12 can be used to mitigate the resistance potential drop. For example, as described below with reference to FIG. 4, the region R21 of the second power rail PR12 can be used for a standard cell (eg, C11) having a relatively large number of input and output pins, and the second power rail The region R22 of PR12 can be used for a standard cell (e.g., C12) in which the electrical characteristics of the output signal are important.

Referring to FIG. 2B, in an exemplary embodiment of the inventive concept, the through holes included in the region R22 of the second power rail PR12 may be rod-shaped. For example, as shown in FIG. 2B, the via holes V11', V12', V13', V21', V22', and V23' for electrically interconnecting the conductive lines L12, L22, and L32 may be A rod shape extending in the X-axis direction and may be referred to as a bar type vias. In other words, the length X20b of the through holes V11' and V21' in the X-axis direction in FIG. 2B may be greater than the length X20a of the through holes V11 and V21 in the X-axis direction in FIG. 2A. Due to the rod shape of the via holes V11' and V21', the resistance value between the conductive lines L12, L22, and L32 shown in FIG. 2B can be reduced and the resistance potential drop can be further alleviated. Although FIG. 2B shows an example in which the through holes V11', V12', V13', V21', V22', and V23' of the second power supply rail PR12 are rod-shaped, it should be understood that the through holes are Only one or no more than the owner may be rod shaped. Further, the through hole included in the second power rail PR12 may have any shape, for example, the through hole may have an oval cross section on the XY axis plane such that the plug filling the through hole ( The size of the plug can be increased to reduce the resistance of the via.

3A to 3C are diagrams of power supply rails PR30a, PR30b, and PR30c according to a comparative example. As described above with reference to FIGS. 1 , 2A, and 2B , the power rail according to an exemplary embodiment of the inventive concept may include conductive lines formed in the M1 layer and the M3 layer, and may partially include the formation in the M2 Conductive lines in the layer.

Referring to FIG. 3A, the power rails PR30a according to the comparative example may include conductive lines L01a and L02a respectively formed in the M1 layer and the M2 layer and extending in parallel with each other in the X-axis direction. The power rail PR30a also includes through holes for electrically interconnecting the conductive lines L01a and L02a to each other. Since the conductive line L02a is present, it may be necessary to electrically connect an input pin and/or an output pin formed in the M2 layer of the standard cell adjacent to the power rail PR30a to the outside of the standard cell. An M3 layer or another upper conductive layer is used. Therefore, signal routing congestion may occur. In some cases, since the semiconductor process for fabricating the integrated circuit is performed, the pattern formed on the M2 layer in the standard cell can be formed only in a direction parallel to the gate line (for example, the Y axis in FIG. 1) Direction). This limitation may exacerbate signal routing congestion. Further, in some cases, since the semiconductor process is performed, the pattern formed on the M2 layer may have a smaller width (for example, a length in the Y-axis direction) and/or a thickness than a pattern formed on the M3 layer. (for example, the length in the Z-axis direction). Therefore, the power supply rails PR30a including the conductive lines L01a of the M1 layer and the conductive lines L02a of the M2 layer may not alleviate the resistance potential drop.

Referring to FIG. 3B, the power rail PR30b according to the comparative example may include a conductive line L01b formed in the M1 layer and extending in the X-axis direction. The conductive line formed in the M2 layer may extend across the power rail PR30b in the Y-axis direction, and the M2 layer is a layer in which the signal of the standard cell is moved. Therefore, in the comparative example shown in FIG. 3B, the degree of freedom of signal routing can be ensured; however, since power is supplied to the standard cell via the single conductive line L01b, the influence of the potential drop generated in the power rail PR30b may be Increase.

Referring to FIG. 3C, the power rails PR30c according to the comparative example may include conductive lines L01c, L02c, and L03c which are respectively formed in the M1 layer, the M2 layer, and the M3 layer and extend in parallel with each other in the X-axis direction. The power rail PR30c may further include a through hole for electrically interconnecting the conductive lines L01c, L02c, and L03c to each other. Compared with the resistance potential drops of the power rails PR30a and PR30b shown in FIGS. 3A and 3B, the resistance potential drop of the power rail PR30c shown in FIG. 3C can be alleviated. However, this is limited to signal routing using both the M2 layer and the M3 layer. Therefore, signal routing congestion may increase.

As described above with reference to FIGS. 1 , 2A, and 2B , the power rail according to an exemplary embodiment of the inventive concept may include conductive lines formed in the M1 layer and the M3 layer, and may partially include the formation in the M2 Conductive lines in the layer. As will be described below with reference to the figures, the power rails can remove the conductive lines from the M2 layer in the zone adjacent to the standard cell in which the signal routing is to be used. Additionally, the power rails can include conductive lines in the M2 layer in a region adjacent to a standard cell in which the resistance potential drop is to be mitigated. Therefore, while ensuring the freedom of signal routing, the potential drop in the power rail can be reduced.

FIG. 4 is a diagram of a portion of an integrated circuit 40, in accordance with an exemplary embodiment of the inventive concept.

Referring to FIG. 4, the integrated circuit 40 may include a plurality of power supply rails PR41 to PR44 extending in parallel with each other in the X-axis direction, and a plurality of standard cells disposed between the plurality of power supply rails PR41 to PR44. C41 to C49. Each of the plurality of standard cells C41 to C49 may include at least one active region extending in the X-axis direction and at least one gate line extending in the Y-axis direction. For example, as shown in FIG. 4, the standard cell C41 may include active regions AC1 and AC2 extending in the X-axis direction and may include a plurality of gate lines including the Y-axis direction The upper extended gate line GL1. In an exemplary embodiment of the inventive concept, the active regions AC1 and AC2 may include a semiconductor such as Si or Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs, or InP, and may include a conductive region such as doping. A well with impurities and a structure doped with impurities. The gate line may include a work function metal layer and a gap fill metal film. For example, the work function metal layer may include at least one of Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd, and the gap fill metal film It may be a W film or an Al film. In an exemplary embodiment of the inventive concept, the gate line may include a TiAlC/TiN/W stacked structure, a TiN/TaN/TiAlC/TiN/W stacked structure, or a TiN/TaN/TiN/TiAlC/TiN/W stacked structure.

Each of the power supply rails PR41 to PR44 shown in FIG. 4 may include conductive lines respectively formed in the M1 layer and the M3 layer and extending in parallel with each other in the X-axis direction. In FIG. 4, the power rails PR41 to PR44 may include conductive lines formed in the M2 layer in a portion in which the pattern of the M2 layer is drawn on the power rails PR41 to PR44.

Referring to FIG. 4, in an exemplary embodiment of the inventive concept, the power rails PR41 to PR44 may include conductive lines formed in the M2 layer at the boundary of a standard cell. For example, as shown in FIG. 4, the first power rail PR41 and the second power rail PR42 may each include an electrically conductive line of an M2 layer overlapping the boundary of the standard cell C43. The second power rail PR42 and the third power rail PR43 may each include an electrically conductive line of an M2 layer overlapping the boundaries of the standard cells C44 and C45. In addition, the third power rail PR43 and the fourth power rail PR44 may each include a conductive line of an M2 layer overlapping the boundary of the standard cell C49. The third power rail PR43 may include a conductive line of the M2 layer overlapping the boundary of the standard cell C48. Further, the conductive lines of the M2 layer may be continuous in standard cells (for example, standard cells C44 and C45) adjacent to each other in the X-axis direction. The area in which the conductive lines of the M2 layer are not arranged in the power rails PR41 to PR44 can be used as signal routing in the standard cells C41 to C49.

As shown in FIGS. 4, 5A, 5B, 6A, and 6B, in an exemplary embodiment of the inventive concept, standard cells may be classified into a first group and a second group. The first group has a boundary overlapping the conductive lines in the M2 layer of the adjacent power supply rails formed in the power supply rails PR41 to PR44, and the second group does not have and is formed in the power supply rails PR41 to PR44 The boundaries of the conductive lines in the M2 layer of adjacent power rails overlap. For example, in FIG. 4, standard cells C43, C44, C45, and C49 may belong to a first group having boundaries that overlap with conductive lines formed in the M2 layer in adjacent power rails, and The standard cells C41, C42, C46, C47, and C48 may belong to a second group that does not have a boundary that overlaps the conductive lines formed in the M2 layer in the adjacent power rail.

The transistors in the standard cells of the first group can be supplied with high currents or can draw high currents from the transistors due to specific performance requirements. Performance requirements that induce high currents may include, for example, a fast rise/fall time of the output signal or a short propagation delay. For example, standard cells C43, C44, C45, and C49 may include a signal buffer, a clock buffer, an inverter, and the like. In other embodiments, standard cells may be included in the timing critical path of integrated circuit 40.

The second group may have a structure for advancing signal routing. For example, the standard cells of the second group may include a large number of input pins and output pins. For example, standard cells C41, C42, C46, C47, and C48 may include and/or-invert AOI 22, etc., and or non-AOI 22 have an input pin number per unit area compared to other standard cells. Large input pin. Additionally, the second group may include standard cells not included in the timing critical path of the integrated circuit 40.

5A and 5B are diagrams showing a standard cell C50 according to an exemplary embodiment of the inventive concept. For example, Figure 5A shows a standard cell C50 and a layout located around a standard cell C50. Figure 5B shows some of the layers surrounding the layout of standard cell C50. The standard cell C50 can be an inverter.

The standard cell C50 as an inverter may be sensitive to the resistance potential drop generated in the power rails PR51 and PR52. For example, the output signal of the inverter can have a fast rise/fall time, and thus, the regions of the power rails PR51 and PR52 adjacent to the standard cell C50 can be as shown in FIGS. 5A and 5B. The conductive lines formed in the M2 layer are reinforced. Therefore, the power rails PR51 and PR52 may include conductive lines respectively formed in the M1 layer, the M2 layer, and the M3 layer extending in the X-axis direction, and include through holes for electrically interconnecting the conductive lines .

Referring to FIG. 5A, the standard cell C50 may include an input pin P51 to which an input signal A is applied and formed in the M2 layer. The standard cell C50 may also include an output pin P52 that outputs an output signal Y and is formed in the M2 layer. As shown in FIG. 5A, the input pin P51 and the output pin P52 may be spaced apart from the conductive line of the M2 layer included in the power rail PR51 by a predetermined distance Y51, and the input pin P51 and the output pin P52 may be spaced apart from each other. Open the predetermined distance X51. The predetermined distances Y51 and X51 may be attributed to semiconductor manufacturing processes or design rules. In an exemplary embodiment of the inventive concept, the distance Y51 in the Y-axis direction may be greater than the distance X51 in the X-axis direction.

Referring to FIG. 5B, a plurality of conductive lines L51, L52, L53, L54, and L55 formed in the M3 layer and extending in parallel with each other in the X-axis direction are arranged on the standard cell C50. At least some of the plurality of conductive lines L51 to L55 can be used to route the input signal A and the output signal Y of the standard cell C50. In other words, the via hole V2 may be placed in at least one of the dots marked with '☆' in FIG. 5B, and thus, the input pin P51 and/or the output pin P52 may be electrically connected to the conductive line of the M3 layer. At least one of L51 to L55. Since the length of the input pin P51 and the output pin P52 in the Y-axis direction is limited by the conductive line of the M2 layer included in the power rails PR51 and PR52 described above with reference to FIG. 5A, the standard cell C50 The point at which the through hole V2 can be placed may be limited. For example, dots marked with '☆' are not shown in the conductive lines L51 and L55 of the M3 layer. However, since the power rails PR51 and PR52 can be reinforced by the conductive lines of the M2 layer, the standard cell C50 can provide good performance due to the reduced resistance potential drop.

6A and 6B are diagrams showing a standard cell C60 according to an exemplary embodiment of the inventive concept. For example, Figure 6A shows a standard cell C60 and a layout located around the standard cell C60. Figure 6B shows some of the layers of the layout located around the standard cell C60. The standard cell C60 can be AOI22.

The standard cell C60 (i.e., AOI 22) can have a relatively large number of input signals A0, A1, B0, and B1. Therefore, as shown in FIGS. 6A and 6B, the conductive lines formed in the M2 layer can be omitted in the regions of the power rails PR61 and PR62 adjacent to the standard cell C60. Therefore, the power rails PR61 and PR62 may include conductive lines respectively formed in the M1 layer and the M3 layer and extending in the X-axis direction.

Referring to FIG. 6A, the standard cell C60 may include input pins P61, P62, P63, and P64 which are applied with input signals A0, A1, B0, and B1 and formed in the M2 layer, and output output signals Y and formed in M2. Output pin P65 in the layer. As shown in FIG. 6A, the input pins P61 to P64 and the output pin P65 may extend in the Y-axis direction to a position close to the boundary of the standard cell C60. The close proximity of the pins P61 to P65 to the boundary of the standard cell C60 is due to the omitting of the conductive lines of the M2 layer in the power rails PR61 and PR62.

Referring to FIG. 6B, similarly to FIG. 5B, a plurality of conductive lines L61, L62, L63, L64, and L65 formed on the M3 layer and extending in parallel with each other in the X-axis direction may be arranged on the standard cell C60. At least some of the plurality of conductive lines L61 to L65 can be used to route the input signals A0, A1, B0, B1 and the output signal Y of the standard cell C60. In other words, the via hole V2 may be placed in at least one of the dots marked with '☆' in FIG. 6B, and thus, the input pins P61 to P64 and the output pin P65 may be electrically connected to the conductive line of the M3 layer. At least one of L61 to L65. Since the input pins P61 to P64 and the output pin P65 extend close to the boundary of the standard cell C60 by omitting the conductive lines of the M2 layer from the power rails PR61 and PR62 as described above with reference to FIG. 6A, the through hole V2 can be placed. Points can be expanded. For example, a dot marked with '☆' is shown in each of the conductive lines L61 to L65. 1 , 2A, 2B, 6A, and 6B, the input pins P61 to P64 and the output pin P65 may extend in the Y-axis direction across the power rails PR61 and PR62, and thus the input signal A0 A1, B0, B1 and output signal Y can be routed outside of standard cell C60. Therefore, the input signals A0, A1, B0, B1, and output signal Y of the standard cell C60 may not be routed.

FIG. 7 is a diagram showing a portion of an integrated circuit 70 according to an exemplary embodiment of the inventive concept. As shown in FIG. 7, the integrated circuit 70 may include a plurality of power supply rails PR71 to PR74 extending in parallel with each other in the X-axis direction, and a plurality of power supply lines PR71 to PR74 arranged between the plurality of power supply rails PR71 to PR74. Standard cells C71 to C79. Referring to FIGS. 1 , 2A, and 2B, each of the power rails PR71 to PR74 of FIG. 7 may be formed in each of the M1 layer and the M3 layer and parallel to each other in the X-axis direction. Extended conductive lines. Similar to FIG. 4, for the sake of convenience, FIG. 7 shows only the M2 layer in the power rails PR71 to PR74.

Referring to FIG. 7, in an exemplary embodiment of the inventive concept, the power rails PR71 to PR74 may include an M2 layer of conductive lines, and the conductive lines of the M2 layer extend in the X-axis direction to the standard with the M2 layer. A pattern (or a conductive line) extending in the Y-axis direction among the cells is spaced apart by a predetermined distance. For example, as shown in FIG. 7, the power rail PR71 may include a pattern L71 of the M2 layer extending from the standard cell C72 in the Y-axis direction, and the M2 layer extending in the X-axis direction to be spaced from the pattern L71. The conductive line L72 of the point of the distance X71 is opened. Therefore, as shown in FIG. 7, in the region in which the pattern of the M2 layer for routing the signals of the standard cells C71 to C79 is not formed, the conductive lines formed in the M2 layer of the power rails PR71 to PR74 are formed. Can be extended. For example, the conductive line L72 may extend in the X-axis direction to a point where the pattern L71 for signal routing is formed. In other words, since the conductive lines formed in the M2 layer of the power supply rails PR71 to PR74 can continue to extend after the signal routing, the power supply rails PR71 to PR74 can be reinforced and the resistance potential drop can be alleviated.

In an exemplary embodiment of the inventive concept, the conductive lines formed in the M2 layer of the power rails PR71 to PR74 may have a minimum area. For example, as shown in FIG. 7, the power rail PR71 may include the conductive lines L72 and L73 of the M2 layer. The conductive line L73 may have a length X72 in the X-axis direction. Conductive lines of the M2 layer that are smaller than the length X72 in the X-axis direction may be omitted. In other words, the conductive lines formed in the M2 layer of the power rails PR71 located between the patterns L71 and L74 can be omitted.

8A, 8B, and 8C are diagrams showing power rails PR80a, PR80b, and PR80c according to an exemplary embodiment of the inventive concept. As shown in FIGS. 8A through 8C, the power rails PR80a, PR80b, and PR80c may include a conductive layer adjacent to a semiconductor device (for example, a transistor). For example, in FIGS. 8A to 8C, conductive lines are formed on the upper wiring layer D1 of the four layers M1 to M4. Although an example in which the upper wiring layer D1 is located on the four layers is illustrated in FIGS. 8A to 8C, it should be understood that the upper wiring layer D1 may be located on less conductive layers or more conductive layers. For example, the upper wiring layer D1 may be located on a two-layer structure.

Referring to FIG. 8A, the power rail PR80a may include a conductive line L81a formed on the M1 layer and extending in the X-axis direction, and a conductive line L85a formed on the upper wiring layer D1 and extending in the X-axis direction. The conductive lines L81a and L85a can be electrically interconnected via a plurality of vias and a pattern of conductive layers. As shown in FIG. 8A, the D1 layer as the upper wiring layer may have a thickness larger than the thickness (for example, Z81) of each of the M1 layer to the M4 layer (for example, the length Z82 in the Z-axis direction) and / or can be formed from a material having high conductivity. Therefore, the resistance potential drop of the power supply rail PR80a can be alleviated due to the relatively low resistance value of the conductive line L85a. In addition, the power rail PR80a can enable the M2 layer to the M4 layer for signal routing, and thus the degree of freedom of signal routing can also be improved.

Referring to FIG. 8B, the power rails PR80b may include conductive lines L81b and L83b respectively formed in the M1 layer and the M3 layer and extending in the X-axis direction, and conductive lines L85b formed in the D1 layer and extending in the X-axis direction. . The conductive lines L81b, L83b, and L85b are electrically interconnected via a plurality of vias and a pattern of conductive layers. Since the conductive line L83b is formed in the M3 layer and the conductive line L85b has a large thickness, the resistance potential drop of the power supply rail PR80b can be alleviated. In addition, the power rail PR80b can use the M2 layer and the M4 layer for signal routing, and thus the degree of freedom of signal routing can be ensured.

Referring to FIG. 8C, the power rail PR80c may include a conductive line L85c formed in the D1 layer and extending in the X-axis direction. The conductive line L85c can supply power to the lower semiconductor device via the plurality of via holes and the pattern of the conductive layer. The resistance potential drop can be alleviated by the large thickness of the conductive line L85c, and the power rails PR80c can be used for signal routing using the M1 layer, the M2 layer, the M3 layer, and the M4 layer. Therefore, the degree of freedom of signal routing can be improved.

9A, 9B, and 9C are diagrams of structures for electrically interconnecting conductive layers of different layers, according to an exemplary embodiment of the inventive concept. As shown in FIGS. 9A to 9C, a plurality of through holes provided in parallel with each other on the same layer can be used to reduce the electric resistance between the conductive lines of the different layers. Such a structure may be referred to herein as a via pillar. For example, the exemplary structure shown in Figures 9A-9C can provide a path for moving input signals, output signals, and/or internal signals in standard cells. The exemplary structure shown in Figures 9A-9C can also be used to connect the conductive lines of power rails that extend in different layers. Hereinafter, the redundant explanation of FIGS. 9A to 9C will be omitted.

Referring to FIG. 9A, the via post VP90 may include conductive lines L91 and L95 respectively formed in the M1 layer and the M5 layer and extending in the X-axis direction. Two through holes V16 and V17 may be arranged between the conductive lines L91 of the M1 layer, and two conductive lines L92a and L92b may be formed on the M2 layer. The two conductive lines L92a and L92b extending in parallel with each other in the Y-axis direction may be disposed on the two through holes V16 and V17 to electrically interconnect the conductive lines L91 and L95. Four through holes V26, V27, V28, and V29 may be disposed on the two conductive lines L92a and L92b, and the four through holes V26 to V29 may be disposed on the M3 layer and at the X Two conductive lines L93a and L93b extending in parallel with each other in the axial direction. Four through holes V36, V37, V38, and V39 may be disposed on the two conductive lines L93a and L93b, and may be disposed in the M4 layer and in the four through holes V36 to V39. Two conductive lines L94a and L94b extending in parallel with each other in the axial direction. Two through holes V46 and V47 may be disposed on the two conductive lines L94a and L94b. Conductive lines L95 formed on the M5 layer may be disposed on the two through holes V46 and V47. By arranging the plurality of via holes in the layer as described above, the resistance value between the conductive line L91 of the M1 layer and the conductive line L95 of the M5 layer can be reduced, and the power is received via the conductive line L91 of the M1 layer. The semiconductor device can have a reduced resistance potential drop.

Referring to FIG. 9B, similar to the via post VP90 shown in FIG. 9A, the via post VP90' may include conductive lines L91' and L95' respectively formed in the M1 layer and the M5 layer and extending in the X-axis direction. Unlike the conductive line L91' formed in the M1 layer, the conductive line L95' of the M5 layer may have a relatively wide width (for example, a length in the Y-axis direction). Therefore, as shown in FIG. 9B, four through holes V46', V47', V48', and V49' may be arranged on the conductive lines L94a' and L94b' of the M4 layer. Conductive line L91' may be connected to a semiconductor device in a standard cell via a contact and/or via (eg, V0) and includes a pattern for signal routing.

Referring to FIG. 9C, similar to the via posts VP90 and VP90' shown in FIGS. 9A and 9B, the via post VP90'' may include conductive lines L91' respectively formed in the M1 layer and the M5 layer and extending in the X-axis direction. 'And L95''. Different from the conductive lines formed in the M2 layer to the M4 layer respectively in the via posts VP90 and VP90' shown in FIGS. 9A and 9B and separated from each other (for example, to form two lines), as shown in FIG. 9C The conductive lines respectively formed in the M2 layer to the M4 layer in the via post VP90'' may be combined into one solid pattern L92, L93, or L94.

Although the via posts VP90, VP90', and VP90'' include conductive lines formed in the M1 layer and the M5 layer, respectively, in FIGS. 9A through 9C, it should be understood that the structures shown in FIGS. 9A through 9C may include another A conductive wire. For example, conductive lines may be formed in the M3 layer, and the conductive lines extend along the conductive lines of the M1 layer and the M5 layer in the X-axis direction. The via posts VP90, VP90', and VP90'' shown in Figures 9A through 9C are examples and the inventive concept is not limited thereto. For example, more than four through holes may be arranged in the same layer (for example, between L93 and L94), and a plurality of rod-shaped through holes may be arranged in the same layer as shown in FIG. 2B and the like.

10A and 10B are diagrams illustrating power supply rails PR100a and PR100b according to an exemplary embodiment of the inventive concept. As shown in FIG. 10A and FIG. 10B, the power rails PR100a and PR100b may include conductive lines L110, L111, L150, and L151 respectively formed in the M1 layer and the D1 layer and extending in the X-axis direction, and may include A plurality of through holes electrically interconnecting the conductive lines L110 and L111 of the M1 layer and the conductive lines L150 and L151 of the D1 layer.

Referring to FIG. 10A, the power rails PR100a may include conductive lines L120, L130, and L140 of M2 to M4 layers connected to a plurality of vias for electrically interconnecting the conductive lines L110 and L150. As shown in FIG. 10A, the conductive lines L120, L130, and L140 may extend in the X-axis direction to enhance the electrical connection between the conductive lines L110 and L150 of the M1 layer and the D1 layer.

Referring to FIG. 10B, the power rails PR100b may include through holes spaced apart in the Y-axis direction in the same layer to connect the conductive lines L111 and L151 extending in the X-axis direction, and the through holes and at the X The conductive lines of the M2 layer to the M4 layer extending in the axial direction or the Y-axis direction are electrically connected. For example, as shown in FIG. 10B, the conductive lines L121, L122, and L123 of the M2 layer may extend in the Y-axis direction, and may be arranged on the Y-axis on the conductive lines L121, L122, and L123 of the M2 layer. A plurality of through holes spaced apart from each other in the direction. While the conductive lines L141, L142, and L143 of the M4 layer can extend in the Y-axis direction, the conductive lines L131 and L132 of the M3 layer can extend in the X-axis direction.

Compared with the power rail PR100a shown in FIG. 10A, the power rail PR100b shown in FIG. 10B can have a space extending in the Y-axis to provide the conductive lines L111 of the M1 layer and the D1 layer while providing space for signal routing. L151 electrically connected structure. In other words, since the conductive lines L120 and L140 are formed in the M2 layer and the M4 layer, the regions R11a, R12a, R13a, and R14a shown in FIG. 10A may be limited in use as a pattern for signal routing, and due to the M2 layer and The conductive lines L121 to L123 and L141 to L143 of the M4 layer extend in the Y-axis direction, and thus the regions R11b, R12b, R13b, and R14b shown in Fig. 10B can be used as patterns for signal routing. For example, when the conductive lines L121, L122, and L123 extending in the Y-axis direction are arranged in the M2 layer at predetermined intervals in FIG. 10B, the regions R11b and R12b may be formed in the M2 layer and used for the Y-axis direction. Signal routing on.

The power rails PR100a and PR100b shown in FIGS. 10A and 10B are examples and the inventive concept is not limited thereto. For example, the power rails PR100a and PR100b shown in FIGS. 10A and 10B include three through holes spaced apart from each other in the X-axis direction, or three pairs of through holes spaced apart from each other in the Y-axis direction in the same layer. . However, the power rail according to an exemplary embodiment of the inventive concept may include a number of vias and/or conductive lines that are smaller or larger than the number of vias and/or conductive lines shown in FIGS. 10A and 10B.

11 is a flowchart of a method of fabricating an integrated circuit including a plurality of standard cells, according to an exemplary embodiment of the inventive concept.

The standard cell library D50 may contain information about the plurality of standard cells, such as function information, feature information, layout information, and the like. As shown in FIG. 11, the standard cell library D50 may include a first group information D51 and a second group information D52. The first group information D51 may include information about a standard cell having a boundary overlapping with a conductive line formed in the M2 layer formed in the adjacent power rail as described above with reference to FIGS. 5A and 5B. The second group information D52 may include information about standard cells that do not have boundaries that overlap the conductive lines formed in the M2 layer in the adjacent power rails as described above with reference to FIGS. 6A and 6B.

Referring to FIG. 11, in operation S100, logic synthesis may be performed to generate a netlist data D20 from a register transfer level (RTL) data D10. For example, a semiconductor design tool (eg, a logic synthesis tool) can be based on a hardware description language (HDL) (eg, a very high speed integrated circuit (VHSIC) hardware description language (VHSIC). HDL, VHDL) and Verilog) write the scratchpad transfer hierarchy data D10 to perform logical synthesis. The semiconductor design tool can reference the standard cell library D50 during logic synthesis, thereby generating netlist data D20 that includes a bitstream or netlist. As described above, the standard cell library D50 may include information about standard cells in which the resistance potential drop is mitigated by enhancing adjacent power rails (for example, D51) and standard cells with improved signal routing degrees of freedom. Meta information (for example, D52). Thus, using such information in the logic synthesis process, standard cells with these characteristics can be included in the integrated circuit.

In operation S200, a placement and routing (P&R) operation for generating layout data D30 from the netlist data D20 may be performed. As shown in FIG. 11, the placement and routing operation S200 can include a plurality of operations S210, S220, and S230.

In operation S210, an operation of placing a standard cell may be performed. For example, a semiconductor design tool (eg, a placement and routing tool) can refer to a standard cell library D50 from netlist data D20 to place a plurality of standard cells. Since the standard cells can have a predetermined height, the semiconductor design tool can place the standard cells on an intersecting grid having a predetermined length. The power rails may extend in one direction that overlaps the grid and may be arranged at regular intervals.

In operation S220, an operation of creating an interconnection may be performed. The interconnect may electrically connect the output pin of the standard cell to the input pin and may include, for example, at least one via and at least one conductive pattern. By generating interconnects, standard cells can be routed and the M2 layer can be used for routing in some areas of the power rail. Further, as described above with reference to FIG. 7, after the signal routing is completed, the conductive lines of the M2 layer included in the power rail can be extended, and thus the resistance potential drop in the power rail can be further alleviated.

In operation S230, an operation of generating the layout material D30 may be performed. The layout data D30 may have a format such as a graphic database system II (GDSII) and may include geometric information of standard cells and interconnects.

In operation S300, an operation of manufacturing a mask may be performed. For example, a pattern formed in a plurality of layers may be defined according to layout material D30, and at least one mask (or photomask) for forming a pattern of each of the plurality of layers may be fabricated ).

In operation S400, an operation of fabricating an integrated circuit can be performed. For example, an integrated circuit can be fabricated by patterning the plurality of layers using the at least one mask fabricated in operation S300. As shown in FIG. 11, operation S400 may include operations S410 and S420.

In operation S410, a front-end-of-line (FEOL) process may be performed. The front section may refer to a process of forming individual components such as transistors, capacitors, resistors, and the like on a substrate during an integrated circuit fabrication process. For example, the front section may include planarizing and cleaning the wafer, forming trenches, forming wells, forming gate lines, forming source and drain electrodes, and the like.

In operation S420, a back end (BEOL) process may be performed. The latter stage may refer to a process of interconnecting individual components such as transistors, capacitors, resistors, etc. during the integrated circuit fabrication process. For example, the back section may include deuterating the gate, source, and drain regions, adding a dielectric, planarizing, forming a hole, adding a metal layer, forming a via, forming a protective layer, and the like. The integrated circuit can then be packaged in a semiconductor package and used as a component in various applications. By the back end process (S420), power rails and patterns for signal routing according to an exemplary embodiment of the inventive concept may be formed.

FIG. 12 is a block diagram of a system wafer (SoC) 120, in accordance with an exemplary embodiment of the inventive concept. System wafer 120 can be a semiconductor device and can include an integrated circuit. The system chip 120 is implemented by integrating complex functional blocks such as intellectual property (IP) that perform various functions into a single wafer. In accordance with an exemplary embodiment of the inventive concept, standard cells and power rails may be included in each of the functional blocks of system wafer 120, such that system wafer 120 may be efficiently routed due to reduced resistance potential drop The pattern has improved performance.

Referring to FIG. 12, the system chip 120 may include a data machine 122, a display controller 123, a memory 124, an external memory controller 125, a central processing unit (CPU) 126, a processing unit 127, and power. A power management integrated circuit (PMIC) 128 and a graphics processing unit (GPU) 129 are provided. The functional blocks of system wafer 120 can communicate with one another via system bus bars 121.

The central processing unit 126, which can control all operations of the system wafer 120, can control, for example, the data machine 122, the display controller 123, the memory 124, the external memory controller 125, the processing unit 127, the power management integrated circuit 128, and the graphics processing The operation of other functional blocks such as unit 129. The data engine 122 can demodulate signals received from outside the system chip 120 or can modulate signals generated in the system wafer 120 and transmit the signals to the outside of the system wafer 120. The external memory controller 125 can control the transfer of data to an external memory device connected to the system chip 120 and the operation of receiving data from the external memory device. For example, the programs and/or materials stored in the external memory device can be provided to the central processing unit 126 or the graphics processing unit 129 under the control of the external memory controller 125. The graphics processing unit 129 can execute the program instructions involved in the graphics processing. Graphics processing unit 129 can receive graphics data via external memory controller 125 and can communicate the processed graphics data to external to system wafer 120 via external memory controller 125. Processing unit 127 can monitor the data processing of each functional block. The power management integrated circuit 128 can control the power supplied to each functional block according to the control of the processing unit 127. Display controller 123 can control a display (or display device) located external to system wafer 120 and transfer the data generated in system wafer 120 to the display.

The memory 124 can be, for example, an electrically erasable programmable read-only memory (EEPROM), a flash memory, or a phase-change random access memory (PRAM). Resistive RAM (RRAM), nano floating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (magnetic RAM, MRAM), or non-volatile memory such as ferroelectric RAM (FRAM), or may be, for example, dynamic random access memory (DRAM), static random access Memory (static RAM, SRAM), mobile DRAM, double data rate (DDR) synchronous dynamic random access memory (SDRAM), low power double Data rate (low power DDR, LPDDR) synchronous dynamic random access memory, graphics double data rate (graphics DDR, GDDR) synchronous dynamics Machine access memory, Rambus dynamic random access memory (Rambus DRAM, RDRAM) and other volatile memory.

FIG. 13 is a block diagram of a computing system 130 including memory for storing programs, in accordance with an exemplary embodiment of the inventive concept. Computing system 130 may perform at least some of the operations included in a method of fabricating an integrated circuit (eg, the method illustrated in FIG. 11) in accordance with an exemplary embodiment of the inventive concept.

Computing system 130 can be a static computing system such as a desktop computer, workstation, or server, or can be a portable computing system such as a laptop. As shown in FIG. 13, computing system 130 can include a processor 131, an input/output (I/O) device 132, a network interface 133, a random access memory 134, a read-only memory 135, and Storage 136. The processor 131, the input/output device 132, the network interface 133, the random access memory 134, the read-only memory 135, and the storage 136 can be connected to the bus bar 137 and can communicate with each other via the bus bar 137.

The processor 131 can be a processing unit and can include at least one core, such as a microprocessor, an application processor (AP), a digital signal processor (DSP), or a graphics processing unit, the at least one Core executable instruction set (for example, Intel 32-bit architecture (Intel Architecture-32, IA-32), 64-bit extended Intel 32-bit architecture (64-bit extension IA-32), x86-64, Power PC (PowerPC), scalable processor architecture (Sparc), microprocessor without interlocked pipeline stage (MIPS), advanced reducted instruction set computer (RISC) machine (advanced RISC machine, ARM), or Intel 64-bit architecture (IA-64)). For example, the processor 131 can access a memory such as the random access memory 134 or the read-only memory 135 via the bus 137 and can execute instructions stored in the random access memory 134 or the read-only memory 135. .

The random access memory 134 can store at least a portion of the program 200 or program 200 in accordance with an exemplary embodiment of the inventive concept. According to an exemplary embodiment of the inventive concept, the program 200 may be capable of causing the processor 131 to perform at least some of the operations included in the method of fabricating the integrated circuit. In other words, the program 200 can include a plurality of instructions that are executable by the processor 131. The instructions included in program 200 may enable processor 131 to perform placement and routing in, for example, logic synthesis and/or operation S200 in operation S100 shown in FIG.

Even when the power supplied to the computing system 130 is turned off, the storage 136 does not lose the data stored in the storage 136. The storage 136 may include a non-volatile memory device or a storage medium such as a magnetic tape, a compact disc, or a magnetic disk. The storage 136 may be removable from the computing system 130. According to an exemplary embodiment of the inventive concept, the storage 136 can store the program 200. At least a portion of the program 200 or program 200 can be loaded from the storage 136 to the random access memory 134 prior to execution by the processor 131. Alternatively, the storage 136 can store files written in a programming language, and at least a portion of the program 200 or program 200 generated by the compiler from the files can be loaded into the random access memory 134. The storage 136 can also store a database (database) 251. The database 251 may contain information for designing integrated circuits (for example, the standard cell library D50 shown in FIG. 11).

The storage 136 can also store data to be processed by the processor 131 or data that has been processed by the processor 131. In other words, the processor 131 may generate data according to the program 200 by processing the data stored in the storage 136, or may store the generated data in the storage 136 according to the program 200. For example, the storage 136 can store the scratchpad transfer hierarchy data D10, the netlist data D20, and/or the layout data D30.

The input/output device 132 may include an input device such as a keyboard or a pointing device, and an output device such as a display device or a printer. For example, the user can trigger the processor 131 to execute the program 200 by using the input/output device 132, input the scratchpad transfer hierarchy data D10 and/or the netlist data D20 shown in FIG. 11, and check the image in FIG. Display layout data D30.

Network interface 133 provides access to a network external to computing system 130. For example, the network can include multiple computing systems and a communication link. The communication link can include a wired link, an optical link, a wireless link, or other type of link.

Although the present invention has been particularly shown and described with reference to the exemplary embodiments of the present invention, it is understood by those of ordinary skill in the art that the spirit and scope of the inventive concept defined by the following claims Under various conditions, various forms and details can be changed.

10, 40, 70‧‧‧ integrated circuits

120‧‧‧System Chip

121‧‧‧System Bus

122‧‧‧Data machine

123‧‧‧Display Controller

124‧‧‧ memory

125‧‧‧External memory controller

126‧‧‧Central Processing Unit

127‧‧‧Processing unit

128‧‧‧Power Management Integrated Circuit

129‧‧‧Graphic Processing Unit

130‧‧‧Computation System

131‧‧‧ processor

132‧‧‧Input/output devices

133‧‧‧Internet interface

134‧‧‧ random access memory

135‧‧‧Read-only memory

136‧‧‧Storage

137‧‧ ‧ busbar

200‧‧‧ program

251‧‧‧Database

A, A0, A1, B0, B1‧‧‧ input signals

AC1, AC2‧‧‧ active area

C11‧‧‧Standard cell/first standard cell

C12, C41, C42, C43, C44, C45, C46, C47, C48, C49, C50, C60, C71, C72, C73, C74, C75, C76, C77, C78, C79‧‧‧ standard cells

D1‧‧‧Upper wiring layer

D10‧‧‧Scratch transfer level data

D20‧‧‧ netlist information

D30‧‧‧Layout information

D50‧‧‧Standard Cell Library

D51‧‧‧Information/First Group Information

D52‧‧‧Information/Second Group Information

GL1‧‧‧ gate line

L01a, L01b, L01c, L02a, L02c, L03c, L11, L12, L21, L22, L23, L24, L25, L31, L32, L51, L52, L53, L54, L55, L61, L62, L63, L64, L65, L72, L73, L81a, L81b, L83b, L85a, L85b, L85c, L91, L91', L91'', L92a, L92b, L93a, L93b, L94a, L94a', L94b, L94b', L95, L95', L95' ', L110, L111, L120, L121, L122, L123, L130, L131, L132, L140, L141, L142, L143, L150, L151‧‧‧ conductive wire

L71, L74‧‧‧ pattern

L92, L93, L94‧‧‧ solid pattern

M1, M2, M3, M4, M5‧‧ layers

P51‧‧‧ input pin

P52‧‧‧ Output pin

P61, P62, P63, P64‧‧‧ pin/input pin

P65‧‧‧ pin/output pin

PR11, PR41‧‧‧Power rail/first power rail

PR12, PR42‧‧‧Power rail / second power rail

PR30a, PR30b, PR30c, PR51, PR52, PR61, PR62, PR71, PR72, PR73, PR74, PR80a, PR80b, PR80c, PR100a, PR100b‧‧‧ Power rails

PR43‧‧‧Power rail/third power rail

PR44‧‧‧Power rail/fourth power rail

R11a, R11b, R12a, R12b, R13a, R13b, R14a, R14b, R21, R22‧‧‧

S100, S200, S210, S220, S230, S300, S400, S410‧‧‧ operations

S420‧‧‧Operation/rear process

V0, V11, V11', V12, V12', V13, V13', V16, V17, V21, V21', V22, V22', V23', V23', V26, V27, V28, V29, V36, V37, V38, V39, V46, V46', V47, V47', V48', V49'‧‧‧ through holes

V1, V3, V4‧‧‧ through-hole layers

V2‧‧‧through/through layer

VP90, VP90', VP90''‧‧‧through hole column

X, Y, Z‧‧ Direction

X1-X1'‧‧‧ line

X20a, X20b, X72‧‧‧ length

X51, Y51‧‧‧ distance/predetermined distance

X71‧‧‧ distance

Y‧‧‧ output signal

Y10‧‧‧ Length / Height

Z81‧‧‧ thickness

Z82‧‧‧ Length / thickness

1 is a circuit diagram of a portion of an integrated circuit in accordance with an exemplary embodiment of the inventive concept.

2A and 2B are cross-sectional views of the integrated circuit cut along the line X1-X1' shown in FIG. 1 in parallel with the Z-axis direction, according to an exemplary embodiment of the inventive concept.

3A, 3B, and 3C are diagrams of power rails according to a comparative example.

4 is a diagram of a portion of an integrated circuit in accordance with an exemplary embodiment of the inventive concept.

5A and 5B are diagrams illustrating a standard cell according to an exemplary embodiment of the inventive concept.

6A and 6B are diagrams illustrating a standard cell according to an exemplary embodiment of the inventive concept.

FIG. 7 is a diagram showing a portion of an integrated circuit according to an exemplary embodiment of the inventive concept.

8A, 8B, and 8C are diagrams illustrating a power rail according to an exemplary embodiment of the inventive concept.

9A, 9B, and 9C are diagrams of structures for electrically interconnecting conductive layers of different layers, according to an exemplary embodiment of the inventive concept.

10A and 10B are diagrams illustrating a power rail according to an exemplary embodiment of the inventive concept.

11 is a flowchart of a method of fabricating an integrated circuit including a plurality of standard cells, according to an exemplary embodiment of the inventive concept.

FIG. 12 is a block diagram of a system-on-chip (SoC) according to an exemplary embodiment of the inventive concept.

FIG. 13 is a block diagram of a computing system including memory for storing programs, according to an exemplary embodiment of the inventive concept.

Claims (24)

An integrated circuit comprising: a power rail comprising: a first conductive line and a second conductive line spaced apart from each other in a vertical direction, wherein the first conductive line and the second conductive line are in a first horizontal direction Extending parallel to each other and electrically connected to each other to supply power to the first standard cell, wherein the first conductive line and the second conductive line are disposed at a boundary of the first standard cell; and a third a conductive line extending between the first conductive line and the second conductive line and extending in a second horizontal direction orthogonal to the first horizontal direction to transmit an input signal of the first standard cell Or output signal. The integrated circuit of claim 1, wherein the power rail further comprises a fourth conductive line electrically connected to the first conductive line and the second conductive line, wherein the fourth A conductive line extends in the first horizontal direction and is formed in the same layer as the third conductive line. The integrated circuit of claim 2, wherein the power rail further comprises: a first through hole electrically connecting the first conductive line and the fourth conductive line; and a second through hole And electrically connecting the second conductive line and the fourth conductive line. The integrated circuit of claim 3, wherein the first through hole or the second through hole is in a rod shape. The integrated circuit of claim 2, wherein the fourth conductive line is spaced apart from the third conductive line by a predetermined distance in the first horizontal direction. The integrated circuit of claim 2, wherein a length of the fourth conductive line in the second horizontal direction is equal to or greater than a length of the third conductive line in the first horizontal direction . The integrated circuit of claim 2, wherein the fourth conductive line completely overlaps the boundary of the first standard cell in the first horizontal direction. The integrated circuit of claim 7, wherein the first standard cell has a propagation delay that is shorter than a second standard cell that overlaps the fourth conductive line. The integrated circuit of claim 1, further comprising: a first signal line and a second signal line spaced apart from each other in the vertical direction and located in different conductive layers; the fourth conductive line and a fifth conductive line spaced apart from each other in the first horizontal direction or the second horizontal direction between the first signal line and the second signal line, and in the second horizontal direction or The first horizontal direction extends parallel to each other; the first through hole is arranged on the fourth conductive line; and the second through hole is arranged on the fifth conductive line, wherein the first signal line and the The second signal line is electrically connected to the fourth conductive line and the fifth conductive line, the first through hole and the second through hole. The integrated circuit of claim 1, wherein the power rail further comprises a fourth conductive line and a fifth conductive line electrically connected to the first conductive line and the second conductive line, The fourth conductive line and the fifth conductive line extend in the second horizontal direction and are formed in the same layer as the third conductive line, wherein the third conductive line is arranged in the fourth conductive line Between the line and the fifth conductive line. The integrated circuit of claim 1, wherein the first standard cell comprises: at least one active region extending in the first horizontal direction; and at least one gate line, in the The two extend in the horizontal direction. The integrated circuit of claim 1, wherein a positive supply voltage or a negative supply voltage is applied to the first conductive line and the second conductive line. An integrated circuit comprising: a first standard cell and a second standard cell arranged in a first horizontal direction; a power rail comprising: a first conductive line and a second conductive line spaced apart from each other in a vertical direction, Wherein the first conductive line and the second conductive line extend in parallel in the first horizontal direction and are electrically connected to each other to supply power to the first standard cell and the second standard cell Wherein the first conductive line and the second conductive line are disposed at a boundary of each of the first standard cell and the second standard cell; and a third conductive line is located at the boundary Extending between a first conductive line and the second conductive line and in a second horizontal direction orthogonal to the first horizontal direction to transmit an input signal or an output signal of the first standard cell, where The power rail further includes a fourth conductive line extending in the first horizontal direction on the boundary of the second standard cell, wherein the fourth conductive line is electrically connected to the first conductive a line and the second conductive line and the third conductive The lines are formed in the same layer. The integrated circuit of claim 13, wherein the fourth conductive line is spaced apart from the third conductive line by a predetermined distance in the first horizontal direction. The integrated circuit of claim 13, wherein the power rail comprises: a first through hole electrically connecting the first conductive line and the fourth conductive line; and a second through hole, Electrically connecting the second conductive line and the fourth conductive line. The integrated circuit according to claim 15, wherein the first through hole or the second through hole is in a rod shape. The integrated circuit of claim 13, wherein a length of the fourth conductive line in the second horizontal direction is equal to or greater than a length of the third conductive line in the first horizontal direction . The integrated circuit of claim 13, wherein each of the first standard cell and the second standard cell comprises: at least one active region, in the first horizontal direction Extending; and at least one gate line extending in the second horizontal direction. The integrated circuit of claim 13, wherein a positive supply voltage or a negative supply voltage is applied to the first conductive line, the second conductive line, and the fourth conductive line. An integrated circuit comprising: a power rail comprising a plurality of conductive lines on a boundary of a plurality of standard cells, wherein the plurality of conductive lines are formed in a plurality of conductive layers and are parallel to each other in a first horizontal direction Extending to supply power to the plurality of standard cells; and a signal line passing through the power rail in a second horizontal direction orthogonal to the first horizontal direction, wherein the signal line is formed in the In one of the plurality of conductive layers, to transmit an input signal or an output signal of at least one of the plurality of standard cells, wherein the power rail includes a first conductive line, the first conductive line Formed in the conductive layer in which the signal line is formed, wherein the first conductive line extends in the first horizontal direction and is insulated from the signal line. The integrated circuit of claim 20, wherein the power rail further comprises a second conductive line and a third conductive line, and the second conductive line and the third conductive line are respectively formed on the And extending in the first horizontal direction of the two conductive layers of the plurality of conductive layers, wherein the signal line is formed in the second conductive line and the third conductive line formed therein In the conductive layer between the two conductive layers. The integrated circuit of claim 20, wherein the power rail further comprises: a through hole electrically connecting the plurality of conductive lines, wherein at least one of the through holes is A rod shape extending in the first horizontal direction. The integrated circuit of claim 20, wherein each of the plurality of standard cells comprises: at least one active region extending in the first horizontal direction; and at least one gate line Extending in the second horizontal direction. The integrated circuit of claim 21, wherein the second conductive line and the third conductive line are applied with a positive supply voltage or a negative supply voltage.