TWI797961B - Storage and display method of display data and display device and information processing device using same - Google Patents

Abstract

The present invention mainly discloses a method for storing and displaying display data, which includes the following steps: dividing the display data of a previous frame stored in a storage unit into m sub-frame display data including sequence number 0 to sequence number m-1; Arrange the display order of the m-1 sub-frame display data from serial number 1 to serial number m-1; receive a frame synchronization signal and a frame display data transmitted by a host computer; and complete the After the frame display data is received, the display panel is driven to display m subframe display data in display order, and after the display of each subframe display data is completed, some bits of the frame display data are stored in an overwriting manner The storage space for storing the display data of the sub-frame in the storage unit until all the display data of the sub-frame is completely displayed, the storage space of the storage unit for storing the display data of the previous frame is completely covered by the display data of the frame.

Description

Storage and display method of display data, display device using same and information processing device

The present invention relates to the technical field of display devices, in particular to a method for storing and displaying display data.

It is known that light-emitting diodes (Light-emitting diodes, LEDs) have many advantages such as small size, light weight, long service life, and high luminous efficiency, and have been widely used in lighting devices and display devices. The LED display device is a self-illuminating flat-panel display device, which has the advantages of bright colors, wide dynamic range, high brightness, long life, and high reliability. The LED display device with a large screen has been widely used in large squares, commercial advertisements, Sports venues, information dissemination, news releases, stock exchange places, as a public display medium.

FIG. 1 shows a structure diagram of a conventional LED display device. As shown in Figure 1, the conventional LED display device 1a mainly includes: an LED display panel 11a and a display driving circuit 12a, the display driving circuit 12a is based on a frame synchronization signal and a frame display data transmitted from the host computer 2a. Display driving is performed on the LED display panel 11a. Traditionally, the grayscale (brightness) of each LED pixel is precisely controlled by controlling the LED current and its conduction time. The conduction time control method is to control the gray level of the LED by changing the duty cycle under the condition of constant current driving. For example, in order to display a frame of image, 16-bit gray level data G is provided for each LED graphic element [15 :0].

In an improved display data driving method, in order to increase the refresh rate of the displayed image, one frame of display data can be divided into multiple sub-frames and displayed one by one. The shorter the duration of each subframe is, the higher the refresh rate index is. In this method, the integer part of the frame display data is evenly distributed among a plurality of sub-frames (that is, broken up), but the remainder part of the frame display data that cannot be divisible by an integer is not broken up, and it is directly assigned In a subframe (usually the subframe with sequence number 0).

The prior art adopts the method of ping-pong frame to receive the display data of the current frame and drive the LED display panel 11a to display the image according to the display data of the previous frame. That is, in the display of the current frame The frame header or frame tail bit of the display data is used as the control bit. After the display driving circuit 12a receives the control bit, it starts to drive the LED display panel 11a to display images according to the display data of the previous frame. This is repeated until the host computer 2a no longer transmits display data. In other words, the method of ping-pong frame is that the storage space of the temporary register can store at least two frames of display data at the same time. However, as the number of bits (that is, the resolution) of the grayscale data increases, the space required to store a single frame display data is also larger, resulting in a large storage space required for the temporary register suitable for the ping-pong frame. Therefore, it is difficult to reduce the manufacturing cost of the display driving circuit 12a.

It can be seen from the above description that there is an urgent need in the art for a new method for storing and displaying display data.

The main purpose of the present invention is to provide a method for storing and displaying display data. Its technical feature is that the upper computer sends a (current) frame of display data according to the graphic element (such as: 16-bit graphic element) and immediately initiates a frame synchronization signal, so that The display driving circuit reads out the display data of the previous frame from the SRAM, divides them into m sub-frame display data including sequence number 0 to sequence number m-1, and sorts them in display sequence. After the display panel is driven to display the first subframe (such as: subframe number 0), the bit corresponding to the received (current) frame display data can be written into the SRAM to replace the bit corresponding to the subframe that has been displayed Yuan. Therefore, by adjusting the display order of the subframes, the low-order bits in the display data of the previous frame can be displayed first, and then the corresponding low-order bits in the display data of the current frame can be written, and so on. , until all subframes are displayed, all bits of the current frame display data are also written into the SRAM. According to this method, the display driving circuit can perform the display driving of the display data of the previous frame, and at the same time store the received current frame display data, so that the SRAM space of less than 2 ping-pong frames can be used to completely store the ping-pong frames, and displayed continuously.

In order to achieve the above object, the present invention proposes an embodiment of the storage and display method of the display data, which is executed by a display driving circuit, and includes: dividing the display data of a previous frame stored in a storage unit into serial numbers m subframes from 0 to serial number m-1 display data, m is a positive integer; Arranging the display order of the m-1 sub-frame display data from serial number 1 to serial number m-1 according to the number of low-order 0s; receiving a frame synchronization signal and a frame of display data transmitted by a host computer; and After receiving the frame display data, drive the display panel to display m sub-frame display data in display order, and after each sub-frame display data is displayed, overwrite the frame display data Partial bits are stored in the storage unit storing the storage space of the sub-frame display data until all the sub-frame display data are fully displayed, and the storage unit originally storing the storage space of the previous frame display data is completely covered by the frame display data .

In one embodiment, the display driving circuit starts to drive the display panel to display m sub-frame display data according to the display sequence according to a trigger display signal.

In one embodiment, the display triggering signal is transmitted from the host computer, or is generated by the display driving circuit by performing a bit-shift processing on the frame synchronization signal.

In an embodiment, the display data of the previous frame includes L display data bits, and the m-1 subframe display data from sequence number 1 to sequence number m-1 include S subframe integer bits and Q subframe remainders bits, and the subframe display data with serial number 0 includes S subframe integer bits, Q subframe remainder bits, and P whole frame remainder bits; S, Q, P, and L are all positive integers, and S+P+Q=L.

In one embodiment, the S subframe integer bits are the first S high order bits of the L display data bits of the frame display data, and the P whole frame remainder bits are the frame display data The last P low-order bits of the L display data bits of the display data, and the Q sub-frame remainder bits are the L display data bits of the frame display data excluding the first S high-order bits and all The middle Q bits after the P low bits.

In one embodiment, the display driving circuit uses the sub-frame display data of serial number 0 to drive the display panel for image display immediately after receiving all the display data bits of the previous frame display data, Then, the display panel is driven for image display according to the display data of the sub-frames with sequence number 1 to sequence number m-1 arranged in sequence.

In one embodiment, after the display data of the sub-frame with sequence number 0 is displayed, the storage unit releases the storage space originally storing the P remainder bits of the whole frame to store the display data of the frame. The corresponding P bits among the L display data bits contained in the display data; after the m-1 sub-frame display data from sequence number 1 to sequence number m-1 are displayed in their display order, the storage unit It is to release the storage space that originally stored the remaining bits of the Q subframes bit by bit, so as to store the corresponding Q bits among the L display data bits included in the frame display data; After the display is completed, the storage unit releases the storage space originally storing the S subframe integer bits to store corresponding S bits among the L display data bits included in the frame display data.

Moreover, the present invention also proposes a display device, which includes a display panel and a display driving circuit, which is characterized in that the display driving circuit utilizes the method for storing and displaying display data of the present invention as described above to store data by bit. A frame of display data transmitted by a host computer, and image display driving of the display panel is performed according to a previous frame of display data.

In one embodiment, the display panel is selected from a light emitting diode display panel, a quantum dot light emitting diode display panel, a micro light emitting diode display panel, a submillimeter light emitting diode display panel, a perovskite A flat display panel in the group consisting of a light emitting diode display panel and an organic light emitting diode display panel.

Furthermore, the present invention also proposes an information processing device, which has the display device of the present invention as described above, and the information processing device is selected from video walls, smart phones, smart watches, smart bracelets, tablet computers, An electronic device in the group consisting of notebook computers, all-in-one computers, and outdoor station devices.

1a: LED display device

11a: LED display panel

12a: Display drive circuit

2a: PC

1: Display device

11: Display panel

12: Display drive circuit

120: Control unit

121: storage unit

122: Display drive unit

2: PC

S1: Divide a previous frame display data stored in a storage unit into m sub-frame display data including sequence number 0 to sequence number m-1

S2: Arrange the display order of the m-1 subframe display data from sequence number 1 to sequence number m-1 according to the number of low-order 0s

S3: Receive a frame synchronization signal and a frame display data transmitted by a host computer

S4: After receiving the frame display data, drive the display panel to display m sub-frame display data in display order, and display the frame in an overlay mode after each sub-frame display data is displayed Some bits of the data are stored in the storage unit storing the storage space of the sub-frame display data until all the sub-frame display data are fully displayed. The storage unit originally stored the storage space of the previous frame display data by the frame display data. full coverage

Fig. 1 is a structural diagram of a known LED display device; Fig. 2 is a structural diagram of a display device applying a storage and display method of display data of the present invention; and Fig. 3 is a storage and display method of display data of the present invention A flow chart of the display method; and FIG. 4 is a working timing diagram of a frame synchronization signal, a frame display data, a trigger display signal, and a sub-frame display data.

In order to enable your examiners to further understand the structure, features, purpose, and advantages of the present invention, drawings and detailed descriptions of preferred embodiments are hereby attached.

FIG. 2 is a structural diagram of a display device applying a method for storing and displaying display data according to the present invention. Moreover, FIG. 3 shows a flowchart of a method for storing and displaying display data in the present invention. As shown in FIG. 2 , the display device 1 mainly includes: a display panel 11 and a display driving circuit 12 , and the display driving circuit 12 has a control unit 120 , a storage unit 121 and a display driving unit 122 . In general, the display driving circuit 12 drives the display panel 11 according to a frame synchronization signal and a frame of display data transmitted from the host computer 2 .

Engineers who have been involved in the design and manufacture of display driver chips for a long time must know that the prior art uses ping-pong frames to receive (current) frame display data and drive the display panel 11 to display images according to the previous frame display data. Differently, in the case of applying the method of the present invention, the display driving circuit 12 divides a previous frame display data stored in a storage unit 121 into m sub-frame display data including sequence number 0 to sequence number m-1, where m is Positive integer (ie, execute step S1).

For example, the display data of the previous frame is a 16-bit data, and the display data of one frame of each graphic element is G[15:0]. Under the condition that the minimum display unit k is also 16, use the following equations (1) to (3) to calculate the basic data of each sub-frame display data of the previous frame display data: r=G%k= G[3:0]................................................ .............................(1)

d=G%(m*k)/k=G[7:4].......................... ............................(2)

I=G/(m*k)=G[15:8].......................... ................................(3)

In order to evenly distribute the display data of a complete previous frame to the 16 sub-frame display data, each sub-frame display data must at least include: sub-frame integer bits and sub-frame remainder bits. Wherein, the above formula (2) calculates that each subframe display data contains Q subframe remainder bits, that is, G[7:4] in the previous frame display data. Moreover, the above formula (3) calculates that each subframe display data contains S subframe integer bits, that is, G[15:8] in the previous frame display data. It is worth noting that r refers to the remaining bits of the entire frame that are not evenly distributed among the 16 sub-frame display data. Through the calculation of the above formula (1), it can be known that r is the number of display data of the previous frame. G[3:0] in . It should be added that usually r (ie, G[3:0]) will be placed in the sub-frame display data of sequence number 0.

In other words, the display driving circuit 12 divides the display data of the previous frame into m sub-frame display data including sequence number 0 to sequence number m-1, wherein the m-1 subframes of sequence number 1 to sequence number m-1 The display data includes S subframe integer bits and Q subframe remainder bits, and the subframe display data of sequence number 0 includes S subframe integer bits, Q subframe remainder bits and P whole frame remainder bits ; Q and P are both positive integers, and S+P+Q=L. In more detail, taking the subframe integer bit I=G[15:8], the subframe remainder bit R=G[7:4] and the whole frame remainder bit r=G[3:0] as an example, The subframe integer bits are 8-bit relay data, the subframe remainder bits are 4-bit relay data, and the whole frame remainder bits are 4-bit relay data.

Therefore, the display data of all m subframes will satisfy the following formula (4) ~ formula (7): gn=I*k+x.......... ................................................... .........(4)

if n=0,x=r................................... ................................................(5)

if 0<n≦d,x=k................................................ ...................................(6)

if n>d,x=0................................... ...................................(7)

It can be known from the above formula (2) that d=G[7:4] is a 4-bit metadata, so the maximum value of the decimal is 15. On the other hand, n is used to represent the serial number of the sub-frame display data, so 0≦n≦m-1=15. According to this design, the gray scale value g0=I*k+x of the 0th (i.e. n=0) subframe display data, the gray scale value gn=I*k+k of the first to dth subframe display data, And the grayscale value gn=I*k of the display data of the d+1th to m−1th subframes. In this way, the sum of display data of all m subframes can be calculated as: m*I*k+d*k+r=(m*I+d)*k+r=(16*G[15:8]+G[ 7:4])*16+G[3:0]=G[15:0]. Therefore, it can be determined that the previous frame display data can indeed be divided into m sub-frame display data including sequence number 0 to sequence number m−1 by using the above formulas (1) to (7). At the same time, for m=16 subframe display data, the S subframe integer bits included in it are the first S high order bits of the L display data bits of the frame display data (that is, I=G [15:8]), the P remaining bits of the entire frame included are the last P low-order bits of the L display data bits of the frame display data (that is, r=G[3:0]) , and the Q subframe remainder bits contained in it (ie, d=G[7:4]) Among the L display data bits of the frame display data, middle Q bits after the first S high-order bits and the P low-order bits are excluded. In other words, S+P+Q=L.

As shown in FIG. 3 , the method flow proceeds to step S2: arranging the display order of the m-1 sub-frame display data from sequence number 1 to sequence number m-1 according to the number of low-order 0s. In more detail, for any subframe display data from sequence number 1 to sequence number m−1, it includes S subframe integer bits (ie, I=G[15:8]) and Q subframe remainder bits element (ie, d=G[7:4]). Obviously, compared with I=G[15:8], d=G[7:4] is low-bit metadata. Therefore, when determining the arrangement of the display order of the subframe display data, the number of bit 0s carried by d=G[7:4] (ie, 4-bit data) can be calculated. In principle, the sub-frame display data that contains more low-order bit 0s will be displayed preferentially, that is, has a priority display order.

It is worth noting that the grayscale value of the subframe display data is related to its sequence number n and d. Multiple binary bits are used to represent the n serial number. If the lower bit of the n serial number is 0, after comparing n with d, it is found that the corresponding lower bit of d is not needed. Therefore, after the n serial numbers are sorted, the display order of the serial numbers whose lower bits are more 0 (except the 0 serial number) is rearranged, so that the lower bits of d and the storage space of r can be released in advance. For example, the subframe display data of sequence number 0 includes S subframe integer bits (ie, I=G[15:8]), Q subframe remainder bits (ie, d=G[7:4] ), and P whole frame remainder bits (that is, r=G[3:0]), therefore, after receiving a frame synchronization signal and a frame of display data transmitted by a host computer 2 (that is, step S3) , and then perform step S4: after completing the reception of the frame display data, drive the display panel to display m sub-frame display data in display order, and after each sub-frame display data is displayed, overlay the Some bits of the frame display data are stored in the storage unit to store the storage space of the sub-frame display data until all the sub-frame display data are fully displayed. The storage unit originally stored the storage space of the previous frame display data by Frames are shown completely covered by the data.

According to the design of the present invention, after the display drive circuit 12 completes the reception of all the display data bits of the previous frame display data, it then uses the sub-frame display data of serial number 0 to display the image on the display panel 11 driving, and then performing image display driving on the display panel according to the display data of the sub-frames with sequence number 1 to sequence number m-1 arranged in sequence. For example, m places The display order of the subframe display data is 0, 15, 7, 11, 3, 13, 5, 9, 1, 14, 6, 10, 2, 12, 4, 8. It should be understood that the (current) frame display data also includes L display data bits, where L is a positive integer, and S+P+Q=L.

In other words, in the case of applying the method of the present invention, the display driving circuit 12 can perform display driving of the display data of the previous frame and at the same time store the received display data of the current frame, so as to realize the use of less than 2 Ping-pong frame SRAM space, complete storage of ping-pong frames, and continuous display. It is supplemented that, in a feasible embodiment, the triggering display signal is transmitted from the host computer 2 , or is generated by the display driving circuit 12 by performing a bit-shift processing on the frame synchronization signal.

FIG. 4 shows a working timing diagram of a frame synchronization signal (Video_Vsync), a frame of display data (Video), a trigger display signal (Display_Vsunc), and a subframe of display data (Display group). For example, the host computer 2 sends a frame synchronization signal (Video_Vsync) and a frame of display data (Video), and sends a trigger display signal (Display_Vsunc) to initiate frame synchronization after the display data is sent. According to the design of the present invention, after the display drive circuit 12 completes the reception of all the display data bits of the previous frame display data, it immediately uses the sub-frame display data of sequence number 0 (that is, g0) to display the display panel 11 Perform image display driving. After the display data of the sub-frame with serial number 0 is displayed, the storage unit 121 releases the storage space originally storing the remainder bits of the P whole frame (that is, r=G[3:0]). Corresponding P bits among the L display data bits included in the stored (current) frame display data are used. And, after the m-1 sub-frame display data from sequence number 1 to sequence number m-1 are displayed according to their display order, the storage unit 121 releases the remainder bits of the Q sub-frames originally stored bit by bit. The storage space of the element (ie, d=G[7:4]) is used to store the corresponding Q bits among the L display data bits included in the (current) frame display data. After the last subframe display data is displayed, the storage unit 121 releases the storage space originally storing the S subframe integer bits (ie, I=G[15:8]) to store the frame display data Corresponding S bits among the included L display data bits.

That is to say, the display order of the m sub-frame display data is 0, 15, 7, 11, 3, 13, 5, 9, 1, 14, 6, 10, 2, 12, 4, 8. Since the display data of the subframe with serial number 0 contains the remainder bits d=G[7:4] of the whole frame without breaking up, or called non-breaking bits, the display data of the subframe with serial number 0 is displayed first. The specific operation is to read the entire frame display data G[15:0] from the storage unit 121 (ie, SRAM), and calculate the sub-frame display data Among them, the subframe integer bit I (as shown in the above formula (3), I=G[15:8]), and calculate the subframe remainder bit r at the same time (as shown in the above formula (1), r=G[ 3:0]). Further, according to the above formulas (4)~(7), the grayscale value g0=I*k+x=G[15:8]* of the subframe display data of the 0th (that is, the serial number n) can be calculated 16+g[3:0]. Next, the display data G[15:4] is written back to the SRAM (that is, the storage unit 121) by bit. When writing back, the same bits of all channels are formed into a 16-byte group to replace a frame originally stored by the SRAM. Display data G[15:0], thereby reducing data storage space.

After the display of the sub-frame display data of sequence number 0 is completed, the display of the sub-frame display data of sequence numbers 15, 7, 11, 3, 13, 5, 9, and 1 is then completed according to the sequence. Firstly, during the period of displaying the sub-frame display data whose serial number n is 15 to 10, read the grayscale data G[15:4] from the SRAM, and then calculate the sub-frame integer bit I=G[15:8], And calculate the remainder bit of the whole frame (or called non-breaking bit) d=G[7:4], and then calculate the sub-frame display data gn=i*K+x. n can be represented by 4-bit data, so it can be calculated that when n<=g[7:4], then x=K, otherwise x=0.

Next, during the period of displaying the subframe display data whose serial number n is 2, read the grayscale data G[15:4] from the SRAM, and then calculate the subframe integer bit I=G[15:8], and calculate Get the remainder bits of the whole frame (or called non-breaking bits) d=G[7:4], and then calculate the sub-frame display data g2=i*K+x. When 2<=g[7:4], then x=K, otherwise x=0.

During the period of displaying the subframe display data whose serial number n is 2, read out the grayscale data G[15:4] from the SRAM, then calculate the subframe integer bit I=G[15:8], and calculate the integer Frame remainder bits (or non-break bits) d=G[7:4], and then the sub-frame display data g2=i*K+x is calculated. When 2<=g[7:4], then x=K, otherwise x=0. At the same time, write each display data G[15:5] back to the SRAM, replace the original SRAM primitive value G[15:4], and shorten the frame data storage space.

During the period of displaying the subframe display data whose serial number n is 12, read out the grayscale data G[15:5] from the SRAM, then calculate the subframe integer bit I=G[15:8], and calculate the integer The frame remainder bit (or non-break bit) d=G[7:4]x2, and then the sub-frame display data g12=i*K+x is calculated. When 12<=g[7:4]x2, then x=K, otherwise x=0. At the same time, each display data G[15:6] is written back to the SRAM to replace the original value G[15:5] of the SRAM to shorten the frame data storage space.

During the period of displaying the subframe display data whose serial number n is 4, read out the grayscale data G[15:6] from the SRAM, then calculate the subframe integer bit I=G[15:8], and calculate the integer The frame remainder bit (or non-break bit) d=G[7:4]x4, and then the sub-frame display data g4=i*K+x is calculated. When 4<=g[7:4]x4, then x=K, otherwise x=0. At the same time, write each display data G[15:7] back to SRAM, replace the original SRAM primitive value G[15:6], and shorten the frame data storage space.

During the period of displaying the subframe display data whose serial number n is 8, read out the grayscale data G[15:7] from the SRAM, then calculate the subframe integer bit I=G[15:8], and calculate the integer The frame remainder bit (or non-break bit) d=G[7:4]x8, and then the sub-frame display data g8=i*K+x is calculated. When 8<=g[7:4]x8, then x=K, otherwise x=0. At the same time, releasing the display data of the last frame stored in the storage space means releasing all the storage space of G[15:7].

As can be seen from the foregoing description, the conventional ping-pong frame method is that the storage space of the temporary register can store at least two frames of display data at the same time. It can be smaller than the memory suitable for ping-pong frames, so it has the advantage of low cost.

In this way, the above has completely and clearly described a method for storing and displaying display data of the present invention; and, through the above, it can be known that the present invention has the following advantages:

(1) The present invention discloses a method for storing and displaying display data. Its technical feature is that the host computer immediately initiates a frame synchronization signal after sending a (current) frame of display data according to the graphics element, so that the display drive circuit will display the previous frame. The data is read from the SRAM, and is divided into m subframes including sequence number 0 to sequence number m−1 to display data, and the display sequence is sorted. After the display panel is driven to display the first subframe (such as: subframe number 0), the bit corresponding to the received (current) frame display data can be written into the SRAM to replace the bit corresponding to the subframe that has been displayed Yuan. Therefore, by adjusting the display order of the subframes, the low-order bits in the display data of the previous frame can be displayed first, and then the corresponding low-order bits in the display data of the current frame can be written into it, and so on until After all the sub-frames are displayed, all bits of the current frame display data are also written into the SRAM. In this way, the display driving circuit can display the display data of the previous frame while displaying the received current frame. Display data for data storage, so as to realize the use of less than 2 ping-pong frame SRAM space, complete storage of ping-pong frames, and continuous display. .

(2) The present invention also provides a display device, which includes a display panel and a display drive circuit, characterized in that the display drive circuit utilizes the method for storing and displaying display data of the present invention as described above, thereby A frame of display data sent by a host computer is stored, and the display panel is driven for image display according to a previous frame of display data. In one embodiment, the display panel is selected from a light emitting diode display panel, a quantum dot light emitting diode display panel, a micro light emitting diode display panel, a submillimeter light emitting diode display panel, a perovskite A flat display panel in the group consisting of a light emitting diode display panel and an organic light emitting diode display panel.

(3) The present invention also provides an information processing device, which has the display device of the present invention as described above, and the information processing device is selected from video walls, smart phones, smart watches, smart bracelets, tablet computers, An electronic device in the group consisting of notebook computers, all-in-one computers, and outdoor station devices.

It must be emphasized that what is disclosed in the above-mentioned case is a preferred embodiment, and all partial changes or modifications derived from the technical ideas of this case and easily deduced by those familiar with the technology are all inseparable from the patent of this case. category of rights.

In summary, regardless of the purpose, means, and efficacy of this case, it shows that it is very different from the conventional technology, and its first invention is practical, and it does meet the patent requirements of the invention. I urge your review committee to clearly understand and grant the patent as soon as possible. Society is for the Most Prayer.

S1: Divide a previous frame display data stored in a storage unit into m sub-frame display data including sequence number 0 to sequence number m-1

S2: Arrange the display order of the m-1 subframe display data from sequence number 1 to sequence number m-1 according to the number of low-order 0s

S3: Receive a frame synchronization signal and a frame display data transmitted by a host computer

S4: After receiving the frame display data, drive the display panel to display m sub-frame display data in display order, and display the frame in an overlay mode after each sub-frame display data is displayed Some bits of the data are stored in the storage unit storing the storage space of the sub-frame display data until all the sub-frame display data are fully displayed. The storage unit originally stored the storage space of the previous frame display data by the frame display data. full coverage

Claims (10)

A method for storing and displaying display data, which is executed by a display driving circuit, and includes: dividing a previous frame display data stored in a storage unit into m sub-frame display data including sequence number 0 to sequence number m-1, m is a positive integer; arrange the display sequence of the m-1 subframe display data from serial number 1 to serial number m-1 according to the number of low-order 0s; receive a frame synchronization signal and a frame synchronization signal sent by a host computer frame display data; and after completing the reception of the frame display data, drive a display panel to display m sub-frame display data in display order, and after each sub-frame display data is displayed, overwrite all the sub-frame display data Some bits of the display data of the frame are stored in the storage space of the storage unit for storing the display data of the sub-frame until all the display data of the sub-frame are fully displayed. Show data completely covered. The method for storing and displaying display data according to claim 1, wherein the display driving circuit starts to drive the display panel to display m sub-frame display data according to the display sequence according to the trigger of a trigger display signal. The method for storing and displaying display data as described in Claim 2, wherein the trigger display signal is transmitted from the host computer, or is generated by the display driving circuit by performing a bit-shift processing on the frame synchronization signal. The method for storing and displaying display data as described in Claim 1, wherein the display data of the previous frame includes L display data bits, and the m-1 sub-frame display data of serial number 1 to serial number m-1 include S subframe integer bits and Q subframe remainder bits, and the subframe display data of sequence number 0 includes S subframe integer bits, Q subframe remainder bits and P whole frame remainder bits; S, Q, P, and L are all positive integers, and S+P+Q=L. The method for storing and displaying display data according to claim 4, wherein the S subframe integer bits are the first S high-order bits of the L display data bits of the frame display data, and the The remaining P bits of the entire frame are the last P low-order bits of the L display data bits of the frame display data and the Q subframe remainder bits are middle Q bits after excluding the first S high-order bits and the P low-order bits among the L display data bits of the frame display data. The method for storing and displaying display data as described in Claim 5, wherein the display driving circuit continues to use the sub-frame display data with sequence number 0 immediately after receiving all the display data bits of the previous frame display data The display panel is driven for image display, and then the display panel is driven for image display by arranging the sub-frame display data from sequence number 1 to sequence number m-1 in the display sequence. The method for storing and displaying display data as described in Claim 6, wherein, after the display data of the sub-frame with serial number 0 is displayed, the storage unit releases the data that originally stored the remainder bits of the P whole frame The storage space is used to store the corresponding P bits among the L display data bits included in the frame display data; the m-1 sub-frame display data from sequence number 1 to sequence number m-1 are displayed according to their display order After the display is completed, the storage unit releases the storage space originally storing the Q subframe remainder bits bit by bit, so as to store the corresponding Q bits among the L display data bits included in the frame display data; After the display data of the last subframe is displayed, the storage unit releases the storage space originally storing the S subframe integer bits to store the corresponding S among the L display data bits included in the frame display data. indivual. A display device, which includes a display panel and a display driving circuit, characterized in that the display driving circuit utilizes the method for storing and displaying display data as described in any one of request item 1 to request item 7. The unit stores a frame of display data sent by a host computer, and performs image display driving on the display panel according to a previous frame of display data. The display device according to claim 8, wherein the display panel is selected from a light-emitting diode display panel, a quantum dot light-emitting diode display panel, a micro-light-emitting diode display panel, and a submillimeter light-emitting diode display panel. A flat display panel in the group consisting of a display panel, a perovskite light-emitting diode display panel, and an organic light-emitting diode display panel. An information processing device, which has a display device as described in claim 8, and it is selected from a video wall, a smart phone, a smart watch, a smart bracelet, a tablet computer, a notebook computer, an all-in-one computer, and a doorway An electronic device in the group consisting of computer devices.

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