TWI797796B - Gate-driving circuit and driver chip containing the same - Google Patents

Abstract

A gate driving circuit is disclosed, including a low-voltage circuit and a high-voltage circuit. The low-voltage circuit outputs a first signal, and a voltage range of the first signal is between a ground voltage and an operating voltage. The high-voltage circuit receives the first signal and converts the first signal into a gate driving signal. The P-type MOSFETs of the high-voltage circuit and the low-voltage circuit include a shared N-type well, and a voltage of the shared N-type well is the operating voltage.

Description

Gate drive circuit and drive chip including it

The present invention relates to a gate driving circuit, in particular, the present invention relates to a gate driving circuit applied to a display driving chip.

In the design of the gate driver chip, due to the limitation of the semiconductor manufacturing process, the circuit of the gate driver must be completely cut into a high-voltage circuit area and a low-voltage circuit area. Since the transistor elements used in the two regions are different, a layout spacing needs to be set between the two regions, such as laying out an active region, N-type well, and deep N-type well, etc., to avoid the circuit in the two regions Mutual interference occurs, thereby affecting the operation of the driver chip.

However, setting the layout pitch is not only affected by the semiconductor manufacturing process, but also reduces the utilization efficiency of the chip area, thereby affecting the manufacturing cost of the driving chip.

In order to solve the above-mentioned conventional technical problems, an object of an embodiment of the present invention is to provide a gate driving circuit with a design structure that does not require layout spacing, so as to improve the utilization efficiency of the chip area.

Another object of the embodiments of the present invention is to provide a gate driver chip having the above-mentioned gate driver circuit with a design architecture that does not require a layout pitch, so as to reduce the manufacturing cost of the driver chip.

According to an embodiment of the present invention, a gate driving circuit is provided, including a low voltage circuit and a high voltage circuit. The low-voltage circuit outputs the first signal, and the voltage range of the first signal is between the ground voltage and the operating voltage. The high-voltage circuit receives the first signal and converts the first signal into a gate drive signal, wherein the P-type metal oxide semiconductor field effect transistor of the high-voltage circuit and the low-voltage circuit includes a common N-type well, and the voltage of the common N-type well is the operating voltage .

According to an embodiment of the present invention, a driving chip is provided, including the above-mentioned gate driving circuit.

Compared with the prior art, in the gate drive circuit of the embodiment of the present invention, the P-type metal-oxide-semiconductor field-effect transistors of the low-voltage circuit and the high-voltage circuit can share the N-type well without setting the layout pitch at the low-voltage circuit. The boundary area of the circuit and the high-voltage circuit makes the use efficiency of the chip area improved. In addition, using the driving chip with the design structure of the above-mentioned gate driving circuit can reduce the area of the chip and further reduce the manufacturing cost of the chip.

In the accompanying drawings, the dimensions of various layers, films, panels, regions, etc., may not be drawn to scale for clarity. Throughout the specification, the same reference numerals refer to the same elements. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connection. Moreover, "electrically connected" or "coupled" means that other elements exist between two elements.

Referring to FIG. 1 , it is a schematic diagram of a gate driving circuit according to an embodiment of the present invention. As shown in the figure, the gate driving circuit 10 of the embodiment of the present invention includes a low voltage circuit 100 and a high voltage circuit 200 . The low voltage circuit 100 outputs the first signal 121 whose voltage range is between the ground voltage GND and the operating voltage VDD through the received signal through components inside the low voltage circuit 100 .

The high voltage circuit 200 converts the received first signal 121 into a gate driving signal 221 through components inside the high voltage circuit 200 . Specifically, the gate driving circuit 10 of the embodiment of the present invention can be applied to a display panel, such as a liquid crystal display, or a light-emitting diode display, to control on and off of transistor elements on the display panel.

According to the embodiment shown in FIG. 1 , the low voltage circuit 100 may be implemented by a circuit including a bidirectional shift register 110 and an output controller 120 . Specifically, the above-mentioned bidirectional shift register 110 controls the signals input to the low-voltage circuit 100 through the enable signal STV and the clock signal CLK, such as performing serial or parallel processing on the input signals. The aforementioned output controller 120 controls the low voltage circuit 100 to output the first signal 121 through the enable signal OE.

According to the embodiment shown in FIG. 1 , the high voltage circuit 200 may be implemented by a circuit including a level converter 210 and an output buffer 220 . Specifically, the level converter 210 converts the voltage range of the first signal 121 received by the high-voltage circuit 200 in stages, from the voltage range between the ground voltage GND to the operating voltage VDD, and converts it into a voltage range in two stages. Between the low driving voltage VGL and the high driving voltage VGH. The output buffer 220 can control the on and off of the transistor elements on the display panel, and transmit the signal of the gate driving circuit 10 to the display panel for driving.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted to have meanings consistent with their meanings in the context of the relevant art and the present invention, and will not be interpreted as idealized or excessive formal meaning, unless expressly so defined herein.

For example, the level converter 210 may include a first-level conversion circuit 211 and a second-level conversion circuit 212. The first-level conversion circuit 211 converts the voltage range of the received first signal 121 from the ground voltage GND to the operating voltage Between VDD, first convert the voltage range from the low driving voltage VGL to the operating voltage VDD, and then convert the voltage range from the low driving voltage VGL to the operating voltage VDD through the second stage conversion circuit 212, and convert the voltage range into the low voltage range. between the driving voltage VGL and the high driving voltage VGH.

It should be understood that the above voltage range conversion method is only described as an embodiment, not as a limitation; the level converter 210 can be properly adjusted according to the actual needs of circuit design. The first stage conversion circuit 211 and the second stage conversion circuit 212 included in the level converter 210 of the above embodiment will be further described below.

It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or or parts thereof shall not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element," "component," "region," "layer" or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

As shown in FIG. 2 , the first stage conversion circuit 211 of the level converter 210 may include a first P-type metal oxide half field effect transistor MP1, a second P type metal oxide half field effect transistor MP2, a first N type metal oxide half field effect transistor A half field effect transistor MN1, and a second N-type metal oxide half field effect transistor MN2.

The first P-type MOSFET MP1 has a first drain terminal, a first base terminal, a first gate terminal, and a first source terminal. The first source terminal is connected to the first base terminal, and the first gate terminal, the first source terminal and the first base terminal receive the operating voltage VDD.

The second P-type MOSFET MP2 has a second drain terminal, a second base terminal, a second gate terminal, and a second source terminal. The second source terminal is connected to the second base terminal, and the second gate terminal, the second source terminal and the second base terminal receive the operating voltage VDD.

The first N-type MOSFET MN1 has a third drain terminal, a third base terminal, a third gate terminal, and a third source terminal. The third source terminal is connected to the third base terminal and receives the low driving voltage VGL, the third drain terminal is connected to the first drain terminal of the first P-type metal oxide semiconductor field effect transistor MP1, and the third drain terminal and the first drain terminal are There is a first node A between them.

The second N-type MOSFET MN2 has a fourth drain terminal, a fourth base terminal, a fourth gate terminal, and a fourth source terminal. The fourth source terminal is connected to the fourth base terminal and receives the low driving voltage VGL, the fourth drain terminal is connected to the second drain terminal of the second P-type metal oxide semiconductor field effect transistor MP2, and the fourth drain terminal and the second drain terminal are There is a second node B between them. The terminal of the fourth gate is connected to the first node A, the terminal of the third gate is connected to the second node B, and the signal of the second node B is the second signal.

Through the above circuit structure, it can be understood that when the low-voltage circuit 100 is input to the high-voltage circuit 200, the voltage range is between the ground voltage GND and the operating voltage VDD, and the first-stage conversion circuit 211 of the level conversion circuit 210 in the high-voltage circuit 200 passes through In switching, the voltage signal at the second node B, that is, the voltage range of the second signal has been switched between the low driving voltage VGL and the operating voltage VDD.

Regarding the embodiment of the second-level conversion circuit 212, further detailed description is given here. As shown in FIG. An effect transistor MP4, a third N-type metal oxide half field effect transistor MN3, and a fourth N type metal oxide half field effect transistor MN4.

The third P-type MOSFET MP3 has a fifth drain terminal, a fifth base terminal, a fifth gate terminal and a fifth source terminal. The fifth source terminal is connected to the fifth base terminal and receives the high driving voltage VGH.

The fourth P-type MOSFET MP4 has a sixth drain terminal, a sixth base terminal, a sixth gate terminal, and a sixth source terminal. The sixth source terminal is connected to the sixth base terminal and receives the high driving voltage VGH.

The third N-type MOSFET MN3 has a seventh drain terminal, a seventh base terminal, a seventh gate terminal, and a seventh source terminal. The seventh gate terminal receives the second signal, the seventh source terminal is connected to the seventh base terminal, and receives the low driving voltage VGL. The seventh drain terminal is connected to the fifth drain terminal of the third P-type metal oxide semiconductor field effect transistor MP3, and there is a third node C between the seventh drain terminal and the fifth drain terminal, and the third node C is connected to the sixth gate terminal .

The fourth N-type MOSFET MN4 has an eighth drain terminal, an eighth base terminal, an eighth gate terminal, and an eighth source terminal. The eighth gate terminal is connected to the first-stage conversion circuit 211, between the third drain terminal of the first N-type metal oxide half-field effect transistor MN1 and the first drain end of the first P-type metal oxide half-field effect transistor MP1 The first node A.

The eighth source terminal is connected to the eighth base terminal and receives the low driving voltage VGL. The eighth drain terminal is connected to the sixth drain terminal of the fourth P-type MOSFET MP4, and there is a fourth node D between the eighth drain terminal and the sixth drain terminal. The fourth node D is connected to the fifth gate terminal of the third P-type MOSFET MP3, and the signal of the fourth node D is the gate driving signal 221 .

Through the above description, with the circuit structure of the second-level conversion circuit 212, the signal of the second node B of the first-level conversion circuit 211, that is, the second signal, can be further converted into a voltage ranging from the low driving voltage VGL to the high driving voltage. Gate driving signal 221 of voltage VGH. Moreover, the signal at the fourth node D in FIG. 2 is the input signal of the output buffer 220, and the output signal of the output buffer 220 is the gate drive signal 221, which can be used as the output signal OUT of the entire gate drive circuit 10, and is applied To turn on and turn off the transistor elements of the above-mentioned display panel.

It should be understood that the above circuit architectures of the first-stage conversion circuit 211 and the second-stage conversion circuit 212 are only described as embodiments, and are not intended to be limiting. The actual circuit configurations of the first-stage conversion circuit 211 and the second-stage conversion circuit 212 can be properly adjusted according to design requirements.

According to an embodiment of the present invention, the low driving voltage VGL in the first conversion circuit 211 can be set to be a negative voltage relative to the ground voltage GND, and first expand the voltage range of the signal input to the high voltage circuit 200 to the operating voltage The range from VDD to the low driving voltage VGL, but the value of the low driving voltage VGL is described only as an embodiment, not as a limitation, and can be properly adjusted according to design requirements.

In the following, an exemplary circuit layout diagram will be used to describe in detail the implementation manner in which the structure of the above-mentioned gate driving circuit 10 can improve the usage efficiency of the chip area.

Exemplary embodiments are described herein with reference to cross section illustrations that are schematic illustrations of idealized embodiments. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances are to be expected. Thus, embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region shown or described as flat, may, typically, have rough and/or non-linear features. Additionally, acute corners shown may be rounded. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.

Referring to FIG. 3 , it is a top view layout diagram of a common N-type well of a gate driving circuit according to an embodiment of the present invention. As shown in the figure, the area surrounded by the dotted rectangular line in the area of the low-voltage circuit 100 represents the low-voltage P-type metal oxide semiconductor field-effect transistor LVPMOS, and the area enclosed by the dotted rectangular line in the area of the high-voltage circuit 200 represents the high-voltage P-type metal oxide half-field Effective transistor HVPMOS. In the above-mentioned 2nd figure, the transistors contained in the first-stage conversion circuit 211 and the second-stage conversion circuit 212 of the level conversion circuit 210, that is, the first P-type metal oxide half-field-effect transistor MP1 to the fourth P-type metal oxide The half field effect transistor MP4 can be implemented by taking the high voltage P-type metal oxide half field effect transistor HVPMOS in FIG. 3 as an example.

Additionally, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe one element's relationship to another element as shown in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "below" can encompass both an orientation of "below" and "upper," depending on the particular orientation of the drawing. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "under" can encompass both an orientation of above and below.

It should be understood that, for the sake of illustration, the top view layout diagram of the high-voltage P-type metal oxide semiconductor field effect transistor HVPMOS in FIG. 3 omits part of the structure. In the area enclosed by the dotted line of the rectangle in the figure, the area enclosed by the solid line of the rectangle can represent the active area AA, which is used to define the first P-type metal oxide half field effect transistor MP1 to the fourth P type metal oxide half field effect transistor MP4. sink and source terminals. In the area enclosed by the dotted line of the rectangle in the figure, the area enclosed by the solid line of the rectangle filled with oblique lines can define the first P-type metal oxide half field effect transistor MP1 to the fourth P type metal oxide half field effect transistor MP4. The gate terminal G, the relative position of the gate terminal G and the active area AA may be that the gate terminal overlaps the active area AA, but it is not limited thereto.

In addition, the base terminals of the first P-type metal oxide half field effect transistor MP1 to the fourth P type metal oxide half field effect transistor MP4 can be implemented by setting the active area AA in other areas within the dotted line of the rectangle. The N-type well of the oxygen-semiconductor field-effect transistor usually has a larger range, and will surround the drain terminal, source terminal, and base terminal of the P-type metal-oxide-semiconductor field-effect transistor, such as the common N-type well NW_C in Figure 3.

In Figure 2, the respective source terminals and base terminals of the first P-type metal oxide half field effect transistor MP1 to the fourth P type metal oxide half field effect transistor MP4 are connected, and their layout in Figure 3, for example In other words, a contact hole can be provided on the active area AA corresponding to the source terminal and the base terminal, and it can be implemented by connecting metal wires to each other, but for the sake of illustration, the setting of the base terminal and the connection with the source terminal Omitted and not shown.

With the above description and FIG. 2 and FIG. 3, it can be understood that the circuit structure of the first P-type metal oxide half field effect transistor MP1 to the fourth P type metal oxide half field effect transistor MP4 in the high voltage circuit 200 is because the source terminal is connected to the The base terminals are connected, and the voltage is the operating voltage VDD, so the base terminals of the first P-type metal oxide half field effect transistor MP1 to the fourth P type metal oxide half field effect transistor MP4 of the high voltage circuit 200 are connected to the adjacent low voltage circuit The base terminals of the P-type transistors in 100 can be connected by the common N-type well NW_C, and the components in the low-voltage circuit 100 will not be damaged by a large voltage signal passing through.

Next, refer to FIG. 4 , which is a top view layout schematic diagram of the high-voltage circuit and the low-voltage circuit of a conventional gate drive circuit. As shown in the figure, if the P-type transistor in the high-voltage circuit 200 does not have the circuit structure shown in FIG. The N-type well NW_H must be separated from the low-voltage N-type well NW_L in the low-voltage circuit 100 through the spacer S to prevent the high-voltage N-type well NW_H of the high-voltage circuit 200 from transmitting large-voltage signals to the low-voltage circuit during operation. The components in 100 are damaged, which requires a larger chip area, resulting in a lower efficiency of chip area usage.

As used herein, "about," "approximately," or "substantially" includes stated values and averages within acceptable deviations from a particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the relative A specific amount of measurement-related error (ie, a limitation of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Furthermore, the terms "about", "approximately" or "substantially" used herein can choose a more acceptable deviation range or standard deviation according to optical properties, etching properties or other properties, and it is not necessary to use one standard deviation to apply to all properties .

According to an embodiment of the present invention, in the high-voltage circuit 200, there is a P-type transistor that shares an N-type well NW_C, and in the low-voltage circuit 100, there is a P-type transistor that shares an N-type well NW_C. In design, for example, consider its performance and It is better to use different components for the voltage it can withstand, such as using a transistor with a thinner gate oxide layer and a lower gate breakdown voltage in the low-voltage circuit 100, and using a gate transistor in the high-voltage circuit 200. A transistor with a thicker oxide layer and a higher gate breakdown voltage.

It should be understood that the various areas in Figure 3 and Figure 4 are not drawn in actual scale for the convenience of description, for example, the P-type wells and N-type wells below Figure 3 and Figure 4, usually their dimensions will be larger than transistors. In addition, in the low-voltage circuit 100, it usually operates at a lower voltage, and its size is smaller than that of the transistor in the high-voltage circuit 200. Considering the voltage difference between the high-voltage circuit 200 and the low-voltage circuit 100 in actual operation, the width of the spacer S Possibly larger than the transistor elements in the low voltage circuit 100 .

Therefore, adopting the level switching circuit 210 with the circuit structure shown in FIG. 2 does not need to set the spacer S as shown in FIG. 4 , reducing the waste of chip area and improving the utilization efficiency of the chip area. However, the above description is only used as an exemplary embodiment, and not as a limitation, as long as the elements in the high-voltage circuit 200 in the gate drive circuit 10 can be properly designed so that the N-type well of the P-type transistor can be used The voltage at this time is the same as the voltage of the N-well of the P-type transistor in the low-voltage circuit 100, both of which can achieve the effect of not needing to set the spacer S as shown in FIG. 4 .

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include plural forms including "at least one" unless the content clearly dictates otherwise. "Or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It should also be understood that when used in this specification, the terms "comprising" and/or "comprising" designate the stated features, regions, integers, steps, operations, the presence of elements and/or parts, but do not exclude one or more Existence or addition of other features, regions as a whole, steps, operations, elements, parts and/or combinations thereof.

Next, refer to FIG. 5 , which is a schematic diagram of a driving chip including a gate driving circuit according to an embodiment of the present invention. As shown in the figure, the above-mentioned gate driving circuit 10 can be applied to the driving chip 20 of the display panel, and the chip area occupied by the driving chip 20 is minimized by the circuit structure described above. In addition to the gate drive circuit 10 described above, the drive chip 20 can also effectively utilize the chip area saved by the gate drive circuit 10 for other circuits, for example, the source drive circuit required to drive the display panel is used And integrated into the driver chip 20 .

The present invention has been described by the above-mentioned related embodiments, but the above-mentioned embodiments are only examples for implementing the present invention. It must be pointed out that the disclosed embodiments do not limit the scope of the present invention. On the contrary, modifications and equivalent arrangements included in the spirit and scope of the patent claims are included in the scope of the present invention.

10: Gate drive circuit 100: low voltage circuit 110: bidirectional shift register 120: Output controller 121: The first signal CLK: clock signal GND: ground voltage OE: enable signal STV: start signal VDD: operating voltage VGL: low driving voltage VGH: high driving voltage 200: high voltage circuit 210: level converter 211: first stage conversion circuit 212: The second conversion circuit A: the first node B: second node C: the third node D: the fourth node MP1: The first P-type metal oxide half field effect transistor MP2: The second P-type metal oxide half field effect transistor MP3: The third P-type metal oxide half field effect transistor MP4: The fourth P-type metal oxide half field effect transistor MN1: The first N-type metal oxide half field effect transistor MN2: The second N-type metal oxide half field effect transistor MN3: The third N-type metal oxide half field effect transistor MN4: The fourth N-type metal oxide half field effect transistor OUT: output endpoint HVPMOS: High Voltage P-Type Metal Oxide Half Field Effect Transistor LVPMOS: Low Voltage P-Type Metal Oxide Half Field Effect Transistor AA: active area G: gate area NW_C: shared N-type well NW_L: Low pressure N-type well NW_H: High pressure N-type well NW:N type well PW: P type well S: spacer 220: output buffer 221: Gate drive signal 20: Driver chip

In order to make the above and other purposes, features, advantages and embodiments of the present invention more clearly understood, the accompanying drawings are described as follows:

FIG. 1 is a schematic diagram of a gate driving circuit according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a circuit structure of a level converter according to an embodiment of the present invention.

FIG. 3 is a top view layout diagram of a shared N-well of a gate driving circuit according to an embodiment of the present invention.

FIG. 4 is a top view layout schematic diagram of a high voltage circuit and a low voltage circuit of a conventional gate driving circuit.

FIG. 5 is a schematic diagram of a driving chip including a gate driving circuit according to an embodiment of the present invention.

10: Gate drive circuit

100: low voltage circuit

200: high voltage circuit

HVPMOS: High Voltage P-Type Metal Oxide Half Field Effect Transistor

LVPMOS: Low Voltage P-Type Metal Oxide Half Field Effect Transistor

AA: active area

G: gate area

NW_C: shared N-type well

NW:N type well

PW: P type well

Claims (12)

A gate drive circuit, comprising: a low-voltage circuit that outputs a first signal, and the voltage range of the first signal is between a ground voltage and an operating voltage; and a high-voltage circuit that receives the first signal, and The first signal is converted into a gate driving signal, wherein the P-type MOSFETs of the high-voltage circuit and the low-voltage circuit include a common N-type well, and the voltage of the common N-type well is the operating voltage. The gate drive circuit according to claim 1, wherein the low-voltage circuit includes a bidirectional shift register and an output controller. The gate drive circuit according to claim 1, wherein the high voltage circuit includes a level converter and an output buffer. The gate driving circuit as claimed in claim 3, wherein the level converter converts the voltage range of the first signal from the ground voltage to the operating voltage into a low driving voltage to a high driving voltage. The gate drive circuit as described in claim 4, wherein the level converter further includes: a first-stage conversion circuit for converting the voltage range of the first signal from the ground voltage to the operating voltage into the low drive voltage to the operating voltage to generate a second signal; and a second stage conversion circuit for converting the voltage range of the second signal from the low driving voltage to the operating voltage to the low driving voltage to the high driving voltage , to generate the gate drive signal. The gate drive circuit as described in claim 5, wherein the first-stage conversion circuit includes: a first P-type metal-oxide-semiconductor field-effect transistor, having a first drain terminal, a first base terminal, a first A gate terminal and a first source terminal, wherein the first source terminal is connected to the first base terminal, and the first gate terminal, the first source terminal and the first base terminal receive the operating voltage; a second P A metal oxide half field effect transistor has a second drain terminal, a second base terminal, a second gate terminal and a second source terminal, wherein the second source terminal is connected to the second base terminal, and the second The gate terminal, the second drain terminal and the second base terminal receive the operating voltage; a first N-type metal oxide semiconductor field effect transistor has a third drain terminal, a third base terminal, a third gate terminal and A third source terminal, wherein the third source terminal is connected to the third base terminal, and receives the low driving voltage, wherein the third drain terminal is connected to the first drain terminal, and the third drain terminal and the first drain terminal There is a first node between the extremes; and a second N-type metal oxide semi-field effect transistor, which has a fourth drain terminal, a fourth base terminal, a fourth gate terminal and a fourth source terminal, wherein the first The four source terminals are connected to the fourth base terminal and receive the low driving voltage, wherein the fourth drain terminal is connected to the second drain terminal, and there is a second node between the fourth drain terminal and the second drain terminal, Wherein the terminal of the fourth gate is connected to the first node, the terminal of the third gate is connected to the second node, and the signal of the second node is the second signal. The gate drive circuit as described in Claim 6, wherein the second-stage conversion circuit includes: a third P-type metal-oxide-semiconductor field-effect transistor, having a fifth drain terminal, a fifth base terminal, and a fifth gate terminal and a fifth source terminal, wherein the fifth source terminal is connected to the fifth base terminal and receives the high driving voltage; a fourth P-type metal-oxide-semiconductor field-effect transistor has a sixth drain terminal, a sixth a base terminal, a sixth gate terminal and a sixth source terminal, wherein the sixth source terminal is connected to the sixth base terminal and receives the high driving voltage; a third N-type metal oxide semiconductor field effect transistor has a first Seven extremes, one seventh base, one first Seven gate terminals and a seventh source terminal, wherein the seventh gate terminal receives the second signal, wherein the seventh source terminal is connected to the seventh base terminal, and receives the low driving voltage, wherein the seventh drain terminal is connected to the The fifth drain terminal, and there is a third node between the seventh drain terminal and the fifth drain terminal, and the third node is connected to the sixth gate terminal; and a fourth N-type metal-oxide-semiconductor field-effect transistor with an eighth drain terminal, an eighth base terminal, an eighth gate terminal and an eighth source terminal, wherein the eighth gate terminal is connected to the first node, wherein the eighth source terminal is connected to the eighth base terminal, and receive the low driving voltage, wherein the eighth drain terminal is connected to the sixth drain terminal, and there is a fourth node between the eighth drain terminal and the sixth drain terminal, wherein the fourth node is connected to the fifth gate extreme, and the signal of the fourth node is the gate driving signal. The gate driving circuit as claimed in claim 4, wherein the low driving voltage is a negative voltage. The gate drive circuit as described in Claim 2, wherein the bidirectional shift register receives a clock signal and an activation signal. The gate drive circuit as described in claim 2, wherein the output controller receives an enable signal to output the first signal. The gate drive circuit as described in Claim 1, wherein the P-type metal oxide semiconductor field-effect transistor of the low-voltage circuit comprising the common N-type well, and the P-type gold of the high-voltage circuit comprising the common N-type well Oxygen half field effect transistors have different gate breakdown voltages. A driving chip, comprising the gate driving circuit according to any one of Claims 1 to 11.

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