TWI794913B - Display device - Google Patents

Abstract

According to an aspect of the present disclosure, a display device includes a display panel in which a plurality of pixels including a first sub pixel, a second sub pixel, a third sub pixel, and a fourth sub pixel each having a different color are disposed; a data driver configured to supply a data voltage to the plurality of pixels by using a plurality of data lines; and a gate driver configured to supply a gate signal to the plurality of pixels by using a plurality of gate lines, each of the plurality of data lines is divided into a plurality of sub data lines and each of the plurality of sub data lines is connected to a plurality of sub pixels having the same color, thereby minimizing data transition of a data voltage.

Description

Display device

The present invention relates to a display device, in particular to a display device capable of minimizing data transition.

Display devices that are screens of computers, televisions, or mobile devices include organic light-emitting displays (OLEDs) that are self-luminous devices and liquid crystal display devices (LCDs) that require individual light sources.

Among various display devices, an organic light emitting display device includes a display panel including a plurality of sub-pixels and a driver for driving the display panel. The driver includes a gate driver and a data driver. The gate driver is used to provide gate signals to the display panel, and the data driver is used to provide data voltage. When signals such as gate signals and data voltages are supplied to the sub-pixels of the OLED device, selected sub-pixels emit light to display images.

In addition, the data voltage applied to the sub-pixel is determined according to the connection relationship between the sub-pixel and the data line. That is, the data migration of the data voltage may frequently occur according to the connection relationship between the sub-pixels and the data lines.

In recent years, one horizontal period of high-speed driving of 120 Hz has become very short, so when data shift of the data voltage frequently occurs, there may be a problem that the data voltage cannot be sufficiently charged in one horizontal period. In addition, when the data migration of the data voltage occurs frequently, there is a problem of severe overheating of the data driver for supplying the data voltage.

The purpose of the present invention is to provide a display device that fully charges the data voltage in the sub-pixel within a horizontal period.

Another object to be achieved by the present invention is to provide a display device which minimizes heat generation of a data driver.

The purpose of the present disclosure is not limited to the above-mentioned purpose, and other purposes not mentioned above can be clearly understood by those skilled in the art through the following description.

In order to achieve the above object, according to an aspect of the present disclosure, a display device includes a display panel, in which a plurality of pixels are arranged, and the pixels include a first sub-pixel, a second sub-pixel, a first sub-pixel each having a different color. Three sub-pixels and a fourth sub-pixel; a data driver for providing a data voltage to the pixels by using a plurality of data lines; and a gate driver for providing a gate by using a plurality of gate lines voltage to the pixels, each of the data lines is divided into a plurality of sub-data lines, and each of the sub-data lines is connected to a plurality of sub-pixels with the same color, thereby minimizing data migration of the data voltage.

According to another aspect of the present disclosure, a display device includes: a display panel in which a plurality of sub-pixels of different colors are disposed; a data driver for providing a data voltage to the sub-pixels by using a plurality of data lines; and A gate driver for providing a gate voltage to the sub-pixels by using a plurality of gate lines, each of the data lines is divided into a plurality of sub-data lines, and each of the sub-data lines is connected to the Sub-pixels with the same color among those sub-pixels. The gate lines include a first gate line disposed on one side of the sub-pixels in a plurality of odd-numbered columns among the sub-pixels, a second gate line and a third gate line disposed on Between the sub-pixels arranged in the odd-numbered columns and the sub-pixels arranged in a plurality of even-numbered columns among the sub-pixels; and a fourth gate line arranged in the plurality of even-numbered columns On the other side of the sub-pixels, the sub-pixels arranged in a 12k-11th row to a 12k-6th row among the sub-pixels are arranged to be compared with the second gate line and the third gate The electrode line is closer to the first gate line and the fourth gate line, and the sub-pixels arranged in a 12k-5th row to a 12kth row among the sub-pixels are arranged to be compared with the first A gate line and the fourth gate line are closer to the second gate line and the third gate line. Therefore, even if the overlay of sub-pixels changes, the image can be consistent.

Additional details of the exemplary embodiments are included in the detailed description and drawings.

According to the present disclosure, the data voltage can be fully charged in one frame, so that the image quality can be improved.

According to the present disclosure, a data voltage is continuously maintained in a frame, so that the heating problem of the data driver for providing the data voltage can be solved.

In addition, according to the present disclosure, a load of the data driver and a load of the multiplexer (MUX) are reduced to drive the display device at high speed.

Furthermore, according to the present disclosure, it is possible to suppress the occurrence of vertical lines or horizontal lines due to overlapping changes.

Effects according to the present disclosure are not limited to those exemplified above, and more various effects are included in this specification.

The advantages and features of the present disclosure and a method of achieving the advantages and features will become apparent by referring to the exemplary embodiments described in detail below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed here, but will be implemented in various forms. The exemplary embodiments are provided only as examples so that those having ordinary knowledge in the art can fully understand the disclosure content and the scope of the present disclosure. Accordingly, the present disclosure is to be limited only by the scope of the appended claims.

The shapes, dimensions, proportions, angles, numbers, etc. shown in the drawings to describe the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Like reference symbols generally refer to like elements throughout the specification. Also, in the following description of the present disclosure, detailed explanations of known related arts may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "comprising", "having" and "consisting of" used herein are generally intended to allow for the addition of other components, unless these terms are used together with the term "only". Any reference to the singular may include the plural unless expressly stated otherwise.

Even if not expressly stated, components are to be construed as including the usual margin of error.

When terms such as "above", "above", "below", "next door" are used to describe the positional relationship between two parts, unless the word "immediately" or "directly" is used, there may be There are one or more sections.

When an element or layer is disposed "on" another element or layer, the other layer or element can be directly on the other element or interposed therebetween.

Although the terms 'first', 'second', etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component to be mentioned below may be the second component in the technical concept of the present disclosure.

Like reference symbols generally refer to like elements throughout the specification.

The size and thickness of each component shown in the drawings are for convenience of description, and the present disclosure is not limited to the size and thickness of the components shown.

The features of the various embodiments of the present invention can be partially or completely attached or combined with each other, and can be technically interlocked and operated in various ways, and the embodiments can be implemented independently or interrelated.

Transistors used in the display device of the present disclosure may be implemented by one or more of n-channel transistors (NMOS) and p-channel transistors (PMOS). The transistor may be realized by an oxide semiconductor transistor having an oxide semiconductor as an active layer or an LTPS transistor having a low temperature polysilicon (LTPS) as an active layer. A transistor may include at least a gate electrode, a source electrode and a drain electrode. Transistors can be realized by thin film transistors (TFTs) on the display panel. In a transistor, carriers flow from source to drain. In the case of n-channel transistors (NMOS), since the carriers are electrons, to allow electrons to flow from source to drain, the source voltage can be lower than the drain voltage. The current direction in the n-channel transistor NMOS flows from the drain to the source, and the source can be used as an output terminal. In the case of a p-channel transistor (PMOS), since the carriers are holes, in order for the holes to flow from the source to the drain, the source voltage is higher than the drain voltage. In the p-channel transistor PMOS, the holes flow from the source to the drain, so that the current flows from the source to the drain, and the drain is used as the output terminal. Therefore, the source and drain can be changed according to the applied voltage, so it should be noted that the source and drain of the transistor are not fixed. In this specification, it is assumed that the transistor is an n-channel transistor (NMOS), but not limited thereto, a p-channel transistor may be used and thus the circuit configuration may be changed.

The gate signal of a transistor used as a switching element swings between a gate-on voltage and a gate-off voltage. The gate turn-on voltage is set higher than the threshold voltage Vth of the transistor, and the gate turn-off voltage is set lower than the threshold voltage Vth of the transistor. The transistor turns on in response to a gate-on voltage and turns off in response to a gate-off voltage. In the case of NMOS, the gate turn-on voltage may be a gate high voltage VGH and the gate turn-off voltage may be a gate low voltage VGL. In the case of PMOS, the gate turn-on voltage may be the gate low voltage VGL, and the gate turn-off voltage may be the gate high voltage VGH.

Hereinafter, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure. Referring to FIG. 1 , a display device 100 includes a display panel 110 , a gate driver 120 , a data driver 130 and a timing controller 140 .

The display panel 110 is a panel for displaying images. The display panel 110 may include various circuits, wires and light emitting diodes disposed on a substrate. The display panel 110 is separated by a plurality of data lines DL and a plurality of gate lines GL crossed with each other and includes a plurality of pixels PX connected to the data lines DL and the gate lines GL. The display panel 110 includes a display area bounded by a plurality of pixels PX and a non-display area in which various signal lines or pads are formed. The display panel 110 may be implemented by the display panel 110 used in various display devices such as a liquid crystal display device, an organic light emitting display device, or an electrophoretic display device. Hereinafter, it will be described that the display panel 110 is a panel used in an organic light emitting display device, but is not limited thereto.

The timing controller 140 receives a timing signal, such as a vertical sync signal, a horizontal sync signal, a data enable signal or a dot clock, through a receiving circuit, such as an LVDS or TMDS interface connected to a host system. The timing controller 140 generates timing control signals based on the input timing signals to control the data driver 130 and the gate driver 120 .

The data driver 130 provides a data voltage DATA to the sub-pixels SP. The data driver 130 may include a plurality of source driving ICs (Integrated Circuits). The source driver ICs may be supplied with digital video data and source timing control signals from the timing controller 140 . The source driving ICs convert digital video data into gamma voltages in response to the source timing control signals to generate data voltages DATA and provide the data voltages DATA through the data lines DL of the display panel 110 . The source driver ICs may be connected to the data lines DL of the display panel 110 through a chip on glass (COG) process or a tape automated bonding (TAB) process. In addition, the source driver IC is formed on the display panel 110 or formed on a separate PCB substrate to be connected to the display panel 110 .

The gate driver 120 provides a gate signal to the sub-pixels SP. The gate driver 120 may include a level shifter and a shift register. The level shifter shifts the level of a clock signal input from the timing controller 140 at a transistor-transistor-logic (TTL) level, and then provides the clock signal for shifting scratchpad. The shift register may be formed in the non-display area of the display panel 110 in the form of a gate-in-panel (GIP), but is not limited thereto. The shift register can be configured in multiple stages to shift the gate signal to the output in response to the clock signal and the drive signal. The stages included in the shift register can sequentially output gate signals through a plurality of output terminals.

The display panel 110 may include a plurality of sub-pixels SP. The sub-pixels SP may be sub-pixels for emitting lights of different colors. For example, the sub-pixels SP may be a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel, but not limited thereto. These sub-pixels SP can configure a pixel PX. That is, the red sub-pixel, the green sub-pixel, the blue sub-pixel and the white sub-pixel configure one pixel PX and the display panel 110 may include a plurality of pixels PX.

The driving circuit for driving a sub-pixel SP will be described in more detail below in conjunction with FIG. 2 .

FIG. 2 is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure. In FIG. 2 , a circuit diagram of one sub-pixel SP among the sub-pixels SP of the display device 100 is shown.

Referring to FIG. 2 , the sub-pixel SP may include a switching transistor SWT, a sensing transistor SET, a driving transistor DT, a storage capacitor SC and a light emitting diode 150 .

The light emitting diode 150 may include an anode, an organic layer and a cathode. The organic layer may include various organic layers such as a hole incident layer, a hole transport layer, an organic light emitting layer, an electron transport layer, and an electron incident layer. The anode of the light emitting diode 150 can be connected to the output terminal of the driving transistor DT and a low potential voltage VSS is applied to the cathode. Although in FIG. 2 , it is described that the light emitting diode 150 is an organic light emitting diode 150 , the present disclosure is not limited thereto, and as the light emitting diode 150 , an inorganic light emitting diode (ie, LED) can also be used.

Referring to FIG. 2 , the switching transistor SWT is a transistor for transmitting the data voltage DATA to a first node N1 corresponding to the gate electrode of the driving transistor DT. The switching transistor SWT may include a drain electrode connected to the data line DL, a gate electrode connected to the gate line GL, and a source electrode connected to the gate electrode of the driving transistor DT. The switching transistor SWT is turned on by the gate voltage GATE applied from the gate line GL to transmit the data voltage DATA supplied from the data line DL to the first node N1 corresponding to the gate electrode of the driving transistor DT.

Referring to FIG. 2 , the driving transistor DT is a transistor that provides a driving current to the light emitting diode 150 to drive the light emitting diode 150 . The driving transistor DT may include a gate electrode corresponding to the first node N1, a source electrode corresponding to a second node N2 and an output terminal, and a drain electrode corresponding to a third node N3 and an input terminal. The gate electrode of the driving transistor DT can be connected to the switching transistor SWT, the drain electrode can be applied with a high potential voltage VDD by using the high potential voltage line VDDL, and the source electrode can be connected to the anode of the LED 150 .

Referring to FIG. 2, a storage capacitor SC is a capacitor to maintain one frame corresponding to the data voltage DATA. One electrode of the storage capacitor SC may be connected to the first node N1 and the other electrode may be connected to the second node N2.

Meanwhile, in the case of the display device 100 , as the driving time of each sub-pixel SP increases, circuit elements such as the driving transistor DT may degrade. Accordingly, characteristic values of unique circuit elements (eg drive transistor DT) may be changed. Herein, the unique characteristic value of the circuit element may include a threshold voltage Vth of the driving transistor DT or a mobility (mobility) α of the driving transistor DT. Changes in characteristic values of circuit elements may result in changes in brightness of the corresponding sub-pixel SP. According to this, the change of the characteristic value of the circuit element can be regarded as the same concept as the change of the luminance of the sub-pixel SP.

Also, the degree of change in characteristic values between circuit elements of each sub-pixel SP may vary depending on the degradation of each circuit element. Such a difference in the degree of change of the characteristic value between such circuit elements may cause luminance deviation among the sub-pixels SP. Accordingly, the characteristic value deviation between circuit elements can be regarded as the same concept as the luminance deviation between sub-pixels SP. Changes in the eigenvalues of circuit components (i.e., brightness variations of sub-pixel SPs) and deviations in eigenvalues between circuit components (i.e., brightness deviations between sub-pixels SPs) may lead to a reduction in the accuracy of brightness performance of sub-pixel SPs or large screens. question.

Therefore, the sub-pixel SP of the display device 100 according to an exemplary embodiment of the present disclosure may provide a sensing function of sensing the characteristic value of the sub-pixel SP, and a compensation function of compensating the characteristic value of the sub-pixel SP using the sensing result. .

Therefore, as shown in FIG. 2, in addition to the switching transistor SWT, the driving transistor DT, the storage capacitor SC and the light emitting diode 150, the sub-pixel SP may further include a sensing transistor SET to effectively control the driving The voltage state of the source electrode of transistor DT.

Referring to FIG. 2, the sensing transistor SET is connected between the source electrode of the driving transistor DT and the reference voltage line RVL providing the reference voltage Vref, and the gate electrode is connected to the gate line GL. Therefore, the sensing transistor SET is turned on by the sensing signal SENSE applied through the gate line GL to apply the reference voltage Vref provided through the reference voltage line RVL to the source electrode of the driving transistor DT. In addition, the sensing transistor SET can be used as one of the voltage sensing paths of the source electrode of the driving transistor DT.

Referring to FIG. 2 , the switching transistor SWT and the sensing transistor SET of the sub-pixel SP may share a gate line GL. That is, the switching transistor SWT and the sensing transistor SET are connected to the same gate line GL to be applied with the same gate signal. However, for ease of description, the voltage applied to the gate electrode of the switching transistor SWT is referred to as the gate voltage GATE, and the voltage applied to the gate electrode of the sensing transistor SET is referred to as the sensing signal SENSE. However, the gate voltage GATE and the sensing signal SENSE applied to one sub-pixel SP are the same signals transmitted from the same gate line GL.

However, the present disclosure is not limited thereto, so only the switching transistor SWT can be connected to the gate line GL, and the sensing transistor SET can be connected to respective sensing lines. Therefore, the gate voltage GATE can be applied to the switching transistor SWT through the gate line GL and the sensing signal SENSE can be applied to the sensing transistor SET through the sensing line.

Accordingly, the reference voltage Vref is applied to the source electrode of the driving transistor DT by using the sensing transistor SET. In addition, a voltage for sensing the threshold voltage Vth of the driving transistor DT or the mobility α of the driving transistor DT is detected by the reference voltage line RVL. In addition, the data driver 120 can compensate the data voltage DATA according to the variation of the threshold voltage Vth of the driving transistor DT or the mobility α of the driving transistor DT.

Hereinafter, the positional relationship of these sub-pixels will be described with reference to FIG. 3 .

FIG. 3 is a block diagram for explaining a positional relationship of sub-pixels of a display device according to an exemplary embodiment of the present disclosure.

2矩陣的四個像素PX被繪示在顯示區域中，設置為2

2矩陣的四個像素PX的位置關係是重複的。此外，電晶體設置在子像素R、G、B、W及資料線之間的電晶體是指參考圖2描述的開關電晶體SWT。In Figure 3, for ease of description, only 2

2 matrix of four pixels PX is drawn in the display area, set to 2

The positional relationship of the four pixels PX of the 2 matrix is repeated. In addition, the transistor disposed between the sub-pixels R, G, B, W and the data line refers to the switching transistor SWT described with reference to FIG. 2 .

Referring to FIG. 3 , one pixel PX includes four sub-pixels R, G, B, W. For example, as shown in FIG. 3 , the pixel PX may include a first sub-pixel R, a second sub-pixel W, a third sub-pixel B, and a fourth sub-pixel G. In addition, the first sub-pixel R is a red sub-pixel, the second sub-pixel W is a white sub-pixel, the third sub-pixel B is a blue sub-pixel, and the fourth sub-pixel G is a green sub-pixel. However, the present disclosure is not limited thereto and the sub-pixels may be changed into various colors such as magenta, yellow, and cyan.

The sub-pixels R, G, B, W of the same color may be arranged in the same row (column). That is, a plurality of first sub-pixels R are arranged in the same row, a plurality of second sub-pixels W are arranged in the same row, a plurality of third sub-pixels B are arranged in the same row, and more The four fourth sub-pixels G are arranged in the same row.

More specifically, as shown in FIG. 3, the first sub-pixels R are arranged in an 8k-7th row and an 8k-third row, and the second sub-pixels W are arranged in an 8k-th row - 6 lines and an 8k - in the second line. In addition, the third sub-pixels B are arranged in an 8k-5th row and an 8k-first row, and the fourth sub-pixels G are arranged in an 8k-4th row and an 8k-th row. Herein, k refers to a natural number of 1 or greater.

That is, the first sub-pixel R, the second sub-pixel W, the third sub-pixel B, and the fourth sub-pixel G are sequentially repeated with respect to an odd row or an even row.

Multiple data lines DL1, DL2, DL3, DL4 can be divided into multiple sub-data lines SDL1-a, SDL1-b, SDL2-a, SDL2-b, SDL3-a, SDL3-b, SDL4-a, SDL4- b. Specifically, the first data line DL1 can be divided into multiple first sub-data lines SDL1-a and SDL1-b, and the second data line DL2 can be divided into multiple second sub-data lines SDL2-a and SDL2 -b. In addition, the third data line DL3 can be divided into a plurality of third sub-data lines SDL3-a and SDL3-b, and the fourth data line DL4 can be divided into a plurality of fourth sub-data lines SDL4-a and SDL4-b. .

As mentioned above, the first sub-data lines SDL1-a and SDL1-b may include a 1-a-th sub-data line SDL1-a and a 1-b-th sub-data line SDL1-b, and the second sub-data line SDL2- a and SD2L-b may include a 2-a-th sub-data line SDL2-a and a 2-b-th sub-data line SDL2-b. In addition, the third sub-data line SDL3-a and SDL3-b may include a 3-a-th sub-data line SDL3-a and a 3-b-th sub-data line SDL3-b, and the fourth sub-data line SDL4-a and SDL4-b may include a 4-a-th sub-data line SDL4-a and a 4-b-th sub-data line SDL4-b.

The first sub-data lines SDL1-a and SDL1-b are disposed adjacent to the first sub-pixels R to be connected to the first sub-pixels R.

Specifically, the 1-ath sub-data line SDL1-a is arranged between the first sub-pixels R arranged in the 8k-7th row and the second sub-pixels W arranged in the 8k-6th row , to be electrically connected to the first sub-pixels R arranged in the 8k-7th row. Specifically, the other one of the 1-bth sub-data lines SDL1-b is arranged on the first sub-pixels R arranged in the 8k-th row and the first sub-pixels R arranged in the 8k-2 row The second sub-pixels W are electrically connected to the first sub-pixels R arranged in the 8kth-third row.

The second sub-data lines SDL2-a and SDL2-b are disposed adjacent to the second sub-pixels W to be connected to the second sub-pixels W.

Specifically, the 2-ath sub-data line SDL2-a is arranged between the first sub-pixels R arranged in row 8k-7 and the second sub-pixels W arranged in row 8k-6 , so as to be electrically connected to the second sub-pixels W arranged in the 8k-6th row. Specifically, the other of the 2-bth sub-data lines SDL2-b is arranged on the first sub-pixels R arranged in the 8k-third row and the first sub-pixel R arranged in the 8k-second row between the second sub-pixels W to be electrically connected to the second sub-pixels W arranged in the 8k-second row.

The third sub-data lines SDL3-a and SDL3-b are disposed adjacent to the third sub-pixels B to be connected to the third sub-pixels B.

Specifically, the 3-ath sub-data line SDL3-a is arranged between the third sub-pixels B arranged in the 8k-5 row and the fourth sub-pixels G arranged in the 8k-4 row , so as to be electrically connected to the third sub-pixels B arranged in the 8k-5th row. The 3-b sub-data line SDL3-b is arranged between the third sub-pixels B arranged in the 8k-first row and the fourth sub-pixels G arranged in the 8k-row for electrical connection In the third sub-pixels B arranged in the 8k-first row.

The fourth sub-data lines SDL4-a and SDL4-b are disposed adjacent to the fourth sub-pixels G to be connected to the fourth sub-pixels G.

Specifically, the 4th-a-th sub-data line SDL4-a is arranged between the third sub-pixels B and the fourth sub-pixels G in the 8k-5th row to electrically connect in the fourth sub-pixels G arranged in the 8k-4 row. Specifically, the other of the 4-bth sub-data lines SDL4-b is arranged on the third sub-pixels B in the 8k-first row and the fourth sub-pixels in the 8k-th row The sub-pixels G are electrically connected to the fourth sub-pixels G arranged in the 8kth row.

The first data voltage DATA1, which is a red data voltage, may be applied to the first data line DL1, and the second data voltage DATA2, which is a white data voltage, may be applied to the second data line DL2. In addition, a third data voltage DATA3 which is a blue material voltage may be applied to the third data line DL3, and a fourth data voltage DATA4 which is a green material voltage may be applied to the fourth data line DL4.

Therefore, the first data voltage DATA1 which is a red data voltage can be applied to the first sub-data lines SDL1-a and SDL1-b, and the second data voltage DATA2 which is a white data voltage can be applied to the second sub-data lines SDL1-a and SDL1-b. Sub data lines SDL2-a and SDL2-b. In addition, the third data voltage DATA3 which is a blue data voltage may be applied to the third sub-data lines SDL3-a and SDL3-b, and the fourth data voltage DATA4 which is a green data voltage may be applied to the third sub-data lines SDL3-a and SDL3-b. Four sub data lines SDL4-a and SDL4-b.

Each of the gate lines GL1 to GL4 can be arranged on both sides of the sub-pixels R, G, B, W, and two gate lines GL2 and GL3 can be arranged on the sub-pixels R, G, B, Between W.

Specifically, referring to FIG. 3, the first gate line GL1 and the second gate line GL2 are arranged on both sides of the sub-pixels R, G, B, and W in odd columns, and the third gate line GL3 And the fourth gate line GL4 is arranged on both sides of the sub-pixels R, G, B, W in the even columns. Therefore, the second gate line GL2 and the third gate line GL3 can be arranged between the sub-pixels R, G, B, W in odd columns and the sub-pixels R, G, B, W in even columns. between.

Meanwhile, each of the pixels PX may be connected to the same gate lines GL1 to GL4 , and adjacent pixels PX among the pixels PX may be connected to different gate lines GL1 to GL4 .

Specifically, referring to FIG. 3 , the sub-pixels R, W, B, and G disposed in the 8k-7th row to the 8k-4th row of odd columns are connected to the first gate line GL1 . The sub-pixels R, W, B, and G disposed in the 8kth-3rd row to the 8kth row of odd columns are connected to the second gate line GL2 . The sub-pixels R, W, B, and G disposed in the 8k-7th row to the 8k-4th row of the even-numbered columns are connected to the third gate line GL3 . The sub-pixels R, W, B, and G disposed in the 8k-3rd row to the 8k-th row of even columns are connected to the fourth gate line GL4 .

Each of the reference voltage lines RVL may be disposed in one pixel PX, and each of the high potential voltage lines VDDL may be disposed between the adjacent pixels PX.

Specifically, the reference voltage lines RVL are arranged between the second subpixels W arranged in row 8k-6 and the third subpixels B arranged in row 8k-5, and arranged in Between the second sub-pixels W in the 8k-2rd row and the third sub-pixels B in the 8k-first row. However, the reference voltage lines RVL can also be arranged between other sub-pixels.

The high potential voltage lines VDDL may be arranged between the fourth sub-pixels G arranged in the 8k-4th row and the first sub-pixels R arranged in the 8k-third row, and arranged in the Outside the first sub-pixels R in row 8k-7 and outside the fourth sub-pixel G in row 8k. However, the high potential voltage lines VDDL can also be arranged between other sub-pixels.

Hereinafter, a monochrome freeze frame driving method and a vertical pattern screen driving method of the display device 100 according to an exemplary embodiment of the present disclosure will be described with reference to FIGS. 4 and 5 .

FIG. 4 is a timing diagram of a gate voltage and a data voltage when a display device according to an exemplary embodiment of the present disclosure realizes freezing in monochrome.

As shown in Figure 12->3 and 4, a first gate voltage GATE1 is output through the first gate line GL1, a second gate voltage GATE2 is output through the second gate line GL2, and a third The gate voltage GATE3 is output through the third gate line GL3 , and a fourth gate voltage GATE4 is output through the fourth gate line GL4 .

The first data voltage DATA1 is output through the first data line DL1, a second data voltage DATA2 is output through the second data line DL2, a third data voltage DATA3 is output through the third data line DL3, and a fourth data voltage is output through the third data line DL3. The data voltage DATA4 is output through the fourth data line DL4.

As shown in FIG. 4, during the first horizontal period H1, the first gate voltage GATE1 is a very high gate voltage, while the second gate voltage GATE2, the third gate voltage GATE3 and the fourth gate voltage GATE4 are Gate low voltage. In addition, during the first horizontal period H1, the first to fourth data voltages DATA1 to DATA4 may be at a predetermined level of data voltages to achieve a predetermined gray scale.

Accordingly, during the first horizontal period H1, the first sub-pixels R arranged in the 8k-7 row, the second sub-pixels W arranged in the 8k-6 row, and the second sub-pixel W arranged in the odd-numbered columns are connected to All transistors of the third sub-pixels B in row 8k-5 and the fourth sub-pixels G in row 8k-4 are turned on.

Therefore, during the first horizontal period H1, in the odd columns, the first data voltage DATA1 can be charged into the first sub-pixels R arranged in the 8k-7th row, and the second data voltage DATA2 can be charged in the set In the second sub-pixels W in row 8k-6. In addition, the third data voltage DATA3 can be charged into the third sub-pixels B arranged in row 8k-5, and the fourth data voltage DATA4 can be charged in the fourth sub-pixels arranged in row 8k-4 in G.

As shown in FIG. 4, during the second horizontal period H2, the second gate voltage GATE2 is a high gate voltage, while the first gate voltage GATE1, the third gate voltage GATE3 and the fourth gate voltage GATE4 are gate voltages. low voltage. In addition, also during the second horizontal period H2, the first to fourth data voltages DATA1 to DATA4 may be at a predetermined level of data voltages to achieve a predetermined gray scale.

Accordingly, during the second horizontal period H2, the first sub-pixels R arranged in the 8k-third row in the odd-numbered columns, the second sub-pixels W arranged in the 8k-second row, All the switching transistors of the third sub-pixels B arranged in the 8k-first row and the fourth sub-pixels G arranged in the 8k row are turned on.

Therefore, during the second horizontal period H2, in the odd columns, the first data voltage DATA1 can be charged in the first sub-pixels R arranged in the 8k-th row, and the second data voltage DATA2 can be charged in the set in the second sub-pixels W in the 8k-second row. In addition, the third data voltage DATA3 can be charged in the third sub-pixels B arranged in the 8k-first row, and the fourth data voltage DATA4 can be charged in the fourth sub-pixels G arranged in the 8k row middle.

As shown in FIG. 4, during the third horizontal period H3, the third gate voltage GATE3 is a high gate voltage, while the first gate voltage GATE1, the second gate voltage GATE2 and the fourth gate voltage GATE4 are gate voltages. low voltage. In addition, also during the third horizontal period H3, the first to fourth data voltages DATA1 to DATA4 may be at a predetermined level of data voltages to achieve a predetermined gray scale.

Accordingly, during the third horizontal period H3, the first sub-pixels R arranged in the 8k-7 row, the second sub-pixels W arranged in the 8k-6 row, and the second sub-pixel W arranged in the even-numbered columns are connected to All the switching transistors of the third sub-pixels B in row 8k-5 and the fourth sub-pixels G in row 8k-4 are turned on.

Therefore, during the third horizontal period H3, in the even columns, the first data voltage DATA1 can be charged into the first sub-pixels R arranged in the 8k-7th row, and the second data voltage DATA2 can be charged in the first sub-pixels R arranged in the 8k-7th row. The second sub-pixels W in row 8k-6. In addition, the third data voltage DATA3 can be charged into the third sub-pixels B arranged in the 8k-5 row, and the fourth data voltage DATA4 can be charged into the fourth sub-pixels G arranged in the 8k-4 row .

As shown in FIG. 4, in the fourth horizontal period H4, the fourth gate voltage GATE4 is a very high gate voltage, and the first gate voltage GATE1, the second gate voltage GATE2 and the third gate voltage GATE3 are gate voltages. low voltage. In addition, also during the fourth horizontal period H4, the first to fourth data voltages DATA1 to DATA4 may be at a predetermined level of data voltages to achieve a predetermined gray scale.

Accordingly, during the fourth horizontal period H4, the first sub-pixels R arranged in the 8k-third row in the even columns, the second sub-pixels W arranged in the 8k-second row, All the switching transistors of the third sub-pixels B arranged in the 8k-first row and the fourth sub-pixels G arranged in the 8k row are turned on.

Therefore, during the fourth horizontal period H4, in the even columns, the first data voltage DATA1 can be charged in the first sub-pixels R arranged in the 8k-th row, and the second data voltage DATA2 can be charged in the set in the second sub-pixels W in the 8k-second row. In addition, the third data voltage DATA3 can be charged in the third sub-pixels B arranged in the 8k-first row, and the fourth data voltage DATA4 can be charged in the fourth sub-pixels G arranged in the 8k row middle.

As described above, when the display device 100 according to an exemplary embodiment of the present disclosure implements monochrome freeze, during the first to fourth horizontal periods H1 to H4, that is, during one frame period, the first to fourth data voltages DATA1 to DATA4 can be the same level. Accordingly, during one frame period, the data transition of the first to fourth data voltages DATA1 to DATA4 does not occur.

FIG. 5 is a timing diagram of gate voltages and data voltages when a display device according to an exemplary embodiment of the present disclosure implements a vertical pattern screen.

As shown in FIG. 5, during the first horizontal period H1, the first gate voltage GATE1 is a gate high voltage, while the second gate voltage GATE2, the third gate voltage GATE3 and the fourth gate voltage GATE4 are gate voltages. low voltage. In addition, during the first horizontal period H1, the first to fourth data voltages DATA1 to DATA4 may be at a predetermined level of data voltages to achieve a predetermined gray scale.

Accordingly, during the first horizontal period H1, the first sub-pixels R arranged in the 8k-7 row, the second sub-pixels W arranged in the 8k-6 row, and the second sub-pixel W arranged in the odd-numbered columns are connected to All the switching transistors of the third sub-pixels B in row 8k-5 and the fourth sub-pixels G in row 8k-4 are turned on.

Therefore, during the first horizontal period H1, in the odd columns, the first data voltage DATA1 can be charged into the first sub-pixels R arranged in the 8k-7th row, and the second data voltage DATA2 can be charged in the first sub-pixels R arranged in the 8k-7th row. The second sub-pixels W in row 8k-6. In addition, the third data voltage DATA3 is charged into the third sub-pixels B arranged in row 8k-5, and the fourth data voltage DATA4 can be charged into the fourth sub-pixels G arranged in row 8k-4 .

As shown in FIG. 5 , during the second horizontal period H2 , all of the first gate voltage GATE1 , the second gate voltage GATE2 , the third gate voltage GATE3 and the fourth gate voltage GATE4 are gate low voltages. In addition, also during the second horizontal period H2, the first to fourth data voltages DATA1 to DATA4 may be at a predetermined level of data voltages to achieve a predetermined gray scale.

Therefore, during the second horizontal period H2, the switching transistors connected to all sub-pixels are turned off. Therefore, during the second horizontal period H2, in odd columns, the first data voltage DATA1 is not charged into the first sub-pixels R arranged in the 8kth-third row, and the second data voltage DATA2 is not charged. It is charged into the second sub-pixels W arranged in the 8k-second row. In addition, the third data voltage DATA3 is not charged into the third sub-pixels B arranged in the 8k-first row, and the fourth data voltage DATA4 is not charged in the fourth sub-pixels B arranged in the 8k-row Pixel G.

As shown in FIG. 5, during the third horizontal period H3, the third gate voltage GATE3 is a high gate voltage, while the first gate voltage GATE1, the second gate voltage GATE2 and the fourth gate voltage GATE4 are gate voltages. low voltage. In addition, also during the third horizontal period H3, the first to fourth data voltages DATA1 to DATA4 may be at a predetermined level of data voltages to achieve a predetermined gray scale.

Accordingly, during the third horizontal period H3, the first sub-pixels R arranged in the 8k-7 row, the second sub-pixels W arranged in the 8k-6 row, and the second sub-pixel W arranged in the even-numbered columns are connected to All the switching transistors of the third sub-pixels B in row 8k-5 and the fourth sub-pixels G in row 8k-4 are turned on.

Therefore, during the third horizontal period H3, in the even columns, the first data voltage DATA1 can be charged in the first sub-pixels R arranged in the 8k-7th row, and the second data voltage DATA2 can be charged in the set In the second sub-pixels W in row 8k-6. In addition, the third data voltage DATA3 can be charged into the third sub-pixels B arranged in row 8k-5, and the fourth data voltage DATA4 can be charged in the fourth sub-pixels arranged in row 8k-4 in G.

As shown in FIG. 5 , during the fourth horizontal period H4 , all of the first gate voltage GATE1 , the second gate voltage GATE2 , the third gate voltage GATE3 and the fourth gate voltage GATE4 are gate low voltages. In addition, also during the fourth horizontal period H4, the first to fourth data voltages DATA1 to DATA4 may be at a predetermined level of data voltages to achieve a predetermined gray scale.

Therefore, during the fourth horizontal period H4, all switching transistors connected to all sub-pixels are turned off. Therefore, during the fourth horizontal period H4, in the even columns, the first data voltage DATA1 may not be charged into the first sub-pixels R arranged in the 8kth-third row, while the second data voltage DATA2 may be charged. are not charged into the second sub-pixels W arranged in the 8k-second row. In addition, the third data voltage DATA3 may not be charged into the third sub-pixels B arranged in the 8k-first row, and the fourth data voltage DATA4 may not be charged in the third sub-pixels B arranged in the 8k-row. Four sub-pixels G.

As described above, when the display device 100 according to an exemplary embodiment of the present disclosure implements a vertical pattern screen, during the first to fourth horizontal periods H1 to H4, that is, during one frame period, the first to fourth data voltages DATA1 to DATA4 can be the same level. Accordingly, during one frame period, the data transition of the first to fourth data voltages DATA1 to DATA4 does not occur.

In prior art display devices, two sub-pixels with different colors are connected to one data line. Therefore, in the display device of the prior art, the data voltages to be applied to the data lines need to be the data voltages corresponding to the colors, so the data migration of the data voltages is essential. That is, the data transition of the data voltage must occur even though the data transition of the data voltage may occur in at least one frame during one horizontal period.

Therefore, when the data shift of the data voltage occurs frequently, there may be a problem that the data voltage is not fully charged during a horizontal period. In addition, when the data migration of the data voltage occurs frequently, there is a problem of overheating of the data driver configured to supply the data voltage.

On the contrary, in the display device according to the exemplary embodiment of the present disclosure, each of the data lines DL1, DL2, DL3 and DL4 is divided into a plurality of sub data lines SDL1-a, SDL1-b, SDL2-a, SDL2- b. SDL3-a, SDL3-b, SDL4-a, SDL4-b. In addition, the separated sub-data lines SDL1-a, SDL1-b, SDL2-a, SDL2-b, SDL3-a, SDL3-b, SDL4-a, SDL4-b can be connected to sub-pixels that realize the same color R, G, B, W. Accordingly, in the display device according to an exemplary embodiment of the present disclosure, the data lines may only output a data voltage corresponding to one color. Therefore, when a monochrome freeze frame or vertical pattern screen is implemented, the data transition of the data voltage may not occur in one frame.

Therefore, the data voltage can be fully charged during one frame period, so that the problem of incomplete charging of the data voltage of the related art display device can be solved. In addition, the data voltage is continuously maintained in one frame, so the problem of overheating of the data driver configured to provide the data voltage can be solved.

In addition, when the display device realizes the vertical pattern screen, the data migration of the data voltage does not occur in one frame, so the load carried by the data driver can be minimized when the vertical pattern screen is realized.

Hereinafter, a display device according to another exemplary embodiment of the present disclosure will be described. A display device according to another exemplary embodiment of the present disclosure is different in a multiplexer (MUX) (MX), so MUX MX will be described in detail. Also, descriptions overlapping between a display device according to another exemplary embodiment of the present disclosure and a display device according to an exemplary embodiment of the present disclosure will be omitted.

<Another Exemplary Embodiment of the Present Disclosure - Addition of MUX>

FIG. 6 is a circuit diagram for explaining a MUX of a display device according to another exemplary embodiment of the present disclosure.

As shown in FIG. 6, the MUX MX is disposed between the plurality of data lines DL1 to DL(2n) and the plurality of sub data lines SDL1-a to SDL(2n)-b. In addition, MUX MX is connected to the data lines DL1 to DL(2n) and the sub data lines SDL1-a to SDL(2n)-b to determine the data lines DL1 to DL(2n) and the sub data lines Connection relation of line SDL1-a to SDL(2n)-b. n refers to a natural number of 1 or greater.

MUX MX includes a plurality of first switching elements SW1 and a plurality of second switching elements SW2. Each of the first switch elements SW1 connects the data line DLn to any one of the sub-data lines SDLn-a according to the first control signal. In addition, each of the second switch elements SW2 connects the data line DLn to any one of the sub-data lines SDLn-b according to the second control signal.

Specifically, the first switch element SW1 includes a gate electrode connected to the first control signal line CSL1 , a drain electrode connected to the n-th data line DLn, and a source electrode connected to the n-a-th sub-data line SDLn-a.

Therefore, when the first control signal applied to the first control signal line CSL1 is at a high potential, the first switch element SW1 is turned on to electrically connect the n-th data line DLn to the n-a-th sub-data line SDLn-a. On the contrary, when the first control signal applied to the first control signal line CSL1 is at a low potential, the first switching element SW1 is turned off, so that the nth data line DLn is electrically isolated from the n-ath sub-data line SDLn-a .

The second switch element SW2 includes a gate electrode connected to the second control signal line CSL2 , a drain electrode connected to the nth data line DLn, and a source electrode connected to the n-bth sub-data line SDLn-b.

Therefore, when the second control signal applied to the second control signal line CSL2 is at a high potential, the second switch element SW2 is turned on so that the nth data line DLn is electrically connected to the n−bth sub data line SDLn-b. On the contrary, when the second control signal applied to the second control signal line CSL2 is at low potential, the second switch element SW2 is turned off to electrically insulate the nth data line DLn from the n−bth sub data line SDLn-b.

Specifically, the above-mentioned operations of the display device according to another exemplary embodiment of the present disclosure will be described below in relation to the sub-pixels.

FIG. 7 is a circuit diagram for explaining a connection relationship between a plurality of sub-pixels and a multiplexer of a display device according to another exemplary embodiment of the present disclosure.

The operation of the sub-pixels connected to the first to fourth gate lines GL4 and the first to fourth data lines DL4 will be described with reference to FIG. 7 . That is, the operation of the sub-pixels will be described by applying 2 to n of FIG. 6 .

When the first control signal CS1 is at a high level and the second control signal CS2 is at a low level, the first switching elements SW1 are turned on and the second switching elements SW2 are turned off. Therefore, by using the first switch elements SW1, the first data line DL1 is electrically connected to the 1-a-th sub-data line SDL1-a; the second data line DL2 is electrically connected to the 2-a-th sub-data line SDL2-a. The third data line DL3 is electrically connected to the 3-a sub-data line SDL3-a; and the fourth data line DL4 is electrically connected to the 4-a sub-data line SDL4-a.

Accordingly, the first data voltage DATA1 is charged into the first sub-pixels R connected to the 1-a-th sub-data line SDL1-a in row 8k-7, and the second data voltage DATA2 is charged in the The 8k-6th row is connected to the second sub-pixels W of the 2-a-th sub-data line SDL2-a. In addition, the third data voltage DATA3 is charged into the third sub-pixels B connected to the 3-a-th sub-data line SDL3-a arranged in row 8k-5, and the fourth data voltage DATA4 is charged in the third sub-pixel B arranged in row 8k-5 8k-4 rows are connected to the fourth sub-pixels G of the 4-a-th sub-data line SDL4-a.

When the first control signal CS1 is at a low level and the second control signal CS2 is at a high level, the first switching elements SW1 are turned off and the second switching elements SW2 are turned on. Therefore, by using the first switch elements SW1, the first data line DL1 is electrically connected to the 1-bth sub-data line SDL1-b; the second data line DL2 is electrically connected to the 2-b-th sub-data line SDL2-b. The third data line DL3 is electrically connected to the 3-b sub-data line SDL3-b; and the fourth data line DL4 is electrically connected to the 4-b sub-data line SDL4-b.

Accordingly, the first data voltage DATA1 is charged into the first sub-pixels R arranged in the 8k-third row connected to the 1-b-th sub-data line SDL1-b, and the second data voltage DATA2 is charged into the set The 8k-second row is connected to the second sub-pixels W of the 2-b-th sub-data line SDL2-b. In addition, the third data voltage DATA3 is charged into the third sub-pixels B connected to the 3-b-th sub-data line SDL3-b in the 8k-first row, and the fourth data voltage DATA4 is charged in the The 8kth row is connected to the fourth sub-pixels G of the 4-bth sub-data line SDL4-b.

As mentioned above, the first switching element SW1 and the second switching element SW2 of the MUX MX are turned on alternately, so that the data voltage is applied to all the sub-pixels R, G, B, and W to realize images in the display area.

As described above, the display device according to another exemplary embodiment of the present disclosure includes a MUX so that the data lines are not connected to all of the sub-data lines, but may be connected to a part of the sub-data lines.

Therefore, the data voltage applied to the data lines is not applied to all of the sub-data lines, but to a part of the sub-data lines.

Accordingly, the load required for the data driver of the display device according to another exemplary embodiment of the present disclosure to output the data voltage can be reduced. Therefore, the data voltage of the display device according to another exemplary embodiment of the present disclosure is fully charged into the sub-pixels, so that the image quality can be improved.

Hereinafter, a display device according to still another exemplary embodiment of the present disclosure will be described. The difference of the display device according to still another exemplary embodiment of the present disclosure lies in the division of the MUX, so the division of the MUX will be described in detail. Also, descriptions overlapping between a display device according to another exemplary embodiment of the present disclosure and a display device according to an exemplary embodiment of the present disclosure will be omitted.

<Another Exemplary Embodiment of the Present Disclosure (Example 3) - Division of MUX>

FIG. 8 is a circuit diagram for explaining two sub-multiplexers of a display device according to still another exemplary embodiment (Example 3) of the present disclosure. FIG. 9 is a circuit diagram for explaining four sub-multiplexers of a display device according to still another exemplary embodiment (Example 3) of the present disclosure.

As shown in FIG. 8, MUX MX can be divided into a first sub-multiplexer SMX1 and a second sub-multiplexer SMX2.

The first sub-multiplexer SMX1 is connected to a first data line to an n-th data line DL1 to DLn and a 1-a-th sub-data line to an n-b-th sub-data line SDL1-a to SDLn-b to judge The connection relationship between the first data line to the nth data line DL1 to DLn and the 1-a-th sub-data line to the n-b-th sub-data line SDL1-a to SDLn-b.

The second sub-multiplexer SMX2 can be connected to an n+1th data line to a 2nth data line DL(n+1) to DL(2n) and a (n+1)-a sub-data line to A (2n)-bth sub-data lines SDL(n+1)-a to SDL(2n)-b. Therefore, the second sub-multiplexer SMX2 judges the n+1th data line to the 2nth data line DL(n+1) to DL(2n) and the (n+1)-a sub-data line to the (2nth )-b connection relationship between SDL(n+1)-a and SDL(2n)-b.

The first sub-multiplexer SMX1 includes a plurality of 1-a switching elements SW1-a and a plurality of 2-a switching elements SW2-a. Each of the 1-a-th switching elements SW1-a determines the first data line to the n-th data line DL1 to DLn and the 1-a-th sub-data line to the n-a-th sub-data line according to the 1-a-th control signal CS1-a Connection relation of lines SDL1-a to SDLn-a. Each of the 2-a-th switching elements SW2-a judges the first data line to the n-th data line DL1 to DLn and the 1-b-th sub-data line to the n-b-th sub-data line according to the 2-a-th control signal CS2-a Connection relation of line SDL1-b to SDLn-b.

The second sub-multiplexer SMX2 includes a plurality of 1-b switching elements SW1-b and a plurality of 2-b switching elements SW2-b. Each of the 1-bth switching elements SW1-b determines the n+1th data line to the 2nth data line DL(n+1) to DL(2n) and the The connection relationship between (n+1)-a sub-data line to (2n)-a-th sub-data line SDL(n+1)-a to SDL(2n)-a. Each of the 2-bth switching elements SW2-b determines the n+1th data line to the 2-bth control signal CS2-b according to the 2nth data line DL(n+1) to DL(2n) and the 2nth data line DL(n+1) to DL(2n) and the The connection relationship between (n+1)-b sub-data lines to (2n)-b-th sub-data lines SDL(n+1)-b to SDL(2n)-b.

However, the present disclosure is not limited thereto, and as shown in FIG. 9 , the MUX MX of another display device of the present disclosure can be divided into four sub-multiplexers SMX1 , SMX2 , SMX3 and SMX4 .

Specifically, the first sub-multiplexer SMX1 may include a 1-a switch element SW1-a controlled by the 1-a control signal CS1-a and a first switch element SW1-a controlled by the 2-a control signal CS2-a. 2-a Switching element SW2-a. The second sub-multiplexer SMX2 may include a 1-b switch element SW1-b controlled by the 1-b control signal CS1-b and a 2-b switch element controlled by the 2-b control signal CS2-b Switching element SW2-b. The third sub-multiplexer SMX3 may include a 1-c switch element SW1-c controlled by the 1-c control signal CS1-c and a 2-c switch controlled by the 2-c control signal CS2-c Element SW2-c. The fourth sub-multiplexer SMX4 may include a 1-d switch element SW1-d controlled by the 1-d control signal CS1-d and a 2-d switch controlled by the 2-d control signal CS2-d Element SW2-d.

As described above, the display device according to still another exemplary embodiment of the present disclosure may divide the MUX into a plurality of sub-multiplexers. Therefore, the load required by each of the sub-multiplexers can be reduced. That is, as the multiplexer is divided into a plurality of sub-multiplexers, the lengths of the first control signal line and the second control signal line driving the sub-multiplexers are reduced, so that the load of the sub-multiplexers can be reduced.

Accordingly, the data voltage can be more efficiently charged into the sub-data lines connected to the sub-multiplexers. Therefore, the data voltage can be fully charged into the sub-pixels, so the problem of image quality degradation caused by incompletely charged data can be solved.

Another exemplary embodiment of the present disclosure and specific effects of still another exemplary embodiment will be described in more detail with reference to FIGS. 10 and 11 .

FIG. 10 is a waveform diagram illustrating a control signal of a display device according to another exemplary embodiment of the present disclosure and yet another exemplary embodiment. FIG. 11 is a waveform diagram illustrating a data voltage of a display device according to another exemplary embodiment of the present disclosure and yet another exemplary embodiment.

Specifically, the control signals shown in FIG. 10 refer to the first control signal and the second control signal of the display device according to another exemplary embodiment and yet another exemplary embodiment of the present disclosure. In addition, the data voltage shown in FIG. 11 refers to the data voltage DATA to be charged into each data line.

In FIGS. 10 and 11 , Example 1 refers to control signals and data voltages in a display device according to another exemplary embodiment of the present disclosure in which MUX is not divided. Example 2 refers to control signals and data voltages in a display device according to yet another exemplary embodiment of the present disclosure, in which the MUX is divided into two sub-multiplexers. In addition, Example 3 refers to a control signal and a data voltage in a display device according to yet another exemplary embodiment of the present disclosure in which the MUX is divided into four sub-multiplexers.

Specifically, referring to FIG. 10 , according to Example 1, the control signal is charged to approximately half of the ideal control signal within a unit period, and according to Example 2, the control signal is charged to be close to the ideal control signal within the unit period. Furthermore, according to Example 3, the control signal is charged to a voltage level corresponding to the ideal control signal during a unit period.

Referring to FIG. 11 , according to Example 1, during the horizontal period, the data voltage is charged with about 89% of the ideal data voltage, and according to Example 2, the data voltage is charged with about 96% of the ideal data voltage. Furthermore, during the horizontal period, according to Example 3, the data voltage is charged with about 97% of the ideal data voltage.

That is, in the display device according to still another exemplary embodiment of the present disclosure, the data voltage may be charged to 95% or more of the ideal data voltage. Accordingly, in the display device according to yet another exemplary embodiment of the present disclosure, the data voltage is fully charged into each of the sub-pixels, so that the image quality can be improved.

<Another Exemplary Embodiment of the Present Disclosure (Example 4) - Pixel Symmetry Structure>

FIG. 12 is a diagram for explaining a positional relationship of sub-pixels of a display device according to still another exemplary embodiment (Example 4) of the present disclosure.

2矩陣且在顯示區域中的四個像素PX被繪示，設置為4

2矩陣的八個像素PX的位置關係是重複的。此外，設置在子像素R、G、B及資料線之間的電晶體是指參考圖2所描述的開關電晶體SWT。In Figure 12, for ease of illustration, only 4

2 matrix and four pixels PX in the display area are drawn, set to 4

The positional relationship of the eight pixels PX of the 2 matrix is repeated. In addition, the transistor disposed between the sub-pixels R, G, B and the data line refers to the switching transistor SWT described with reference to FIG. 2 .

Referring to FIG. 12, one pixel PX includes three sub-pixels B, G, R. For example, as shown in FIG. 12 , the pixel PX may include a first sub-pixel B, a second sub-pixel G, and a third sub-pixel R. In addition, the first sub-pixel B is a blue sub-pixel, the second sub-pixel G is a green sub-pixel, and the third sub-pixel R is a red sub-pixel. However, the present disclosure is not limited thereto, and the sub-pixels may be changed into various colors such as magenta, yellow, and cyan.

The sub-pixels B, G, R of the same color may be arranged in the same row. That is, the first sub-pixels B are arranged in the same row, the second sub-pixels G are arranged in the same row, and the third sub-pixels R are arranged in the same row.

More specifically, as shown in FIG. 12, the blue sub-pixels of the first sub-pixels B are arranged in the 12k-11th row, the 12k-8th row, the 12k-5th row and the 12k-second row . In addition, the sub-pixels for the second sub-pixels G are arranged in the 12k-10th row, the 12k-7th row, the 12k-4th row and the 12k-first row, and the third sub-pixels R The red sub-pixels are arranged in the 12k-9 row, the 12k-6 row, the 12k-the third row and the 12k row. Herein, k refers to a natural number of 1 or greater.

That is, the first sub-pixel R, the second sub-pixel W, and the third sub-pixel B are sequentially repeated with respect to one odd row or one even row.

Each of the plurality of data lines DL1, DL2, and DL3 may be divided into a plurality of sub-data lines SDL1-a, SDL1-b, SDL2-a, SDL2-b, SDL3-a, SDL3-b, respectively. Specifically, the first data line DL1 can be divided into multiple first sub-data lines SDL1-a and SDL1-b, and the second data line DL2 can be divided into multiple second sub-data lines SDL2-a and SDL2- b, and the third data line DL3 can be divided into a plurality of third sub-data lines SDL3-a and SDL3-b.

As mentioned above, the first sub-data lines SDL1-a and SDL1-b may include a 1-a-th sub-data line SDL1-a and a 1-b-th sub-data line SDL1-b, and the second sub-data line SDL2- a and SD2L-b may include a 2-a-th sub-data line SDL2-a and a 2-b-th sub-data line SDL2-b. In addition, the third sub-data lines SDL3-a and SDL3-b may include a 3-a-th sub-data line SDL3-a and a 3-b-th sub-data line SDL3-b.

The first sub-data lines SDL1-a and SDL1-b are disposed adjacent to the first sub-pixels B to be connected to the first sub-pixels B.

Specifically, the 1-ath sub-data line SDL1-a is arranged between the first sub-pixels B arranged in the 12k-8 row and the second sub-pixels G arranged in the 12k-7 row , to be electrically connected to the first sub-pixels B arranged in the 12k-8th row. Alternatively, the 1-a-th sub-data line SDL1-a is arranged on the first sub-pixels B arranged in the 12k-second row and the second sub-pixels G arranged in the 12k-first row Between them, they are electrically connected to the first sub-pixels B arranged in the 12k-second row.

The 1-bth sub-data lines SDL1-b are arranged between the first sub-pixels B arranged in the 12k-5 row and the second sub-pixels G arranged in the 12k-4 row, so as to It is electrically connected to the first sub-pixels B arranged in row 12k-5. Alternatively, the 1-bth sub-data lines SDL1-b are arranged on the first sub-pixels B arranged in row 12k-11 and the second sub-pixels G arranged in row 12k-10 Between them, they are electrically connected to the first sub-pixels B arranged in the 12k-11th row.

The second sub-data lines SDL2-a and SDL2-b are disposed adjacent to the second sub-pixels G to be connected to the second sub-pixels G.

Specifically, the 2-a-th sub-data line SDL2-a is arranged between the second sub-pixels G arranged in row 12k-7 and the third sub-pixels R arranged in row 12k-6 , to be electrically connected to the second sub-pixels G arranged in the 12k-7th row. Alternatively, the 2-ath sub-data line SDL2-a is arranged between the second sub-pixels G arranged in the 12k-first row and the third sub-pixels R arranged in the 12k-row, and electrically connected to the second sub-pixels G disposed in the 12k-th first row.

The 2-b sub-data line SDL2-b is arranged between the first sub-pixels B arranged in the 12k-11th row and the second sub-pixels G arranged in the 12k-10th row, electrically It is connected to the second sub-pixels G arranged in row 12k-10. Alternatively, the 2-bth sub-data line SDL2-b is arranged between the first sub-pixels B arranged in row 12k-5 and the second sub-pixels G arranged in row 12k-4 , to be electrically connected to the second sub-pixels G disposed in the 12k-4th row.

The third sub-data lines SDL3-a and SDL3-b are disposed adjacent to the third sub-pixels R to be connected to the third sub-pixels R.

Specifically, the 3-ath sub-data line SDL3-a is arranged between the second sub-pixels G arranged in row 12k-7 and the third sub-pixels R arranged in row 12k-6 , to be electrically connected to the third sub-pixels R arranged in the 12k-6th row. Alternatively, the 3-ath sub-data line SDL3-a is arranged between the second sub-pixels G arranged in the 12k-first row and the third sub-pixels R arranged in the 12k-row, and electrically connected to the third sub-pixels R arranged in the 12kth row.

The 3-b sub-data line SDL3-b is arranged between the second sub-pixels G arranged in the 12k-10th row and the third sub-pixels R arranged in the 12k-9 row, electrically It is connected to the third sub-pixels R arranged in row 12k-9. Alternatively, the 3-bth sub-data line SDL3-b is arranged between the second sub-pixels G arranged in the 12k-first row and the third sub-pixels R arranged in the 12k-row, and electrically connected to the third sub-pixels R arranged in the 12kth row.

A first data voltage DATA1 which is a blue data voltage is applied to the first data line DL1, a second data voltage DATA2 which is a green data voltage is applied to the second data line DL2, and a third data voltage DATA3 which is a red data voltage is applied to the first data line DL1. applied to the third data line DL3.

Therefore, the first data voltage DATA1 which is the blue data voltage is applied to the first sub-data lines SDL1-a and SDL1-b, and the second data voltage DATA2 which is the green data voltage is applied to the second sub-data lines SDL1-a and SDL1-b. Data lines SDL2-a and SDL2-b. In addition, the third data voltage DATA3 which is a red data voltage is applied to the third sub-data lines SDL3-a and SDL3-b.

Each of the gate lines GL1 to GL4 can be disposed on both sides of the sub-pixels B, G, R, and two gate lines GL2 and GL3 can be disposed between the sub-pixels B, G, R.

Specifically, referring to FIG. 12, the first gate line GL1 and the second gate line GL2 are arranged on both sides of the sub-pixels B, G, and R in odd columns, and the third gate line GL3 and the second gate line The four gate lines GL4 are arranged on both sides of the sub-pixels B, G, R in the even columns.

Therefore, the first gate line GL1 may be disposed on one side of the sub-pixels B, G, R in odd columns. In addition, the second gate line GL2 and the third gate line GL3 are disposed between the sub-pixels B, G, R in odd columns and the sub-pixels B, G, R in odd columns. In addition, the fourth gate line GL4 may be disposed on the other side of the sub-pixels B, G, R in even columns. As mentioned above, one side refers to a direction in which a plurality of sub-pixels in a previous column are arranged, and the other side refers to a direction in which a plurality of sub-pixels in a next column are arranged.

Meanwhile, each of the pixels PX may be connected to the same gate lines GL1 to GL4 .

Specifically, referring to FIG. 12 , the sub-pixels B, G, and R disposed in rows 12k-11 to 12k-6 of odd columns are connected to the first gate line GL1 . In addition, the sub-pixels B, G, and R arranged in the 12k-5th row to the 12kth row of odd columns are connected to the second gate line GL2. In addition, the subpixels B, G, and R arranged in the 12k-5th row to the 12kth row of the even columns are connected to the third gate line GL3. In addition, the sub-pixels B, G, R disposed in the 12k-11th row to the 12k-6th row of the even columns are connected to the fourth gate line GL4.

At the same time, the sub-pixels B, G, and R arranged in the 12k-11th row to the 12k-6th row are arranged to be more adjacent to the first gate line GL1 than the second gate line GL2 and the third gate line GL3 and the fourth gate line GL4. The sub-pixels B, G, and R arranged in the 12k-5th row to the 12kth row are arranged to be more adjacent to the second gate line GL2 and the third gate line than the first gate line GL1 and the fourth gate line GL4 Polar Line GL3.

Specifically, referring to FIG. 12 , the sub-pixels B, G, and R arranged in the 12k-11th row to the 12k-6th row of the odd-numbered columns are arranged more adjacent to the first gate electrode than the second gate electrode line GL2 Line GL1. In addition, the sub-pixels B, G, and R arranged in the 12k-5th row to the 12kth row of odd columns are arranged more adjacent to the second gate line GL2 than the first gate line GL1 . In addition, the sub-pixels B, G, and R arranged in the 12k-5th row to the 12kth row of the even columns are arranged more adjacent to the third gate line GL3 than the fourth gate line GL4 . In addition, the sub-pixels B, G, and R disposed in the 12k-11th row to the 12k-6th row of the even columns are disposed more adjacent to the fourth gate line GL4 than the third gate line GL3 .

That is, in the display device according to another exemplary embodiment (Example 4) of the present disclosure, the positional relationship of the sub-pixels B, R, and G may be original symmetry.

The reference voltage lines RVL1 and RVL2 , the high potential voltage lines VDDL1 and VDDL2 , and the low potential voltage line VSSL may be disposed between a plurality of adjacent pixels PX.

Specifically, the high-potential voltage lines VDDL1 and VDDL2 may be disposed outside the first sub-pixels B arranged in row 12k-11 or outside the third sub-pixel R arranged in row 12k.

Specifically, the first high-potential voltage line VDDL1 can be set outside the first sub-pixels B set in row 12k-11, and the second high-potential voltage line VDDL2 can be set outside the first sub-pixels B set in row 12k. outside the third sub-pixel R.

Each of the high potential voltage lines VDDL1 and VDDL2 may be divided into a plurality of sub high potential voltage lines SVDDL1 and SVDDL2.

Specifically, the first high potential voltage line VDDL1 may be divided into a plurality of first sub high potential voltage lines SVDDL1. These first sub-high potential voltage lines SVDDL1 can be arranged on the sub-pixels B, G, and R arranged in the 12k-11th row to the 12k-6th row of the odd-numbered columns and the 12k-11th rows to the 12k-11th row of the even-numbered columns. Between sub-pixels B, G, and R of 12k-6 rows.

In other words, the high-potential voltage lines are arranged on the sub-pixels B, G, and R arranged in the 12k-11th row to the 12k-6th row in the odd-numbered columns and the 12k-11th row to the 12k-6th row in the even-numbered columns. Between the sub-pixels B, G, and R of the sub-pixels, a high potential voltage is applied to the sub-pixels B, G, and R arranged in the 12k-11th row to the 12k-6th row.

The second high potential voltage line VDDL2 may be divided into a plurality of second sub high potential voltage lines SVDDL2. These second sub-high potential voltage lines SVDDL2 can be arranged on one side of the sub-pixels B, G, and R arranged in the 12k-5th row to the 12kth row of the odd-numbered column and arranged on the 12k-5th row to the even-numbered column. The other side of the sub-pixels B, G, R of the 12kth row.

In other words, the high-potential voltage lines are arranged on one side of the sub-pixels B, G, and R arranged in the 12k-5th row to the 12kth row of the odd-numbered columns and on the side of the sub-pixels B, G, and R arranged in the 12k-5th row to the 12k-th row of the even-numbered columns. The other side of the sub-pixels B, G, and R is to apply a high potential voltage to the sub-pixels B, G, and R arranged in the 12k-5th row to the 12kth row.

Meanwhile, the reference voltage lines RVL1 and RVL2 may be disposed between the third sub-pixels R arranged in the 12k-9 row and the first sub-pixels B arranged in the 12k-8 row. In addition, the reference voltage lines RVL1 and RVL2 may be disposed between the third sub-pixels R in the 12k-th row and the first sub-pixels B in the 12k-second row.

Specifically, the first reference voltage line RVL1 may be disposed between the third sub-pixels R arranged in row 12k-9 and the first sub-pixels B arranged in row 12k-8. The second reference voltage line RVL2 may be disposed between the third sub-pixels R arranged in the 12k-th row and the first sub-pixels B arranged in the 12k-second row.

Each of the reference voltage lines RVL1 and RVL2 can be divided into a plurality of sub-reference voltage lines SRVL1 and SRVL2.

Specifically, the first reference voltage line RVL1 may be divided into a plurality of first sub-reference voltage lines SRVL1. These first sub-reference voltage lines SRVL1 can be arranged on one side of the sub-pixels B, G, R arranged in the 12k-11th row to the 12k-6th row of the odd-numbered column and arranged in the 12k-11th row of the even-numbered column To the other side of sub-pixels B, G, R in row 12k-6.

In other words, the reference voltage line is arranged on one side of the sub-pixels B, G, R arranged in the 12k-11th row to the 12k-6th row of the odd-numbered column and arranged on the 12k-11th row to the 12k-th row of the even-numbered column. The other side of the sub-pixels B, G, and R in the 6th row is used to apply a reference voltage to the sub-pixels B, G, and R arranged in the 12k-11th row to the 12k-6th row.

Also, the second reference voltage line RVL2 may be divided into a plurality of second sub-reference voltage lines SRVL2. The second sub-reference voltage line SRVL2 can be set on the sub-pixels B, G, R arranged in the 12k-5th row to the 12kth row of the odd-numbered column and the sub-pixels arranged in the 12k-5th row to the 12k-th row of the even-numbered column Between B, G, and R.

In other words, the reference voltage lines are arranged on the sub-pixels B, G, R arranged in the 12k-5th row to the 12kth row of the odd-numbered columns and the sub-pixels B, G, R arranged in the 12k-5th row to the 12k-th row of the even-numbered columns. Between G and R, to apply a reference voltage to the sub-pixels B, G, and R arranged in the 12k-5th row to the 12kth row.

The low-potential voltage line VSSL is arranged between the third sub-pixel R arranged in the 12k-6 row and the first sub-pixel B arranged in the 12k-5 row, so as to apply the low-potential voltage VSS to the row 12k-5. Sub-pixels B, G, and R from the 11th row to the 12kth row.

Meanwhile, a display device according to still another exemplary embodiment of the present disclosure may include a plurality of repair patterns RP, which may connect adjacent sub-pixels B, G, R. Referring to FIG.

Specifically, the repair patterns RP can be set on the sub-pixels B, G, and R arranged in the 12k-11th row to the 12k-6th row of the odd-numbered columns and the 12k-11th rows to the 12k-th row of the even-numbered columns. - Between the sub-pixels B, G, R of the 6 rows. The repairing patterns RP may be connected to the sub-pixels B, G, R arranged in the same row.

Therefore, if any of the sub-pixels B, G, and R arranged in the 12k-11th row to the 12k-6th row is damaged, the repair pattern RP connected to the damaged sub-pixel is welded to electrically The damaged sub-pixel is connected to the sub-pixel located in the same row. With this, damaged sub-pixels are repaired to emit light.

In addition, these repair patterns RP can be arranged on one side of the sub-pixels B, G, R arranged in the 12k-5th row to the 12kth row of the odd-numbered columns and arranged in the 12k-5th row to the 12k-th row of the even-numbered columns. The other side of the sub-pixels B, G, R. It can be connected to these sub-pixels B, G, R arranged in the same row.

Therefore, if any one of the sub-pixels B, G, and R arranged in the 12k-5th row to the 12kth row is damaged, the repair pattern RP connected to the damaged sub-pixel is welded to electrically connect the received Lost sub-pixels are located in the same row as the sub-pixels. With this, damaged sub-pixels are repaired to emit light.

FIG. 13 is a diagram for explaining changes in overlay of sub-pixels of a display device according to still another exemplary embodiment (Example 4) of the present disclosure.

Due to the manufacturing process of the display device, when the sub-pixels are formed, the overlapping of the sub-pixels may change.

As shown in FIG. 13, only the sub-pixels B, G, R may be formed to be shifted to one side. Therefore, the overlapping variation of the sub-pixels B, G, R and the gate lines connected to the sub-pixels B, G, R may occur.

Specifically, the sub-pixels B, G, and R arranged in the 12k-11th to 12k-6th rows of the odd-numbered columns are closer to the first gate line GL1, so that the 12k-11th to 12k-11th rows of the odd-numbered columns are arranged The overlap of sub-pixels B, G, R of 12k-6 rows with the first gate line GL1 may be increased ((+) offset).

On the contrary, the sub-pixels B, G, and R arranged in the 12k-11th row to the 12k-6th row of the even-numbered column are farther away from the fourth gate line GL4, so that the sub-pixels arranged in the 12k-11th row to the 12k-th row of the even-numbered column The overlap of the sub-pixels B, G, R of the -6 row with the fourth gate line GL4 can be reduced ((-) offset).

In addition, the sub-pixels B, G, R arranged in the 12k-5th row to the 12kth row of the odd-numbered columns are farther away from the second gate line GL2, so that the sub-pixels arranged in the 12k-5th row to the 12k-th row of the odd-numbered columns The overlap of pixels B, G, R with the second gate line GL2 can be reduced ((-) offset).

In addition, the sub-pixels B, G, R arranged in the 12k-5th row to the 12kth row of the even-numbered columns are closer to the third gate line GL3, so that the sub-pixels arranged in the 12k-5th row to the 12k-th row of the even-numbered columns The overlap of pixels B, G, R with the third gate line GL3 may be increased ((+) offset).

Therefore, the overlap ((+) offset) of the sub-pixels B, G, R disposed in the 12k-11th row to the 12k-6th row of the odd-numbered column and the first gate line GL1 is increased (+) offset, so that the driving current can be increased.

In addition, the overlapping ((-) offset) of the sub-pixels B, G, R arranged in the 12k-11th row to the 12k-6th row of the even-numbered column and the fourth gate line GL4 is reduced, so that the driving current can be reduced.

In addition, the overlapping ((-) offset) of the sub-pixels B, G, R arranged in the 12k-5th row to the 12kth row of the odd-numbered column and the second gate line GL2 is reduced, so that the driving current can be reduced.

In addition, the overlap ((+) offset) of the sub-pixels B, G, R arranged in the 12k-5th row to the 12kth row of the even-numbered column and the third gate line GL3 increases, so that the driving current can be increased.

That is, in the display device according to still another exemplary embodiment (Example 4) of the present disclosure, even if the overlap of sub-pixels is changed, the driving current of adjacent pixels does not increase or decrease.

That is, in the display device according to still another exemplary embodiment (Example 4) of the present disclosure, even if the overlap of sub-pixels is changed, the driving current of pixels arranged on the same line does not always increase or decrease. According to this, vertical or horizontal lines due to overlapping changes do not occur.

Furthermore, in the display device according to still another exemplary embodiment (Example 4) of the present disclosure, in the sub-pixels, sub-high potential voltage lines, sub-reference voltage lines, and repair patterns may be provided. Accordingly, the components disposed in the display panel are integrated, so that the aperture ratio of the display panel can also be increased.

Embodiments of the invention can also be described as follows:

According to an aspect of the present disclosure, a display device includes a display panel, in which a plurality of pixels are disposed, and the pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel. Each of the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel configured to emit light of different colors is provided; a data driver for using a plurality of data lines providing a data voltage to the pixels; and a gate driver for providing a gate voltage to the pixels by using a plurality of gate lines, each of the data lines being divided into a plurality of sub-data lines, and each One of the sub-data lines is connected to a plurality of sub-pixels with the same color, wherein the sub-pixels with the same color are a plurality of the first sub-pixels, a plurality of the second sub-pixels, a plurality of the third sub-pixels or A plurality of the fourth sub-pixels minimizes the data migration of the data voltage.

The first sub-pixels arranged in the pixels may be arranged in the same row, the second sub-pixels arranged in the pixels may be arranged in the same row, and the first sub-pixels arranged in the pixels may be arranged in the same row. The three sub-pixels may be arranged in the same row, and the fourth sub-pixels in the pixels may be arranged in the same row.

The first sub-pixel can be a red sub-pixel, the second sub-pixel can be a white sub-pixel, the third sub-pixel can be a blue sub-pixel, and the fourth sub-pixel can be a green sub-pixel.

The sub-data lines may include a plurality of first sub-data lines connected to the first sub-pixels in the pixels, and a plurality of second sub-data lines connected to the pixels in the pixels The second sub-pixel, a plurality of third sub-data lines connected to the third sub-pixels arranged in the pixels, and a plurality of fourth sub-data lines connected to the third sub-data lines arranged in the pixels Four sub-pixels.

One of the first sub-data lines and one of the second sub-data lines may be arranged between the first sub-pixel and the second sub-pixel, and the third sub-data lines One of them and one of the fourth sub-data lines may be disposed between the third sub-pixel and the fourth sub-pixel.

Each of the pixels can be connected to the same gate line, and two adjacent pixels among the pixels can be connected to different gate lines.

When the display panel implements a monochrome screen or a vertical pattern screen, the data voltage can be continuously maintained in a frame.

Each of the first subpixel, the second subpixel, the third subpixel, and the fourth subpixel may include a switching transistor, a driving transistor, a storage capacitor, a sensing transistor, and a LEDs.

The display panel may further include a plurality of reference voltage lines connected to the sensing transistor; and a plurality of high potential voltage lines connected to the driving transistor, and each of the reference voltage lines is arranged in a pixel, And each of the high potential voltage lines is arranged between a plurality of adjacent pixels in the pixels.

The display device may further include a multiplexer (MUX) disposed between the data lines and the sub-data lines, and the multiplexer controls the connection between the data lines and the sub-data lines according to a control signal A connection relationship.

The multiplexer may include a plurality of first switching elements, connected to one of the data lines and any one of the sub-data lines according to a first control signal, and a plurality of second switching elements, according to a first control signal Two control signals are connected to one data line of the data lines and another one of the sub-data lines.

The multiplexer can be combined into one to apply a first control signal to the first switching elements and a second control signal to the second switching elements.

The multiplexer can be divided into a plurality of sub-multiplexers, each of the sub-multiplexers includes the first switching elements and the second switching elements, and a separate first control signal and a separate A second control signal is applied to each of the sub-multiplexers.

According to another aspect of the present disclosure, a display device includes: a display panel in which a plurality of sub-pixels of different colors are disposed; a data driver for providing a data voltage to the sub-pixels by using a plurality of data lines; and A gate driver for providing a gate voltage to the sub-pixels by using a plurality of gate lines, each of the data lines is divided into a plurality of sub-data lines, and each of the sub-data lines is connected to the Sub-pixels with the same color among those sub-pixels. The gate lines include a first gate line disposed on one side of a plurality of sub-pixels in a plurality of odd-numbered columns among the sub-pixels; a second gate line and a third gate line disposed on The sub-pixels in the odd columns and the sub-pixels in the even columns; and a fourth gate line, arranged in the sub-pixels in the even columns On the other side of the pixel, among the sub-pixels, a plurality of sub-pixels arranged in a 12k-11th row to a 12k-6th row are arranged to be smaller than the second gate line and the third gate line Adjacent to the first gate line and the fourth gate line, and the plurality of sub-pixels arranged in a 12k-5th row to a 12kth row among the sub-pixels are arranged to be compared with the first gate line And the fourth gate line is closer to the second gate line and the third gate line. Therefore, even if the overlap of sub-pixels varies, the image can still be consistent.

The sub-pixels arranged in the 12k-11th row to the 12k-6th row of one of the even-numbered columns may be connected to the first gate line, and may be arranged to be compared with the second gate line. the pole line is closer to the first gate line, and the sub-pixels of the 12k-th row to the 12k-5th row arranged in one of the odd-numbered columns may be connected to the second gate line, and It may be arranged closer to the second gate line than to the first gate line.

Among the sub-pixels, the sub-pixels arranged in the 12k-11th row to the 12k-6th row in one of the even-numbered columns can be connected to the fourth gate line, and can be arranged to compare The third gate line is closer to the fourth gate line, and the sub-pixels of the 12k-5th row to the 12kth row arranged in one of the odd columns can be connected to the third gate line. The gate line may be arranged closer to the third gate line than the fourth gate line.

Among the sub-pixels, the sub-pixels that may be arranged in the 12k-11th row, the 12k-8th row, the 12k-5th row, and the 12k-second row may be a plurality of blue sub-pixels , among these sub-pixels, a plurality of sub-pixels that can be arranged in a 12k-10th row, a 12k-7th row, a 12k-4th row and a 12k-first row can be a plurality of green sub-pixels , and among the sub-pixels, the sub-pixels that may be arranged in a 12k-9th row, the 12k-6th row, a 12k-third row, and the 12k-th row may be a plurality of red sub-pixels.

A plurality of repairing patterns may be arranged on the sub-pixels from the 12k-11th row to the 12k-6th row which may be arranged in one of the odd-numbered columns and may be arranged in one of the even-numbered columns Between the sub-pixels from the 12k-11th row to the 12k-6th row.

A plurality of repair patterns may be arranged on one side of the sub-pixels from the 12k-5th row to the 12kth row in one of the odd-numbered columns, and may be arranged in the even-numbered columns The other side of the sub-pixels from the 12k-5th row to the 12kth row of one of them.

At least one high potential voltage line may be arranged on the sub-pixels from the 12k-11th row to the 12k-6th row which may be arranged in one of the odd-numbered columns and may be arranged in one of the even-numbered columns between the sub-pixels of the 12k-11th row to the 12k-6th row.

At least one high potential voltage line may be arranged on one side of the sub-pixels from the 12k-5th row to the 12kth row of one of the odd-numbered columns, and may be arranged on one side of the even-numbered columns The other side of the sub-pixels from the 12k-5th row to the 12kth row of one of them.

At least one reference voltage line may be disposed on one side of the sub-pixels from the 12k-11th row to the 12k-6th row of one of the odd-numbered columns, and may be disposed on the even-numbered columns The other side of the sub-pixels of the 12k-11th row to the 12k-6th row of one of them.

At least one high potential voltage line can be arranged on the sub-pixels from the 12k-5th row to the 12kth row which can be arranged in one of the odd-numbered columns and can be arranged in one of the even-numbered columns Between the sub-pixels from the 12k-5th row to the 12kth row.

Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for the purpose of illustration only, and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above-described exemplary embodiments are illustrative in all aspects and do not limit the present disclosure. The scope of protection of the present invention should be based on the scope of the appended patents, and all technical concepts within the same scope should be understood as falling within the scope of protection of the present invention.

100: Display device 110: display panel 120: Gate driver 130:Data drive 140: Timing controller 150: light emitting diode DL, DL1 to DL(2n): data line DL1: the first data line DL2: the second data line DL3: third data line DL4: The fourth data line SDL1-a to SDL(2n)-b: sub data lines SDL1-a, SDL1-b: the first sub-data line SDL2-a, SDL2-b: the second sub-data line SDL3-a, SDL3-b: the third sub-data line SDL4-a, SDL4-b: the fourth sub-data line GL: gate line GL1: the first gate line GL2: The second gate line GL3: The third gate line GL4: The fourth gate line PX: pixel SP: sub-pixel DATA: data voltage DATA1: first data voltage DATA2: second data voltage DATA3: the third data voltage DATA4: Fourth data voltage GATE: gate voltage GATE1: first gate voltage GATE2: the second gate voltage GATE3: the third gate voltage GATE4: The fourth gate voltage SWT: switching transistor SET: Sensing transistor DT: drive transistor SC: storage capacitor VSS: low potential voltage VSSL: low potential voltage line VDD: high potential voltage VDDL: high potential voltage line VDDL1: the first high potential voltage line VDDL2: the second high potential voltage line SVDDL1: The first sub high potential voltage line SVDDL2: Second sub high potential voltage line N1: the first node N2: second node N3: the third node Vref: reference voltage RVL: reference voltage line RVL1: the first reference voltage line RVL2: Second reference voltage line SRVL1: The first sub-reference voltage line SRVL2: The second sub-reference voltage line SENSE: Sensing signal R, W, B, G: sub-pixel H1: first horizontal period H2: second horizontal period SW1: first switching element SW2: second switching element CSL1: the first control signal line CSL2: The second control signal line MX: multiplexer SMX1: first sub-multiplexer SMX2: second sub multiplexer SMX3: The third sub-multiplexer SMX4: The fourth sub-multiplexer SW1-a: Switching element 1-a SW2-a: Switching element 2-a SW1-b: 1-b switching element SW2-b: 2-b switching element CS1-a, CS2-a, CS1-b, CS2-b, CS1-c, CS2-c, CS1-d, CS2-d: control signal RP: Repair pattern

The above and other aspects, features and other advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, wherein: FIG. 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure. FIG. 2 is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure. FIG. 3 is a block diagram for explaining a positional relationship of sub-pixels of a display device according to an exemplary embodiment of the present disclosure. FIG. 4 is a timing diagram of a gate voltage and a data voltage when a display device implements a freeze frame in monochrome according to an exemplary embodiment of the present disclosure. FIG. 5 is a timing diagram of gate voltages and data voltages when a display device according to an exemplary embodiment of the present disclosure implements a vertical pattern screen. FIG. 6 is a circuit diagram for explaining a multiplexer (MUX) of a display device according to another exemplary embodiment of the present disclosure. FIG. 7 is a circuit diagram for explaining a connection relationship between a plurality of sub-pixels and a multiplexer of a display device according to another exemplary embodiment of the present disclosure. FIG. 8 is a circuit diagram for explaining a multiplexer (MUX) of a display device according to still another exemplary embodiment of the present disclosure. FIG. 9 is a circuit diagram for explaining four sub-multiplexers of a display device according to still another exemplary embodiment of the present disclosure. FIG. 10 is a waveform diagram illustrating a control signal of a display device according to another exemplary embodiment of the present disclosure and yet another exemplary embodiment. FIG. 11 is a waveform diagram illustrating a data voltage of a display device according to another exemplary embodiment of the present disclosure and yet another exemplary embodiment. FIG. 12 is a diagram for explaining a positional relationship of sub-pixels of a display device according to still another exemplary embodiment (Example 4) of the present disclosure. FIG. 13 is a diagram for explaining changes in overlapping of sub-pixels of a display device according to still another exemplary embodiment (Example 4) of the present disclosure.

DL1: the first data line

DL2: the second data line

DL3: third data line

DL4: The fourth data line

SDL1-a, SDL1-b: the first sub-data line

SDL2-a, SDL2-b: the second sub-data line

SDL3-a, SDL3-b: the third sub-data line

SDL4-a, SDL4-b: the fourth sub-data line

VSS: low potential voltage

VSSL: low potential voltage line

VDD: high potential voltage

VDDL: high potential voltage line

VDDL1: the first high potential voltage line

VDDL2: the second high potential voltage line

SVDDL1: The first sub high potential voltage line

SVDDL2: Second sub high potential voltage line

GL1: the first gate line

GL2: The second gate line

GL3: The third gate line

GL4: The fourth gate line

PX: pixel

DATA1: first data voltage

DATA2: second data voltage

DATA3: the third data voltage

DATA4: Fourth data voltage

GATE1: first gate voltage

GATE2: the second gate voltage

GATE3: the third gate voltage

GATE4: The fourth gate voltage

RVL1: the first reference voltage line

RVL2: Second reference voltage line

SRVL1: The first sub-reference voltage line

SRVL2: The second sub-reference voltage line

R, B, G: sub-pixel

RP: Repair pattern

Claims (23)

A display device, comprising: a display panel, wherein a plurality of pixels are arranged; each of the pixels includes a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel; the first Each of the sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel is configured to emit light of different colors; a data driver is used to provide a data voltage to the the pixels; and a gate driver for providing a gate voltage to the pixels by using a plurality of gate lines, wherein each of the data lines is divided into a plurality of sub-data lines, and each of the sub-data lines The data line is connected to a plurality of sub-pixels with the same color, and each of the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel includes a switching transistor, a driving voltage Crystal, a storage capacitor, a sensing transistor and a light emitting diode. The display device as described in claim 1, wherein the plurality of first sub-pixels arranged in the pixels are arranged in the same row, and the plurality of second sub-pixels arranged in the pixels are arranged in the same row, set A plurality of third sub-pixels in the pixels are arranged in the same row, and a plurality of fourth sub-pixels in the pixels are arranged in the same row. The display device as claimed in claim 1, Wherein the first sub-pixel is a red sub-pixel, the second sub-pixel is a white sub-pixel, the third sub-pixel is a blue sub-pixel, and the fourth sub-pixel is a green sub-pixel. The display device according to claim 1, wherein the sub-data lines include: a plurality of first sub-data lines connected to a plurality of first sub-pixels arranged in the pixels, a plurality of second sub-data lines, connected to a plurality of second sub-pixels arranged in these pixels, a plurality of third sub-data lines connected to a plurality of third sub-pixels arranged in these pixels, and a plurality of fourth sub-data lines connected to A plurality of fourth sub-pixels disposed in the pixels. The display device according to claim 4, wherein one of the first sub-data lines and one of the second sub-data lines are arranged between the first sub-pixel and the second sub-pixel , and one of the third sub-data lines and one of the fourth sub-data lines are disposed between the third sub-pixel and the fourth sub-pixel. The display device as claimed in claim 1, wherein each of the pixels is connected to the same gate line. The display device according to claim 1, wherein two adjacent pixels are connected to different gate lines. The display device as claimed in claim 1, Wherein when the display panel implements a monochrome screen or a vertical pattern screen, the data voltage is continuously maintained in one frame. The display device as described in claim 1, wherein the display panel further includes: a plurality of reference voltage lines connected to the sensing transistor; and a plurality of high potential voltage lines connected to the driving transistor, and each of the The reference voltage lines are arranged in a pixel, and each of the high potential voltage lines is arranged between a plurality of adjacent pixels in the pixels. The display device as described in claim 1, further comprising: a multiplexer disposed between the data lines and the sub-data lines, and the multiplexer controls the data lines and the sub-data lines according to a control signal A connection relationship of the child data line. The display device according to claim 10, wherein the multiplexer includes: a plurality of first switching elements, connected to one data line of the data lines and any one of the sub-data lines according to a first control signal; and a plurality of second switching elements, connected to one data line of the data lines and another one of the sub-data lines according to a second control signal. The display device as claimed in claim 11, wherein the multiplexer is composed of a single multiplexer to apply a first control signal to the first switching elements and a second control signal to the second switch element. The display device as claimed in claim 11, Wherein the multiplexer is divided into a plurality of sub-multiplexers, each of the sub-multiplexers includes the first switching elements and the second switching elements, and a separate first control signal and a separate first control signal Two control signals are applied to each of the sub-multiplexers. A display device comprising: a display panel in which a plurality of sub-pixels of different colors are arranged; a data driver for providing a data voltage to the sub-pixels by using a plurality of data lines; and a gate driver for A gate voltage is provided to the sub-pixels by using a plurality of gate lines, wherein each of the data lines is divided into a plurality of sub-data lines, and each of the sub-data lines is connected to the sub-pixels with the same The sub-pixels of the color, the gate lines include: a first gate line, arranged on one side of a plurality of sub-pixels in a plurality of odd columns among the sub-pixels: a second gate line and a third gate line a gate line arranged between the sub-pixels arranged in the odd-numbered columns and a plurality of sub-pixels arranged in a plurality of even-numbered columns in the sub-pixels; and a fourth gate line arranged in the On the other side of the sub-pixels in the even-numbered columns, a plurality of sub-pixels arranged in a 12k-11th row to a 12k-6th row among the sub-pixels are arranged to be compared with the second gate line and the The third gate line is closer to the first gate line and the fourth gate line, and A plurality of sub-pixels arranged in a 12k-5th row to a 12kth row among the sub-pixels are arranged closer to the second gate line and the fourth gate line than the first gate line and the fourth gate line The third gate line, wherein k is 1 or a natural number greater than 1. The display device according to claim 14, wherein the sub-pixels arranged in one of the even columns from the 12k-11th row to the 12k-6th row are connected to the first gate line, And it is arranged to be closer to the first gate line than the second gate line, and the sub-pixels are arranged in the 12k-5th row to the 12kth row of one of the odd-numbered columns is connected to the second gate line and is disposed closer to the second gate line than to the first gate line. The display device according to claim 14, wherein the sub-pixels of the 12k-11th row to the 12k-6th row arranged in one of the even-numbered columns among the sub-pixels are connected to the first four gate lines disposed closer to the fourth gate line than the third gate line, and disposed in the 12k-5th row to the 12kth row of one of the odd-numbered columns The sub-pixels are connected to the third gate line and are arranged closer to the third gate line than to the fourth gate line. The display device according to claim 14, wherein among the sub-pixels, the 12k-11th row, the 12k-8th row, the 12k-5th row and the 12k-2nd row are arranged A sub-pixel is a plurality of blue sub-pixels, and among these sub-pixels, a plurality of sub-pixels arranged in the 12k-10th row, the 12k-7th row, the 12k-4th row and the 12k-first row The pixel is a plurality of green sub-pixels, and in Among the sub-pixels, the sub-pixels arranged in the 12k-9th row, the 12k-6th row, the 12k-third row and the 12k-th row are a plurality of red sub-pixels. The display device as claimed in claim 14, wherein a plurality of repair patterns are arranged on the sub-pixels from the 12k-11th row to the 12k-6th row of one of the odd-numbered columns and the sub-pixels arranged on the row 12k-6 Between the sub-pixels of the 12k-11th row to the 12k-6th row of one of the even-numbered columns. The display device as claimed in claim 14, wherein a plurality of repair patterns are arranged on one side of the sub-pixels from the 12k-5th row to the 12kth row in one of the odd columns, and It is disposed on the other side of the sub-pixels disposed in the 12k-5th row to the 12kth row in one of the even columns. The display device according to claim 14, wherein at least one high potential voltage line is arranged between the sub-pixels in the 12k-11th row to the 12k-6th row in one of the odd-numbered columns and It is disposed between the sub-pixels in the 12k-11th row to the 12k-6th row of one of the even-numbered columns. The display device according to claim 14, wherein at least one high potential voltage line is arranged on one side of the sub-pixels from the 12k-5th row to the 12kth row in one of the odd-numbered columns , and the other side of the sub-pixels disposed on the 12k-5th row to the 12kth row of one of the even-numbered columns. The display device as claimed in claim 14, Wherein at least one reference voltage line is arranged on one side of the sub-pixels from the 12k-11th row to the 12k-6th row of one of the odd-numbered columns, and on the side of the even-numbered columns The other side of the sub-pixels of the 12k-11th row to the 12k-6th row of one of them. The display device as described in claim 14, wherein at least one high potential voltage line is arranged on the sub-pixels from the 12k-5th row to the 12kth row in one of the odd-numbered columns and the Between the sub-pixels of the 12k-5th row to the 12kth row of one of the even-numbered columns.

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