KR20200050871A - Liquid crystal display device and method of driving thereof - Google Patents

Abstract

A liquid crystal display device according to one embodiment of the present invention includes: a plurality of pixel units including sub-pixels arranged in a 2x4 matrix form; a first data line disposed on a first side of a plurality of sub-pixels in a first column; a second data line disposed between a plurality of sub-pixels of a second column and a plurality of sub-pixels of a third column; and a third data line disposed on a second side of a plurality of sub-pixels of a fourth column, wherein each of the plurality of pixel units includes a first sub-pixel unit including a first sub-pixel disposed in a first row and a first column and a second sub-pixel disposed in a first row and a second column, a second sub-pixel unit including a third sub-pixel disposed in a first row and a third column and a fourth sub-pixel disposed in a first row and a fourth column, a third sub-pixel unit including a fifth sub-pixel disposed in a second row and a first column and a sixth sub-pixel disposed in a second row and a second column, and a fourth sub-pixel unit including a seventh sub-pixel disposed in a second row and a third column and an eighth sub-pixel disposed in a second row and a fourth column, and wherein the sixth sub-pixel is connected to the first data line, the fifth sub-pixel is connected to the second data line, the fourth sub-pixel is connected to the second data line, and the third sub-pixel is connected to the third data line, thereby improving image quality issues occurring in a DRD column inversion structure, so that the display quality is improved.

Description

Liquid crystal display device and its driving method {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF DRIVING THEREOF}

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device having a double rate driving (DRD) structure in which the number of data lines is halved and a driving method thereof.

In recent years, as the society has entered a full-fledged information age, the display field that processes and displays a large amount of information has rapidly developed, and recently, a thin film transistor (Thin Film Transistor) with excellent performance in light weight, thinness, and low power consumption has been developed. ; TFT) Liquid Crystal Display (LCD) was developed to replace the existing cathode ray tube (CRT).

An active matrix type liquid crystal display device in which a thin film transistor (TFT) is used as a switching element is suitable for displaying a dynamic image.

An active matrix type liquid crystal display device includes a liquid crystal panel composed of a plurality of thin film transistors provided at intersections of a plurality of gate lines and data lines, and the liquid crystal panel converts a digital video signal into an analog signal based on gamma voltage. By supplying the data signal to the data line and supplying the gate signal to the gate line, the data signal is charged in the liquid crystal cell.

The gate electrode of the thin film transistor is connected to the gate line, the source electrode is connected to the data line, and the drain electrode of the thin film transistor is connected to the pixel electrode of the liquid crystal cell.

The common voltage is supplied to the common electrode of the liquid crystal cell through the vertical common line. When the gate signal is applied to the gate line, the thin film transistor is turned on to form a channel between the source electrode and the drain electrode to supply the voltage on the data line to the pixel electrode of the liquid crystal cell. At this time, the liquid crystal molecules of the liquid crystal cell are arranged by an electric field between the pixel electrode and the common electrode, and an image according to incident light is displayed.

At this time, a twisted nematic (TN) mode or an in-plane switching (IPS) mode, which is a driving mode of the liquid crystal display device, is determined according to the positions of the common electrode and the pixel electrode of the liquid crystal panel. The IPS mode in which the electrode and the pixel electrode are disposed in parallel on one substrate to form a horizontal electric field has a wide viewing angle compared to a TN mode in which a vertical electric field is formed.

On the other hand, the liquid crystal panel of the liquid crystal display device is connected to a gate driving unit for driving a plurality of gate lines and a data driving unit for driving a plurality of data lines, and an integrated circuit constituting a driving unit required as the liquid crystal display becomes larger and higher in resolution. The number of (Integrated Circuit; IC) will increase.

In addition, since the IC of the data driver is relatively expensive compared to other devices, recently, a technology that can reduce the number of ICs is being researched and developed in order to lower the production cost of the liquid crystal display device. A double rate driving (DRD) structure has been developed to realize the same resolution as the previous one while halving the number of required ICs by halving the number of data lines by half, instead of doubling it.

The problem to be solved by the present invention is to provide a liquid crystal display device that applies column inversion in a double rate driving (DRD) driving method and a driving method thereof.

Another problem to be solved by the present invention is to provide a liquid crystal display device driven by a DRD method while minimizing a decrease in aperture ratio and a driving method thereof.

Another problem to be solved by the present invention is to provide a liquid crystal display device and a driving method thereof, which improve image quality issues occurring in a DRD column inversion structure.

Another problem to be solved by the present invention is to provide a liquid crystal display device using a color filter on TFT (COT) structure in which a color filter is formed on a TFT of an array substrate and a driving method thereof.

The problems of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

In order to solve the problems as described above, a liquid crystal display device according to an exemplary embodiment of the present invention includes a plurality of pixel units including sub-pixels arranged in a 2 x 4 matrix form, and a plurality of sub-pixels in a first column. A first data line disposed on the first side, a second data line disposed between the plurality of sub-pixels in the second column and a plurality of sub-pixels in the third column, and a second side of the plurality of sub-pixels in the fourth column A first sub-pixel unit including a third data line disposed, each of the plurality of pixel units including a first sub-pixel disposed in one row and one column and a second sub-pixel disposed in one row and two columns , A second sub-pixel unit including a third sub-pixel disposed in row 1 and column 3 and a fourth sub-pixel disposed in row 1 and column 4, a fifth sub-pixel disposed in row 2, column 1, and row 2 in column 2 A third sub-pixel unit including the arranged sixth sub-pixel and a seventh sub-picture arranged in row 2 and column 3 And a fourth sub-pixel unit including an eighth sub-pixel disposed in the second row and fourth column, wherein the sixth sub-pixel is connected to the first data line, and the fifth to the second data line. A sub-pixel may be connected, the fourth sub-pixel may be connected to the second data line, and the third sub-pixel may be connected to the third data line.

Details of other embodiments are included in the detailed description and drawings.

The present invention provides an effect of lowering the production cost of a liquid crystal display device by applying a DRD structure in which the number of data lines is halved.

The present invention can improve the luminous efficiency of a liquid crystal display device by arranging a plurality of transistors adjacent to each other to increase the aperture ratio. In addition, according to the present invention, by disposing adjacent transistors in diagonal directions, the non-opening area can be dispersed as much as possible, thereby minimizing image quality defects that may occur due to agglomeration of transistors.

The present invention provides an effect of improving display quality by improving image quality issues occurring in a DRD column inversion structure. That is, in the present invention, the polarities of adjacent sub-pixels are all different, and even when the image quality is confirmed at a certain viewing angle, the image quality defects such as defects in purlins are not generated. In addition, the present invention can prevent a defect in purlining due to coupling with an adjacent gate line when a pixel is charged, and minimize overlap variation of a GIP (Gate in Panel) -array internal link. In addition, the present invention can prevent the generation of zig-zag-shaped brick-like patterns and vertical lines by placing the thin film transistors in a 2 x 4 sub-pixel in a symmetrical, origin that is inverted vertically.

The effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the present specification.

1 is a block diagram showing a liquid crystal display device according to the present invention.
2 is a view for explaining a display panel of a liquid crystal display device according to a first embodiment of the present invention.
3A and 3B are diagrams illustrating a pixel unit of a liquid crystal display according to a first embodiment of the present invention.
4 is a timing diagram for describing the data voltage of the liquid crystal display according to the first embodiment of the present invention.
5 is a view for explaining a data voltage applied to a sub-pixel of a liquid crystal display according to a first embodiment of the present invention.
6 is a plan view showing a structure of an array substrate of a liquid crystal display according to a second embodiment of the present invention.
7 exemplarily shows a pixel structure of a liquid crystal display according to a second embodiment of the present invention.
8A and 8B are diagrams showing an example of a pixel structure and a driving method of the liquid crystal display according to the second embodiment of the present invention.
9 is a plan view illustrating a portion of a pixel of a liquid crystal display according to a second embodiment of the present invention as an example.
FIG. 10 is a view showing a cross-section cut along the line A-A 'in the liquid crystal display device according to the second embodiment of the present invention shown in FIG. 9.
11 is a view showing another cross-section of a liquid crystal display according to a second embodiment of the present invention as an example.
12 is a plan view illustrating a portion of a pixel of a liquid crystal display according to a third embodiment of the present invention as an example.
13 is a diagram illustrating a cross-section cut along the line B-B 'in the liquid crystal display device according to the third embodiment of the present invention shown in FIG. 12.
14 is a diagram illustrating another cross-section of a liquid crystal display device according to a third exemplary embodiment of the present invention.
15 is a view showing a cross-section of a liquid crystal display device according to a fourth embodiment of the present invention as an example.
16 is a plan view illustrating a portion of a pixel of a liquid crystal display according to a fifth embodiment of the present invention as an example.
FIG. 17 is a diagram illustrating a cross-section cut along line C-C 'in the liquid crystal display device according to the fifth embodiment of the present invention shown in FIG. 16.
18 is a view showing a cross-section of a liquid crystal display device according to a sixth embodiment of the present invention as an example.
19 is a view for showing a driving method according to a comparative example.
20 is a view for showing a driving method according to an embodiment.
21 is a view for showing a driving method according to another embodiment.
22 is a diagram illustrating an example of a GIP-array internal link design according to an embodiment.
23 is a diagram showing an example of a GIP-array internal link design according to another embodiment.

Advantages and features of the present invention, and a method of achieving them will be apparent by referring to embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different shapes, and only the present embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention pertains. It is provided to completely inform the person having the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for describing the embodiments of the present invention are exemplary, and the present invention is not limited to the illustrated matters. The same reference numerals refer to the same components throughout the specification. In addition, in the description of the present invention, when it is determined that detailed descriptions of related known technologies may unnecessarily obscure the subject matter of the present invention, detailed descriptions thereof will be omitted. In the present invention, when the above-mentioned 'include', 'have', 'consist of' is used, other parts may be added unless '~ man' is used. When a component is expressed as a singular number, the plural number is included unless otherwise specified.

In interpreting the components, it is interpreted as including the error range even if there is no explicit description.

In the case of the description of the positional relationship, for example, if the positional relationship of the two parts is described as '~ above', '~ above', '~ below', '~ next to', etc., 'right' or One or more other parts may be placed between the two parts unless 'direct' is used.

An element or layer being referred to as being "on" another element or layer includes all instances of other layers or other elements immediately above or in between.

Also, the first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another component. Accordingly, the first component mentioned below may be the second component within the technical spirit of the present invention.

The same reference numerals refer to the same components throughout the specification.

The area and thickness of each configuration shown in the drawings are shown for convenience of description, and the present invention is not necessarily limited to the area and thickness of the configuration.

Each of the features of the various embodiments of the present invention may be partially or wholly combined or combined with each other, technically various interlocking and driving is possible, and each of the embodiments may be independently performed with respect to each other or may be implemented together in an association relationship. It might be.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a liquid crystal display device according to the present invention.

Referring to FIG. 1, the liquid crystal display device according to the present invention may include a display panel 100 in which a plurality of pixels P are arranged in a matrix form and a driving circuit driving the display panel 100. The driving circuit for driving the display panel 100 may include a data driving circuit 200, a gate driving circuit 300 and a timing control circuit 400.

Looking at the display panel 100, various wirings that transmit driving signals for driving the pixels P may be formed on the display panel 100.

In this case, as an example, each of the plurality of data lines DL transmitting the data voltage may be extended along a column (or column) line direction to be connected to the pixel P of the corresponding column line. Further, each of the plurality of gate lines GL transferring the gate voltage may be extended along the row (or row) line direction to be connected to the pixel P of the corresponding row line.

The timing control circuit 400 may control driving timings of the data driving circuit 200 and the gate driving circuit 300. The timing control circuit 400 may rearrange digital data (RGB) input from an external system according to the resolution of the display panel 100 and supply it to the data driving circuit 200.

In addition, the timing control circuit 400 is based on the timing signals of the vertical synchronization signal (Vsync), the horizontal synchronization signal (Hsync), the clock signal (CLK) and the data enable signal (DE) of the data driving circuit (200) The data control signal DCS for controlling the operation timing and the gate control signal GCS for controlling the operation timing of the gate driving circuit 300 may be generated.

The data driving circuit 200 drives the data line DL. That is, the data driving circuit 200 may convert the input digital data RGB based on the data control signal DCS into an analog data voltage and supply it to the corresponding data line DL.

The gate driving circuit 300 drives the gate line GL. That is, the gate driving circuit 300 may generate a gate voltage based on the gate control signal GCS and supply it to the gate line GL in a line sequential manner.

In the liquid crystal display according to the present invention, instead of doubling the number of gate lines GL compared to the existing one, the number of data lines DL is reduced by 1/2, and the required number of ICs is halved while the same resolution as before. It may be configured as a DRD (Double Rate Driving) structure that implements.

In addition, the liquid crystal display device according to the present invention may be configured as a color filter on TFT (COT) structure in which a color filter is formed with a thin film transistor on an array substrate, but is not limited thereto.

In the liquid crystal display device of the COT structure, since the color filter is formed on the array substrate on which the thin film transistor is formed, the adhesion margin considered in the process of bonding the color filter substrate and the array substrate can be reduced, thereby improving the aperture ratio.

Hereinafter, a part of the display panel 100 of the liquid crystal display device according to the first embodiment of the present invention is taken as an example, and the connection relationship between the components of the display panel 100 of the liquid crystal display device according to the first embodiment of the present invention To explain.

2 is a view for explaining the display panel 100 of the liquid crystal display according to the first embodiment of the present invention.

As described above, the display panel 100 of the liquid crystal display device according to the first embodiment of the present invention includes a plurality of data lines DL1 to DL5, a plurality of gate lines GL1 to GL8, and a plurality of sub-pixels. (SP11 to SP48) and a plurality of thin film transistors (T11 to T48) for driving the plurality of sub-pixels (SP11 to SP48).

For example, referring to FIG. 2, the first data lines to the fifth data lines DL1 to DL5 are arranged in the column direction in the display panel 100, and the first to eighth gate lines GL1 in the row direction. To GL8). However, the present invention is not limited thereto.

Each of the first data line to the fifth data line DL1 to DL5 is disposed for each of a plurality of sub-pixels SP11 to SP48 arranged in two columns.

The first data line DL1 is disposed on the first side that is the left side of the plurality of sub-pixels SP11, SP21, SP31, and SP41 in the first column, and the plurality of sub-pixels SP12, SP22, SP32 in the second column, A second data line DL2 is disposed between the SP42) and a plurality of sub-pixels SP13, SP23, SP33, SP43 in the third column, and a plurality of sub-pixels SP14, SP24, SP34, SP44 in the fourth column. The third data line DL3 is disposed on the right side of the second side.

In other words, the plurality of sub-pixels in the first column SP11, SP21, SP31, SP41 and the plurality of sub-pixels in the second column arranged in two columns between the first data line DL1 and the second data line DL2. A plurality of sub-pixels SP13, SP23, SP33, SP43 arranged in two columns (SP12, SP22, SP32, SP42) are disposed, and between the second data line DL2 and the third data line DL3 ) And a plurality of sub-pixels SP14, SP24, SP34, SP44 in the fourth row.

Data lines after the fourth data line DL4 may also be arranged in the same manner as the first data line to the third data line DL1 to DL3.

Here, the plurality of sub-pixels in the first column (SP11, SP21, SP31, SP41), the plurality of sub-pixels in the fourth column (SP14, SP24, SP34, SP44), and the plurality of sub-pixels in the seventh column (SP17, SP27, SP37 and SP47) may be red sub-pixels (R) that embody red. Then, a plurality of sub-pixels in the second column (SP12, SP22, SP32, SP42), a plurality of sub-pixels in the fifth column (SP15, SP25, SP35, SP45), and a plurality of sub-pixels in the eighth column (SP18, SP28) , SP38) may be a green sub-pixel (G) that implements green. Further, the plurality of sub-pixels in the third column (SP13, SP23, SP33, SP43) and the plurality of sub-pixels in the sixth column (SP16, SP26, SP36, SP46) are blue sub-pixels (B) that embody blue. Can be.

The first to eighth gate lines GL1 to GL8 may be disposed on both sides of a plurality of sub-pixels SP11 to SP48 in each row.

Specifically, the first gate line GL1 is disposed on the third side, which is the upper side of the plurality of sub-pixels SP11 to SP18 in the first row, and the lower side of the plurality of sub-pixels SP11 to SP18 in the first row. A second gate line GL2 may be disposed on the phosphorus fourth side. Further, a third gate line GL3 is disposed on a third side of the plurality of sub-pixels SP21 to SP28 in the second row, and a fourth that is the lower side of the plurality of sub-pixels SP21 to SP28 in the second row. A fourth gate line GL4 may be disposed on the side. In addition, a fifth gate line GL5 is disposed on a third side that is an upper side of the plurality of sub-pixels SP31 to SP38 in the third row, and a lower side of the plurality of sub-pixels SP31 to SP38 in the third row. The sixth gate line GL6 may be disposed on the fourth side. Further, a seventh gate line GL7 is disposed on the third side of the plurality of sub-pixels SP41 to SP48 in the fourth row, and the fourth is the lower side of the plurality of sub-pixels SP41 to SP48 in the fourth row. An eighth gate line GL8 may be disposed on the side.

Here, for convenience of description, the plurality of sub-pixels SP11 to SP48 defined in the display panel 100 include a plurality of pixel units including a plurality of sub-pixels SP41 to SP48 arranged in a 2 x 4 matrix form ( PU1 to PU4).

Specifically, the sub-pixels of the first to fourth columns in the first row (SP11, SP12, SP13, SP14) and the sub-pixels of the first to fourth columns in the second row (SP21, SP22, SP23, SP24) May constitute the first pixel unit PU1, and the sub-pixels SP15, SP16, SP17, and SP18 in the fifth to eighth columns in the first row and the fifth through eighth sub in the second row -The pixels SP25, SP26, SP27, and SP28 may constitute the second pixel unit PU2. In addition, the sub-pixels of the first to fourth columns (SP31, SP32, SP33, SP34) in the third row and the sub-pixels of the first to fourth columns (SP41, SP42, SP43, SP44) in the fourth row are The third pixel unit PU3 may be configured, and the third column to the eighth column sub-pixels SP35, SP36, SP37, SP38, and the fourth column to eighth column sub-pixels in the third row. The pixels SP45, SP46, SP47, and SP48 may constitute the fourth pixel unit PU4.

In the liquid crystal display device according to the first embodiment of the present invention, the connection relationship between the sub-pixels SP11 to SP48 of the entire display panel 100 and the gate lines GL1 to GL8 and the data lines DL1 to DL5 is Since one sub-pixel unit PU1 is in a repeated form, the first pixel unit PU1 will be described in detail below.

3A and 3B are diagrams illustrating a pixel unit of a liquid crystal display according to a first embodiment of the present invention.

Specifically, FIG. 3A is a circuit diagram for explaining a connection relationship of sub-pixels in a pixel unit, and FIG. 3B shows an example of an actual sub-pixel of a pixel unit.

Referring to FIG. 3A, the first pixel unit PU1 of the liquid crystal display according to the first embodiment of the present invention includes a plurality of sub-pixels SP11 to SP24 arranged in a 2 x 4 matrix form. Can be deployed.

In addition, the first pixel unit PU1 may include a plurality of sub-pixel units SPU1 to SPU4 including a plurality of sub-pixels SP11 to SP24 arranged in a 1 x 2 matrix form.

Specifically, the first pixel unit PU1 includes a first sub-pixel unit including a first sub-pixel SP11 arranged in one row and one column and a second sub-pixel SP12 arranged in one row and two columns. (SPU1), a second sub-pixel unit (SPU2) including a third sub-pixel (SP13) arranged in a row 1 and 3 columns and a fourth sub-pixel (SP14) arranged in a 1 row and 4 columns, 2 rows and 1 columns A third sub-pixel unit (SPU3) including a fifth sub-pixel (SP21) disposed and a sixth sub-pixel (SP22) disposed in a second row and second column, and a seventh sub-pixel (2) placed in a second row and third column ( SP23) and a fourth sub-pixel unit SPU4 including the eighth sub-pixel SP24 disposed in the second row and fourth column.

In addition, each of the sub-pixels SP11 to SP24 may be connected one-to-one with a plurality of thin film transistors T11 to T24 for driving.

Specifically, the gate electrode of the first thin film transistor T11 driving the first sub-pixel SP11 is connected to the first gate line GL1, and the source electrode of the first thin film transistor T11 is the first data The drain electrode of the first thin film transistor T11 is connected to the line DL1 and the pixel electrode of the first sub-pixel SP1. The gate electrode of the second thin film transistor T12 driving the second sub-pixel SP12 is connected to the first gate line GL1, and the source electrode of the second thin film transistor T12 is the second data line. (DL2) and the drain electrode of the second thin film transistor T12 is connected to the pixel electrode of the second sub-pixel SP12. In addition, the gate electrode of the third thin film transistor T13 driving the third sub-pixel SP13 is connected to the second gate line GL2, and the source electrode of the third thin film transistor T13 is the third data line. (DL3) and the drain electrode of the third thin film transistor T13 is connected to the pixel electrode of the third sub-pixel SP3. The gate electrode of the fourth thin film transistor T14 driving the fourth sub-pixel SP14 is connected to the second gate line GL2, and the source electrode of the fourth thin film transistor T14 is the second data line. (DL2), and the drain electrode of the fourth thin film transistor T14 is connected to the pixel electrode of the fourth sub-pixel SP14. In addition, the gate electrode of the fifth thin film transistor T21 driving the fifth sub-pixel SP21 is connected to the fourth gate line GL4, and the source electrode of the fifth thin film transistor T21 is the second data line. (DL2), and the drain electrode of the fifth thin film transistor T21 is connected to the pixel electrode of the fifth sub-pixel SP21. The gate electrode of the sixth thin film transistor T22 driving the sixth sub-pixel SP22 is connected to the fourth gate line GL4, and the source electrode of the sixth thin film transistor T22 is the first data line. (DL1) and the drain electrode of the sixth thin film transistor T22 is connected to the pixel electrode of the sixth sub-pixel SP22. In addition, the gate electrode of the seventh thin film transistor T23 driving the seventh sub-pixel SP23 is connected to the third gate line GL3, and the source electrode of the seventh thin film transistor T23 is the second data line. (DL2), and the drain electrode of the seventh thin film transistor T23 is connected to the pixel electrode of the seventh sub-pixel SP23. The gate electrode of the eighth thin film transistor T24 driving the eighth sub-pixel SP24 is connected to the third gate line GL3, and the source electrode of the eighth thin film transistor T24 is the third data line. (DL3), and the drain electrode of the eighth thin film transistor T24 is connected to the pixel electrode of the eighth sub-pixel SP24.

Also, the third thin film transistor T13 and the fourth thin film transistor T14 of the second sub-pixel unit SPU2 and the seventh thin film transistor T23 and the eighth thin film transistor of the fourth sub-pixel unit SPU4. (T24) may be disposed adjacent to each other.

Specifically, the third thin film transistor T13 and the fourth thin film transistor T14 may be disposed adjacent to and connected to the second gate line GL2, and the seventh thin film transistor T23 and the eighth thin film transistor T24. May be disposed adjacent to and connected to the third gate line GL3. In addition, since the second gate line GL2 and the third gate line GL3 are disposed adjacently, the third thin film transistor T13, the fourth thin film transistor T14, the seventh thin film transistor T23, and the eighth thin film Transistors T24 may be disposed adjacent to each other.

3B, in the liquid crystal display according to the first embodiment of the present invention, four adjacent thin film transistors T13, T14, T23, and T24 are disposed in the non-transmissive region NTA. Due to the adjacent thin film transistors T13, T14, T23, and T24, light incident from the rear side does not transmit to the front side.

However, in the conventional liquid crystal display, thin film transistors connected to respective sub-pixels are not adjacent to each other and are separately arranged. Accordingly, the non-transmissive region is relatively increased due to the separated thin film transistors, and in the case of the conventional liquid crystal display, the aperture ratio is only about 68%.

However, in the case of the liquid crystal display device according to the first exemplary embodiment of the present invention, the thin film transistors T13, T14, T23, and T24 that block light incident from the rear surface are densely arranged, so that the thin film transistors T13, T14, T23 , T24) may reduce the ratio of the non-transmissive area NTA. Accordingly, the aperture ratio of the liquid crystal display according to the first embodiment of the present invention is improved to about 71%.

By increasing the aperture ratio of the liquid crystal display device according to the first embodiment of the present invention, it is possible to improve the luminous efficiency of the liquid crystal display device.

In addition, as shown in FIGS. 2 and 3A, four adjacent thin film transistors are not disposed adjacent to each other.

Specifically, in the above-described first pixel unit PU1, the thin film transistors T13 and T14 of the second sub-pixel unit SPU2 and the thin film transistors T23 and T24 of the fourth sub-pixel unit SPU4 are One non-opening area is formed adjacent to each other.

In addition, the thin film transistor of the first sub-pixel unit in the second pixel unit PU2 is not continuous with the four thin film transistors T13, T14, T23, and T24 adjacent to the first pixel unit PU1 described above. T15 and T16) and the thin film transistors T25 and T26 of the third sub-pixel are not adjacent to each other, but the thin film transistors T17 and T18 of the second sub-pixel unit and the fourth sub-pixel T27 and T28. The thin film transistors are adjacent to each other.

In addition, the thin film transistor of the second sub-pixel unit in the third pixel unit PU3 is not continuous with the four thin film transistors T13, T14, T23, and T24 adjacent to the first pixel unit PU1 described above. T33 and T34) and the thin film transistors T43 and T44 of the fourth sub-pixel are adjacent to each other.

In other words, the four adjacent thin film transistors described above may not be continuously arranged in a linear direction, but may be arranged to be crossed in a diagonal direction.

Specifically, the thin film transistors arranged in the first column to the second column in the second row, arranged in diagonal directions with the four thin film transistors T13, T14, T23, and T24 adjacent to the first pixel unit PU1 described above. The thin film transistors T31 and T32 arranged in the first column to the second column in the (T21, T22) and the third row may be disposed adjacent to each other. In addition, the thin film transistors arranged in the fifth to sixth columns in the second row, disposed in diagonal directions different from the four thin film transistors T13, T14, T23, and T24 adjacent to the first pixel unit PU1 described above. The thin film transistors T35 and T36 arranged in the fifth to sixth columns in (T25, T26) and the third row may also be disposed adjacent to each other.

In this way, a plurality of adjacent thin film transistors are not continuously arranged in the linear direction, so that the non-opening regions are not continuously arranged in the linear direction. Accordingly, a screen abnormality such as a vertical line that may occur due to the continuous non-opening area is not generated. In other words, by disposing four adjacent thin film transistors in diagonal directions, the non-aperture region can be dispersed as much as possible, thereby minimizing image quality defects that may occur due to agglomeration of the thin film transistors.

In addition, in the liquid crystal display according to the first embodiment of the present invention, some of the plurality of sub-pixel units SPU1 to SPU4 intersect adjacent data lines of the first data line to the third data line DL1 to DL3. Can be connected.

As an example, as shown in FIGS. 3A and 3B, the second sub-pixel unit SPU2 and the fourth sub-pixel unit SPU4 are adjacent among the first data line to the third data line DL1 to DL3. Data lines can be cross-connected.

Specifically, as described above, in the second sub-pixel unit SPU2, the third thin film transistor T13 is connected to the third data line DL3 that is not connected to the adjacent second data line DL2. In addition, the fourth thin film transistor T14 may also be connected to the second data line DL2 rather than to the adjacent third data line DL3.

Further, in the third sub-pixel unit SPU3, the fifth thin film transistor T21 is connected to the second data line DL2, not to the adjacent first data line DL1, and the sixth thin film transistor The T22 may also be connected to the first data line DL1 rather than to the adjacent second data line DL2.

Referring again to the data line reference and the sub-pixel reference, the first data line DL1 and the first sub-pixel SP11 and the sixth sub-pixel SP22 are connected, and the second data line DL2 is connected. The fourth sub-pixel SP14 and the fifth sub-pixel SP21 may be connected, and the third data line DL3 and the third sub-pixel SP13 and the eighth sub-pixel SP24 may be connected. .

In this way, in the liquid crystal display device according to the first embodiment of the present invention, some sub-pixel units cross-connect with adjacent data lines, so that when applying the column inversion method as described below, data of each sub-pixel The polarity of the voltage and the polarity of the data voltage of the adjacent sub-pixels are different. Accordingly, the agglomeration of sub-pixels charged with the same polarity is eliminated, thereby improving the image quality. Details of this will be described later with reference to FIG. 5.

Hereinafter, a driving method of the liquid crystal display device according to the first embodiment of the present invention will be described.

4 is a timing diagram for describing the data voltage of the liquid crystal display according to the first embodiment of the present invention.

5 is a view for explaining a data voltage applied to a sub-pixel of a liquid crystal display according to a first embodiment of the present invention.

As described above, the display device according to the first embodiment of the present invention is driven by a double rate driving (DRD) method and column inversion is applied.

Referring to FIG. 2 with respect to the double rate driving (DRD) method, data lines DL1 to DL5 are arranged for each of a plurality of sub-pixels SP11 to SP48 arranged in two columns, thereby comparing data lines DL1 to DL5 as compared to the conventional method. ) May be reduced to half, but the gate lines GL1 to GL8 may be doubled between the plurality of sub-pixels SP11 to SP48, thereby doubling the gate lines GL1 to GL8.

Accordingly, in order to achieve the same resolution as the existing data lines DL1 to DL5 are reduced in half, the driving frequency is doubled.

With respect to the column inversion scheme, the polarity of the data voltage Vdata applied to one data line DL1 to DL5 during one frame remains the same.

Referring to FIG. 4, a positive polarity data voltage Vdata may be applied to the odd-numbered data lines DL (2n-1) during a plurality of horizontal periods H of one frame, and even-numbered data lines A data voltage Vdata of negative polarity may be applied to (DL (2n)). Here, n means a natural number.

For example, when the common voltage is assumed to be 8V, the odd-numbered data line DL (2n-1) may be applied with a positive polarity data voltage Vdata of 8V to 16V, and the even-numbered data line DL A data voltage Vdata having a negative polarity of 0V to 8V may be applied to (2n)).

In addition, in the liquid crystal display device according to the first embodiment of the present invention, the data voltage Vdata of the same polarity applied to each data line DL1 to DL5 is charged in a dummy period before the first horizontal period H Can be. Accordingly, when the first horizontal period H starts, the data voltages Vdata are completely charged in the data lines DL1 to DL5, and the same polarity occurs during one frame while the data voltages Vdata are fully charged. As it is maintained, when the data voltage Vdata is applied to each sub-pixel SP11 to SP48, the problem of charging failure of the data voltage Vdata does not occur.

In contrast, the conventional liquid crystal display device uses an inversion method of converting the polarity of the data voltage Vdata every four horizontal periods. In this case, since the polarity of the data voltage Vdata needs to be changed every four horizontal periods, the sub-pixels charged after the polarity change in the middle of one frame cannot fully charge the data voltage Vdata, so that unwanted grayscale There was a problem expressed. Due to this sub-pixel incomplete filling, an unintended vertical dotted shape may be recognized.

However, since the liquid crystal display according to the first embodiment of the present invention applies column inversion in a double rate driving (DRD) driving method, the data voltage Vdata maintains the same polarity during one frame. , Polarity is not converted in the middle of one frame. Accordingly, all of the data voltages Vdata charged in the sub-pixels SP11 to SP48 are completely charged, thereby improving screen defects such as vertical dotted lines, thereby improving the uniformity of image quality.

Specifically, in relation to the uniformity of image quality, the conventional liquid crystal display device has a low charging rate of 91.63% due to a charging delay of the data voltage, but the liquid crystal display device according to the first embodiment of the present invention has a data voltage (Vdata). There was almost no charging delay, so the lowest charging rate rose to 94.38%. Accordingly, in the liquid crystal display according to the first embodiment of the present invention, since the lowest charge rate is increased, the difference between the highest charge rate and the lowest charge rate is further reduced, so that uniformity of image quality can also be increased.

In addition, since the liquid crystal display according to the first embodiment of the present invention applies column inversion in a double rate driving (DRD) driving method, the data voltage Vdata maintains the same polarity during one frame. , The variation range of each data voltage Vdata is between 0V to 8V when a negative polarity data voltage Vdata is applied, and between 8V to 16V when a positive polarity data voltage Vdata is applied. Can be

In this regard, since the polarity of the data voltage of the conventional liquid crystal display device needs to be changed even within one frame, the range of change of the data voltage may be 0V to 16V. Accordingly, since the change range of the data voltage of the display device 100 according to an embodiment of the present invention is narrower than the change range of the data voltage of the conventional liquid crystal display device, the heat generation level of the display device may be reduced.

Specifically, in the case of a full-white gradation in the conventional liquid crystal display, the temperature may be increased to 139 ° C, but in the case of the full-white gradation, the liquid crystal display according to the first embodiment of the present invention is only raised to 61 ° C, It can be seen that the fever level was reduced.

Hereinafter, for convenience of explanation related to a rendering order of the liquid crystal display according to the first embodiment of the present invention, the second data line DL2 and the positive polarity to which the negative polarity data voltage Vdata is applied The sub-pixel connected to the third data line DL3 to which the data voltage Vdata is applied will be mainly described.

During the first horizontal period, a gate high voltage is applied to the first gate line GL1, and a negative polarity data voltage through the second data line DL2 is applied to the sub-pixel SP12 disposed in one row and two columns ( Vdata) is applied, and a positive polarity data voltage Vdata is applied to the sub-pixel SP15 arranged in row 1 and column 5 through the third data line DL3.

In addition, during the second horizontal period, a gate high voltage is applied to the second gate line GL2 and data of negative polarity is applied to the sub-pixel SP14 disposed in the first row and fourth column through the second data line DL2. The voltage Vdata is applied, and a positive polarity data voltage Vdata is applied to the sub-pixel SP13 arranged in one row and three columns through the third data line DL3.

In addition, during the third horizontal period, a gate high voltage is applied to the third gate line GL3, and data of negative polarity is applied to the sub-pixel SP23 disposed in the second row and third column through the second data line DL2. The voltage Vdata is applied, and a positive polarity data voltage Vdata is applied to the sub-pixel SP24 arranged in 2 rows and 4 columns through the third data line DL3.

In addition, during the fourth horizontal period, a gate high voltage is applied to the fourth gate line GL4, and data of negative polarity is applied to the sub-pixel SP21 disposed in the second row and one column through the second data line DL2. The voltage Vdata is applied, and a positive polarity data voltage Vdata is applied to the sub-pixel SP26 arranged in 2 rows and 6 columns through the third data line DL3.

In addition, during the fifth horizontal period, a gate high voltage is applied to the fifth gate line GL5, and data of negative polarity is applied to the sub-pixel SP32 disposed in the third row and second column through the second data line DL2. The voltage Vdata is applied, and a positive polarity data voltage Vdata is applied to the sub-pixel SP35 arranged in 3 rows and 5 columns through the third data line DL3.

In addition, during the sixth horizontal period, the gate high voltage is applied to the sixth gate line GL6, and data of negative polarity is applied to the sub-pixel SP34 disposed in the third row and fourth column through the second data line DL2. The voltage Vdata is applied, and a positive polarity data voltage Vdata is applied to the sub-pixel SP33 arranged in 3 rows and 3 columns through the third data line DL3.

In addition, during the seventh horizontal period, a gate high voltage is applied to the seventh gate line GL7, and data of negative polarity is applied to the sub-pixel SP43 disposed in the fourth row and third column through the second data line DL2. The voltage Vdata is applied, and a positive polarity data voltage Vdata is applied to the sub-pixel SP44 arranged in 4 rows and 4 columns through the third data line DL3.

In addition, during the eighth horizontal period, a gate high voltage is applied to the eighth gate line DL8, and data of negative polarity is applied to the sub-pixel SP41 disposed in the fourth row and one column through the second data line DL2. The voltage Vdata is applied, and a positive polarity data voltage Vdata is applied to the sub-pixel SP46 arranged in 4 rows and 6 columns through the third data line DL3.

Due to this charging method, the polarity of the data voltage Vdata charged in each sub-pixel is different from the polarity of the data voltage Vdata charged in the sub-pixel adjacent thereto. That is, there is no aggregation of sub-pixels charged with the same polarity in the liquid crystal display according to the first embodiment of the present invention.

In addition, in the case of the conventional liquid crystal display device, four sub-pixels are charged with the same polarity, and thus, a defect in the purlin, which shows a certain boundary, occurs when the image quality is checked at a certain viewing angle.

However, in the liquid crystal display according to the first embodiment of the present invention, the polarities of adjacent sub-pixels are all different, and even when the image quality is checked at a certain viewing angle, the image quality defects such as the above-described defects in purlins occur. Does not work.

However, even in the case of the above-described first embodiment, the generation of zigzag brick-like patterns and vertical lines cannot be completely prevented. Hereinafter, other embodiments of the present invention to solve this will be described in detail with reference to the drawings.

6 is a plan view showing a structure of an array substrate of a liquid crystal display according to a second embodiment of the present invention.

7 exemplarily shows a pixel structure of a liquid crystal display according to a second embodiment of the present invention.

8A and 8B are diagrams showing an example of a pixel structure and a driving method of the liquid crystal display according to the second embodiment of the present invention.

In this case, FIGS. 6 and 7 show a planar structure of 8 sub-pixels of 2 x 4 (P11, P12, P13, P14; P21, P22, P23, P24) as an example, and FIGS. 8A and 8B 2 x 12 24 sub-pixels (P11, P12, P13, P14, P15, P16, P17, P18, P19, P110, P111, P112; P21, P22, P23, P24, P25, P26, P27, P28, P29, P210, P211, and P212) are shown as examples. However, the present invention is not limited thereto.

In addition, FIGS. 8A and 8B show an example of a driving method of column inversion. 8A shows an example of a pixel structure in a n-th frame and its driving method, and FIG. 8B shows an example of a pixel structure in a n + 1th frame and a driving method thereof.

First, referring to FIGS. 6 and 7, the liquid crystal display according to the second embodiment of the present invention may include a plurality of sub-pixels P11, P12, P13, P14; P21, P22, P23, P24 have.

In this case, FIGS. 6 and 7 show a planar structure of 8 sub-pixels (P11, P12, P13, P14; P21, P22, P23, P24) of 2 x 4 as an example, but the present invention is limited to this. no.

The plurality of sub-pixels P11, P12, P13, P14; P21, P22, P23, P24 includes a plurality of gate lines GL1, GL2, GL3, GL4, GL5 and data lines DL1, DL2, on the array substrate. DL3) may be arranged in a matrix form crossing each other.

The gate lines GL1, GL2, GL3, GL4, and GL5 may be disposed on the array substrate in the first direction. Further, the data lines DL1, DL2, DL3 are arranged in a second direction different from the first direction, and the gate lines GL1, GL2, GL3, GL4, GL5 together with a plurality of sub-pixels P11, P12, P13, P14; P21, P22, P23, P24).

The vertical common line CL may be disposed in the second direction between the data lines DL1, DL2, and DL3, but is not limited thereto.

The vertical common line CL may be disposed on the same layer as the data lines DL1, DL2, and DL3, but is not limited thereto.

The data lines DL1, DL2, DL3 and the vertical common line CL may have a bent structure according to the shape of a plurality of sub-pixels P11, P12, P13, P14; P21, P22, P23, P24, It is not limited thereto.

The plurality of sub-pixels P11, P12, P13, and P14; P21, P22, P23, and P24 may be arranged in a column direction and a row direction to be arranged in a matrix form. For example, FIGS. 6 and 7 show an example in which a plurality of sub-pixels P11, P12, P13, P14; P21, P22, P23, and P24 are arranged in four columns and two rows. . That is, in FIG. 6 and FIG. 7, only 8 sub-pixels of any 2 × 4 (P11, P12, P13, P14; P21, P22, P23, P24) are illustrated as examples, but the present invention is not limited thereto. . Hereinafter, for convenience of description, a group of sub-pixels arranged in a row direction among a plurality of sub-pixels P11, P12, P13, and P14; P21, P22, P23, and P24 is defined as a row sub-pixel unit, and column direction A group of sub-pixels arranged as is defined as a column sub-pixel unit.

For example, the row sub-pixel units may include row sub-pixel units P11, P12, P13, and P14 in the first row and row sub-pixel units P21, P22, P23, and P24 in the second row. . In addition, the column sub-pixel units include column sub-pixel units P11 and P21 in the first column, column sub-pixel units P12 and P22 in the second column, and column sub-pixel units P13 and P23 in the third column, and And the fourth column column sub-pixel units P14 and P24.

The plurality of sub-pixels P11, P12, P13, and P14; P21, P22, P23, and P24, respectively, may embody light of a specific color. For example, the sub-pixels (P11, P12, P13, P14; P21, P22, P23, P24) are red sub-pixels that implement red color, green sub-pixels that implement green color, and blue sub-pixels that implement blue color. It may be composed of any one of pixels. In this case, a group of red sub-pixels, green sub-pixels, and blue sub-pixels may constitute one pixel. However, the present invention is not limited to this, and one pixel may be composed of a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.

Meanwhile, the present invention features a liquid crystal display device having a DRD structure in which the number of data lines DL1, DL2, and DL3 is halved. In the DRD structured liquid crystal display, for example, a plurality of sub-pixels P11, P12, P13, and P14 disposed on one horizontal line include two gate lines GL1 and GL2 and one data line DL1 and DL2. , DL3), and one data line DL1 in which a plurality of sub-pixels P21, P22, P23, and P24 disposed on another horizontal line are the same as the other two gate lines GL3 and GL4. , DL2, DL3).

For example, in the pixel array, each of the red sub-pixels to which red data is applied, the green sub-pixel to which green data is applied, and the blue sub-pixels to which blue data is applied may be arranged along the column direction, but is not limited thereto. Does not. One pixel in this pixel array may include neighboring red sub-pixels, green sub-pixels, and blue sub-pixels along a row direction orthogonal to the column direction.

6 and 7, a pair of sub-pixels P11, P12, P13, P14; P21, P22, P23, P24 sharing the same data lines DL1, DL2, and DL3 in each row are transferred. , May be connected to the gate lines GL1, GL2, GL3, GL4, and GL5 of the rear end, respectively. For example, a pair of sub-pixels P12 and P13 of the first row sharing the second data line DL2 may be connected to the first and second gate lines GL1 and GL2, respectively. The other pair of sub-pixels P22 and P23 of the second row sharing the data line DL2 may be connected to the third and fourth gate lines GL3 and GL4, respectively.

The sub-pixels P11, P12, P13, P14, P21, P22, P23, P24 according to the second embodiment of the present invention include gate lines GL1, GL2, GL3, GL4, GL5 and data lines DL1, A thin film transistor may be configured at an intersection of DL2 and DL3).

The thin film transistor includes a gate electrode 121 connected to the gate lines GL1, GL2, GL3, GL4, and GL5, an active layer, a source electrode 122 connected to the data lines DL1, DL2, and DL3, and a source electrode 122. And a drain electrode 123 disposed opposite to and electrically connected to the pixel electrode 118.

Meanwhile, hereinafter, for convenience of description, a pair of sub-pixels P11, P12, P13, P14; P21, P22, P23, and P24 disposed between data lines DL1, DL2, and DL3 in each row are It will be referred to as a pair of neighboring sub-pixels (P11, P12, P13, P14; P21, P22, P23, P24).

For a pair of neighboring sub-pixels (P11, P12, P13, P14; P21, P22, P23, P24), each sub-pixel (P11, P12, P13, P14; P21, P22, P23, P24) The thin film transistors may be connected to different data lines DL1, DL2, and DL3.

For a pair of neighboring sub-pixels (P11, P12, P13, P14; P21, P22, P23, P24), each sub-pixel (P11, P12, P13, P14; P21, P22, P23, P24) The thin film transistors of can be connected to the same gate line (GL1, GL2, GL3, GL4, GL5).

In addition, each of the thin film transistors of one neighboring pair of sub-pixels P11, P12, P13, and P14; P21, P22, P23, and P24, is one data line near one of the data lines DL1, DL2, and DL3. (DL1, DL2, DL3) while the other neighboring pair is adjacent to one neighboring pair of sub-pixels (P11, P12, P13, P14; P21, P22, P23, P24) Each of the thin film transistors of the sub-pixels P11, P12, P13, P14; P21, P22, P23, P24 is one of the data lines DL1, DL2, and DL3, which is the farther one of the data lines DL1, DL2, DL3. Can be connected to.

At this time, one pair of thin film transistors of one neighboring pair of sub-pixels (P11, P12, P13, P14; P21, P22, P23, P24) has one identical gate line (GL1, GL2, GL3, GL4, GL5) While connected to, one neighboring pair of sub-pixels (P11, P12, P13, P14; P21, P22, P23, P24), the other neighboring pair of sub-pixels (P11, P12) , P13, P14; A pair of thin film transistors of P21, P22, P23, P24 is adjacent to one gate line (GL1, GL2, GL3, GL4, GL5) and another identical gate line (GL1, GL2, GL3, GL4, GL5). As an example, a pair of thin film transistors of a pair of neighboring sub-pixels P11 and P12 in rows 1 and 2 of columns are connected to one and the same first gate line GL1, while a neighbor of rows 1 to 1 of 2 columns A pair of thin film transistors of a pair of neighboring sub-pixels P13 and P14 in one row 3-4 columns adjacent to a pair of sub-pixels P11 and P12 has one identical first gate line GL1 It may be connected to the same second gate line (GL2) of the other adjacent to.

A plurality of common electrodes 108 and pixel electrodes 118 may be alternately disposed in the sub-pixels P11, P12, P13, and P14; P21, P22, P23, and P24.

The pixel electrode 118 is electrically connected to the drain electrode 123 of the thin film transistor through the first contact hole 140a to receive a pixel voltage, and the common electrode 108 is horizontal through the second contact hole 140b. The common line 108l is electrically connected to a common voltage. An electric field is generated between the pixel electrode 118 and the common electrode 108 due to a voltage difference between the applied pixel voltage and the common voltage, so that an image can be displayed by changing the arrangement of the liquid crystal molecules.

Meanwhile, the horizontal common line 108l may be disposed between the gate lines GL1, GL2, GL3, GL4, and GL5 in the first direction substantially the same as the gate lines GL1, GL2, GL3, GL4, and GL5. .

The horizontal common line 108l may be disposed on the same layer as the gate lines GL1, GL2, GL3, GL4, and GL5, but is not limited thereto.

The common electrode 108 and the pixel electrode 118 have a bent structure along the data lines DL1, DL2, and DL3, whereby liquid crystal molecules are arranged in two directions to form a 2-domain, thereby forming a mono-domain. Compared, the viewing angle is further improved. However, the present invention is not limited to a two-domain structure, and is applicable to a multi-domain structure of two or more domains.

As described above, according to the present invention, the production cost of the liquid crystal display device can be reduced by applying a DRD structure in which the number of data lines DL1, DL2, and DL3 is reduced in half.

In addition, the present invention can improve display quality by improving image quality issues that occur in the DRD column inversion structure. For example, the second embodiment of the present invention is the origin symmetric design in which the thin film transistor arrangement is reversed vertically and horizontally based on 2 x 4 sub-pixels (P11, P12, P13, P14; P21, P22, P23, P24). By doing so, it is possible to completely prevent generation of zigzag brick-like patterns and vertical lines that may occur in the first embodiment.

That is, according to the first embodiment, the gap between the sub-pixel units adjacent to the top and bottom neighbors occurs according to the design of the thin film transistor clustering (the thin film transistors in one pixel unit are arranged). Accordingly, a difference occurs in the area of the black strip (BS) between the upper and lower neighboring sub-pixel units, whereby a zigzag brick-like pattern can be recognized when viewed in close proximity. In addition, domains are formed asymmetrically according to the structural difference, and vertical lines may occur on a specific screen such as a flicker pattern.

Thus, the second embodiment of the present invention, for example, based on 2 x 4 sub-pixels (P11, P12, P13, P14; P21, P22, P23, P24), the origin of the symmetry of the thin film transistor is inverted up and down and left and right By arranging with it, it is possible to prevent the occurrence of vertical zigzag brick-like patterns and vertical lines. That is, in 2 x 4 sub-pixels (P11, P12, P13, P14; P21, P22, P23, P24), the pair of thin film transistors of the upper left pair of sub-pixels (P11, P12) is the lower right pair The thin-film transistors of the sub-pixels P23 and P24 are arranged in origin symmetry, and the thin-film transistors of the upper right pair of sub-pixels P13 and P14 are the lower left pair of sub-pixels P21 and P22. ) May be disposed symmetrically with the thin film transistor.

Accordingly, a thin film transistor of a pair of sub-pixels P11 and P12 in the upper left and a pair of sub-pixels in the lower right (originally symmetric to the pair of sub-pixels P11 and P12 in the upper left) Each of the thin film transistors of (P23, P24) is connected to the adjacent data lines (DL1, DL2, DL3), a pair of sub-pixels in the upper right (P13, P14), and a pair of sub (in the upper right) Each of the thin film transistors of the pair of lower left pairs of sub-pixels P21 and P22 that are origin-symmetric to the pixels P13 and P14 may be connected to further data lines DL1, DL2, and DL3. That is, the sub-pixels P11 of the first row and the first column and the sub-pixels P12 of the first row and the second column are connected to the first data line DL1 and the second data line DL2, respectively. The sub-pixels P23 of 2 rows and 3 columns and the sub-pixels P24 of 2 rows and 4 columns may be connected to the second data line DL2 and the third data line DL3, respectively. On the other hand, the sub-pixels P13 of the first row and the third column and the sub-pixels P14 of the first row and the fourth column are connected to the farther third data line DL3 and the second data line DL2, respectively. The sub-pixels P21 of the second row and the second column at the lower left and the sub-pixels P22 of the second row and the second column may be connected to the farther second data line DL2 and the first data line DL1, respectively.

In addition, while the thin film transistors of the pair of sub-pixels P11 and P12 in the upper left are all connected to the same first gate line GL1, (the pair of sub-pixels P11 and P12 in the upper left) are connected. All of the thin film transistors of the pair of upper-right neighboring sub-pixels P13 and P14 may be connected to the same second gate line GL2 adjacent to the first gate line GL1. That is, the sub-pixel P11 of the first row and the first column and the sub-pixel P12 of the first row and the second column are connected to the same first gate line GL1, while the sub-pixel of the first row and the third column of the upper right. The sub-pixels P14 of P13 and row 1 and column 4 may be connected to the same second gate line GL2 adjacent to the first gate line GL1.

Also, while the thin film transistors of the lower left pair of sub-pixels P21 and P22 are all connected to the same third gate line GL3, (the lower left pair of sub-pixels P21 and P22) All of the thin film transistors of the pair of sub-pixels P23 and P24 in the lower right may be connected to the same fourth gate line GL4 adjacent to the third gate line GL3. That is, the sub-pixel P21 in the lower left 2 rows and 1 column and the sub-pixel P22 in the 2 lower rows and 2 columns are connected to the same third gate line GL3, while the sub-pixel in the lower right 2 rows and 3 columns. The sub-pixels P24 of P23 and 2 rows and 4 columns may be connected to the same fourth gate line GL4 adjacent to the third gate line GL3.

Further, as an example, the thin film transistor of the third sub-pixel P13 and the thin film transistor of the fourth sub-pixel P14 connected to the second gate line GL2 are disposed adjacent to the second gate line GL2. The thin film transistor of the fifth sub-pixel P21 and the thin film transistor of the sixth sub-pixel P22 connected to the third gate line GL3 may be disposed adjacent to the third gate line GL3. .

In addition, the thin film transistor of the first sub-pixel P11 and the thin film transistor of the second sub-pixel P12 connected to the first gate line GL1 are disposed adjacent to the first gate line GL1. The thin film transistor of the seventh sub-pixel P23 and the thin film transistor of the eighth sub-pixel P24 connected to the fourth gate line GL4 may be disposed adjacent to the fourth gate line GL4.

The liquid crystal display according to the second embodiment of the present invention configured as described above may be driven by a column inversion method as shown in FIGS. 8A and 8B.

That is, the controller 400 uses the polarity control signals to sub-pixels P11, P12, P13, P14, P15, P16, P17, P18, P19, P110, P111, P112; P21, P22, P23, P24, P25 , P26, P27, P28, P29, P210, P211, and P212) to control the polarity of the data voltage applied to each, thereby controlling the driving of the liquid crystal display using various inversion methods.

Referring to FIGS. 8A and 8B, a rectangle marked with polarity (+,-) is one sub-pixel (P11, P12, P13, P14, P15, P16, P17, P18, P19, P110, P111, P112 ; P21, P22, P23, P24, P25, P26, P27, P28, P29, P210, P211, P212).

In the present invention, the column inversion driving method corresponding to FIGS. 8A and 8B will be described as an example, but is not limited thereto. The liquid crystal display device of the present invention includes sub-pixels (P11, P12, P13, P14, P15, P16, P17, P18, P19, P110, P111, P112; P21, P22, P23, P24, P25) disposed on the display panel , P26, P27, P28, P29, P210, P211, P212), data lines (DL1, DL2, DL3, DL4, DL5, DL6, DL7), connection structures of gate lines (GL1, GL2, GL3, GL4), etc. It can be driven by various inversion driving methods by modifying or adjusting the data voltage supplied from the data driver 200.

In particular, as the display panel becomes larger and higher resolution, the frame rate frequency (Hz) of the input image increases, but when the frame rate frequency increases, each gate line (GL1, GL2, GL3, GL4) The horizontal period (H: pulse width) of the gate signal supplied to the gate is shortened, so that each sub-pixel (P11, P12, P13, P14, P15, P16, P17, P18, P19, P110, P111, P112; P21, P22, P23, P24, P25, P26, P27, P28, P29, P210, P211, P212) has a problem that the polarity data voltage is not sufficiently charged. As such, each sub-pixel (P11, P12, P13, P14, P15, P16, P17, P18, P19, P110, P111, P112; P21, P22, P23, P24, P25, P26, P27, P28, P29, If the data voltage is not sufficiently charged in P210, P211, P212, each sub-pixel (P11, P12, P13, P14, P15, P16, P17, P18, P19, P110, P111, P112) that the inversion driving method intended; The residual charges of P21, P22, P23, P24, P25, P26, P27, P28, P29, P210, P211, and P212) fail to completely cancel, and flicker defects and afterimage defects occur again.

However, in the second embodiment of the present invention, even if the frame rate frequency (Hz) of the input image is high, each sub-pixel (P11, P12, P13, P14, P15, P16, P17, P18, P19, P110, P111, P112 ; P21, P22, P23, P24, P25, P26, P27, P28, P29, P210, P211, P212) to ensure that the polarity data voltage is sufficiently charged to eliminate flicker defects and afterimage defects caused by the inversion driving method Was made possible.

In addition, the second embodiment of the present invention includes 8 sub-pixels (P11, P12, P13, P14, P21, P22, P23, P24; P15, P16, P17, P18, P25, P26 of the display panel) , P27, P28; P19, P110, P111, P112, P29, P210, P211, P212 are defined in units of rendering pixels, and sub-pixels (P11, P12, P13, P14, P21, within each rendering pixel) P22, P23, P24; P15, P16, P17, P18, P25, P26, P27, P28; P19, P110, P111, P112, P29, P210, P211, P212) drive each sub-pixel (P11, P12) , P13, P14, P21, P22, P23, P24; P15, P16, P17, P18, P25, P26, P27, P28; P19, P110, P111, P112, P29, P210, P211, P212) It can be charged.

In addition, the second embodiment of the present invention, the rendering order, for example, based on the first 2 x 4 sub-pixels (P11, P12, P13, P14; P21, P22, P23, P24) In a pair of sub-pixels P11 and P12, a pair of sub-pixels at the top right (P13, P14), a pair of sub-pixels at the bottom right (P23, P24) and a pair of sub-pixels at the bottom left It is characterized by changing in the order of (P21, P22).

In addition, as described above, the second embodiment of the present invention is characterized in that the arrangement of some thin film transistors is inverted up and down in accordance with a gate driving (or scanning) order change described later, and the structure of the rendering pixel unit is origin-symmetric. . This is a structure capable of avoiding the design of agglomeration of the thin film transistor, and accordingly, it is possible to completely prevent a zigzag screen defect and a vertical line defect in a viewing angle.

In addition, the second embodiment of the present invention is a sub-pixel (P11, P12, P13, P14, P21, P22, P23, P24; P15, P16, P17, P18, P25, P26, P27, P28; P19 in terms of image quality) , P110, P111, P112, P29, P210, P211, P212) is characterized by a symmetrical design of the transmissive region and the non-transmissive region (BS region).

In addition, the second embodiment of the present invention is a sub-pixel adjacent to the drain electrode in terms of charging (P11, P12, P13, P14, P21, P22, P23, P24; P15, P16, P17, P18, P25, P26, P27, P28; P19, P110, P111, P112, P29, P210, P211, P212) are characterized by a symmetric design of the origin.

Hereinafter, the laminated structure of the liquid crystal display device according to the present invention configured as described above will be described in detail.

9 is a plan view illustrating a portion of a pixel of a liquid crystal display according to a second embodiment of the present invention as an example.

FIG. 10 is a view showing a cross-section cut along the line A-A 'in the liquid crystal display device according to the second embodiment of the present invention shown in FIG. 9.

In this case, FIG. 9 shows a portion of a pair of vertically adjacent sub-pixels connected to the nth gate line GL and the n + 1th gate line GLn + 1, respectively, as the gate lines GLn and GLn + 1. It is showing mainly.

In the liquid crystal display device according to the second exemplary embodiment of the present invention illustrated in FIGS. 9 and 10, a shield line 125 of a power source that is equal to or higher than the gate voltage is n-th gate line GLn on the light blocking layer It is characterized in that it is formed between the and the pixel electrode 118 to shield the electric field between the gate lines GLn and GLn + 1 and the pixel electrode 118.

In the liquid crystal display device according to the second embodiment of the present invention illustrated in FIGS. 9 and 10, a color filter on TFT (COT) structure in which color filters 109a and 109b are formed on a array substrate 110 together with thin film transistors It may be configured, but is not limited thereto.

In addition, in the liquid crystal display device according to the second embodiment of the present invention, instead of removing the existing black matrix, a light shielding pattern is formed of an opaque conductive material at the left and right boundaries of the sub-pixel region, while the upper and lower portions of the sub-pixel region are formed. It is characterized by laminating a light-shielding layer made of a color pigment on the border.

In this case, the light blocking pattern is formed to cover the data lines DLm and DLm + 1 on the data lines DLm and DLm + 1, thereby preventing color interference between adjacent sub-pixels.

The light-blocking layer is formed by mixing and laminating the color pigments constituting the red and blue color filters 109a and 109b in the vertical black matrix region where the gate lines GLn and GLn + 1 and the horizontal common line 108l pass. can do.

9 and 10, the gate lines GLn and GLn + 1, the gate electrode 121, the vertical common line CL and the horizontal common line 108l are disposed on the same layer on the array substrate 110. Can be.

The gate lines GLn and GLn + 1 and the horizontal common line 108l may be arranged in a direction parallel to the first direction.

The vertical common line CL may be arranged in a direction parallel to a second direction different from the first direction.

One end of the vertical common line CL may be connected to the horizontal common line 108l.

The array substrate 110 may be made of a transparent insulating material such as glass.

The gate electrode 121 may form part of the gate lines GLn and GLn + 1.

The gate lines GLn and GLn + 1, the gate electrode 121, the vertical common line CL and the horizontal common line 108l may be formed as a first metal layer on the array substrate 110.

As the first metal layer, aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy), gold ( Conductive metal groups including Au), gold alloys (Au alloy), chromium (Cr), titanium (Ti), titanium alloys, molybdenum tungsten (MoW), molybdenum titanium (MoTi), copper / mortitanium titanium (Cu / MoTi) It may include at least any one selected from, or a combination of two or more thereof, or other suitable materials.

In addition, the first insulating layer 115a may be provided on the gate lines GLn, GLn + 1, the gate electrode 121, the vertical common line CL, and the horizontal common line 108l.

As the first insulating layer 115a, a silicon (Si) -based oxide film, a nitride film, or a compound containing the same, and a metal oxide film containing Al ₂ O ₃ (metal oxide), an organic insulating film, and a low dielectric constant (low- k) may include a material having a value.

For example, as the first insulating layer 115a, silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), tantalum oxide ( Ta ₂ O ₅ ), barium-strontium-titanium-oxygen compound (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compound (Bi-Zn-Nb-O). , Or a combination of two or more of these, or other suitable materials.

The active layer may be disposed on the first insulating layer 115a.

The active layer may be formed of a semiconductor layer.

As the semiconductor layer, amorphous silicon (a-Si), low temperature polysilicon (LTPS), oxide semiconductor of IGZO series, compound semiconductor, carbon nano tube, graphene and organic semiconductor And the like.

As the oxide semiconductor, one or more materials selected from the group consisting of germanium (Ge), tin (Sn), lead (Pb), indium (In), titanium (Ti), gallium (Ga), and aluminum (Al) and zinc ( Zn) may be made of a material in which silicon (Si) is added to the oxide semiconductor. For example, the semiconductor layer may be made of silicon indium zinc oxide (Si-InZnO: SIZO) in which silicon ions are added to indium zinc composite oxide (InZnO).

When the semiconductor layer is made of SIZO, the composition ratio of the atomic content of silicon (Si) to the total content of zinc (Zn), indium (In) and silicon (Si) atoms in the active layer is about 0.001% by weight (wt%) to about 30 It may also be wt%. The higher the silicon (Si) atom content is, the stronger the role of controlling electron generation is, the lower the mobility may be, but the stability of the device may be improved.

As the oxide semiconductor, in addition to the above-mentioned materials, Group I elements such as lithium (Li) or potassium (K), Group II elements such as magnesium (Mg), calcium (Ca) or strontium (Sr), gallium (Ga), aluminum Group III elements such as (Al), indium (In) or yttrium (Y), elements of Group IV such as titanium (Ti), zirconium (Zr), silicon (Si), tin (Sn) or germanium (Ge), tantalum (Ta), a group V element such as vanadium (V), niobium (Nb) or antimony (Sb), or lanthanum (La), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm) , Europium (Eu), Gadolinium (Gd), Cerium (Ce), Terbium (Tb), Dysprosium (Dy), Holmium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb) or Ruthedium A lanthanide (Ln) -based element such as (Lu) may be further included.

The data lines DLm and DLm + 1, the source electrode 122 and the drain electrode 123 may be disposed on the same layer on the active layer.

A semiconductor pattern made of the same semiconductor layer as the active layer may be disposed under the data lines DLm and DLm + 1. However, the present invention is not limited thereto, and when the data lines DLm and DLm + 1 and the active layer are formed in different mask processes, a semiconductor pattern may not be disposed under the data lines DLm and DLm + 1. have.

The data lines DLm and DLm + 1, the source electrode 122 and the drain electrode 123 may be formed of a second metal layer.

As the second metal layer, aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy), gold ( Au), Gold alloy (Au alloy), Chromium (Cr), Titanium (Ti), Titanium alloy (Ti alloy), Moly tungsten (MoW), Molytitanium (MoTi), Copper / Molytitanium (Cu / MoTi) It may include at least one selected from the group of conductive metal, or a combination of two or more thereof, or other suitable materials.

The data lines DLm and DLm + 1 may be disposed in a second direction different from the first direction to partition the plurality of sub-pixels along with the gate lines GLn and GLn + 1.

The gate electrode 121 connected to the gate lines GLn and GLn + 1, the active layer disposed on the gate electrode 121, the source electrode 122 and the source electrode 122 connected to the data lines DLm and DLm + 1 ) And a drain electrode 123 disposed opposite to and electrically connected to the pixel electrode 118 may constitute a thin film transistor.

The second insulating layer 115b may be disposed on the data lines DLm and DLm + 1, the source electrode 122 and the drain electrode 123.

As the second insulating layer 115b, a silicon (Si) -based oxide film, a nitride film, or a compound containing the same, and a metal oxide film containing Al ₂ O ₃ (metal oxide), an organic insulating film, and a low dielectric constant (low- k) may include a material having a value. For example, as the second insulating layer 115b, silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), tantalum oxide ( Ta ₂ O ₅ ), barium-strontium-titanium-oxygen compound (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compound (Bi-Zn-Nb-O). , Or a combination of two or more of these, or other suitable materials.

Red, green, and blue color filters 109a and 109b may be formed in the sub-pixel region of the array substrate 110 on which the second insulating layer 115b is formed.

At this time, in the vertical black matrix area where the gate lines GLn and GLn + 1 and the horizontal common line 108l pass, a color blocking layer of red and blue color filters 109a and 109b is mixed and stacked to form a light-shielding layer. Can form. That is, a light blocking layer may be disposed on the second insulating layer 115b at the upper and lower boundaries of the sub-pixel.

A third insulating layer 115c may be disposed on the array substrate 110 on which the red, green, and blue color filters 109a and 109b are formed.

As the third insulating layer 115c, a silicon (Si) -based oxide film, a nitride film, or a compound containing the same, and a metal oxide film containing Al ₂ O ₃ , an organic insulating film, and a low dielectric constant (low- k) may include a material having a value. For example, as the third insulating layer 115c, silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), tantalum oxide ( Ta ₂ O ₅ ), barium-strontium-titanium-oxygen compound (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compound (Bi-Zn-Nb-O). , Or a combination of two or more of these, or other suitable materials.

The shielding line 125 may be disposed on the third insulating layer 115c.

For example, the shielding line 125 may be disposed on the third insulating layer 115c between the n-th gate line GLn and the pixel electrode 118, but is not limited thereto.

The shielding line 125 may be disposed in the same first direction as the gate lines GLn and GLn + 1.

The shielding line 125 may be disposed under the common electrode 108 and overlapped by the common electrode 108.

The shielding line 125 may be disposed on the light blocking layer and partially overlap the light blocking layer.

The shielding line 125 may be made of a third metal layer.

As the third metal layer, aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy), gold (Au) ), Including gold alloy (Au alloy), chromium (Cr), titanium (Ti), titanium alloy (Ti alloy), molybdenum tungsten (MoW), molybdenum titanium (MoTi), copper / molybdenum titanium (Cu / MoTi) It may also include at least one selected from conductive metal groups, or a combination of two or more thereof, or other suitable materials.

A power source equal to or higher than the gate voltage supplied to the gate lines GLn and GLn + 1 may be applied to the shielding line 125. Accordingly, an electric field generated between the n-th gate line GLn and the pixel electrode 118 can be shielded.

Accordingly, for example, the parasitic capacitance formed between the n-th gate line GLn and the pixel electrode 118 is reduced by about 15.2% to about 4.31x10 ^-16 F compared to the existing (= about 5.08x10 ^-16 F). Able to know.

A fourth insulating layer 115d may be disposed on the array substrate 110 on which the shielding line 125 is formed.

As the fourth insulating layer 115d, a silicon (Si) -based oxide film, a nitride film, or a compound containing the same, and a metal oxide film including Al ₂ O ₃ , an organic insulating film, and a low dielectric constant (low- k) may include a material having a value. For example, as the fourth insulating layer 115d, silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), tantalum oxide ( Ta ₂ O ₅ ), barium-strontium-titanium-oxygen compound (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compound (Bi-Zn-Nb-O). , Or a combination of two or more of these, or other suitable materials.

The common electrode 108 and the pixel electrode 118 may be disposed on the fourth insulating layer 115d.

The pixel electrode 118 may be alternately disposed with the common electrode 108 in the sub-pixel to form a lateral electric field.

Some regions of the second insulating layer 115b, the third insulating layer 115c, and the fourth insulating layer 115d may be removed to form a first contact hole exposing a portion of the drain electrode 123.

At this time, one end of the plurality of pixel electrodes 118 may be connected to a pixel line arranged side by side with respect to the gate lines GLn and GLn + 1. Therefore, the pixel electrode line may be electrically connected to the drain electrode 123 through the first contact hole.

Meanwhile, the shield line of the present invention may be disposed not only between the nth gate line and the pixel electrode, but also between the n + 1th gate line and the pixel electrode, which will be described in detail with reference to the following drawings.

11 is a view showing another cross-section of a liquid crystal display according to a second embodiment of the present invention as an example.

The other cross section of the liquid crystal display according to the second embodiment of the present invention shown in FIG. 11 is that the shielding lines 125a and 125b are n + as well as between the n-th gate line GLn and the pixel electrode 118 described above. It has the same configuration as the liquid crystal display device according to the second embodiment of the present invention shown in FIGS. 9 and 10 except that it is also disposed between the first gate line GLn + 1 and the pixel electrode 118. Therefore, the description of the same configuration will be omitted.

Referring to FIG. 11, shielding lines 125a and 125b may be disposed on the third insulating layer 115c.

The shielding lines 125a and 125b are the first shielding line 125a and the n + 1th gate line GLn + 1 and the pixel electrode 118 disposed between the nth gate line GLn and the pixel electrode 118. It may be composed of a second shielding line (125b) disposed between.

That is, the shielding lines 125a and 125b may be disposed on both sides of the upper and lower boundaries of the sub-pixels.

The shielding lines 125a and 125b may be disposed in the same first direction as the gate lines GLn and GLn + 1.

The shielding lines 125a and 125b may be made of a third metal layer.

As the third metal layer, aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy), gold (Au) ), Including gold alloy (Au alloy), chromium (Cr), titanium (Ti), titanium alloy (Ti alloy), molybdenum tungsten (MoW), molybdenum titanium (MoTi), copper / molybdenum titanium (Cu / MoTi) It may also include at least one selected from conductive metal groups, or a combination of two or more thereof, or other suitable materials.

A power source equal to or higher than the gate voltage supplied to the gate lines GLn and GLn + 1 may be applied to the shielding lines 125a and 125b. Accordingly, an electric field generated between the n-th gate line GLn and the pixel electrode 118 and between the n + 1th gate line GLn + 1 and the pixel electrode 118 can be shielded.

Meanwhile, the shield line of the present invention may be disposed between the gate line and the horizontal common line on the same layer as the gate line, which will be described in detail through the third embodiment of the present invention.

12 is a plan view illustrating a portion of a pixel of a liquid crystal display according to a third embodiment of the present invention as an example.

13 is a diagram illustrating a cross-section cut along the line B-B 'in the liquid crystal display device according to the third embodiment of the present invention shown in FIG. 12.

In this case, FIG. 12 shows a portion of a pair of vertically adjacent sub-pixels connected to the nth gate line GL and the n + 1th gate line GLn + 1, respectively, as the gate lines GLn and GLn + 1. It is showing mainly.

In the liquid crystal display according to the third embodiment of the present invention shown in FIGS. 12 and 13, the shielding line 235 of a power source equal to or higher than the gate voltage is horizontally common to the n-th gate line GLn. It is characterized by forming between the lines 208l to shield the electric field between the gate lines GLn, GLn + 1 and the pixel electrode 218.

In the liquid crystal display device according to the third embodiment of the present invention shown in FIGS. 12 and 13, a color filter on TFT (COT) structure in which color filters 209a and 209b are formed on a array substrate 210 together with thin film transistors It may be configured, but is not limited thereto.

In addition, the liquid crystal display according to the third embodiment of the present invention, instead of removing the existing black matrix, forms a light-shielding pattern with an opaque conductive material at the left and right borders of the sub-pixel region, while the upper and lower portions of the sub-pixel region are formed. It is characterized by laminating a light-shielding layer made of a color pigment on the border.

In this case, the light blocking pattern is formed to cover the data lines DLm and DLm + 1 on the data lines DLm and DLm + 1, thereby preventing color interference between adjacent sub-pixels.

The light-blocking layer is formed by mixing and laminating the color pigments constituting the red and blue color filters 209a and 209b in the vertical black matrix area where the gate lines GLn and GLn + 1 and the horizontal common line 208l pass. can do.

12 and 13, the gate lines GLn and GLn + 1, the gate electrode 221, the vertical common line CL, the horizontal common line 208l, and the shielding line 235 are array substrate 210 It can be placed on the same layer above.

The gate lines GLn and GLn + 1, the horizontal common line 208l, and the shielding line 235 may be arranged in a direction parallel to the first direction.

Also, the vertical common line CL may be arranged in a parallel direction with respect to a second direction different from the first direction.

One end of the vertical common line CL may be connected to the horizontal common line 208l.

For example, the shielding line 235 may be disposed on the array substrate 210 between the n-th gate line GLn and the horizontal common line 208l, but is not limited thereto.

A power source equal to or higher than the gate voltage supplied to the gate lines GLn and GLn + 1 may be applied to the shielding line 235. Accordingly, an electric field generated between the n-th gate line GLn and the pixel electrode 218 may be shielded.

Accordingly, for example, the parasitic capacitance formed between the n-th gate line GLn and the pixel electrode 218 is reduced by about 27.2% to about 3.70x10 ^-16 F compared to the existing (= about 5.08x10 ^-16 F). Able to know.

The array substrate 210 may be made of a transparent insulating material such as glass.

The gate electrode 221 may form part of the gate lines GLn and GLn + 1.

The gate lines GLn and GLn + 1, the gate electrode 221, the vertical common line CL, the horizontal common line 208l, and the shielding line 235 may be formed as a first metal layer on the array substrate 210. have.

As the first metal layer, aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy), gold ( Conductive metal groups including Au), gold alloys (Au alloy), chromium (Cr), titanium (Ti), titanium alloys, molybdenum tungsten (MoW), molybdenum titanium (MoTi), copper / mortitanium titanium (Cu / MoTi) It may include at least any one selected from, or a combination of two or more thereof, or other suitable materials.

In addition, the first insulating layer 215a may be provided on the gate lines GLn and GLn + 1, the gate electrode 221, the vertical common line CL, the horizontal common line 208l, and the shielding line 235. .

As the first insulating layer 215a, a silicon (Si) -based oxide film, a nitride film, or a compound containing the same, and a metal oxide film containing Al ₂ O ₃ (metal oxide), an organic insulating film, and a low dielectric constant (low- k) may include a material having a value.

For example, as the first insulating layer 215a, silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), tantalum oxide ( Ta ₂ O ₅ ), barium-strontium-titanium-oxygen compound (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compound (Bi-Zn-Nb-O). , Or a combination of two or more of these, or other suitable materials.

The active layer may be disposed on the first insulating layer 215a.

The active layer may be formed of a semiconductor layer.

As the semiconductor layer, amorphous silicon (a-Si), low temperature polysilicon (LTPS), oxide semiconductor of IGZO series, compound semiconductor, carbon nano tube, graphene and organic semiconductor And the like.

As the oxide semiconductor, one or more materials selected from the group consisting of germanium (Ge), tin (Sn), lead (Pb), indium (In), titanium (Ti), gallium (Ga), and aluminum (Al) and zinc ( Zn) may be made of a material in which silicon (Si) is added to the oxide semiconductor. For example, the semiconductor layer may be made of silicon indium zinc oxide (Si-InZnO: SIZO) in which silicon ions are added to indium zinc composite oxide (InZnO).

When the semiconductor layer is made of SIZO, the composition ratio of the atomic content of silicon (Si) to the total content of zinc (Zn), indium (In) and silicon (Si) atoms in the active layer is about 0.001% by weight (wt%) to about 30 It may also be wt%. The higher the silicon (Si) atom content is, the stronger the role of controlling electron generation is, the lower the mobility may be, but the stability of the device may be improved.

As the oxide semiconductor, in addition to the above-mentioned materials, Group I elements such as lithium (Li) or potassium (K), Group II elements such as magnesium (Mg), calcium (Ca) or strontium (Sr), gallium (Ga), aluminum Group III elements such as (Al), indium (In) or yttrium (Y), elements of Group IV such as titanium (Ti), zirconium (Zr), silicon (Si), tin (Sn) or germanium (Ge), tantalum (Ta), a group V element such as vanadium (V), niobium (Nb) or antimony (Sb), or lanthanum (La), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm) , Europium (Eu), Gadolinium (Gd), Cerium (Ce), Terbium (Tb), Dysprosium (Dy), Holmium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb) or Ruthedium A lanthanide (Ln) -based element such as (Lu) may be further included.

The data lines DLm and DLm + 1, the source electrode 222 and the drain electrode 223 may be disposed on the same layer on the active layer.

A semiconductor pattern made of the same semiconductor layer as the active layer may be disposed under the data lines DLm and DLm + 1. However, the present invention is not limited thereto, and when the data lines DLm, DLm + 1 and the active layer are formed in different mask processes, a semiconductor pattern may not be disposed under the data lines DLm, DLm + 1. have.

The data lines DLm and DLm + 1, the source electrode 222 and the drain electrode 223 may be formed of a second metal layer.

As the second metal layer, aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy), gold ( Au), Gold alloy (Au alloy), Chromium (Cr), Titanium (Ti), Titanium alloy (Ti alloy), Moly tungsten (MoW), Molytitanium (MoTi), Copper / Molytitanium (Cu / MoTi) It may include at least one selected from the group of conductive metal, or a combination of two or more thereof, or other suitable materials.

The data lines DLm and DLm + 1 may be disposed in a second direction different from the first direction to partition the plurality of sub-pixels along with the gate lines GLn and GLn + 1.

The gate electrode 221 connected to the gate lines GLn and GLn + 1, the active layer disposed on the gate electrode 221, the source electrode 222 and the source electrode 222 connected to the data lines DLm and DLm + 1 ) And the drain electrode 223 disposed opposite to and electrically connected to the pixel electrode 218 may constitute a thin film transistor.

The second insulating layer 215b may be disposed on the data lines DLm and DLm + 1 and the source electrode 222 and the drain electrode 223.

As the second insulating layer 215b, a silicon (Si) -based oxide film, a nitride film, or a compound containing the same, and a metal oxide film containing Al ₂ O ₃ (metal oxide), an organic insulating film, and a low dielectric constant (low- k) may include a material having a value. For example, as the second insulating layer 215b, silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), tantalum oxide ( Ta ₂ O ₅ ), barium-strontium-titanium-oxygen compound (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compound (Bi-Zn-Nb-O). , Or a combination of two or more of these, or other suitable materials.

Red, green and blue color filters 209a and 209b may be formed in the sub-pixel region of the array substrate 210 on which the second insulating layer 215b is formed.

At this time, in the vertical black matrix area where the gate lines GLn and GLn + 1 and the horizontal common line 208l pass, a color blocking layer comprising red and blue color filters 209a and 209b is mixed and stacked to form a light-shielding layer. Can form. That is, a light blocking layer may be disposed on the second insulating layer 215b at the upper and lower boundaries of the sub-pixel.

A third insulating layer 215c may be disposed on the array substrate 210 on which the red, green, and blue color filters 209a and 209b are formed.

As the third insulating layer 215c, a silicon (Si) -based oxide film, a nitride film, or a compound containing the same, and a metal oxide film containing Al ₂ O ₃ (metal oxide), an organic insulating film, and a low dielectric constant (low- k) may include a material having a value. For example, as the third insulating layer 215c, silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), tantalum oxide ( Ta ₂ O ₅ ), barium-strontium-titanium-oxygen compound (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compound (Bi-Zn-Nb-O). , Or a combination of two or more of these, or other suitable materials.

The common electrode 208 and the pixel electrode 218 may be disposed on the third insulating layer 215c.

The pixel electrode 218 may be alternately disposed with the common electrode 208 within the sub-pixel to form a transverse electric field.

The shielding line of the present invention may be disposed not only between the nth gate line and the horizontal common line, but also between the n + 1th gate line and the horizontal common line, which will be described in detail with reference to the following drawings.

14 is a diagram illustrating another cross-section of a liquid crystal display device according to a third exemplary embodiment of the present invention.

Another cross section of the liquid crystal display device according to the third embodiment of the present invention shown in FIG. 14 includes not only between the nth gate line GLn and the horizontal common line 208l described above by the shielding lines 235a and 235b. It is made of the same configuration as the liquid crystal display device according to the third embodiment of the present invention shown in FIGS. 12 and 13 except that it is also disposed between the + 1st gate line GLn + 1 and the horizontal common line 208l. have. Therefore, the description of the same configuration will be omitted.

Referring to FIG. 14, the gate lines GLn and GLn + 1, the gate electrode 221, the vertical common line CL, the horizontal common line 208l, and the shielding lines 235a and 235b are placed on the array substrate 210. Can be placed on the same layer.

The gate lines GLn and GLn + 1, the horizontal common line 208l, and the shielding lines 235a and 235b may be arranged in a direction parallel to the first direction.

Also, the vertical common line CL may be arranged in a parallel direction with respect to a second direction different from the first direction.

One end of the vertical common line CL may be connected to the horizontal common line 208l.

For example, the shielding lines 235a and 235b are horizontal to the first shielding line 235a and the n + 1th gate line GLn + 1 disposed between the n-th gate line GLn and the horizontal common line 208l. It may be configured as a second shielding line 235b disposed between the common lines 208l.

A power source equal to or higher than the gate voltage supplied to the gate lines GLn and GLn + 1 may be applied to the shielding lines 235a and 235b. Accordingly, an electric field generated between the nth gate line GLn and the pixel electrode 218 and the n + 1th gate line GLn + 1 and the pixel electrode 218 may be shielded.

The array substrate 210 may be made of a transparent insulating material such as glass.

The gate electrode 221 may form part of the gate lines GLn and GLn + 1.

The gate lines GLn and GLn + 1, the gate electrode 221, the vertical common line CL, the horizontal common line 208l, and the shielding lines 235a and 235b are formed of a first metal layer on the array substrate 210. Can be.

As the first metal layer, aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy), gold ( Conductive metal groups including Au), gold alloys (Au alloy), chromium (Cr), titanium (Ti), titanium alloys, molybdenum tungsten (MoW), molybdenum titanium (MoTi), copper / mortitanium titanium (Cu / MoTi) It may include at least any one selected from, or a combination of two or more thereof, or other suitable materials.

On the other hand, the shielding line of the present invention may be disposed on both the gate line and the pixel electrode on the light-shielding layer and between the gate line and the horizontal common line on the same layer as the gate line, and through the fourth embodiment of the present invention It is explained in detail.

15 is a view showing a cross-section of a liquid crystal display device according to a fourth embodiment of the present invention as an example.

The liquid crystal display according to the fourth embodiment of the present invention shown in FIG. 15 gates the upper shielding lines 325a and 325b and the lower shielding lines 335a and 335b of a power source equal to or higher than the gate voltage. It is characterized in that the electric field between the gate lines GLn and GLn + 1 and the pixel electrode 318 is shielded by forming between the lines GLn and GLn + 1 and the pixel electrode 318. That is, in the liquid crystal display according to the fourth embodiment of the present invention, the upper shielding lines 325a and 325b are formed on the light blocking layer between the gate lines GLn and GLn + 1 and the pixel electrode 318, and the lower shielding is performed. The lines 335a and 335b are formed between the gate lines GLn and GLn + 1 and the horizontal common line 308l to shield the electric field between the gate lines GLn and GLn + 1 and the pixel electrode 318. Is done.

The liquid crystal display device according to the fourth embodiment of the present invention illustrated in FIG. 15 may be formed of a COT structure in which color filters 309a and 309b are formed on the array substrate 310 together with a thin film transistor, but is not limited thereto. It is not.

In addition, the liquid crystal display according to the fourth embodiment of the present invention, instead of removing the existing black matrix, forms a light shielding pattern with an opaque conductive material at the left and right borders of the sub-pixel region, while the upper and lower portions of the sub-pixel region are formed. It is characterized by laminating a light-shielding layer made of a color pigment on the border.

In this case, the light blocking pattern is formed to cover the data line on the data line, thereby preventing color interference between adjacent sub-pixels.

The light-blocking layer is formed by mixing and laminating the color pigments constituting the red and blue color filters 309a and 309b in the vertical black matrix region where the gate lines GLn and GLn + 1 and the horizontal common line 308l pass. can do.

Referring to FIG. 15, gate lines GLn and GLn + 1, gate electrodes, vertical common lines, horizontal common lines 308l, and lower shielding lines 335a and 335b are disposed on the same layer on the array substrate 310. Can be.

The gate lines GLn and GLn + 1, the horizontal common line 308l, and the lower shielding lines 335a and 335b may be arranged in a direction parallel to the first direction.

Further, the vertical common line may be arranged in a direction parallel to the second direction different from the first direction.

One end of the vertical common line may be connected to the horizontal common line 308l.

For example, the lower shielding lines 335a and 335b include the lower first shielding line 335a and the n + 1th gate line GLn + 1 disposed between the nth gate line GLn and the horizontal common line 308l. And a lower second shielding line 335b disposed between the horizontal common line 308l.

A power source equal to or higher than the gate voltage supplied to the gate lines GLn and GLn + 1 may be applied to the lower shielding lines 335a and 335b.

Accordingly, an electric field generated between the nth gate line GLn and the pixel electrode 318 and the n + 1th gate line GLn + 1 and the pixel electrode 318 can be shielded.

The array substrate 310 may be made of a transparent insulating material such as glass.

The gate electrode may form part of the gate lines GLn and GLn + 1.

The gate lines GLn and GLn + 1, the gate electrode, the vertical common line, the horizontal common line 308l, and the lower shielding lines 335a and 335b may be formed as a first metal layer on the array substrate 310.

As the first metal layer, aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy), gold ( Conductive metal groups including Au), gold alloys (Au alloy), chromium (Cr), titanium (Ti), titanium alloys, molybdenum tungsten (MoW), molybdenum titanium (MoTi), copper / mortitanium titanium (Cu / MoTi) It may include at least any one selected from, or a combination of two or more thereof, or other suitable materials.

In addition, the first insulating layer 315a may be provided on the gate lines GLn and GLn + 1, the gate electrode, the vertical common line, the horizontal common line 308l, and the lower shielding lines 335a and 335b.

As the first insulating layer 315a, a silicon (Si) -based oxide film, a nitride film, or a compound containing the same, and a metal oxide film containing Al ₂ O ₃ (metal oxide), an organic insulating film, and a low dielectric constant (low- k) may include a material having a value.

For example, as the first insulating layer 315a, silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), tantalum oxide ( Ta ₂ O ₅ ), barium-strontium-titanium-oxygen compound (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compound (Bi-Zn-Nb-O). , Or a combination of two or more of these, or other suitable materials.

The active layer may be disposed on the first insulating layer 315a.

The active layer may be formed of a semiconductor layer.

As the semiconductor layer, amorphous silicon (a-Si), low temperature polysilicon (LTPS), oxide semiconductor of IGZO series, compound semiconductor, carbon nano tube, graphene and organic semiconductor And the like.

The data line and the source electrode and the drain electrode may be disposed on the same layer on the active layer.

The data line, the source electrode, and the drain electrode may be made of a second metal layer.

As the second metal layer, aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy), gold ( Au), Gold alloy (Au alloy), Chromium (Cr), Titanium (Ti), Titanium alloy (Ti alloy), Moly tungsten (MoW), Molytitanium (MoTi), Copper / Molytitanium (Cu / MoTi) It may include at least one selected from the group of conductive metal, or a combination of two or more thereof, or other suitable materials.

The data lines are arranged in the second direction to partition the plurality of sub-pixels along with the gate lines GLn and GLn + 1.

The second insulating layer 315b may be disposed on the data line, the source electrode, and the drain electrode.

As the second insulating layer 315b, a silicon (Si) -based oxide film, a nitride film, or a compound containing the same, and a metal oxide film containing Al ₂ O ₃ (metal oxide), an organic insulating film, and a low dielectric constant (low- k) may include a material having a value. For example, as the second insulating layer 315b, silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), tantalum oxide ( Ta ₂ O ₅ ), barium-strontium-titanium-oxygen compound (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compound (Bi-Zn-Nb-O). , Or a combination of two or more of these, or other suitable materials.

Red, green and blue color filters 309a and 309b may be formed in a sub-pixel region of the array substrate 310 on which the second insulating layer 315b is formed.

At this time, in the vertical black matrix region where the gate lines GLn and GLn + 1 and the horizontal common line 308l pass, the color pigments constituting the red and blue color filters 309a and 309b are mixed and stacked to form a light-shielding layer Can form. That is, a light blocking layer may be disposed on the second insulating layer 315b at the upper and lower boundaries of the sub-pixel.

A third insulating layer 315c may be disposed on the array substrate 310 on which the red, green, and blue color filters 309a and 309b are formed.

As the third insulating layer 315c, a silicon (Si) -based oxide film, a nitride film, or a compound containing the same, and a metal oxide film containing Al ₂ O ₃ , an organic insulating film, and a low dielectric constant (low- k) may include a material having a value. For example, as the third insulating layer 315c, silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), tantalum oxide ( Ta ₂ O ₅ ), barium-strontium-titanium-oxygen compound (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compound (Bi-Zn-Nb-O). , Or a combination of two or more of these, or other suitable materials.

Upper shielding lines 325a and 325b may be disposed on the third insulating layer 315c.

The upper shielding lines 325a and 325b include an upper first shielding line 325a and an n + 1th gate line GLn + 1 and a pixel electrode disposed between the n-th gate line GLn and the pixel electrode 318. 318) may be disposed between the upper second shielding line (325b).

The upper shielding lines 325a and 325b may be disposed in the same first direction as the gate lines GLn and GLn + 1.

The upper shielding lines 325a and 325b may be disposed under the common electrode 308 and overlapped by the common electrode 308.

The upper shielding lines 325a and 325b may be disposed on the light blocking layer to partially overlap the light blocking layer.

The upper shielding lines 325a and 325b may be made of a third metal layer.

As the third metal layer, aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy), gold (Au) ), Including gold alloy (Au alloy), chromium (Cr), titanium (Ti), titanium alloy (Ti alloy), molybdenum tungsten (MoW), molybdenum titanium (MoTi), copper / molybdenum titanium (Cu / MoTi) It may also include at least one selected from conductive metal groups, or a combination of two or more thereof, or other suitable materials.

A power source equal to or higher than the gate voltage supplied to the gate lines GLn and GLn + 1 may be applied to the upper shielding lines 325a and 325b. Accordingly, an electric field generated between the nth gate line GLn and the pixel electrode 318 and the n + 1th gate line GLn + 1 and the pixel electrode 318 may be shielded.

A fourth insulating layer 315d may be disposed on the array substrate 310 on which the upper shielding lines 325a and 325b are formed.

As the fourth insulating layer 315d, a silicon (Si) -based oxide film, a nitride film, or a compound containing the same, and a metal oxide film including Al ₂ O ₃ , an organic insulating film, and a low dielectric constant (low- k) may include a material having a value. For example, as the fourth insulating layer 315d, silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), tantalum oxide ( Ta ₂ O ₅ ), barium-strontium-titanium-oxygen compound (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compound (Bi-Zn-Nb-O). , Or a combination of two or more of these, or other suitable materials.

The common electrode 308 and the pixel electrode 318 may be disposed on the fourth insulating layer 315d.

The pixel electrode 318 may be alternately disposed with the common electrode 308 within the sub-pixel to form a lateral electric field.

On the other hand, the present invention can fundamentally shield the parasitic capacitance between the gate line and the pixel electrode by shielding the electric field formed under the array substrate, which will be described in detail through the following fifth and fifth embodiments of the present invention. Explain.

16 is a plan view illustrating a portion of a pixel of a liquid crystal display according to a fifth embodiment of the present invention as an example.

FIG. 17 is a view showing an example of a cross-section cut along line C-C 'in the liquid crystal display according to the fifth embodiment of the present invention shown in FIG. 16.

In this case, FIG. 16 shows a portion of a pair of vertically adjacent sub-pixels connected to the nth gate line GL and the n + 1th gate line GLn + 1, respectively, as the gate lines GLn and GLn + 1. It is showing mainly.

In the liquid crystal display device according to the fifth embodiment of the present invention shown in FIGS. 16 and 17, by forming a shield line 408la of a power source equal to or higher than the gate voltage as part of the horizontal common line 408l It is characterized in that it shields the electric field formed under the array substrate 410.

In the liquid crystal display device according to the fifth embodiment of the present invention shown in FIGS. 16 and 17, a color filter on TFT (COT) structure in which color filters 409a and 409b are formed on the array substrate 410 together with thin film transistors It may be configured, but is not limited thereto.

In addition, the liquid crystal display according to the fifth embodiment of the present invention, instead of removing the existing black matrix, forms a light shielding pattern with an opaque conductive material at the left and right borders of the sub-pixel region, while the top and bottom of the sub-pixel region It is characterized by laminating a light-shielding layer made of a color pigment on the border.

In this case, the light blocking pattern is formed to cover the data lines DLm and DLm + 1 on the data lines DLm and DLm + 1, thereby preventing color interference between adjacent sub-pixels.

The light-blocking layer is formed by mixing and laminating the color pigments constituting the red and blue color filters 409a and 409b in the vertical black matrix area where the gate lines GLn and GLn + 1 and the horizontal common line 408l pass. can do.

16 and 17, the gate lines GLn, GLn + 1, the gate electrode 421, the vertical common line CL, and the horizontal common line 408l are disposed on the same layer on the array substrate 410. Can be.

The gate lines GLn and GLn + 1 and the horizontal common line 408l may be arranged in a direction parallel to the first direction.

Also, the vertical common line CL may be arranged in a parallel direction with respect to a second direction different from the first direction.

One end of the vertical common line CL may be connected to the horizontal common line 408l.

The gate lines GLn and GLn + 1, the gate electrode 421, the vertical common line CL, and the horizontal common line 408l may be formed of a double layer structure of a transparent first metal layer and an opaque second metal layer.

As the first metal layer, a transparent conductive material of indium tin oxide (ITO) or indium zinc oxide (IZO) may be included.

As the second metal layer, aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy), gold ( Conductive metal groups including Au), gold alloys (Au alloy), chromium (Cr), titanium (Ti), titanium alloys, molybdenum tungsten (MoW), molybdenum titanium (MoTi), copper / mortitanium titanium (Cu / MoTi) It may include at least any one selected from, or a combination of two or more thereof, or other suitable materials.

For example, the gate lines GLn and GLn + 1 may include upper gate lines GLnb and GLn + 1b and lower gate lines GLna and GLn + 1a.

In addition, the horizontal common line 408l may be composed of an upper horizontal common line 408lb and a lower horizontal common line 408la.

At this time, the lower horizontal common line 408la extends toward the pixel electrode 418 compared to the upper horizontal common line 408lb to form a shielding line. A power source equal to or higher than the gate voltage supplied to the gate lines GLn and GLn + 1 may be applied to the horizontal common line 408l including the shielding line. Accordingly, the electric field generated between the gate lines GLn and GLn + 1 and the pixel electrode 418 can be shielded.

Accordingly, for example, the parasitic capacitance formed between the n-th gate line GLn and the pixel electrode 418 is reduced by about 99% to about 1.54x10 ^-19 F compared to the existing (= about 5.08x10 ^-16 F). Able to know.

The gate electrode 421 may form part of the gate lines GLn and GLn + 1.

The first insulating layer 415a may be provided on the gate lines GLn and GLn + 1, the gate electrode 421, the vertical common line CL, and the horizontal common line 408l.

The active layer may be disposed on the first insulating layer 415a.

The data lines DLm and DLm + 1, the source electrode 422 and the drain electrode 423 may be disposed on the same layer on the active layer.

The data lines DLm and DLm + 1, the source electrode 422 and the drain electrode 423 may be formed of a third metal layer.

As the third metal layer, aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy), gold ( Au), Gold alloy (Au alloy), Chromium (Cr), Titanium (Ti), Titanium alloy (Ti alloy), Moly tungsten (MoW), Molytitanium (MoTi), Copper / Molytitanium (Cu / MoTi) It may include at least one selected from the group of conductive metal, or a combination of two or more thereof, or other suitable materials.

The data lines DLm and DLm + 1 may be disposed in a second direction different from the first direction to partition the plurality of sub-pixels along with the gate lines GLn and GLn + 1.

A second insulating layer 415b may be disposed on the data lines DLm and DLm + 1, the source electrode 422 and the drain electrode 423.

Red, green and blue color filters 409a and 409b may be formed in the sub-pixel region of the array substrate 410 on which the second insulating layer 415b is formed.

At this time, in the vertical black matrix area where the gate lines GLn and GLn + 1 and the horizontal common line 408l pass, the color pigments constituting the red and blue color filters 409a and 409b are mixed and stacked to form a light-shielding layer. Can form. That is, a light blocking layer may be disposed on the second insulating layer 415b at the upper and lower boundaries of the sub-pixel.

A third insulating layer 415c may be disposed on the array substrate 410 on which the red, green, and blue color filters 409a and 409b are formed.

The common electrode 408 and the pixel electrode 418 may be disposed on the third insulating layer 415c.

The pixel electrode 418 may be alternately disposed with the common electrode 408 within the sub-pixel to form a lateral electric field.

18 is a diagram illustrating a cross-section of a liquid crystal display device according to a fifth embodiment of the present invention as an example.

In the liquid crystal display according to the fifth embodiment of the present invention shown in FIG. 18, the shield line 545 of the power source equal to or higher than the gate voltage is formed below the gate lines GLn and GLn + 1. It is characterized in that it shields the electric field formed under the array substrate 510.

The liquid crystal display device according to the fifth embodiment of the present invention illustrated in FIG. 18 may be formed of a COT structure in which color filters 509a and 509b are formed on a array substrate 510 together with a thin film transistor, but is not limited thereto. It is not.

In addition, the liquid crystal display according to the fifth embodiment of the present invention, instead of removing the existing black matrix, forms a light shielding pattern with an opaque conductive material at the left and right borders of the sub-pixel region, while the top and bottom of the sub-pixel region It is characterized by laminating a light-shielding layer made of a color pigment on the border.

In this case, the light blocking pattern is formed to cover the data line on the data line, thereby preventing color interference between adjacent sub-pixels.

The light-blocking layer is formed by mixing and laminating the color pigments constituting the red and blue color filters 509a and 509b in the vertical black matrix region where the gate lines GLn and GLn + 1 and the horizontal common line 508l pass. can do.

Referring to FIG. 18, a shielding line 545 may be disposed on the array substrate 510.

The shielding line 545 may be formed of an opaque metal layer.

As the metal layer, aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy), gold (Au) , Gold alloy (Au alloy), chromium (Cr), titanium (Ti), titanium alloy, molybdenum tungsten (MoW), selected from the group of conductive metals including molybdenum (MoTi), copper / molybdenum (Cu / MoTi) It may also include at least one, or a combination of two or more thereof, or other suitable materials.

At this time, a power source equal to or higher than the gate voltage supplied to the gate lines GLn and GLn + 1 may be applied to the shielding line 545. Accordingly, an electric field generated between the gate lines GLn and GLn + 1 and the pixel electrode 518 can be shielded.

Accordingly, for example, the parasitic capacitance formed between the n-th gate line GLn and the pixel electrode 518 is reduced by about 99% to about 8.00x10 ^-21 F compared to the existing (= about 5.08x10 ^-16 F). Able to know.

In addition, the shielding line 545 may overlap the gate lines GLn and GLn + 1 thereon and a portion of the horizontal common line 508l.

A buffer layer 511 may be disposed on the shielding line 545.

The gate lines GLn and GLn + 1, the gate electrode, the vertical common line, and the horizontal common line 508l may be disposed on the same layer on the buffer layer 511.

The gate lines GLn and GLn + 1 and the horizontal common line 508l may be arranged in a direction parallel to the first direction.

The vertical common line may be arranged in a direction parallel to a second direction different from the first direction.

One end of the vertical common line may be connected to the horizontal common line 508l.

The gate electrode may form part of the gate lines GLn and GLn + 1.

In addition, the first insulating layer 515a may be provided on the gate lines GLn and GLn + 1, the gate electrode, the vertical common line, and the horizontal common line 508l.

The active layer may be disposed on the first insulating layer 515a.

The data line and the source electrode and the drain electrode may be disposed on the same layer on the active layer.

The data lines are arranged in the second direction to partition the plurality of sub-pixels along with the gate lines GLn and GLn + 1.

The second insulating layer 515b may be disposed on the data line, the source electrode, and the drain electrode.

Red, green and blue color filters 509a and 509b may be formed in a sub-pixel region of the array substrate 510 on which the second insulating layer 515b is formed.

At this time, in the vertical black matrix area where the gate lines GLn and GLn + 1 and the horizontal common line 508l pass, the color pigments constituting the red and blue color filters 509a and 509b are mixed and stacked to form a light-shielding layer Can form. That is, a light blocking layer may be disposed on the second insulating layer 515b at the upper and lower boundaries of the sub-pixel.

A third insulating layer 515c may be disposed on the array substrate 510 on which red, green, and blue color filters 509a and 509b are formed.

The common electrode 508 and the pixel electrode 518 may be disposed on the third insulating layer 515c.

The pixel electrode 518 may be alternately disposed with the common electrode 508 within the sub-pixel to form a lateral electric field.

On the other hand, the present invention is characterized by changing the gate driving method by gate swap driving or out-of-order driving in order to solve polar asymmetry due to structural differences, which will be described in detail. .

19 is a view for showing a driving method according to a comparative example.

20 is a view for showing a driving method according to an embodiment.

21 is a view for showing a driving method according to another embodiment.

20 shows an example of a cross drive method according to an embodiment of the present invention, and FIG. 21 shows an example of a non-sequential drive method according to another embodiment of the present invention. Such a cross driving and a non-sequential driving method may be repeatedly applied using eight gate lines (GL1, GL2, GL3, GL4, GL5, GL6, GL7, and GL8) shown as examples.

19 to 21, eight gate lines (GL1, GL2, GL3, GL4, GL5, GL6, GL7, GL8) and three data lines (DL1, DL2, DL3) cross each other and 16 sub-pixels of 4x4 The case where is divided is given as an example.

19 to 21 show the order in which eight gate lines (GL1, GL2, GL3, GL4, GL5, GL6, GL7, and GL8) are scanned, and gate lines (GL1, GL2, GL3, GL4, GL5, GL6, GL7, GL8) ), ①, ②, ③, ④, ⑤, ⑥, ⑦, ⑧ are displayed on the right side of).

Referring to FIG. 19, sequentially driving in the order of ①, ②, ③, ④, ⑤, ⑥, ⑦, ⑧ along the normal gate lines GL1, GL2, GL3, GL4, GL5, GL7, GL8 You can see that

In the past, due to structural limitations of the DRD column inversion structure, voltage drop and polarity asymmetry caused by coupling between the gate line and the pixel electrode occurred. For reference, the polarity asymmetry is due to, for example, the occurrence of a voltage drop due to the n + 1th gate voltage when charging the nth sub-pixel. As a result, image quality issues such as defective purlins occurred.

Accordingly, the present invention can adopt a cross driving method that intersects the scanning order of neighboring gate lines GL1, GL2, GL3, GL4, GL5, GL6, GL7, GL8.

Referring to FIG. 20, it is possible to drive the scanning order of some of the gate lines GL1, GL2, GL3, GL4, GL5, GL6, GL7, and GL8 crossing.

That is, for example, it can be seen that the fourth gate line GL4 is driven after the second gate line GL2, and then the third gate line GL3 is driven. Also, it can be seen that the 8th gate line GL8 is driven after the 6th gate line GL6, and the 7th gate line GL7 is then driven. That is, the scanning order of the third gate line GL3 and the fourth gate line GL4 is changed, and the scanning order of the seventh gate line GL7 and the eighth gate line GL8 is changed.

As described above, when any pair of gate lines GL1, GL2, GL5, and GL6 are scanned in a normal order, any other pair of gate lines GL1, GL2, GL5, and GL6 neighboring another pair of gates The lines GL3, GL4, GL7, GL8 can be changed to intersect the scanning order.

This causes a voltage drop due to parasitic capacitance when charging the n-th sub-pixel when driving the n + 1th gate line. However, when driving the n + 2th gate line, there is no effect when charging the nth sub-pixel.

Alternatively, the present invention can drive the scanning order of the gate lines out of order in order to prevent a voltage drop by neighboring gate lines during sub-pixel driving.

Referring to FIG. 21, for example, it can be seen that the sixth gate line GL6 is driven after the first gate line GL1 and the third gate line GL3 is driven. Subsequently, it can be seen that the eighth gate line GL8 is driven, and then the fifth gate line GL8 is driven. Next, it can be seen that the second gate line GL2 is driven, and then the seventh gate line GL7 is driven. Finally, the fourth gate line GL4 is driven.

That is, for example, the first gate line GL1, the sixth gate line GL6, the third gate line GL3, the eighth gate line GL8, the fifth gate line GL5, and the second gate line Gate scanning may be performed in the order of (GL2), 7th gate line GL7 and 4th gate line GL4. However, the present invention is not limited thereto.

When this non-sequential driving method is applied, it can be seen that there is no coupling effect due to the n + 3 gate line when the n-th sub-pixel is charged, and the effect is excellent.

As described above, the present invention can improve display quality by improving image quality issues occurring in the DRD column inversion structure. On the other hand, the present invention, it is possible to minimize the overlap deviation of the GIP (Gate in Panel) -array internal link by changing the connection order between the link wiring and the gate line in a non-sequential driving method.

22 is a diagram showing an example of a GIP-array internal link design according to an embodiment.

23 is a diagram illustrating an example of a GIP-array internal link design according to another embodiment.

FIG. 22 shows a GIP-array internal link design as an example of the non-sequential driving method illustrated in FIG. 21. In addition, FIG. 23 shows an example of a GIP-array internal link design when another non-sequential driving method is applied. This GIP-array internal link design can be applied repeatedly using the eight gate lines (GL1, GL2, GL3, GL4, GL5, GL6, GL7, GL8) shown as an example as a basic unit.

Referring to FIG. 22, according to an embodiment of the present invention, the first gate line GL1, the sixth gate line GL6, the third gate line GL3, the eighth gate line GL8, and the fifth gate line When gate scanning is performed in the order of (GL5), second gate line (GL2), seventh gate line (GL7), and fourth gate line (GL4), the first gate block (through each link wiring LL) GIP Block # 1) is connected to the first gate line (GL1), the second gate block (GIP Block # 2) is connected to the sixth gate line (GL6), and the third gate block (GIP Block # 3) is It may be connected to the third gate line GL3. In addition, the fourth gate block (GIP Block # 4) is connected to the eighth gate line GL8, the fifth gate block (GIP Block # 5) is connected to the fifth gate line GL5, and the sixth gate block (GIP Block # 6) may be connected to the second gate line GL2. Also, the seventh gate block (GIP Block # 7) may be connected to the seventh gate line GL7, and the eighth gate block (GIP Block # 8) may be connected to the fourth gate line GL4.

In this case, for example, odd-numbered gate blocks (GIP Block # 1, GIP Block # 3, GIP Block # 5, GIP Block # 7) are respectively connected to the corresponding gate lines (GL1, GL3, GL5, GL7). You can.

In addition, in this case, overlapping occurs four times between the link wirings LL, and since overlapping between the link wirings LL exists only in the specific link wiring LL, there is a possibility that image quality deteriorates due to signal deviation between the link wirings LL.

On the other hand, in FIG. 23, it can be seen that the second gate line GL2 is driven after the fourth gate line GL4 and the sixth gate line GL6 is driven. Subsequently, it can be seen that the first gate line GL1 is driven, and then the eighth gate line GL8 is driven. Next, it can be seen that the third gate line GL3 is driven, and then the seventh gate line GL7 is driven. Finally, the fifth gate line GL5 is driven.

That is, for example, the fourth gate line GL4, the second gate line GL2, the sixth gate line GL6, the first gate line GL1, the eighth gate line GL8, the third gate line Gate scanning may be performed in the order of (GL3), 7th gate line GL7 and 5th gate line GL5.

In this case, referring to FIG. 23, according to another embodiment of the present invention, the fourth gate line GL4, the second gate line GL2, the sixth gate line GL6, the first gate line GL1, 8 When gate scanning is performed in the order of the first gate line GL8, the third gate line GL3, the seventh gate line GL7, and the fifth gate line GL5, the first through the respective link wiring LL The gate block (GIP Block # 1) is connected to the fourth gate line (GL4), the second gate block (GIP Block # 2) is connected to the second gate line (GL2), and the third gate block (GIP Block # 1). 3) may be connected to the sixth gate line GL6. In addition, the fourth gate block (GIP Block # 4) is connected to the first gate line GL1, the fifth gate block (GIP Block # 5) is connected to the eighth gate line GL8, and the sixth gate block (GIP Block # 6) may be connected to the third gate line GL3. Further, the seventh gate block (GIP Block # 7) may be connected to the seventh gate line GL7, and the eighth gate block (GIP Block # 8) may be connected to the fifth gate line GL5.

In this case, for example, each of the second gate block (GIP Block # 2) and the fifth gate block (GIP Block # 5) may be connected to the second gate line GL2 and the fifth gate line GL5, respectively. .

In addition, in this case, the overlap between the link wires LL is repeated 4 times, and as the overlap between the link wires LL does not exist only in the specific link wires LL and is dispersed, image quality deterioration can be prevented.

Exemplary embodiments of the present invention can be described as follows.

A liquid crystal display according to an exemplary embodiment of the present invention includes a plurality of pixel units including sub-pixels arranged in a 2 x 4 matrix form, and first data arranged on a first side of a plurality of sub-pixels in a first column. A line, a second data line disposed between a plurality of sub-pixels in the second column and a plurality of sub-pixels in the third column, and a third data line disposed on the second side of the plurality of sub-pixels in the fourth column, , Each of the plurality of pixel units includes a first sub-pixel unit including a first sub-pixel disposed in one row and one column and a second sub-pixel disposed in one row and two columns, and a third disposed in one row and three columns. A second sub-pixel unit comprising a sub-pixel and a fourth sub-pixel disposed in row 1 and column 4, a fifth sub-pixel disposed in row 2 and column 1, and a sixth sub-pixel disposed in row 2 and column 2 Includes a third sub-pixel unit and a seventh sub-pixel disposed in the second row and third column and an eighth sub-pixel disposed in the second row and fourth column A fourth sub-pixel unit, the sixth sub-pixel is connected to the first data line, the fifth sub-pixel is connected to the second data line, and the second data line is connected to the A fourth sub-pixel may be connected, and the third sub-pixel may be connected to the third data line.

According to another feature of the present invention, each of the first data line to the third data line may apply a data voltage of the same polarity during one frame.

According to another feature of the present invention, polarities of data voltages applied by a plurality of data lines adjacent to each other among the first to third data lines may be different from each other.

According to another feature of the invention, the polarity of the data voltage of the first sub-pixel, the third sub-pixel, the fifth sub-pixel and the seventh sub-pixel and the second sub-pixel, the Polarities of data voltages of the fourth sub-pixel, the sixth sub-pixel, and the eighth sub-pixel may be different from each other.

According to another feature of the present invention, the first data line and the third data line apply a data voltage of positive polarity, the second data line applies a data voltage of negative polarity, and the first The sub-pixel, the third sub-pixel, the fifth sub-pixel and the seventh sub-pixel are charged with the data voltage of the positive polarity, and the second sub-pixel, the fourth sub-pixel, Data voltages of the negative polarity may be charged in the sixth sub-pixel and the eighth sub-pixel.

According to another feature of the present invention, a liquid crystal display device includes a first gate line disposed on a third side of a plurality of sub-pixels in a first row, a plurality of sub-pixels in a first row, and a second row. And a second gate line and a third gate line sequentially disposed between a plurality of sub-pixels, and a fourth gate line disposed on a fourth side of the plurality of sub-pixels in the second row, wherein the plurality of Each of the sub-pixels may further include a thin film transistor connected to any one of the first data line to the third data line and one of the first gate line and the fourth gate line.

According to another feature of the present invention, the thin film transistor of the third sub-pixel connected to the second gate line and the thin film transistor of the fourth sub-pixel are disposed adjacent to the second gate line, and the second The thin film transistor of the seventh sub-pixel connected to the three gate line and the thin film transistor of the eighth sub-pixel may be disposed adjacent to the third gate line.

According to another feature of the present invention, the first sub-pixel thin film transistor connected to the first gate line and the second sub-pixel thin film transistor are disposed adjacent to the first gate line, and the first The thin film transistor of the fifth sub-pixel connected to the four gate line and the thin film transistor of the sixth sub-pixel may be disposed adjacent to the third gate line.

According to another feature of the present invention, the thin film transistors based on 2 x 4 sub-pixels may be arranged symmetrically in an origin that is inverted up, down, left, and right.

According to another feature of the present invention, the thin film transistor of the third sub-pixel connected to the second gate line and the thin film transistor of the fourth sub-pixel are disposed adjacent to the second gate line, and the second The fifth sub-pixel thin film transistor connected to the gate line and the sixth sub-pixel thin film transistor may be disposed adjacent to the third gate line.

According to another feature of the present invention, the first sub-pixel thin film transistor connected to the first gate line and the second sub-pixel thin film transistor are disposed adjacent to the first gate line, and the first The thin film transistor of the seventh sub-pixel connected to the four gate line and the thin film transistor of the eighth sub-pixel may be disposed adjacent to the fourth gate line.

According to another feature of the present invention, the liquid crystal display device further includes a light blocking layer formed at a boundary between a color filter provided in the sub-pixel and the sub-pixels neighboring up and down, and composed of at least one color filter. It can contain.

According to another feature of the present invention, the light blocking layer may be configured by stacking a blue color filter on a red color filter.

According to another feature of the present invention, a liquid crystal display device may include one side of the sub-pixel and one of the first gate line to the fourth gate line in a direction parallel to the first gate line to the fourth gate line. It may further include a horizontal common line disposed between any one.

According to another feature of the present invention, the liquid crystal display device may further include a shielding line disposed between any one of the first gate line to the fourth gate line and the pixel electrode on the light blocking layer.

According to another feature of the present invention, the shielding line may be disposed on both sides of the upper and lower boundaries of the sub-pixel in a direction parallel to the first gate line to the fourth gate line.

According to another feature of the present invention, the shielding line may be disposed under the common electrode and overlap the common electrode.

According to another feature of the present invention, the liquid crystal display device includes the horizontal common line and the first gate line to the fourth gate on the same layer as the first gate line to the fourth gate line and the horizontal common line. A shielding line disposed between any one of the lines may be further included.

According to another feature of the present invention, the liquid crystal display device includes the horizontal common line and the first gate line to the fourth gate on the same layer as the first gate line to the fourth gate line and the horizontal common line. Another shielding line disposed between any one of the lines may be further included.

According to another feature of the present invention, the liquid crystal display device may further include a shielding line disposed below the horizontal common line and extending toward the pixel electrode compared to the horizontal common line.

According to another feature of the present invention, the shielding line may overlap any one of the first to fourth gate lines and a portion of the horizontal common line.

According to another feature of the present invention, when any pair of gate lines is scanned in a normal order, the pair of gate lines adjacent to the other pair of gate lines may be changed so that the scanning order intersects each other. You can.

According to another feature of the present invention, the scanning order of the third and fourth gate lines may be changed based on the eight gate lines, and the scanning order of the seventh and eighth gate lines may be changed.

According to another feature of the invention, based on the eight gate lines, the first gate line, the sixth gate line, the third gate line, the eighth gate line, the fifth gate line, the second gate line, the seventh gate Gate scanning may proceed in the order of the line and the fourth gate line.

According to another feature of the present invention, through each link wiring, a first gate block is connected to the first gate line, a second gate block is connected to the sixth gate line, and a third gate block is the A third gate line, a fourth gate block connected to the eighth gate line, a fifth gate block connected to the fifth gate line, a sixth gate block connected to the second gate line, The seventh gate block may be connected to the seventh gate line, and the eighth gate block may be connected to the fourth gate line.

According to another feature of the invention, based on the eight gate lines, the fourth gate line, the second gate line, the sixth gate line, the first gate line, the eighth gate line, the third gate line, the seventh gate Gate scanning may be performed in the order of the line and the fifth gate line.

According to another feature of the present invention, through each link wiring, a first gate block is connected to the fourth gate line, a second gate block is connected to the second gate line, and a third gate block is the Connected to the 6th gate line, 4th gate block connected to the 1st gate line, 5th gate block connected to the 8th gate line, 6th gate block connected to the 3rd gate line, The seventh gate block may be connected to the seventh gate line, and the eighth gate block may be connected to the fifth gate line.

According to another feature of the invention, a power equal to or higher than the gate voltage supplied to any one of the first gate line to the fourth gate line may be applied to the shield line.

The embodiments of the present invention have been described in more detail with reference to the accompanying drawings, but the present invention is not necessarily limited to these embodiments, and may be variously modified without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The scope of protection of the present invention should be interpreted by the claims below, and all technical spirits within the equivalent range should be interpreted as being included in the scope of the present invention.

108: common electrode
108l: horizontal common line
110: array substrate
118: pixel electrode
121: gate electrode
122: source electrode
123: drain electrode
125,125a, 125b, 235,235a, 235b, 325a, 325b, 335a, 335b, 408la, 545: shielding line
200: data driving circuit
300: gate driving circuit
400: timing control circuit
CL: Vertical common line
DL1, DL2, DL3, DL4, DL5, DL6, DL7: Data line
GL1, GL2, GL3, GL4, GL5, GL6, GL7, GL8: Gate line
LL: Link line

Claims (28)

A plurality of pixel units including sub-pixels arranged in a 2 x 4 matrix form;
A first data line disposed on a first side of a plurality of sub-pixels in the first column;
A second data line disposed between the plurality of sub-pixels in the second column and the plurality of sub-pixels in the third column; And
A third data line disposed on a second side of the plurality of sub-pixels in the fourth column,
Each of the plurality of pixel units,
A first sub-pixel unit including a first sub-pixel disposed in a first row and a second column and a second sub-pixel disposed in a first row and second column;
A second sub-pixel unit including a third sub-pixel disposed in the first row and third column and a fourth sub-pixel disposed in the first row and fourth column;
A third sub-pixel unit including a fifth sub-pixel disposed in the second row and one column and a sixth sub-pixel disposed in the second row and second column; And
A fourth sub-pixel unit including a seventh sub-pixel disposed in the second row and third column and an eighth sub-pixel disposed in the second row and fourth column,
The sixth sub-pixel is connected to the first data line,
The fifth sub-pixel is connected to the second data line,
The fourth sub-pixel is connected to the second data line,
And the third sub-pixel is connected to the third data line. According to claim 1,
Each of the first data line to the third data line,
A liquid crystal display device that applies data voltages of the same polarity during one frame. According to claim 1,
A polarity of data voltages applied by a plurality of data lines adjacent to each other among the first data line to the third data line is different from each other. According to claim 1,
Polarities of data voltages of the first sub-pixel, the third sub-pixel, the fifth sub-pixel and the seventh sub-pixel and the second sub-pixel, the fourth sub-pixel, and the sixth The polarity of the data voltages of the sub-pixels and the eighth sub-pixels is different from each other. According to claim 1,
The first data line and the third data line apply a positive polarity data voltage,
The second data line applies a negative polarity data voltage,
The first sub-pixel, the third sub-pixel, the fifth sub-pixel and the seventh sub-pixel are charged with the data voltage of the positive polarity,
The second sub-pixel, the fourth sub-pixel, the sixth sub-pixel and the eighth sub-pixel are charged with a data voltage of the negative polarity. According to claim 1,
A first gate line disposed on a third side of the plurality of sub-pixels in the first row;
A second gate line and a third gate line sequentially arranged between the plurality of sub-pixels in the first row and the plurality of sub-pixels in the second row; And
And a fourth gate line disposed on a fourth side of the plurality of sub-pixels in the second row,
Each of the plurality of sub-pixels further includes a thin film transistor connected to any one of the first data line to the third data line and one of the first gate line and the fourth gate line. . The method of claim 6,
The thin film transistor of the third sub-pixel connected to the second gate line and the thin film transistor of the fourth sub-pixel are disposed adjacent to the second gate line,
The thin film transistor of the seventh sub-pixel connected to the third gate line and the thin film transistor of the eighth sub-pixel are disposed adjacent to the third gate line. The method of claim 6,
The thin film transistor of the first sub-pixel and the thin film transistor of the second sub-pixel connected to the first gate line are disposed adjacent to the first gate line,
The fifth sub-pixel thin film transistor and the sixth sub-pixel thin film transistor connected to the fourth gate line are disposed adjacent to the third gate line. The method of claim 6,
The liquid crystal display device, wherein the thin film transistors are arranged symmetrically with respect to each other by flipping vertically and horizontally based on 2 x 4 sub-pixels. The method of claim 6,
The thin film transistor of the third sub-pixel connected to the second gate line and the thin film transistor of the fourth sub-pixel are disposed adjacent to the second gate line,
The fifth sub-pixel thin film transistor and the sixth sub-pixel thin film transistor connected to the third gate line are disposed adjacent to the third gate line. The method of claim 6,
The thin film transistor of the first sub-pixel and the thin film transistor of the second sub-pixel connected to the first gate line are disposed adjacent to the first gate line,
The thin film transistor of the seventh sub-pixel connected to the fourth gate line and the thin film transistor of the eighth sub-pixel are disposed adjacent to the fourth gate line. The method of claim 6,
A color filter provided in the sub-pixel; And
A liquid crystal display device which is provided at a boundary between the sub-pixels neighboring up and down and further includes a light blocking layer formed of at least one color filter. The method of claim 12,
The light blocking layer is a liquid crystal display device comprising a blue color filter laminated on a red color filter. The method of claim 12,
And in a direction parallel to the first gate line to the fourth gate line, further comprising a horizontal common line disposed between one side of the sub-pixel and one of the first gate line to the fourth gate line, Liquid crystal display device. The method of claim 14,
And a shielding line disposed between any one of the first gate line to the fourth gate line and the pixel electrode on the light blocking layer. The method of claim 15,
The shielding line is disposed on both sides of the upper and lower boundaries of the sub-pixel in a direction parallel to the first gate line to the fourth gate line. The method of claim 15,
The shielding line is disposed under the common electrode and overlaps the common electrode. The method of claim 14,
The first gate line to the fourth gate line and the horizontal common line on the same layer, the horizontal common line and a shielding line disposed between any one of the first gate line to the fourth gate line further comprises , Liquid crystal display. The method of claim 15,
The first gate line to the fourth gate line and the horizontal common line on the same layer, the horizontal common line and another shield line disposed between any one of the first gate line to the fourth gate line further includes A liquid crystal display device. The method of claim 14,
The liquid crystal display device further includes a shielding line disposed below the horizontal common line and extending toward the pixel electrode compared to the horizontal common line. The method of claim 20,
The shielding line overlaps any one of the first gate line to the fourth gate line and a portion of the horizontal common line. According to claim 1,
When any pair of gate lines are scanned in a normal order, the pair of gate lines adjacent to the other pair of gate lines is changed such that the scanning order intersects each other. The method of claim 22,
A liquid crystal display device for changing the scanning order of the third and fourth gate lines based on the eight gate lines and changing the scanning order of the seventh and eighth gate lines. According to claim 1,
Based on the eight gate lines, in order of the first gate line, the sixth gate line, the third gate line, the eighth gate line, the fifth gate line, the second gate line, the seventh gate line, and the fourth gate line A liquid crystal display device in which gate scanning proceeds. The method of claim 24,
Through each link wiring, a first gate block is connected to the first gate line, a second gate block is connected to the sixth gate line, a third gate block is connected to the third gate line, and four The fifth gate block is connected to the eighth gate line, the fifth gate block is connected to the fifth gate line, the sixth gate block is connected to the second gate line, and the seventh gate block is the seventh gate A liquid crystal display device connected to a line and an eighth gate block connected to the fourth gate line. According to claim 1,
Based on the eight gate lines, in the order of the fourth gate line, the second gate line, the sixth gate line, the first gate line, the eighth gate line, the third gate line, the seventh gate line, and the fifth gate line A liquid crystal display device in which gate scanning proceeds. The method of claim 26,
Through each link wiring, a first gate block is connected to the fourth gate line, a second gate block is connected to the second gate line, and a third gate block is connected to the sixth gate line, and 4 The first gate block is connected to the first gate line, the fifth gate block is connected to the eighth gate line, the sixth gate block is connected to the third gate line, and the seventh gate block is the seventh gate A liquid crystal display device connected to a line and an eighth gate block connected to the fifth gate line. The method according to any one of claims 15 and 18 to 20,
A liquid crystal display device having a power equal to or higher than a gate voltage supplied to any one of the first gate line to the fourth gate line is applied to the shield line.

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