TWI793148B - Multilayer ceramic capacitor and manufacturing method thereof - Google Patents

Abstract

A multilayer ceramic capacitor includes: a multilayer structure in which each of dielectric layers and each of internal electrode layers are alternately stacked, a main component of the dielectric layers being ceramic, wherein: a second-phase has an average diameter of 150 nm or less and is in at least one of interfaces between the dielectric layers and the internal electrode layers; and at least one of the internal electrode layers includes a grain of which a main component is ceramic.

Description

Multilayer ceramic capacitor and its manufacturing method

The present invention relates to a laminated ceramic capacitor and its manufacturing method.

In recent years, along with the miniaturization of electronic equipment such as smart phones and mobile phones, the miniaturization of electronic components mounted therein has been rapidly advancing. For example, in multilayer ceramic capacitors, in order to ensure specific characteristics and reduce the chip size, it is required to reduce the thickness of the dielectric layer and the internal electrode layer. Regarding multilayer ceramic capacitors, techniques for controlling the secondary phase to obtain desired performance are disclosed (see, for example, Patent Documents 1 and 2). [Prior Art Document] [Patent Document]

[Patent Document 1] Japanese Patent Laid-Open No. 2014-123698 [Patent Document 2] International Publication No. WO2013/018789

[Problem to be solved by the invention]

In addition, it is difficult to maintain a high continuity rate if the internal electrode layer is to be thinned. Therefore, it is considered to delay shrinkage of the internal electrode layer by adding a common material to the internal electrode layer. However, there is concern that the common material diffuses into the dielectric layer during the firing process, reducing the relative permittivity. In the techniques of Patent Documents 1 and 2, the solution to this problem is not disclosed.

The present invention was made in view of the above problems, and an object of the present invention is to provide a multilayer ceramic capacitor capable of suppressing a decrease in the relative permittivity of a dielectric layer and a method for manufacturing the same. [Technical means to solve the problem]

The multilayer ceramic capacitor of the present invention is characterized in that it has a laminated structure in which dielectric layers mainly composed of ceramics and internal electrode layers mainly composed of metal are laminated alternately, and between the dielectric layer and the internal electrode layer A secondary phase with an average diameter of 150 nm or less exists at the interface, and particles mainly composed of ceramics exist in the above-mentioned internal electrode layer.

In the above-mentioned multilayer ceramic capacitor, the average diameter of the above-mentioned secondary phase may be an average value of 200 values obtained by measuring the major axis of the secondary phase.

In the above-mentioned multilayer ceramic capacitor, the total area of the above-mentioned secondary phases may be 0.8% or more and 5.1% of the total area of the above-mentioned dielectric layers in a cross section in the lamination direction of the above-mentioned dielectric layer and the above-mentioned internal electrode layer. the following.

In the multilayer ceramic capacitor, the average diameter of the secondary phase may be set to be 35% or less of the average particle diameter of the main component ceramic of the dielectric layer.

In the above multilayer ceramic capacitor, the average particle size of the main component ceramics of the dielectric layer may be an average value of values obtained by measuring 200 major axes of the main component ceramics of the dielectric layer.

In the above-mentioned multilayer ceramic capacitor, the above-mentioned secondary phase may contain Si.

In the multilayer ceramic capacitor, the area ratio of the particles may be 10% or more in a cross section of the internal electrode layer in the lamination direction of the dielectric layer and the internal electrode layer.

In the above-mentioned multilayer ceramic capacitor, the main component metal of the above-mentioned internal electrode layer may be nickel.

In the above-mentioned multilayer ceramic capacitor, barium titanate may be used as the main component ceramic of the above-mentioned particles.

In the above-mentioned multilayer ceramic capacitor, barium titanate may be used as a main component ceramic of the above-mentioned dielectric layer.

The manufacturing method of the multilayer ceramic capacitor of the present invention is characterized in that it includes: a first step, which is to arrange a pattern of metal conductive paste on the green sheet containing ceramic powder and Si raw material, the metal conductive paste has an average particle size of 100 nm or less and A metal powder whose standard deviation of particle size distribution is 1.5 or less is the main component, and ceramic powder having an average particle size of 10 nm or less and a standard deviation of particle size distribution of 5 or less is used as a common material; and the second step, which is by Firing the ceramic laminate obtained by laminating multiple layers of the laminate unit obtained in the first step above, forming the internal electrode layer by sintering the above metal powder, and forming the dielectric layer by sintering the ceramic powder of the above green sheet ; In the above-mentioned second step, a secondary phase with an average diameter of 150 nm or less is formed at the interface between the above-mentioned dielectric layer and the above-mentioned internal electrode layer, and particles mainly composed of ceramics are formed on the above-mentioned internal electrode layer.

In the above-mentioned method for producing a multilayer ceramic capacitor, in the first step, when the main component ceramic of the above-mentioned ceramic powder is 100 mol, the above-mentioned Si may be added in an amount of 0.3 mol or more and 2.1 mol or less in terms of SiO ₂ . raw material.

In the above-mentioned method of manufacturing a multilayer ceramic capacitor, the specific surface area of the above-mentioned Si raw material can be set to 200 m ² /g or more.

In the above-mentioned method of manufacturing a laminated ceramic capacitor, in the above-mentioned second step, the average rate of temperature rise from room temperature to the maximum temperature may be set to be 30° C./min or more and 80° C./min or less.

In the above-mentioned method of manufacturing a laminated ceramic capacitor, in the second step, the above-mentioned ceramic laminate may be fired in such a manner that the cross-section of the above-mentioned internal electrode layer in the lamination direction of the above-mentioned dielectric layer and the above-mentioned internal electrode layer, The area ratio of the above-mentioned particles is 10% or more. [Effect of Invention]

According to the present invention, there can be provided a multilayer ceramic capacitor capable of suppressing a decrease in the relative permittivity of a dielectric layer and a method of manufacturing the same.

Hereinafter, an embodiment will be described with reference to the drawings.

(Embodiment) FIG. 1 is a partially cutaway perspective view of a multilayer ceramic capacitor 100 according to an embodiment. As shown in FIG. 1 , a multilayer ceramic capacitor 100 includes a multilayer chip 10 having a rectangular parallelepiped shape, and external electrodes 20 a and 20 b provided on two opposing end surfaces of any one of the multilayer chip 10 . In addition, among the four surfaces of the laminated wafer 10 other than the two end surfaces, two surfaces other than the upper surface and the lower surface in the lamination direction are referred to as side surfaces. The external electrodes 20a, 20b extend on the upper surface, the lower surface, and two side surfaces of the laminated wafer 10 in the lamination direction. However, the external electrodes 20a, 20b are separated from each other.

The laminated wafer 10 has a structure in which a dielectric layer 11 mainly composed of a ceramic material functioning as a dielectric and an internal electrode layer 12 made of a base metal material are alternately laminated. A metal material is set as the main component. The edge of each internal electrode layer 12 is alternately exposed on the end surface on which the external electrode 20a is provided and the end surface on which the external electrode 20b is provided on the laminated wafer 10 . Thereby, each internal electrode layer 12 is alternately conducted to the external electrode 20 a and the external electrode 20 b. As a result, the laminated ceramic capacitor 100 has a configuration in which a plurality of dielectric layers 11 are laminated with internal electrode layers 12 interposed therebetween. In addition, in the laminated body of the dielectric layer 11 and the internal electrode layer 12 , the internal electrode layer 12 is arranged on the outermost layer in the lamination direction, and the upper surface and the lower surface of the laminated body are covered with the cover layer 13 . The cover layer 13 has a ceramic material as a main component. For example, the material of the cover layer 13 is the same as the main component of the ceramic material of the dielectric layer 11 .

The dimensions of the multilayer ceramic capacitor 100 are, for example, length 0.2 mm, width 0.125 mm, height 0.125 mm, or length 0.4 mm, width 0.2 mm, height 0.2 mm, or length 0.6 mm, width 0.3 mm, height 0.3 mm, or length 1.0 mm , width 0.5 mm, height 0.5 mm, or length 3.2 mm, width 1.6 mm, height 1.6 mm, or length 4.5 mm, width 3.2 mm, height 2.5 mm, but not limited to these dimensions.

The internal electrode layer 12 mainly contains base metals such as Ni (nickel), Cu (copper), and Sn (tin). As the internal electrode layer 12, noble metals such as Pt (platinum), Pd (palladium), Ag (silver), and Au (gold), or alloys containing these can be used as main components. The thickness of the internal electrode layer 12 is, for example, 0.5 μm or less, preferably 0.3 μm or less. The dielectric layer 11 has, for example, a ceramic material having a perovskite structure represented by the general formula ABO ₃ as a main component. Furthermore, the perovskite structure contains ABO _{3 - α} deviated from the stoichiometric composition. For example, as the ceramic material, BaTiO ₃ (barium titanate), CaZrO ₃ (calcium zirconate), CaTiO ₃ (calcium titanate), SrTiO ₃ (strontium titanate), Ba _{1- x - y} Ca _x Sr _y Ti _{1 - z} Zr _z O ₃ (0≦x≦1, 0≦y≦1, 0≦z≦1), etc.

In order to reduce the size and increase the capacitance of the multilayer ceramic capacitor 100 , it is required to reduce the thickness of the dielectric layer 11 and the internal electrode layer 12 . However, it is difficult to maintain a high continuity rate if the internal electrode layer 12 is to be thinned. The reason for this is as follows. When the internal electrode layer 12 is obtained by firing the metal powder, if the sintering progresses, the surface energy is minimized and the surface energy is spheroidized. Since the sintering of the metal component of the internal electrode layer 12 is easier to advance than the main component ceramic of the dielectric layer 11, if the temperature is increased before the sintering of the main component ceramic of the dielectric layer 11, the metal component of the internal electrode layer 12 is excessively sintered and the Spheroidization. In this case, if there is a crack start (defect), the internal electrode layer 12 breaks based on the defect, and the continuity ratio decreases. If the thinning of the dielectric layer 11 and the internal electrode layer 12 advances, the continuity rate may further decrease.

Fig. 2 is a graph showing the continuity rate. As shown in Figure 2, in the observation area of length L0 in a certain internal electrode layer 12, the lengths L1, L2, ..., Ln of its metal parts can be measured and summed, and the ratio of the metal parts is ΣLn /L0 is defined as the continuity rate of the layer.

Therefore, it is considered that the shrinkage of the internal electrode layer 12 is delayed by adding a common material mainly composed of ceramics to the internal electrode layer 12 . From the viewpoint of thinning the internal electrode layer 12 , it is conceivable to fire a highly dispersed metal conductive paste containing a small-diameter material with a steep particle size distribution as the main component metal and common materials constituting the internal electrode layer 12 . However, since the relative permittivity of the fine common material is low, there is a concern that if the fine common material diffuses into the dielectric layer 11, the capacitance of the multilayer ceramic capacitor 100 will decrease. Therefore, it is desired not to diffuse the fine common material with a low relative permittivity from the internal electrode layer 12 to the dielectric layer 11 .

In this embodiment, as shown in FIG. 3 , at least one of the generated secondary phases is arranged at the interface between the dielectric layer 11 and the internal electrode layer 12 . The so-called secondary phase refers to a phase having a composition different from the crystals of the main component ceramics of the dielectric layer 11 and also different from the crystals of the main component metal of the internal electrode layer 12 . For example, the secondary phase is a phase containing an oxide of Si (silicon). Hereinafter, the secondary phase disposed at the interface between the dielectric layer 11 and the internal electrode layer 12 is referred to as the secondary phase 14 .

Since the secondary phase 14 is located at the interface between the dielectric layer 11 and the internal electrode layer 12 , the diffusion of the common material into the dielectric layer 11 is suppressed. If the diameter of the secondary phase 14 is small, the secondary phase 14 can be dispersedly arranged at the interface between the dielectric layer 11 and the internal electrode layer 12, further suppressing the diffusion of the common material. Therefore, in this embodiment, the average particle size of the secondary phase 14 is set to be 150 nm or less. Thereby, the diffusion of the dielectric with a low relative permittivity used as a common material to the dielectric layer 11 is suppressed and remains in the internal electrode layer 12, so continuous The internal electrode layer 12 with a higher rate can obtain good bias voltage characteristics. Even with thinner layers and multi-layered layers, cracks after firing are less likely to occur, which contributes to improved reliability.

Furthermore, if there are few secondary phases 14 at the interface between the dielectric layer 11 and the internal electrode layer 12, the diffusion of the common material may not be sufficiently suppressed. Therefore, it is preferable to set the total area of secondary phases 14 to 0.7% or more of the total area of dielectric layer 11 in a cross section in the lamination direction of dielectric layer 11 and internal electrode layer 12 . Thereby, the diffusion of the common material can be sufficiently suppressed. Furthermore, the total area of the secondary phases 14 is more preferably 0.8% or more, and still more preferably 0.9% or more, with respect to the total area of the dielectric layer 11 .

On the other hand, if there are too many secondary phases 14 on the interface between the dielectric layer 11 and the internal electrode layer 12, the relative permittivity of the dielectric layer 11 may be reduced due to the high ratio of the secondary phase with a low dielectric constant. risk of reduction. Therefore, it is preferable to set the total area of secondary phases 14 to 5.4% or less of the total area of dielectric layer 11 in a cross section in the lamination direction of dielectric layer 11 and internal electrode layer 12 . Thereby, the relative permittivity of the dielectric layer 11 can be suppressed from being lowered due to an excessively high ratio of the secondary phase with a low dielectric constant. Furthermore, the total area of the secondary phases 14 is preferably 5.1% or less, more preferably 5.0% or less, of the total area of the dielectric layer 11 .

Also, if the diameter of the secondary phase 14 is large due to the relationship with the grain size of the main component ceramics of the dielectric layer 11, there is a concern that the secondary phase may be disposed at the interface between the dielectric layer 11 and the internal electrode layer 12. The amount of phase 14 decreases, so cracking occurs. Therefore, the average diameter of the secondary phase 14 is preferably less than 35% of the average particle diameter of the main component ceramics of the dielectric layer 11 . Accordingly, the number of secondary phases 14 that can be disposed at the interface between the dielectric layer 11 and the internal electrode layer 12 increases, and the occurrence of cracks is suppressed. Furthermore, the average diameter of the secondary phase 14 is preferably not more than 32%, more preferably not more than 30%, of the average particle diameter of the main component ceramics of the dielectric layer 11 .

Also, it is preferable that the crystal grain size of the internal electrode layer 12 is small. FIG. 4( a ) is a diagram illustrating an example of the internal electrode layer 12 when the crystal grain size is large. FIG. 4( b ) is a diagram illustrating an example of the internal electrode layer 12 when the crystal grain size is small. As shown in FIG. 4( a ) and FIG. 4( b ), when the crystal grains 15 become smaller, the common material is likely to remain in the internal electrode layer 12 . For example, it is considered that the number of crystal grain boundaries 17 increases as the crystal grains 15 become smaller, and the common material tends to remain on the crystal grain boundaries 17 , so that a large number of particles 16 mainly composed of ceramics exist in the entire internal electrode layer 12 . Particles 16 are in the form of fired common materials. Specifically, it is preferable that the particles 16 exist in the cross section of the internal electrode layer 12 in the lamination direction of the dielectric layer 11 and the internal electrode layer 12 by making the crystal grain size of the internal electrode layer 12 small. The area ratio is set to be 10% or more. For example, this cross section is a cross section on a plane formed by the stacking direction of the dielectric layer 11 and the internal electrode layer 12 and the opposing direction of the external electrode 20a and the external electrode 20b. In this configuration, the residual amount of common materials increases. Thereby, the diffusion of the common material toward the dielectric layer 11 is suppressed, and the reduction of the relative permittivity of the dielectric layer 11 is suppressed. In addition, excessive sintering of the metal component of the internal electrode layer 12 during sintering is suppressed, and cracking of the internal electrode layer 12 is suppressed. As a result, reduction in the continuity rate of the internal electrode layer 12 can be suppressed. In addition, it is preferable to set the said area ratio to 15% or more. In addition, the said area ratio can be calculated|required from the area of the whole internal electrode layer 12 and the area of the particle|grains 16 mainly composed of ceramics using the SEM image of the cross-section of the internal electrode layer 12, etc. FIG.

Furthermore, when the common material does not diffuse to the dielectric layer 11 but remains sufficiently in the internal electrode layer 12 , the common material gathers in the internal electrode layer 12 . More specifically, it is considered that the common material in the vicinity of the central portion of the internal electrode layer 12 gathers the surrounding common material to perform grain growth. As a result, it remains in the central portion of the internal electrode layer 12 in the thickness direction. In this case, the particles 16 do not exist in the upper and lower 5% regions in the thickness direction of the internal electrode layer 12 . Therefore, it is preferable that the particles 16 do not exist in the upper and lower 5% regions in the thickness direction of the internal electrode layer 12 .

Next, a method of manufacturing multilayer ceramic capacitor 100 will be described. FIG. 5 is a diagram illustrating a flow of a manufacturing method of the multilayer ceramic capacitor 100 .

(Raw material powder production step) First, as shown in FIG. 5 , a dielectric material for forming the dielectric layer 11 is prepared. The A-site element and the B-site element contained in the dielectric layer 11 are generally contained in the dielectric layer 11 in the form of a sintered body of ABO ₃ particles. For example, BaTiO ₃ is a tetragonal compound with a perovskite structure and exhibits a relatively high dielectric constant. This BaTiO ₃ can generally be obtained by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate to synthesize barium titanate. As a method for synthesizing the ceramics constituting the dielectric layer 11, various methods have been previously known, for example, known solid-phase method, sol-gel method, hydrothermal method and the like. In this embodiment, any of these methods can be adopted.

Specific additive compounds are added to the obtained ceramic powder according to the purpose. Examples of additive compounds include: Mn (manganese), V (vanadium), Cr (chromium), rare earth elements (Y (yttrium), Sm (samarium), Eu (europium), Gd (釓), Tb (鋱), Dy (dysprosium), Ho (â), Er (erbium), Tm (銩) and Yb (ytterbium)) oxides, and Co (cobalt), Ni, Zn (zinc), Li (lithium), B (boron ), Na (sodium), K (potassium) and Si (silicon) oxide or glass. Among these additive compounds, Si, Mn, V, Ni, Zn, Li, B, Y, Dy, Ho, and Yb, and a part of Ba contained in the ceramic powder become the secondary phase components for forming the secondary phase. , forming a secondary phase 14 after firing.

In this embodiment, it is preferable to firstly mix a compound including an additive compound with the ceramic particles constituting the dielectric layer 11, and then calcine it at 820-1150°C. Then, the obtained ceramic particles are wet-mixed together with the additive compound, dried and pulverized to prepare a ceramic powder. For example, from the viewpoint of thinning the dielectric layer 11, the average particle diameter of the ceramic powder is preferably 50-300 nm. For example, regarding the ceramic powder obtained in the above manner, the particle size may be adjusted by pulverization treatment as necessary, or may be adjusted by combining with classification treatment.

(Lamination step) Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as methanol and toluene, and a plasticizer such as dioctyl phthalate (DOP) are added to the obtained dielectric material. agent and perform wet mixing. Using the obtained slurry, for example, a strip-shaped dielectric green sheet having a thickness of 0.8 μm or less is coated on a substrate by, for example, a die coating method or a doctor blade method, and dried.

Next, a metal conductive paste for forming internal electrodes containing an organic binder is printed on the surface of the dielectric green sheet by screen printing, gravure printing, etc., thereby disposing internal electrodes that are alternately drawn to a pair of external electrodes with different polarities layer pattern. The metal material of the metal conductive paste is used, for example, with an average particle diameter of 100 nm or less. In addition, the standard deviation of the particle diameter was set to 15 or less. Thereby, a steep particle size distribution is obtained. The average particle diameter is preferably at most 100 nm, more preferably at most 70 nm. The standard deviation of the particle size is preferably 15 or less, more preferably 12 or less. Also, the slope of the cumulative particle size distribution is preferably 8 or more. Furthermore, regarding the slope of the cumulative particle size distribution, a logarithmic graph can be drawn on the cumulative particle size distribution and defined as the slope between D20 and D80 (=1/(logD80−logD20).

Also, ceramic particles are added to the metal conductive paste as a common material. The main component ceramics of the ceramic particles is not particularly limited, and is preferably the same as the main component ceramics of the dielectric layer 11 . For example, barium titanate can be uniformly dispersed. Common materials used are, for example, those with an average particle diameter of 10 nm or less. In addition, the standard deviation of the particle size was set to 5 or less. Thereby, a steep particle size distribution is obtained. The average particle diameter is preferably at most 15 nm, more preferably at most 10 nm. The standard deviation of the particle size is preferably 5 or less, more preferably 3 or less. Also, the slope of the cumulative particle size distribution is preferably 7 or more. Furthermore, regarding the slope of the cumulative particle size distribution, a logarithmic graph can be drawn on the cumulative particle size distribution and defined as the slope between D20 and D80 (=1/(logD80−logD20)).

Thereafter, the dielectric green sheet printed with the internal electrode layer pattern is punched into a specific size, and the punched dielectric green sheet is laminated with a specific number of layers in the following manner with the substrate peeled off (for example 100 to 500 layers), that is, the internal electrode layer 12 and the dielectric layer 11 are interlaced, and the internal electrode layer 12 alternately exposes the edge on both ends of the dielectric layer 11 in the longitudinal direction, and is alternately drawn to a pair of external surfaces with different polarities. The electrodes 20a, 20b are laminated. The cover sheet to be the cover layer 13 is crimped on the top and bottom of the laminated dielectric green sheet and cut into a specific wafer size (for example, 1.0 mm×0.5 mm). After that, the external electrodes 20a, 20b are formed by dipping or the like. The metal conductive paste of the base layer is applied to both ends of the cut laminate and allowed to dry. Thereby, the molded body of the multilayer ceramic capacitor 100 was obtained.

(Sintering step) After the molded body obtained in this way is subjected to binder removal treatment in an N ₂ environment at 250-500°C, it is ^heated at ^1100-1300 in a reducing environment with an oxygen partial pressure ^{of 10-5-10-8} atm. Firing is carried out at °C for 10 minutes to 2 hours, thereby sintering each compound and growing grains. In this way, laminated ceramic capacitor 100 is obtained. Furthermore, by adjusting the Si raw material and firing conditions, the secondary phase 14 can be formed at the interface between the dielectric layer 11 and the internal electrode layer 12 . For example, the secondary phase 14 can be formed in the dielectric layer 11 and the internal electrode layer by using fine particles with a specific surface area of 200 m ² /g or more for SiO ₂ as a raw material of Si and slowing down the temperature rise rate from 1000°C to the maximum temperature. 12 interface. Also, by adjusting the firing conditions, the average diameter of the secondary phase 14 formed at the interface between the dielectric layer 11 and the internal electrode layer 12 can be adjusted to be 150 nm or less. For example, by lowering the maximum temperature, the average diameter of the secondary phase 14 can be set to a small value of 150 nm or less.

Also, by adjusting the firing conditions, the remaining amount of the common material remaining in the internal electrode layer 12 can be adjusted. Specifically, by increasing the heating rate in the firing step, the main component metal is sintered before the common material is discharged from the metal conductive paste, so the common material is likely to remain in the internal electrode layer 12 . For example, from the viewpoint of increasing the residual amount of the common material in the internal electrode layer 12, the average temperature rise rate from room temperature to the highest temperature in the firing step is preferably set at 30° C./min or more, more preferably set at 30° C./min. It is above 45°C/min. Furthermore, if the average temperature increase rate is too high, there is a concern that the discharge of the organic components remaining in the molded body is not sufficiently performed, and problems such as cracks may occur during the firing step. Alternatively, there is a concern that densification is not sufficient due to internal and external differences in the sintering of the molded body, resulting in problems such as a decrease in electrostatic capacitance. Therefore, it is preferable to set the average temperature increase rate to be 80° C./min or less, more preferably 65° C./min or less.

(Re-oxidation treatment step) Thereafter, re-oxidation treatment may be performed at 600° C. to 1000° C. in a nitrogen atmosphere.

(Plating Treatment Step) Thereafter, metal coating of Cu, Ni, Sn, or the like is performed on the base layer of the external electrodes 20a, 20b by a plating treatment.

According to the method of manufacturing a multilayer ceramic capacitor of this embodiment, a highly dispersed metal conductive paste is produced by using a small-diameter material with a steep particle size distribution as the main component metal and the common material constituting the internal electrode layer 12 . Also, the incorporation of larger materials can be partially suppressed. By using such a metal conductive paste, the diffusion of the common material to the dielectric layer 11 is suppressed during the sintering process, and the common material remains in the internal electrode layer 12 . Also, according to the method of manufacturing the multilayer ceramic capacitor of this embodiment, the secondary phase 14 having an average diameter of 150 nm or less can be formed at the interface between the dielectric layer 11 and the internal electrode layer 12 . By setting the average diameter of the secondary phase 14 to a small value of 150 nm or less, the secondary phase 14 can be dispersedly formed. Thereby, the diffusion of the common material to the dielectric layer 11 can be suppressed. Thereby, since the dielectric with a low relative permittivity used as a common material remains in the internal electrode layer 12, the internal electrode layer 12 with a high continuous rate can be obtained without lowering the relative permittivity of the dielectric layer 11. , can obtain good bias characteristics. Even with thinner layers and multi-layered layers, cracks after firing are less likely to occur, which contributes to improved reliability.

Furthermore, by reducing the particle diameter of the Si raw material added to the dielectric material, the average diameter of the secondary phase 14 obtained after firing can be reduced. For example, by setting the specific surface area of the Si raw material to 200 m ² /g or more, the average diameter of the secondary phase 14 can be adjusted to 150 nm or less.

If the amount of Si raw material added to the dielectric material is small, there is a concern that the secondary phase 14 at the interface between the dielectric layer 11 and the internal electrode layer 12 will decrease, and the diffusion of the common material will not be sufficiently suppressed. Therefore, it is preferable to set a lower limit on the amount of Si raw material added to the dielectric material. Specifically, when the main component ceramic of the dielectric material is 100 mol, it is preferable to set the addition amount of the Si raw material to 0.3 mol or more in terms of SiO ₂ . In this case, for example, the total area of secondary phases 14 can be set to be 0.9% or more of the total area of dielectric layer 11 in a cross section in the lamination direction of dielectric layer 11 and internal electrode layer 12 . Furthermore, when the main component ceramic of the dielectric material is 100 mol, it is preferable to set the addition amount of the Si raw material to 0.4 mol or more in terms of SiO ₂ .

On the other hand, if the amount of Si raw material added to the dielectric material is large, there is a concern that the secondary phase 14 on the interface between the dielectric layer 11 and the internal electrode layer 12 will increase, and the secondary phase 14 with a low dielectric constant The ratio of the phases increases, whereby the relative permittivity of the dielectric layer 11 decreases. Therefore, it is preferable to set an upper limit on the amount of Si raw material added to the dielectric material. Specifically, when the main component ceramic of the dielectric material is 100 mol, it is preferable to set the addition amount of the Si raw material to be 2.1 mol or less in terms of SiO ₂ . In this case, for example, the total area of secondary phases 14 can be set to be 5.1% or less of the total area of dielectric layer 11 in a cross section in the lamination direction of dielectric layer 11 and internal electrode layer 12 . Furthermore, when the main component ceramic of the dielectric material is 100 mol, it is more preferable to set the addition amount of the Si raw material to 2.0 mol or less in terms of SiO ₂ , and it is more preferable to set it to 1.0 mol or less .

Also, if the diameter of the secondary phase 14 is large due to the relationship with the grain size of the main component ceramics of the dielectric layer 11, there is a possibility that the secondary phase 14 can be arranged at the interface between the internal electrode layer 12 and the dielectric layer 11. There is a risk of a reduction in the number and a risk of cracking. Therefore, the average diameter of the secondary phase 14 is preferably less than 35% of the average particle diameter of the main component ceramics of the dielectric layer 11 . Accordingly, the number of secondary phases 14 that can be disposed at the interface between the internal electrode layer 12 and the dielectric layer 11 increases, and the occurrence of cracks is suppressed. Furthermore, the average diameter of the secondary phase 14 is preferably less than 30% of the average particle diameter of the main component ceramic of the dielectric layer 11 .

In addition, in the cross section of the internal electrode layer 12 in the stacking direction of the dielectric layer 11 and the internal electrode layer 12 after firing, it is preferable to set the area ratio of the particles 16 mainly composed of ceramics to 10% or more. . If the common material remains in the internal electrode layer 12, excessive sintering of the metal component of the internal electrode layer 12 during sintering is suppressed, and cracking of the internal electrode layer 12 is suppressed. As a result, reduction in the continuity rate of the internal electrode layer 12 can be suppressed. In addition, it is more preferable to set the said area ratio to 15 % or more. In addition, in the thickness direction of the internal electrode layer 12, it is preferable that the particles 16 mainly composed of ceramics do not exist in the upper and lower 5% regions. [Example]

Hereinafter, multilayer ceramic capacitors according to the embodiments were produced and their characteristics were examined.

Necessary additives were added to barium titanate powder with an average particle diameter of 100 nm (specific surface area: 10 m ² /g), and the dielectric material was obtained by fully performing wet mixing and pulverization with a ball mill. In Example 1, when the barium titanate was 100 mol, the addition amount of the Si raw material was 0.3 mol in terms of SiO ₂ . In Example 2, when the barium titanate was 100 mol, the addition amount of the Si raw material was 0.4 mol in terms of SiO ₂ . In Example 3, when the barium titanate was 100 mol, the addition amount of the Si raw material was 0.7 mol in terms of SiO ₂ . In Example 4, when the barium titanate was 100 mol, the addition amount of the Si raw material was 2.0 mol in terms of SiO ₂ . In Example 5, when the barium titanate was 100 mol, the addition amount of the Si raw material was 2.1 mol in terms of SiO ₂ . In Example 6, when the barium titanate was 100 mol, the addition amount of the Si raw material was 0.7 mol in terms of SiO ₂ . In Example 7, when the barium titanate was 100 mol, the addition amount of the Si raw material was 0.4 mol in terms of SiO ₂ . Non-porous SiO ₂ having a specific surface area of 200 m ² /g or more is used as the Si raw material.

In Comparative Example 1, when the barium titanate was 100 mol, the addition amount of the Si raw material was 2.5 mol in terms of SiO ₂ . In Comparative Examples 2 and 3, when the barium titanate was 100 mol, the addition amount of the Si raw material was 0.4 mol in terms of SiO ₂ . In Comparative Example 4, when the barium titanate was 100 mol, the addition amount of the Si raw material was 0.2 mol in terms of SiO ₂ . In Comparative Examples 1 and 4, non-porous SiO ₂ having a specific surface area of 200 m ² /g or more was used as the Si raw material. In Comparative Examples 2 and 3, non-porous SiO ₂ having a specific surface area of about 50 m ² /g was used as the Si raw material.

An organic binder and a solvent are added to the dielectric material, and a dielectric green sheet is produced by a doctor blade method. The coating thickness of the dielectric green sheet is set to 0.8 μm, polyvinyl butyral (PVB) or the like is used as an organic binder, and methanol, toluic acid, or the like is added as a solvent. In addition, a plasticizer and the like are added.

Next, use a planetary ball mill to produce powder (50 wt% based on Ni solid content) of the main component metal (Ni) including the internal electrode layer 12, 10 parts of common material (barium titanate), binder (ethyl fiber element) 5 parts, solvent, and other auxiliaries if necessary, the conductive paste for internal electrode formation. As shown in Table 1, in Examples 1 to 6 and Comparative Examples 1 to 4, the powder of the main component metal was used with an average particle diameter of 70 nm (specific surface area 10 m ² /g) and a standard deviation of particle diameter of 12 , The slope of the cumulative particle size distribution is 8. The common material is the average particle size of 8.6 nm (specific surface area 110 m ² /g), the standard deviation of particle size is 2.7, and the slope of cumulative particle size distribution is 7. In Example 7, the powder of the main component metal was used with an average particle size of 120 nm (specific surface area: 6 m ² /g), a standard deviation of particle size of 33, and a slope of cumulative particle size distribution of 6. Common materials used are those with an average particle size of 29 nm (specific surface area of 40 m ² /g), a standard deviation of particle size of 8.7, and a slope of cumulative particle size distribution of 5. [Table 1]

The conductive paste for internal electrode formation was screen-printed on the dielectric green sheet. 250 green sheets on which the conductive paste for internal electrode formation was printed were stacked, and cover sheets were respectively laminated on the upper and lower sides. Thereafter, a ceramic laminate was obtained by thermocompression bonding, and cut into a specific shape.

After removing the binder from the obtained ceramic laminate in an _N2 environment, coat the ceramic laminate with a metal filler containing Ni as the main component, a common material, a binder, a solvent, etc. from both ends of the ceramic laminate toward each side. metal paste and allow to dry. Thereafter, the metal paste is fired simultaneously with the ceramic laminate in a reducing atmosphere at 1100° C. to 1300° C. for 10 minutes to 2 hours to obtain a sintered body. The average temperature rise rate from room temperature to the highest temperature was set at 55°C/min in Examples 1-7 and Comparative Examples 1-3, and was set at 30°C/min in Comparative Example 4. Furthermore, comparing Examples 1 to 5, 7 and Comparative Example 1, in Example 6, firing was carried out at a low temperature with the highest temperature set to about 100°C, and in Comparative Example 2, the highest temperature was set to 100°C. The firing was carried out at a low temperature of about 50°C. In Comparative Example 3 and Comparative Example 4, the firing was carried out at a low temperature of about 100°C at the highest temperature.

The shape and size of the obtained sintered body were 0.6 mm in length, 0.3 mm in width and 0.3 mm in height. The sintered body was subjected to reoxidation treatment at 800° C. under N ₂ atmosphere, and then plating treatment was performed to form a copper plating layer, a nickel plating layer, and a zinc plating layer on the surface of the base layer, thereby obtaining the multilayer ceramic capacitor 100 .

(Analysis) FIG. 6(a) is a graph showing the particle size distribution of the main component metal of the conductive paste for internal electrode formation in Examples 1-7 and Comparative Examples 1-4. In FIG. 6( a ), "Example 1 and the like" correspond to Examples 1-6 and Comparative Examples 1-4. As shown in FIG. 6( a ), it can be seen that in Examples 1-6 and Comparative Examples 1-4, the metal powder with a small average particle diameter and a steep particle size distribution was used. Also, in Example 7, it can be seen that a metal powder having a large average particle size and a wide particle size distribution was used. FIG. 6( b ) is a graph showing the particle size distribution of the common material of the conductive paste for internal electrode formation in Examples 1-7 and Comparative Examples 1-4. In FIG.6(b), "Example 1 etc." correspond to Examples 1-6 and Comparative Examples 1-4. As shown in FIG. 6( b ), it can be seen that in Examples 1-6 and Comparative Examples 1-4, a common material having a small average particle diameter and a steep particle size distribution was used. Moreover, in Example 7, it turns out that the common material with a large average particle diameter and a wide particle size distribution was used.

7 is an SEM (scanning electron microscope) photograph of a cross-section in the lamination direction of the dielectric layer 11 and the internal electrode layer 12 in the central part in the width direction of Example 2. FIG. From the results in FIG. 7 , it can be known that a secondary phase 14 is formed at the interface between the dielectric layer 11 and the internal electrode layer 12 . In addition, when the secondary phase 14 was analyzed by EDS (energy dispersive x-ray analysis), it was confirmed that Si was included. Moreover, the average diameter of the secondary phase 14 was measured based on the result of FIG. 7. Specifically, the value obtained by measuring and averaging 200 major axes randomly selected from the plurality of secondary phases 14 observed by the SEM image was set as the average diameter of the secondary phases 14 . The results are shown in Fig. 8 . In addition, the measurement results other than Example 2 in FIG. 7 were obtained by measuring each sample similarly.

As shown in FIG. 8 , in any one of Examples 1 to 7, the relative permittivity was 2500 or more of the target. The reason for this is considered to be that secondary phase 14 having an average diameter of 150 nm or less is formed at the interface between dielectric layer 11 and internal electrode layer 12 . On the other hand, in Comparative Examples 1 and 3, the relative permittivity was lower than 2500. The reason for this is considered to be that since the average diameter of the secondary phase 14 exceeded 150 nm, the secondary phase 14 was not dispersed, and the diffusion of the common material was not suppressed. In Comparative Examples 2 and 4, cracks occurred due to firing, and the relative permittivity could not be measured. The reason for this is considered to be that the secondary phase 14 was not dispersed because the average diameter of the secondary phase 14 exceeded 150 nm. In addition, it is considered that the reason is that the secondary phase that can be arranged at the interface between the dielectric layer 11 and the internal electrode layer 12 can be disposed because the average diameter of the secondary phase 14 exceeds 35% of the average particle diameter of the main component ceramics of the dielectric layer 11. 14 decreased in number. In addition, the average particle size of the main component ceramics of the dielectric layer 11 is measured and averaged at 200 major axes randomly selected from a plurality of main component ceramic particles observed by the SEM image. value.

Furthermore, compared with Example 1, in Examples 2-4, the relative permittivity was improved. The reason for this is considered to be that the total area of the secondary phase 14 is 0.9% or more of the total area of the dielectric layer 11 in the cross-section in the lamination direction of the dielectric layer 11 and the internal electrode layer 12, and the common material cannot be sufficiently suppressed. The diffusion. Regarding the total area of the secondary phases 14, in a rectangular area of 12.6 μm×8.35 μm by adjusting the magnification of the field of view of the SEM photograph of the above cross-section observed in FIG. The particles are regarded as circles with their respective major axes as diameters, and the area thereof is calculated, and the value obtained by adding them is set as the total area of the secondary phase 14 . In addition, in the rectangular area of the same field of view of the above SEM photograph, a straight line is extrapolated at the boundary between the dielectric layer 11 and the internal electrode layer 12, and the area of the dielectric layer 11 surrounded by the straight line and the outer periphery of the above-mentioned rectangular area is calculated, And the value obtained by adding up the areas of all the dielectric layers 11 in the above-mentioned rectangular area is set as the total area of the dielectric layers 11 . From the total area of the secondary phase 14 and the total area of the dielectric layer 11 thus obtained, the ratio of the two can be calculated. The ratio can be set as the average of 3 ratios obtained from 3 different rectangular areas of each article. Furthermore, the above-mentioned rectangular area is selected from the central area when the cross-sectional area where the internal electrode layers 12 intersect to generate capacitance values is divided into three parts in the stacking direction and the stretching direction of the internal electrode layer 12.

Also, in Examples 2 and 7, the area ratio of the particles 16 mainly composed of ceramics in the cross section of the internal electrode layer 12 in the lamination direction of the dielectric layer 11 and the internal electrode layer 12 was measured. Specifically, the field of view of the SEM photograph obtained from the SEM image is defined as a rectangular area of 12.6 μm×8.35 μm, the major axes of the particles 16 are measured, and the particle 16 is regarded as a circle whose major axis is the diameter. The area of the particle 16 is calculated by summing up the areas of all the particles 16 in the above-mentioned rectangular area. In addition, a straight line is extrapolated at the boundary between the dielectric layer 11 and the internal electrode layer 12, and the area of the internal electrode layer 12 surrounded by the straight line and the outer periphery of the above-mentioned rectangular area is calculated, and all the internal electrode layers in the above-mentioned rectangular area are The value obtained by adding the areas of 12 is set as the total area of the internal electrode layer 12 . The area ratio was calculated by calculating the total area of the particles 16 with respect to the total area of the internal electrode layer 12 (including the particles 16 ). The area ratio may also be the average of 3 ratios obtained from 3 different rectangular areas of each product. Furthermore, the above-mentioned rectangular area is selected from the central area when the cross-sectional area where the internal electrode layers 12 intersect to generate capacitance values is divided into three parts in the stacking direction and the stretching direction of the internal electrode layer 12. As shown in FIG. 8 , the area ratio was 16.2 in Example 2 and 8.7 in Example 7. The reason for this is considered to be that by using a small-diameter material with a steep particle size distribution as the metal material and the common material of the metal conductive paste for internal electrode formation, the common material remains in the internal electrode layer 12 during the sintering process and faces the dielectric layer. The spread of 11 was inhibited. Also, compared with Example 7, the relative permittivity in Example 2 is improved. The reason for this is considered to be that by setting the area ratio of the particles 16 to be 10% or more, the residual amount of the common material in the internal electrode layer 12 increases, the diffusion of the common material to the dielectric layer 11 is suppressed, and the gap between the dielectric layer 11 is reduced. Decrease in relative permittivity is suppressed. In addition, the continuity rate shown in FIG. 2 was measured using the obtained SEM photograph. In Examples 1 to 6, the continuity rate was 100%, and in Example 7, the continuity rate was 96%, and the continuity rate was very high. Regarding the measurement of the continuity rate, specifically, for the 10-layer internal electrode layer 12 observed by the cross-section of the product, a plurality of SEM photographs are taken over the entire area in the extending direction, and these photographs are pasted and connected to grasp the 10-layer The internal electrode layer 12. Next, L0, L1, L2... of the internal electrode layers were measured to calculate the continuity rate for each layer, and the continuity rate of the obtained 10 layers was averaged to obtain the continuity rate. In addition, the magnification of the SEM image described above may be selected within the range of, for example, 5000 times to 50000 times according to the specification of the product or the purpose of measurement.

The embodiments of the present invention have been described in detail above, but the present invention is not limited to the specific embodiments, and various changes and changes can be made within the scope of the gist of the present invention described in the claims.

10‧‧‧layer chip 11‧‧‧dielectric layer 12‧‧‧internal electrode layer 13‧‧‧covering layer 14‧‧‧secondary phase 15‧‧‧crystal grain 16‧‧‧particle 17‧‧‧crystal Boundary 20a, 20b‧‧‧External electrode 100‧‧‧Multilayer ceramic capacitor L0～L4‧‧‧length S1～S5‧‧‧step

Fig. 1 is a partially cutaway perspective view of a multilayer ceramic capacitor. Figure 2 shows the graph of the continuity rate. Figure 3 is a diagram illustrating a secondary phase. 4( a ) is a diagram illustrating an example of an internal electrode layer when the crystal grain size is large, and (b) is a diagram illustrating an example of an internal electrode layer when the crystal grain size is small. FIG. 5 is a diagram illustrating a flow of a method of manufacturing a multilayer ceramic capacitor. 6( a ) is a graph showing the particle size distribution of the main component metal of the conductive paste for internal electrode formation in Examples 1 to 7 and Comparative Examples 1 to 4, and (b) is a graph showing Examples 1 to 7 and Comparative Example 1. The particle size distribution of the common material of the conductive paste for internal electrode formation in ~4. FIG. 7 is a diagram depicting a SEM (scanning electron microscope, scanning electron microscope) photograph of a cross-section in the lamination direction of the dielectric layer and the internal electrode layer. Fig. 8 is a graph showing the results of Examples and Comparative Examples.

11‧‧‧dielectric layer

12‧‧‧internal electrode layer

14‧‧‧Secondary phase

Claims (15)

A multilayer ceramic capacitor characterized in that it has a laminated structure in which dielectric layers mainly composed of ceramics and internal electrode layers mainly composed of metal are alternately laminated, and between the dielectric layer and the internal electrode layer There is a secondary phase with an average diameter of 150 nm or less at the interface, there are particles mainly composed of ceramics in the above-mentioned internal electrode layer, there are at least two metal crystal particles in contact with any adjacent dielectric layer in the above-mentioned internal electrode layer, The above-mentioned two metal crystal particles are arranged in contact with each other in the extending direction of the above-mentioned internal electrode layer, and the above-mentioned two metal crystal particles form a crystal grain boundary that spreads and extends between adjacent dielectric layers, and the above-mentioned ceramic-based The particles are arranged at the above-mentioned crystal grain boundaries. The multilayer ceramic capacitor according to claim 1, wherein the average diameter of the secondary phase is the average value of 200 measurements of the major diameter of the secondary phase. The multilayer ceramic capacitor according to claim 1 or 2, wherein the total area of the secondary phase is 0.8% or more of the total area of the dielectric layer in a cross-section in the lamination direction of the dielectric layer and the internal electrode layer And below 5.1%. The multilayer ceramic capacitor according to claim 1 or 2, wherein the average diameter of the above-mentioned secondary phase is 35% or less of the average particle diameter of the main component ceramic of the above-mentioned dielectric layer. The multilayer ceramic capacitor according to claim 4, wherein the average particle size of the main component ceramics of the dielectric layer is the average value of 200 measurements of the long axis of the main component ceramics of the dielectric layer. A multilayer ceramic capacitor according to claim 1 or 2, wherein said secondary phase contains Si. The multilayer ceramic capacitor according to claim 1 or 2, wherein in a cross section of the internal electrode layer in the lamination direction of the dielectric layer and the internal electrode layer, the area ratio of the particles present is 10% or more. The multilayer ceramic capacitor according to claim 1 or 2, wherein the main component metal of the internal electrode layer is nickel. The multilayer ceramic capacitor according to claim 1 or 2, wherein the main component ceramic of the above-mentioned particles is barium titanate. The multilayer ceramic capacitor according to claim 1 or 2, wherein the main ceramic component of the dielectric layer is barium titanate. A method for manufacturing a laminated ceramic capacitor, characterized by comprising: a first step of disposing a pattern of a metal conductive paste on a green sheet containing ceramic powder and Si raw materials, the metal conductive paste having an average particle diameter of 100 nm or less and a particle diameter of The standard deviation of the distribution is 15 or less and the main component is metal powder, and the average particle size is 10nm or less and the particle size distribution is included. A ceramic powder with a standard deviation of 5 or less is used as a common material; and the second step is to fire a ceramic laminate obtained by laminating a plurality of layers of the laminated unit obtained in the first step above, and the above-mentioned metal powder The internal electrode layer is formed by sintering, and the dielectric layer is formed by sintering the ceramic powder of the above-mentioned green sheet; in the above-mentioned second step, a secondary layer with an average diameter of 150 nm or less is formed at the interface between the above-mentioned dielectric layer and the above-mentioned internal electrode layer. phase, and particles mainly composed of ceramics are formed in the internal electrode layer, there are at least two metal crystal particles in contact with any adjacent dielectric layer in the internal electrode layer, and the two metal crystal particles are in the internal The electrode layers are arranged in contact with each other in the extending direction, and the two metal crystal particles form a crystal grain boundary that spreads and extends between adjacent dielectric layers, and the above-mentioned particles mainly composed of ceramics are arranged at the crystal grain boundary. A method for manufacturing a multilayer ceramic capacitor according to claim 11, wherein in the first step, when the main component ceramic of the ceramic powder is 100 mol, the above-mentioned 0.3 mol to 2.1 mol is added in terms of SiO ₂ . Si raw material. A method of manufacturing a laminated ceramic capacitor according to claim 11 or 12, wherein the specific surface area of the Si material is set to be 200 m ² /g or more. The method of manufacturing a multilayer ceramic capacitor according to claim 11 or 12, wherein in the second step, the average temperature rise rate from room temperature to the maximum temperature is set to 30°C/min or more and 80°C/min or less. The method for manufacturing a laminated ceramic capacitor according to claim 11 or 12, wherein in the second step above, the above-mentioned ceramic laminate is fired in such a manner that the above-mentioned In the cross-section of the internal electrode layer, the area ratio of the particles described above is 10% or more.

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