TWI792939B - Signal conversion circuit - Google Patents

Abstract

The present disclosure provides a signal conversion circuit including a phase interpolator and a bias voltage generating circuit. The phase interpolator is configured to convert input clock signals into an output clock signal according to a digital signal. The bias voltage generating circuit is electrically coupled to the phase interpolator, is configured to generate a bias voltage according to reference information, and is configured to output the bias voltage to the phase interpolator, so that the output clock signal has a predetermined phase corresponding to one of multiple bit configurations of the digital signal, in which the reference information is related to a change of the phase interpolator due to the temperature variation.

Description

signal conversion circuit

The present disclosure relates to a circuit, in particular to a signal conversion circuit.

Affected by process variation, temperature variation or a combination thereof, the prior art phase interpolator has poor linearity, resulting in many limitations in its application. Therefore, it is necessary to improve the prior art phase interpolator to solve the existing problems.

One aspect of the disclosure is a signal conversion circuit. The signal converting circuit includes a phase interpolator circuit and a bias voltage generating circuit. The phase interpolator circuit is used for converting a plurality of input clock signals into an output clock signal according to a digital signal. The bias generating circuit is electrically coupled to the phase interpolator circuit, and is used to generate a bias voltage according to a reference information, and to output the bias voltage to the phase interpolator circuit, so that the output clock The signal has a predetermined phase corresponding to one of the plurality of bit configurations of the digital signal, wherein the reference information is related to the variation of the phase interpolator circuit due to temperature variation.

In summary, the signal conversion of the present disclosure is accomplished by generating appropriate bias voltages to compensate the phase interpolator circuit based on reference information associated with changes in the phase interpolator circuit due to temperature variation (and process variation). The circuit has the advantage of improved linearity.

The following is a detailed description of the embodiments in conjunction with the accompanying drawings, but the described specific embodiments are only used to explain the present case, and are not used to limit the present case, and the description of the structure and operation is not used to limit the order of its execution. The recombined structure and the devices with equivalent functions are all within the scope of this disclosure.

The terms (terms) used throughout the specification and claims, unless otherwise noted, generally have the ordinary meaning of each term used in this field, in the disclosed content and in the special content.

As used herein, "coupling" or "connection" can refer to two or more components that are in direct physical or electrical contact with each other, or indirect physical or electrical contact with each other, and can also refer to two or more elements. Components operate or act on each other.

For the convenience of explanation, the lowercase English indexes 1~n in the component numbers used in the specification and drawings of this case are only for the convenience of referring to individual components, and are not intended to limit the number of the aforementioned components to a specific number. In the description and drawings of this application, if a certain component number is used without specifying the index of the component number, it means that the component number refers to any unspecified component in the component group to which it belongs. For example, the component number TP[1] refers to the transistor pair TP[1], and the component number TP refers to any unspecified transistor pair among the transistor pairs TP[1]~TP[n].

Please refer to FIG. 1 , which is a schematic structural diagram of a signal conversion circuit 100 according to some embodiments of the present disclosure. The signal conversion circuit 100 includes a phase interpolator circuit 10 and a bias voltage generation circuit. In some embodiments, as shown in FIG. 1 , the bias generating circuit includes an impedance element 20 , a temperature sensitive circuit 30 and a voltage regulator 40 . Structurally, the impedance element 20 and the temperature sensitive circuit 30 are coupled to a node N1 , and the voltage regulator 40 is coupled between the node N1 , a system high voltage AVDD and the phase interpolator circuit 10 .

In some embodiments, the impedance element 20 can be realized by a resistor, and has a preset resistance value. The voltage regulator 40 can be realized by a low-dropout regulator (LDO).

In the embodiment shown in FIG. 1, the bias generating circuit can provide a bias voltage Vbias to the phase interpolator circuit 10 through the voltage regulator 40, and the phase interpolator circuit 10 is used to convert The plurality of input clock signals CLK ₀ , CLK ₉₀ , CLK ₁₈₀ , CLK ₂₇₀ are converted into an output clock signal CLKout. The structure and operation of the phase interpolator circuit 10 will be described in detail below with reference to FIG. 2 .

Please refer to FIG. 2 , which is a schematic circuit diagram of a phase interpolator circuit 10 according to some embodiments of the present disclosure. In some embodiments, as shown in FIG. 2 , the phase interpolator circuit 10 includes a plurality of transistor pairs TP[1]˜TP[n] connected in parallel between the bias voltage Vbias and a ground voltage Gnd, Where n is a positive integer greater than 1.

In some embodiments, the plurality of transistor pairs TP[1]˜TP[n] are divided into multiple groups, and each group of transistor pairs is used to receive a plurality of input clock signals CLK ₀ , CLK ₉₀ , CLK ₁₈₀ , CLK A corresponding input clock signal in ₂₇₀ . In detail, the input clock signal CLK ₀ represents a clock signal with a phase of 0 degrees, the input clock signal CLK ₉₀ represents a clock signal with a phase of 90 degrees, and the input clock signal CLK ₁₈₀ represents a clock signal with a phase of 180 degrees. signal, and the input clock signal CLK ₂₇₀ represents a clock signal with a phase of 270 degrees. In other words, the phases of the plurality of input clock signals CLK ₀ , CLK ₉₀ , CLK ₁₈₀ , CLK ₂₇₀ input to the phase interpolator circuit 10 are different from each other.

In some practical applications, the phase interpolator circuit 10 includes 32 transistor pairs TP[ 1 ]˜TP[ 32 ], which are divided into 4 groups. In other words, multiple transistor pairs TP[1]~TP[8] form a group, multiple transistor pairs TP[9]~TP[16] form a group, and multiple transistor pairs TP[17]~TP[ 24] as a group, and multiple transistor pairs TP[25]~TP[32] as a group. Multiple transistor pairs TP[1]~TP[8] receive the input clock signal CLK ₀ , multiple transistor pairs TP[9]~TP[16] receive the input clock signal CLK ₉₀ , multiple transistor pairs TP [17]~TP[24] receive the input clock signal CLK ₁₈₀ , and a plurality of transistor pairs TP[25]~TP[32] receive the input clock signal CLK ₂₇₀ .

In some embodiments, the structures of the plurality of transistor pairs TP[1]˜TP[n] are identical to each other. The following will take the transistor pair TP[1] as an example to illustrate the structure of the transistor pair TP. As shown in FIG. 2, the transistor pair TP[1] includes a first transistor T1, a second transistor T2, a first switch ST1 and a second switch ST2. A first end (for example: source) of the first transistor T1 receives the bias voltage Vbias, a first end (for example: source) of the second transistor T2 receives the ground voltage Gnd, and a first end (for example: source) of the first transistor T1 receives the ground voltage Gnd. The control terminal (for example: gate) and a control terminal (for example: gate) of the second transistor T2 receive the input clock signal CLK ₀ (or, a plurality of input clock signals CLK ₀ , CLK ₉₀ , CLK ₁₈₀ , CLK ₂₇₀ ). The first switch ST1 and the second switch ST2 are connected in series and then coupled between a second end (eg drain) of the first transistor T1 and a second end (eg drain) of the second transistor T2 .

In some embodiments, the digital signal Scode has a plurality of bits, and the number of bits of the digital signal Scode is the same as the number of transistor pairs TP[1]˜TP[n]. The plurality of transistor pairs TP[1]˜TP[n] each receive a bit corresponding to one of the bits of the digital signal Scode. For example, the transistor pair TP[1] receives the first bit of the digital signal Scode, and the transistor pair TP[2] receives the second bit of the digital signal Scode. Furthermore, each bit of the digital signal Scode has a logic value. Accordingly, the first switch ST1 and the second switch ST2 in the transistor pair TP[1] can select according to the logic value of the first bit of the digital signal Scode (that is, logic "0" or logic "1") ground conduction. In the embodiment shown in FIG. 2 , the first switch ST1 and the second switch ST2 in the transistor pair TP[1] are turned on or off at the same time. Operations of the remaining transistors on the switches in TP[2]~TP[n] can be deduced by analogy, so details are not described here.

It should be understood that the digital signal Scode may have multiple bit configurations, and the multiple bit configurations respectively represent different combinations of the multiple bits of the digital signal Scode. In some practical applications, the digital signal Scode is 32 bits and consists of 8 logic "1"s and 24 logic "0". For example, at a point in time, the 1st to 8th bits of the digital signal Scode are logic "1", and the 9th to 32nd bits of the digital signal Scode are logic "0", which is the digital signal Scode One bit configuration. The rest of the bit configurations of the digital signal Scode can be deduced in the same way, so it will not be repeated here.

In some embodiments, the digital signal Scode can have a specific bit configuration (ie, one of the multiple bit configurations of the digital signal Scode) controlled by the operator. The multiple transistor pairs TP[1]~TP[n] in the phase interpolator circuit 10 respond to multiple input clock signals CLK ₀ , CLK ₉₀ , CLK ₁₈₀ , The CLK ₂₇₀ performs an interpolation operation to synthesize an output clock signal CLKout. Theoretically, the output clock signal CLKout generated by the phase interpolator circuit 10 according to the digital signal Scode should have a specific phase corresponding to the specific bit configuration (ie, a phase preset by the operator). In other words, the digital signal Scode with different bit configurations should correspond to the output clock signal CLKout with different phases respectively. However, in practice, the phase interpolator circuit 10 is often affected by temperature variation, resulting in the output clock signal CLKout not having a phase preset by the operator.

It is worth noting that, by using the bias voltage Vbias provided by the bias generating circuit, the error of the phase interpolator circuit 10 due to temperature variation can be corrected, so that the output output by the phase interpolator circuit 10 is The pulse signal CLKout may have a predetermined phase corresponding to one of the multiple bit configurations of the digital signal Scode. It should be understood that the preset phase may be any phase between 0 and 360 degrees. How to generate the bias voltage Vbias will be described in detail below.

In some embodiments, the aforementioned bias voltage generation circuit generates a suitable bias voltage Vbias to the phase interpolator circuit according to a reference information (not shown in the figure) associated with the change of the phase interpolator circuit 10 due to temperature variation 10. In the embodiment of FIG. 1 , the reference information is provided by the temperature sensitive circuit 30 . In detail, as shown in FIG. 1 , the temperature sensitive circuit 30 is used to generate a current I _PTAT proportional to absolute temperature (proportional to absolute temperature, PATA) according to an operating temperature of the signal conversion circuit 100 (ie, temperature dependent current). In other words, current I _PTAT is positively correlated with temperature. For example, the current I _PTAT increases as the temperature increases and decreases as the temperature decreases.

In the embodiment of FIG. 1, the temperature sensitive circuit 30 includes an amplifier Amp, a first reference transistor pair TPs1, a second reference transistor pair TPs2, a resistor Res, and a plurality of bias transistors Mb1-Mb3 . It should be understood that the amplifier Amp has a positive input terminal (indicated by a symbol "+" in FIG. 1 ), a negative input terminal (indicated by a symbol "-" in FIG. 1 ) and an output terminal. The first reference transistor pair TPs1 and the negative input terminal of the amplifier Amp are coupled to a node N2. The second reference transistor pair TPs2 is coupled to a node N3. The resistor Res and the second reference transistor pair TPs2 are coupled to the node N3, and are coupled to the positive input terminal of the amplifier Amp to a node N4. A control terminal of the bias transistor Mb1 , a control terminal of the bias transistor Mb2 and a control terminal of the bias transistor Mb3 are all coupled to the output terminal of the amplifier Amp. A first terminal of the bias transistor Mb1 , a first terminal of the bias transistor Mb2 and a first terminal of the bias transistor Mb3 all receive the system high voltage AVDD. In addition, a second end of the bias transistor Mb1 is coupled to the node N2, a second end of the bias transistor Mb2 is coupled to the node N4, and a second end of the bias transistor Mb3 is coupled to the node N1. .

In some embodiments, the plurality of bias transistors Mb1 - Mb3 can be realized by PMOS field effect transistors. It should be understood that the control terminals of the multiple bias transistors Mb1~Mb3 can be gates, the first terminals of the multiple bias transistors Mb1~Mb3 can be source electrodes, and the first terminals of the multiple bias transistors Mb1~Mb3 can be source electrodes. The two ends can be drain poles.

Also as shown in FIG. 1 , the first reference transistor pair TPs1 includes a transistor Mp1 and a transistor Mn1 . A first terminal of the transistor Mp1 is coupled to the node N2, a first terminal of the transistor Mn1 is coupled to the ground voltage Gnd, and a control terminal and a second terminal of the transistor Mp1 and a control terminal of the transistor Mn1 coupled with a second end. The second reference transistor pair TPs2 includes a transistor Mp2 and a transistor Mn2. A first terminal of the transistor Mp2 is coupled to the node N3, a first terminal of the transistor Mn2 is coupled to the ground voltage Gnd, and a control terminal and a second terminal of the transistor Mp2 and a control terminal of the transistor Mn2 coupled with a second end. In the embodiment of FIG. 1, the size (or called aspect ratio) of the second reference transistor pair TPs2 is N times larger than the size of the first reference transistor pair TPs1, where N is greater than 1 positive integer.

In some embodiments, both the transistor Mp1 and the transistor Mp2 can be implemented by a P-type MOSFET, and both the transistor Mn1 and the transistor Mn2 can be implemented by an N-type MOSFET. Transistors are implemented.

During the operation of the temperature sensitive circuit 30, the first reference transistor pair TPs1 is biased by the bias transistor Mb1 to form a voltage V _N2 at the node N2, and the voltage V _N2 is equivalent to the control terminal and the first terminal of the transistor Mn1 twice the voltage difference between In addition, the second reference transistor pair TPs2 is biased by the bias transistor Mb2 to form a voltage V _N3 at the node N3, and the voltage V _N3 is equivalent to a voltage difference between the control terminal and the first terminal of the transistor Mn2. double.

…(1)， 其中，

為偏壓電晶體Mb1的增益，

為第一參考電晶體對TPs1的等效電阻值，而

為放大器Amp的增益。 In the embodiment of FIG. 1, the amplifier Amp, the bias transistor Mb1 and the first reference transistor pair TPs1 form a positive feedback path, and the gain of the positive feedback path can be roughly expressed by formula (1):

…(1), where,

is the gain of the bias transistor Mb1,

is the equivalent resistance value of the first reference transistor pair TPs1, and

is the gain of the amplifier Amp.

…(2)， 其中，

為偏壓電晶體Mb2的增益，

為電阻器Res的電阻值，而

為第二參考電晶體對TPs2的等效電阻值。 Also, the amplifier Amp, the bias transistor Mb2, the resistor Res and the second reference transistor pair TPs2 form a negative feedback path, and the gain of the negative feedback path can be roughly expressed by formula (2):

…(2), where,

is the gain of the bias transistor Mb2,

is the resistance value of resistor Res, and

is the equivalent resistance value of the second reference transistor pair TPs2.

In the embodiment of FIG. 1, the resistance value of the resistor Res is much larger than the equivalent resistance value of the first reference transistor pair TPs1 or the second reference transistor pair TPs2, and the bias transistor Mb1 and the bias transistor Mb2 have the same gain. It can be seen from the calculation of the aforementioned formulas (1) and (2), that the gain of the negative feedback path will be greater than the gain of the positive feedback path. Therefore, the negative feedback of the amplifier Amp is established, which further causes the node N4 to have the same voltage as the voltage V _N2 of the node N2.

It can be seen from the above description that two different voltages V _N2 and V _N3 are respectively applied to both ends of the resistor Res, so that a cross voltage V _Res is generated. Also, according to Ohm's law, a current I _Res will be generated and pass through the resistor Res. It should be understood that the magnitude of the cross voltage V _Res is the voltage V _N2 minus the voltage V _N3 , and the magnitude of the current I _Res is the cross voltage V _Res divided by the resistance value of the resistor Res. In addition, the current I _Res is replicated through a current mirror circuit composed of the bias transistor Mb2 and the bias transistor Mb3 , so that the second terminal of the bias transistor Mb3 generates the aforementioned current I _PTAT to the impedance element 20 . Since the bias transistor Mb2 and the bias transistor Mb3 are manufactured by the same process and have the same size, the current I _PTAT is substantially the same as the current I _Res . That is, the magnitude of the current I _PTAT is also divided by the voltage V _Res divided by the resistance value of the resistor Res. In some embodiments, the magnitude of the transvoltage V _Res is positively correlated with temperature. For example, the transvoltage V _Res increases with increasing temperature and decreases with decreasing temperature. Accordingly, the magnitude of the current I _PTAT is also positively correlated with the temperature.

As shown in FIG. 1 , the current I _PTAT output by the temperature sensitive circuit 30 flows into the impedance element 20 to generate a node voltage Vnode at the node N1 . In the embodiment of FIG. 1 , the magnitude of the node voltage Vnode is the magnitude of the current I _PTAT multiplied by the preset resistance value of the impedance element 20 . Then, the voltage regulator 40 can receive and stabilize the node voltage Vnode to generate the bias voltage Vbias to the phase interpolator circuit 10 .

It should be noted that since the first reference transistor pair TPs1 and the second reference transistor pair TPs2 in the temperature sensitive circuit 30 have a structure similar to that of the transistor pair TP in the phase interpolator circuit 10, the temperature sensitive circuit 30 generates The current I _PTAT will be related to the variation of the phase interpolator circuit 10 due to temperature variation. Accordingly, the bias voltage Vbias generated by the aforementioned bias voltage generating circuit according to the impedance element 20 and the current I _PTAT will have a voltage magnitude capable of compensating the temperature variation of the phase interpolator circuit 10 .

For example, when the temperature of the phase interpolator circuit 10 is too low and the internal transistor rise time (rise time) or fall time (fall time) is short, the current I _PTAT generated by the temperature sensitive circuit 30 is relatively small . Since the resistance value of the impedance element 20 is fixed, the aforementioned bias generating circuit will generate a smaller bias voltage Vbias to the phase interpolator circuit 10 according to the smaller node voltage Vnode, so as to elongate the internal transistor of the phase interpolator circuit 10 rise or fall time. For another example, when the temperature of the phase interpolator circuit 10 is too high and the rising or falling time of the internal transistor is relatively long, the current I _PTAT generated by the temperature sensitive circuit 30 is relatively large. Since the resistance value of the impedance element 20 is fixed, the aforementioned bias generating circuit will generate a larger bias voltage Vbias to the phase interpolator circuit 10 according to the larger node voltage Vnode, so as to shorten the internal transistor of the phase interpolator circuit 10. rise or fall time.

In the embodiment of FIG. 1 , the bias voltage generation circuit of the present disclosure generates an appropriate bias voltage Vbias according to the reference information associated with the change of the phase interpolator circuit 10 due to temperature variation, so as to compensate for the influence of temperature variation The phase interpolator circuit 10, but in practice, the phase interpolator circuit 10 will also be affected by other variations. Accordingly, the present disclosure is not limited thereto. In other embodiments, the phase interpolator circuit 10 is affected by both temperature variation and process variation, so the bias generating circuit of the present disclosure will generate a suitable bias for the phase interpolator circuit 10 affected by temperature variation and process variation. Voltage Vbias, which will be described in detail in the following paragraphs with FIG. 3 .

Please refer to FIG. 3 . FIG. 3 is a schematic structural diagram of a signal conversion circuit 300 according to some embodiments of the present disclosure. It should be understood that the same symbols in FIG. 3 as those in FIG. 1 denote the same or similar components, and thus will not be repeated here. In the embodiment of FIG. 3 , the bias generating circuit in the signal conversion circuit 300 includes a reference circuit 50 . Structurally, the reference circuit 50 replaces the impedance element 20 in FIG. 1 and is coupled to the temperature sensitive circuit 30 at the node N1 to provide reference information related to the variation of the phase interpolator circuit 10 due to process variation.

In the embodiment of FIG. 3 , the reference circuit 50 is a replica of the phase interpolator circuit 10 , that is, the circuit structure of the reference circuit 50 is substantially the same as that of the phase interpolator circuit 10 . The configuration of the reference circuit 50 will be described in detail below with reference to FIG. 4 .

Please refer to FIG. 4 , which is a schematic circuit diagram of a reference circuit 50 according to some embodiments of the disclosure. The reference circuit 50 includes a plurality of transistor pairs TP′[1]˜TP′[n] connected in parallel. In order to reflect the variation of the phase interpolator circuit 10 due to process variations, the plurality of transistor pairs TP'[1]~TP'[n] of the reference circuit 50 also operate according to the same multiple transistor pairs of the phase interpolator circuit 10 The crystal pairs TP[1]~TP[n] are grouped into complex groups to respectively receive a plurality of input clock signals CLK ₀ , CLK ₉₀ , CLK ₁₈₀ , and CLK ₂₇₀ that are also input to the phase interpolator circuit 10 .

Similar to the plurality of transistor pairs TP[ 1 ]˜TP[n] of the phase interpolator circuit 10 , the structures of the plurality of transistor pairs TP′[ 1 ]˜TP′[n] are identical to each other. The following will take the transistor pair TP'[1] as an example to illustrate the structure of the transistor pair TP'. As shown in FIG. 4 , the transistor pair TP′[1] includes a first transistor T1 ′, a second transistor T2 ′, a first switch ST1 ′, and a second switch ST2 ′. A first end of the first transistor T1' is coupled to the node N1, a first end of the second transistor T2' receives the ground voltage Gnd, a control end of the first transistor T1' is connected to the second transistor T2' A control terminal of a control terminal receives the input clock signal CLK ₀ (or, one of the plurality of input clock signals CLK ₀ , CLK ₉₀ , CLK ₁₈₀ , and CLK ₂₇₀ ). The first switch ST1' and the second switch ST2' are connected in series and coupled between a second terminal of the first transistor T1' and a second terminal of the second transistor T2'.

As shown in FIG. 4 , the reference circuit 50 also receives a reference digital signal Scode_ref similar to the digital signal Scode. In some embodiments, the number of bits of the reference digital signal Scode_ref is the same as the number of bits of the digital signal Scode, but the reference digital signal Scode_ref is configured to have only one fixed bit configuration (ie, the default bit configuration ). The default bit configuration of the reference digital signal Scode_ref can be one of the multiple bit configurations of the aforementioned digital signal Scode. It should be understood that the default bit configuration of the reference digital signal Scode_ref includes a plurality of bits, and the plurality of transistor pairs TP'[1]~TP'[n] of the reference circuit 50 each receive a plurality of bits of the reference digital signal Scode_ref. One of the bits corresponds to a bit.

Also, although receiving a plurality of input clock signals CLK ₀ , CLK ₉₀ , CLK ₁₈₀ , CLK ₂₇₀ and the reference digital signal Scode_ref, the reference circuit 50 may not output a synthesized clock signal, because the reference circuit 50 receives the aforementioned multiple signals only for In order to reflect the variation of the phase interpolator circuit 10 due to process variation. It should be understood that the power consumption of the reference circuit 50 can also be reduced when the reference digital signal Scode_ref is received and the synthesized clock signal is not output.

In some embodiments, the rise time or fall time of the internal transistor may be longer or shorter in the reference circuit 50 due to process variation, which further affects an equivalent resistance value of the reference circuit 50 . In some embodiments, the equivalent resistance value of the reference circuit 50 includes the following components: (1) resistance error caused by process variation; and (2) ideal resistance set by the preset bit configuration of the reference digital signal Scode_ref value (that is, the ideal resistance value is the resistance value caused by the transistor pair TP' turned on by the first switch ST1 ′ and the second switch ST2 ′ in the reference circuit 50 when the process variation is not considered). The aforementioned reference information is the equivalent resistance value of the reference circuit 50 due to process variation. Further, since the reference circuit 50 and the phase interpolator circuit 10 are manufactured in the same process, the reference information provided by the reference circuit 50 is related to the variation of the phase interpolator circuit 10 due to process variation.

As shown in FIG. 3 , the temperature sensitive circuit 30 can generate the current I _PTAT to the reference circuit 50 according to the operating temperature of the signal converting circuit 300 to generate the node voltage Vnode at the node N1 . In the embodiment of FIG. 3 , the node voltage Vnode is the current I _PTAT multiplied by the equivalent resistance value of the reference circuit 50 . Then, the voltage regulator 40 can receive and stabilize the node voltage Vnode to generate the bias voltage Vbias to the phase interpolator circuit 10 .

It is worth noting that since the reference circuit 50 and the phase interpolator circuit 10 are manufactured in the same manufacturing process, the bias voltage Vbias generated by the aforementioned bias voltage generation circuit according to the equivalent resistance value of the reference circuit 50 will have a compensation for phase interpolation. The voltage magnitude of the process variation of the device circuit 10. For example, if the rising or falling time of the internal transistor of the phase interpolator circuit 10 is short due to process variation, the equivalent resistance of the reference circuit 50 is relatively small. Assuming that the temperature is stable and the magnitude of the current I _PTAT is fixed, the aforementioned bias generating circuit will generate a smaller bias voltage Vbias to the phase interpolator circuit 10 according to the smaller node voltage Vnode, so as to lengthen the phase interpolator circuit 10 The rise or fall time of the internal transistor. For another example, if the rising or falling time of the internal transistor of the phase interpolator circuit 10 is relatively long due to process variation, the equivalent resistance of the reference circuit 50 is relatively large. Assuming that the temperature is stable and the magnitude of the current I _PTAT is fixed, the aforementioned bias generating circuit will generate a larger bias voltage Vbias to the phase interpolator circuit 10 according to the larger node voltage Vnode, so as to shorten the internal voltage of the phase interpolator circuit 10. The rise or fall time of a transistor.

It can be known from the description of the embodiment in FIG. 1 that the bias voltage Vbias generated according to the current I _PTAT provided by the temperature sensitive circuit 30 can compensate the temperature variation of the phase interpolator circuit 10 . It can be seen that the signal conversion circuit 300 in FIG. 3 can simultaneously use the current I _PTAT provided by the temperature sensitive circuit 30 and the equivalent resistance value of the reference circuit 50 to generate a signal capable of compensating the temperature variation and manufacturing process of the phase interpolator circuit 10. Vary the bias voltage Vbias. Accordingly, the phase interpolator circuit 10 can generate the output clock signal CLKout having a preset phase corresponding to one of the multiple bit configurations of the digital signal Scode.

In the foregoing embodiments, the bias voltage generation circuit stabilizes the node voltage Vnode through the voltage regulator 40 to generate the bias voltage Vbias, but the present disclosure is not limited thereto. It can be seen from the foregoing that the node voltage Vnode and the bias voltage Vbias are positively correlated, so in some embodiments, the voltage regulator 40 can be omitted and the aforementioned bias voltage generating circuit directly outputs the node voltage Vnode as the bias voltage Vbias to the phase interpolation tor circuit 10.

In the foregoing embodiments, only one output clock signal CLKout is shown in FIG. 1 or FIG. 3 , but the present disclosure is not limited thereto. In other embodiments, the phase interpolator circuit 10 can generate two output clock signals with a specific phase difference (for example: 180 degree phase, 90 degree phase). In other words, the phase interpolator circuit of the present disclosure can generate at least one output clock signal.

Please refer to Figures 5 and 6, Figure 5 shows experimental data for a phase interpolator circuit 10 showing uncompensated temperature variations according to some embodiments of the present disclosure, and Figure 6 shows some embodiments according to the present disclosure. Experimental data of the temperature variation compensated phase interpolator circuit 10 shown in the embodiment. In FIGS. 5 and 6 , multiple scales on the horizontal axis respectively represent multiple bit configurations of the digital signal Scode, and multiple scales on the vertical axis respectively represent the magnitude of differential nonlinearity (DNL). It should be understood that the smaller the differential nonlinearity, the higher the linearity of the conversion circuit. Therefore, in an ideal conversion circuit, its differential nonlinearity is close to zero.

As shown in Figure 5, the three curves FF (fast-fast), TT (typical-typical) and SS (slow-slow) respectively represent the experimental data under three different process parameters, and the vertical axis range D represents the temperature variation. The magnitude distribution of the differential nonlinearity of the compensated phase interpolator circuit 10 . As shown in FIG. 6, the three curves FF', TT' and SS' respectively represent the experimental data under three different process parameters, and the range D' on the vertical axis represents the differential differential of the phase interpolator circuit 10 after the temperature variation is compensated. Size distribution of linearity. It can be seen from FIGS. 5 and 6 that the phase interpolator circuit 10 with temperature variation compensation has better linearity than the phase interpolator circuit 10 without temperature variation compensation. For example, the range D' of the vertical axis in FIG. 6 is reduced by about 22% compared to the range D' of the vertical axis in FIG. 5 .

As can be seen from the above embodiments of the present disclosure, the phase interpolator circuit is compensated by generating an appropriate bias voltage based on reference information associated with changes in the phase interpolator circuit due to temperature variation (and process variation) , the signal conversion circuit of the present disclosure has the advantage of improving linearity.

Although the present disclosure has been disclosed above in terms of implementation, it is not intended to limit the present disclosure. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, this disclosure The scope of protection of the disclosed content shall be subject to the definition of the appended patent application scope.

10: Phase interpolator circuit 20: Impedance element 30: Temperature sensitive circuit 40: Regulator 50: Reference circuit 100,300: Signal conversion circuit Amp: Amplifier AVDD: System high voltage CLK ₀ , CLK ₉₀ , CLK ₁₈₀ , CLK ₂₇₀ : Input clock signal CLKout: Output clock signal Gnd: Ground voltage I _PTAT : Current I _Res : Current Mb1, Mb2.Mb3: Bias transistors Mp1, Mp2, Mn1, Mn2: Transistors N1, N2, N3, N4: Node Res: resistor Scode: digital signal Scode_ref: reference digital signal ST1, ST1': first switch ST2, ST2': second switch T1, T1': first transistor T2, T2': second transistor TP[ 1]~TP[n],TP'[1]~TP'[n]: transistor pair TPs1: first reference transistor pair TPs2: second reference transistor pair Vbias: bias voltage Vnode: node voltage V _N2 , V _N3 : voltage V _Res : voltage across FF, FF', SS, SS', TT, TT': curve D, D': vertical axis range

FIG. 1 is a schematic structural diagram of a signal conversion circuit according to some embodiments of the present disclosure. FIG. 2 is a schematic circuit diagram of a phase interpolator circuit according to some embodiments of the present disclosure. FIG. 3 is a schematic structural diagram of a signal conversion circuit according to some embodiments of the present disclosure. FIG. 4 is a schematic circuit diagram of a reference circuit according to some embodiments of the disclosure. FIG. 5 is a schematic diagram illustrating experimental data of a phase interpolator circuit affected by temperature variation according to some embodiments of the present disclosure. FIG. 6 is a schematic diagram of experimental data illustrating a temperature variation compensated phase interpolator circuit according to some embodiments of the present disclosure.

Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

10: Phase interpolator circuit

20: Impedance element

30: Temperature Sensitive Circuit

40: Regulator

100: Signal conversion circuit

Amp: Amplifier

AVDD: system high voltage

CLK ₀ , CLK ₉₀ , CLK ₁₈₀ , CLK ₂₇₀ : input clock signal

CLKout: output clock signal

Gnd: ground voltage

I _PTAT : Current

I _Res : current

Mb1,Mb2.Mb3: bias transistor

Mp1, Mp2, Mn1, Mn2: Transistor

N1, N2, N3, N4: nodes

Res: Resistor

Scode: digital signal

TPs1: the first reference transistor pair

TPs2: The second reference transistor pair

Vbias: bias voltage

Vnode: node voltage

V _N2 , V _N3 : Voltage

V _Res : across voltage

Claims (10)

A signal conversion circuit, comprising: a phase interpolator circuit for converting a plurality of input clock signals into an output clock signal according to a digital signal; and a bias generating circuit electrically coupled in the phase The interpolator circuit is used to generate a bias voltage according to a reference information, and to output the bias voltage to the phase interpolator circuit, so that the output clock signal has a plurality of bit configurations corresponding to the digital signal One of them corresponds to a preset phase, wherein the bias voltage generating circuit includes a temperature sensitive circuit, the temperature sensitive circuit is used to detect an operating temperature of the signal conversion circuit to generate a temperature-dependent current, and the bias voltage generates The circuit is used to generate the bias voltage according to the temperature-dependent current; wherein the reference information is related to the change of the phase interpolator circuit due to temperature variation. The signal conversion circuit as described in Claim 1, wherein the phase interpolator circuit includes a plurality of transistor pairs connected in parallel, and each of the transistor pairs receives one corresponding bit of the plurality of bits of the digital signal , wherein the transistor pairs are divided into plural groups, and each transistor pair is used to receive a corresponding input clock signal among the input clock signals, and the phases of the input clock signals are different from each other. The signal conversion circuit as described in claim 1, wherein the bias The voltage generation circuit includes an impedance element with a preset resistance value, and the bias voltage generation circuit generates the bias voltage according to the preset resistance value and the temperature-dependent current input to the impedance element. The signal conversion circuit as claimed in item 3, wherein the temperature sensitive circuit and the impedance element are coupled to a first node, and used to generate the temperature-dependent current to the impedance element to generate a node voltage at the first node . The signal conversion circuit as described in claim 4, wherein the temperature sensitive circuit comprises: an amplifier having a positive input terminal, a negative input terminal and an output terminal; a first reference transistor pair, connected to the negative input terminal of the amplifier The input terminal is coupled to a second node; a second reference transistor pair is coupled to a third node; a resistor is coupled to the second reference transistor pair to the third node and is connected to the amplifier The positive input end is coupled to a fourth node; and a first bias transistor, a second bias transistor and a third bias transistor, wherein a control terminal of the first bias transistor , a control terminal of the second bias transistor and a control terminal of the third bias transistor are both coupled to the output terminal of the amplifier, and a first terminal of the first bias transistor, the A first end of the second bias transistor and a first end of the third bias transistor are both coupled to a system high voltage, wherein a second end of the first bias transistor is coupled to the second node, A second terminal of the second bias transistor is coupled to the fourth node, and a second terminal of the third bias transistor is coupled to the first node. The signal conversion circuit as described in Claim 5, wherein the amplifier, the first bias transistor and the first reference transistor pair form a positive feedback path, the amplifier, the second bias transistor, the resistor The device and the second reference transistor pair form a negative feedback path, and the gain of the negative feedback path is greater than the gain of the positive feedback path. The signal conversion circuit as claimed in claim 5, wherein the temperature-dependent current is a voltage across the fourth node and the third node divided by a resistance value of the resistor, and is positively correlated with temperature. The signal conversion circuit as described in claim 4, wherein the bias voltage generating circuit further includes a voltage regulator, and the voltage regulator is coupled between the first node and the phase interpolator circuit, and is used to receive and The node voltage is stabilized to generate the bias voltage to the phase interpolator circuit. The signal conversion circuit as claimed in claim 1, wherein the reference information is also related to the variation of the phase interpolator circuit due to process variation. The signal conversion circuit as described in Claim 9, wherein the bias voltage generation circuit includes: A reference circuit is a copy circuit of the phase interpolator circuit, and is used to reflect the change of the phase interpolator circuit due to process variation, wherein the reference circuit has an equivalent resistance value due to process variation, so that the The bias voltage generation circuit generates the bias voltage according to the equivalent resistance value and the temperature-dependent current input to the reference circuit.

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