TWI792469B - Motor controller - Google Patents

Abstract

A motor controller comprises a switch circuit, a control unit, and a duty cycle processing unit. The switch circuit is coupled to a motor for driving the motor. The control unit is configured to generate a plurality of control signals to control the switch circuit. The duty cycle processing unit receives a first pulse width modulation signal, where the first pulse width modulation signal has a first duty cycle. The duty cycle processing unit is configured to judge if the first duty cycle is equal to 0% or 100%. The duty cycle processing unit comprises a duty cycle computing unit, where the duty cycle computing unit is configured to capture the first duty cycle.

Description

motor controller

The present invention relates to a motor controller, in particular to a motor controller applicable to a fan motor system.

Traditionally, a motor controller uses a duty cycle of an input pulse width modulation signal to control the motor speed. Early practice was to use this input PWM signal directly to drive the motor. That is, the output duty cycle of the driving motor is equal to the duty cycle of the input PWM signal. However, when the motor controller directly utilizes the input PWM signal to enter a soft switching driving mode, the frequency of the output PWM signal may fall into the audio frequency range after being modulated and generate noise. In addition, when the motor controller adopts this early practice to perform a speed open loop operation, if the power supply voltage or temperature changes, the speed of the motor will also change. Therefore, a new technology is needed to solve the above-mentioned problems.

In view of the aforementioned problems, the object of the present invention is to provide a motor controller applicable to a fan motor system. The motor controller has a switch circuit, a control unit, a pulse width modulation processing unit, a duty cycle processing unit, and a soft switching processing unit. The switching circuit is coupled to a motor to drive the motor. The control unit is used for generating a plurality of control signals to control the switch circuit. The duty cycle processing unit receives a first PWM signal for generating a first signal to the PWM processing unit. The soft switching processing unit generates a second signal to the pulse width modulation processing unit, so that the motor controller is in a soft switching driving mode. The PWM processing unit is used to generate a second PWM signal to the control unit according to the first signal and the second signal.

The first PWM signal has a conduction time, a non-conduction time, a period, and a first duty cycle, wherein the first duty cycle is equal to (conduction time/period)×100%. The duty cycle processing unit has a duty cycle calculation unit, wherein the duty cycle calculation unit has a conduction time calculation unit, a non-conduction time calculation unit, a period calculation unit, a charging unit, a discharge unit, and a memory unit. The duty cycle calculating unit is used for retrieving the first duty cycle. According to an embodiment of the present invention, the duty cycle processing unit is configured to determine whether the first duty cycle is equal to 0% or 100%. For example, when the first PWM signal maintains a low level for longer than a first predetermined time, the duty cycle calculation unit may determine that the first duty cycle is equal to 0%. When the first pulse width modulation signal maintains a high level for longer than a second predetermined time, the duty cycle calculation unit can determine that the first duty cycle is equal to 100%. When the first pulse width modulation signal maintains a level for longer than a third predetermined time, the duty cycle calculating unit can determine that the first duty cycle is equal to 0% or 100%. If the level is the low level, the first duty cycle is equal to 0%. If the level is the high level, the first duty cycle is equal to 100%. The duty cycle calculation unit may further have an application-specific calculation unit to determine whether the first duty cycle is equal to 0% or 100%. In addition, the charging unit or the discharging unit can also be used to determine whether the first duty cycle is equal to 0% or 100%.

The pulse width modulation processing unit has a multiplication unit, a comparison unit, and a triangular wave generation unit. In order to avoid noise when switching phases, the soft switching processing unit generates a second duty cycle. Then the pulse width modulation processing unit performs a multiplication operation on the first duty cycle and the second duty cycle to generate a modulation duty cycle. Finally, the pulse width modulation processing unit by The modulation duty cycle is compared with a comparison value to generate the second PWM signal to the control unit. That is to say, the multiplication unit can generate a third signal to the comparison unit according to the first signal and the second signal, wherein the first signal has the first duty cycle, the second signal has the The second duty cycle, and the third signal has the modulation duty cycle. The multiplication operation unit can utilize a multiplier or a plurality of adders to realize the multiplication operation. The triangular wave generation unit is used to generate a fourth signal to the comparison unit, wherein the fourth signal has the comparison value. The comparing unit can be a digital comparator. The comparison unit receives the third signal and the fourth signal, and compares the third signal with the fourth signal to generate the second PWM signal to the control unit. The fourth signal can be a constant frequency signal, so that the second PWM signal is also a constant frequency signal. For example, when the fourth signal is greater than the third signal, the second PWM signal can be the low level. When the fourth signal is less than or equal to the third signal, the second PWM signal can be at the high level. The soft handover processing unit can adjust the second duty cycle so that the second duty cycle gradually decreases or gradually increases with time. That is to say, both the duty cycle of the modulation and the duty cycle of the second PWM signal can change gradually when switching phases, thus causing a phase current to change gradually when switching phases to avoid noise. Therefore, when the motor controller is in the soft switching driving mode, the motor controller can achieve a current wave shaping function and avoid generating an audio signal when switching phases. Furthermore, the motor controller can utilize the first duty cycle to operate in a rotational speed closed-loop mode. The motor controller can make the motor reach a target speed by capturing the first duty cycle. When the power supply voltage or temperature changes, the speed of the motor can remain unchanged. The motor controller can make the motor rotate stably and the rotation speed of the motor will not deviate. Therefore, the motor controller can overcome the problems encountered in earlier approaches.

10: Motor controller

M: motor

100: switch circuit

101: The first transistor

102: second transistor

103: The third transistor

104: The fourth transistor

O1: first endpoint

O2: second endpoint

VCC: endpoint

GND: endpoint

110: Control unit

C1: The first control signal

C2: Second control signal

C3: The third control signal

C4: The fourth control signal

120: Pulse width modulation processing unit

130: work cycle processing unit

140: Soft switching processing unit

Vp1: the first PWM signal

Vp2: the first PWM signal

V1: first signal

V2: second signal

131: Duty cycle calculation unit

132: On-time calculation unit

133: Non-conduction time calculation unit

134: Period calculation unit

135: charging unit

136: discharge unit

137: memory unit

121: Multiplication operation unit

122: Comparison unit

123: Triangular wave generating unit

V3: The third signal

V4: The fourth signal

Fig. 1 is a schematic diagram of a motor controller according to an embodiment of the present invention.

Figure 2 is a timing diagram of an embodiment of the present invention.

Fig. 3 is a schematic diagram of a duty cycle processing unit according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of a pulse width modulation processing unit according to an embodiment of the present invention.

Fig. 5 is a waveform diagram of an embodiment of the present invention.

The following description will make the objects, features and advantages of the present invention more apparent. Preferred embodiments according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a schematic diagram of a motor controller 10 according to an embodiment of the present invention. The motor controller 10 has a switch circuit 100 , a control unit 110 , a pulse width modulation processing unit 120 , a duty cycle processing unit 130 , and a soft switching processing unit 140 . The switch circuit 100 has a first transistor 101 , a second transistor 102 , a third transistor 103 , and a fourth transistor 104 for driving a motor M. The first transistor 101 is coupled to a first terminal O1 and a terminal VCC, and the second transistor 102 is coupled to the first terminal O1 and a terminal GND. The third transistor 103 is coupled to a second terminal O2 and the terminal VCC, and the fourth transistor 104 is coupled to the second terminal O2 and the terminal GND. The first transistor 101 , the second transistor 102 , the third transistor 103 , and the fourth transistor 104 can be a P-type MOS transistor or an N-type MOS transistor. As shown in FIG. 1 , the first transistor 101 and the third transistor 103 are two P-type metal oxide semiconductor transistors as an example. The second transistor 102 and the fourth transistor 104 are two N-type metal oxide semiconductor transistors as an example. The control unit 110 generates a first control signal C1, a second control signal C2, a third control signal C3, and a fourth control signal C4 for respectively controlling the first transistor 101, the second transistor 102, the second transistor The conduction status of the three transistors 103 and the fourth transistor 104 . The duty cycle processing unit 130 receives a first PWM signal Vp1 to generate a first signal V1 to the PWM processing unit 120, wherein the first PWM signal Vp1 is an input PWM signal And the first signal V1 can be an M-shaped wave signal. Soft Handover Processing Unit 140 generates a second signal V2 to the PWM processing unit 120 so that the motor controller 10 is in a soft switching driving mode. The PWM processing unit 120 is used to generate a second PWM signal Vp2 to the control unit 110 according to the first signal V1 and the second signal V2, wherein the second PWM signal Vp2 is an output PWM change signal. The motor controller 10 adjusts the rotation speed of the motor M through the second pulse width modulation signal Vp2. In addition, the motor controller 10 can be applied to a fan motor system.

Figure 2 is a timing diagram of an embodiment of the present invention. The first PWM signal Vp1 has a conduction time, a non-conduction time, a period, and a first duty cycle, wherein the first duty cycle is equal to (conduction time/period)×100%. In order to overcome the problems encountered in earlier methods, the motor controller 10 needs to have the function of capturing the first duty cycle. FIG. 3 is a schematic diagram of a duty cycle processing unit 130 according to an embodiment of the present invention. The duty cycle processing unit 130 has a duty cycle calculation unit 131, wherein the duty cycle calculation unit 131 has a conduction time calculation unit 132, a non-conduction time calculation unit 133, a cycle calculation unit 134, a charging unit 135, a discharge unit 136 , and a memory unit 137 . The duty cycle calculating unit 131 is used for retrieving the first duty cycle. The duty cycle calculation unit 131 can be a part of a microcontroller, wherein the microcontroller is implemented on an integrated circuit chip. The on-time calculation unit 132 receives the first PWM signal Vp1 for calculating the on-time. The on-time calculation unit 132 can calculate the on-time by using a plurality of flip-flops. The memory unit 137 is coupled to the on-time calculation unit 132 to store the on-time. The non-conduction time calculation unit 133 receives the first PWM signal Vp1 to calculate the non-conduction time. The non-conduction time calculation unit 133 can calculate the non-conduction time by using a plurality of flip-flops. The memory unit 137 is coupled to the non-conduction time calculation unit 133 to store the non-conduction time. The period calculating unit 134 receives the first PWM signal Vp1 for calculating the period. The period calculating unit 134 can calculate the period by using a plurality of flip-flops. The memory unit 137 is coupled to the period calculation unit 134 to store the period. Therefore, the duty cycle calculation unit 131 can retrieve the first duty cycle according to the conduction time, the non-conduction time, and the cycle stored in the memory unit 137 . In order to simplify the duty cycle calculation unit 131, the designer can choose to use two of the conduction time calculation unit 132, the non-conduction time calculation unit 133, and the period calculation unit 134 to calculate the second One working cycle. In addition, the first duty cycle can be represented by an N-bit value, where N is a positive integer greater than 1. According to a preferred embodiment of the present invention, N may be equal to 8.

However, the above-mentioned formula for calculating the first duty cycle cannot accurately calculate the two extreme values of 0% and 100%. Therefore, a specific method is required to retrieve 0% and 100%. According to an embodiment of the present invention, the duty cycle processing unit 130 is configured to determine whether the first duty cycle is equal to 0% or 100%. For example, when the first PWM signal Vp1 maintains a low level for longer than a first predetermined time, the duty cycle calculation unit 131 may determine that the first duty cycle is equal to 0%. When the first PWM signal Vp1 maintains a high level for longer than a second predetermined time, the duty cycle calculation unit 131 can determine that the first duty cycle is equal to 100%. When the first PWM signal Vp1 maintains a level for longer than a third predetermined time, the duty cycle calculation unit 131 can determine that the first duty cycle is equal to 0% or 100%. If the level is a low level, the first duty cycle is equal to 0%. If the level is high, the first duty cycle is equal to 100%. Therefore, the non-conduction time calculation unit 133 or the period calculation unit 134 can be used to determine whether the first duty cycle is equal to 0%. The on-time calculation unit 132 or the period calculation unit 134 can be used to determine whether the first duty cycle is equal to 100%. The duty cycle calculation unit 131 may further have an application-specific calculation unit (not shown) to determine whether the first duty cycle is equal to 0% or 100%. The specific application calculation unit is used to determine whether the first duty cycle is equal to 0% or 100%. In addition, the charging unit 135 or the discharging unit 136 can also be used to determine whether the first duty cycle is equal to 0% or 100%. For example, the charging unit 135 can charge an element according to the first PWM signal Vp1, and then the duty cycle calculation unit 131 determines whether the first duty cycle is equal to 0% or 100% according to a parameter value of the element. The discharge unit 136 can discharge a device according to the first PWM signal Vp1, and then the duty cycle calculation unit 131 determines whether the first duty cycle is equal to 0% or 100% according to a parameter value of the device. That is to say, the duty cycle calculation unit 131 can use a charging procedure to determine whether the first duty cycle is equal to 0% or 100%. The duty cycle calculation unit 131 can use a discharge procedure to determine whether the first duty cycle is equal to 0% or 100%.

FIG. 4 is a schematic diagram of a pulse width modulation processing unit 120 according to an embodiment of the present invention. PWM The variable processing unit 120 has a multiplication unit 121 , a comparison unit 122 , and a triangular wave generation unit 123 . Please refer to Figure 1 and Figure 4 at the same time. In order to avoid noise when switching phases, the soft switching processing unit 140 generates a second duty cycle, wherein the second duty cycle can be represented by an N-bit value. Next, the PWM processing unit 120 performs a multiplication operation on the first duty cycle and the second duty cycle to generate a modulation duty cycle, wherein the modulation duty cycle can be represented by an N-bit value. Finally, the PWM processing unit 120 generates the second PWM signal Vp2 to the control unit 110 by comparing the modulation duty cycle with a comparison value, wherein the comparison value can be represented by an N-bit value. According to a preferred embodiment of the present invention, N may be equal to 8. That is to say, the multiplication unit 121 can generate a third signal V3 to the comparison unit 122 according to the first signal V1 and the second signal V2, wherein the first signal V1 has a first duty cycle, and the second signal V2 has a first duty cycle. Two duty cycles, and the third signal V3 has a modulation duty cycle. The multiplication unit 121 can utilize a multiplier or a plurality of adders to implement multiplication. The triangular wave generation unit 123 is used to generate a fourth signal V4 to the comparison unit 122, wherein the fourth signal V4 has a comparison value. The comparison unit 122 can be a digital comparator. The comparison unit 122 receives the third signal V3 and the fourth signal V4 for comparing the third signal V3 and the fourth signal V4 to generate the second PWM signal Vp2 to the control unit 110 . The fourth signal V4 can be a constant frequency signal, so that the second PWM signal Vp2 is also a constant frequency signal. For example, when the fourth signal V4 is greater than the third signal V3, the second PWM signal Vp2 can be at a low level. When the fourth signal V4 is less than or equal to the third signal V3, the second PWM signal Vp2 can be at a high level. Fig. 5 is a waveform diagram of an embodiment of the present invention. The soft handover processing unit 140 can adjust the second duty cycle so that the second duty cycle gradually decreases or gradually increases with time. That is to say, the duty cycle of the modulation and the duty cycle of the second PWM signal Vp2 can be changed gradually when switching phases, thus causing a phase current to change gradually when switching phases to avoid noise. As shown in FIG. 5, the waveform of the first signal V1 is gradually modulated into the waveform of the third signal V3 during a soft switching process. The first signal V1 and the third signal V3 can be M-shaped wave signals respectively. The fourth signal V4 can be a triangular wave signal or a sawtooth wave signal. Therefore, when the motor controller 10 is in the soft switching driving mode, the motor controller 10 can achieve a certain level when switching phases. The function of current wave shaping and avoid generating an audio signal. Furthermore, the motor controller 10 can utilize the first duty cycle to operate in a rotational speed closed-loop mode. The motor controller 10 can make the motor M reach a target speed by capturing the first duty cycle. When the power supply voltage or temperature changes, the rotational speed of the motor M can remain unchanged. The motor controller 10 can make the motor M rotate stably and the rotation speed of the motor M will not deviate.

According to an embodiment of the present invention, the motor controller 10 can be applied to a single-phase motor or a multi-phase motor. The motor controller 10 can operate smoothly and avoid noise when the motor controller 10 enters a soft switching driving mode by capturing the first duty cycle. In addition, the motor controller 10 can operate in a rotational speed closed-loop mode by capturing the first duty cycle. When the power supply voltage or temperature changes, the rotational speed of the motor M can remain unchanged. Thus, the motor controller 10 of the present invention overcomes the problems encountered with earlier approaches.

Although the present invention has been described by way of examples of preferred embodiments, it should be understood that the present invention is not limited to the disclosed embodiments. On the contrary, the invention is intended to cover various modifications and similar arrangements apparent to those skilled in the art. Accordingly, the scope of claims should be construed in the broadest way to encompass all such modifications and similar arrangements.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

10: Motor controller

M: motor

100: switch circuit

101: The first transistor

102: second transistor

103: The third transistor

104: The fourth transistor

O1: first endpoint

O2: second endpoint

VCC: endpoint

GND: endpoint

110: Control unit

C1: The first control signal

C2: Second control signal

C3: The third control signal

C4: The fourth control signal

120: Pulse width modulation processing unit

130: work cycle processing unit

140: Soft switching processing unit

Vp1: the first PWM signal

Vp2: the first PWM signal

V1: first signal

V2: second signal

Claims (48)

A motor controller includes: a switch circuit coupled to a motor for driving the motor; a control unit for generating a plurality of control signals to control the switch circuit; a duty cycle processing unit, wherein the duty cycle processing unit receiving a first pulse width modulation signal, the first pulse width modulation signal has a first duty cycle, and the duty cycle processing unit is used to determine whether the first duty cycle is equal to 0% or 100%; and a pulse width A modulation processing unit, wherein the duty cycle processing unit generates a first signal to the pulse width modulation processing unit, and the pulse width modulation processing unit receives the first signal to generate a second pulse width modulation signal to the control unit. The motor controller as described in item 1 of the scope of the patent application, wherein the duty cycle processing unit includes a duty cycle calculation unit, when the first pulse width modulation signal maintains a low level for a time greater than a first predetermined time , the duty cycle calculation unit determines that the first duty cycle is equal to 0%. The motor controller as described in item 1 of the scope of the patent application, wherein the duty cycle processing unit includes a duty cycle calculation unit, when the first pulse width modulation signal maintains a high level for a time greater than a second predetermined time , the duty cycle calculation unit determines that the first duty cycle is equal to 100%. The motor controller as described in item 1 of the scope of the patent application, wherein the duty cycle processing unit includes a duty cycle calculation unit, when the first pulse width modulation signal maintains a level for a time greater than a third predetermined time , the duty cycle calculation unit determines that the first duty cycle is equal to 0% or 100%. The motor controller as described in item 4 of the scope of the patent application, wherein if the level is a low level standard, the first duty cycle is equal to 0%. The motor controller as described in item 4 of the scope of application, wherein if the level is a high level, the first duty cycle is equal to 100%. The motor controller described in claim 1, wherein the duty cycle processing unit includes a duty cycle calculation unit, and the duty cycle calculation unit uses a charging program to determine whether the first duty cycle is equal to 0% or 100%. . The motor controller as described in item 1 of the scope of the patent application, wherein the duty cycle processing unit includes a duty cycle calculation unit, and the duty cycle calculation unit uses a discharge program to determine whether the first duty cycle is equal to 0% or 100%. . The motor controller described in item 1 of the scope of the patent application, wherein the duty cycle processing unit includes a duty cycle calculation unit, the duty cycle calculation unit is used to obtain the first duty cycle, and the motor controller utilizes the first The duty cycle is to operate in a one-speed closed-loop mode. The motor controller described in item 1 of the scope of the patent application, wherein the pulse width modulation processing unit performs a multiplication operation on the first duty cycle and a second duty cycle to generate a modulation duty cycle. The motor controller as described in claim 10, wherein the pulse width modulation processing unit generates the second pulse width modulation signal to the control unit by comparing the modulation duty cycle with a comparison value. The motor controller described in claim 11 of the patent application, wherein the comparison value is represented by an N-bit value, where N is a positive integer greater than 1. The motor controller as described in item 12 of the scope of application, wherein N is equal to 8. The motor controller as described in claim 10, wherein the second duty cycle gradually decreases with time. The motor controller as described in claim 10, wherein the second duty cycle gradually increases with time. The motor controller as described in item 1 of the scope of the patent application, wherein the duty cycle processing unit includes a duty cycle calculation unit, the duty cycle calculation unit is used to capture the first duty cycle, and the duty cycle calculation unit is a micro part of the controller. The motor controller as described in claim 16, wherein the microcontroller is implemented on an integrated circuit chip. The motor controller described in item 1 of the scope of the patent application, wherein the duty cycle processing unit includes a duty cycle calculation unit, the first pulse width modulation signal further has a conduction time and a non-conduction time, and the duty cycle calculation unit The unit includes: a conduction time calculation unit for receiving the first pulse width modulation signal to calculate the conduction time; a non-conduction time calculation unit for receiving the first pulse width modulation signal to calculate the non-conduction time and a memory unit, wherein the memory unit is coupled to the conduction time calculation unit to store the conduction time, and the memory unit is coupled to the non-conduction time calculation unit to store the non-conduction time. The motor controller as described in item 18 of the scope of the patent application, wherein the non-conduction time calculation unit is used to determine whether the first duty cycle is equal to 0%, and the conduction time calculation unit is used to determine whether the first duty cycle is equal to 100%. . The motor controller as described in item 1 of the scope of the patent application, wherein the duty cycle processing unit includes a duty cycle calculation unit, the first pulse width modulation signal further has a conduction time and a period, and the duty cycle calculation unit includes : a conduction time calculation unit, used to receive the first pulse width modulation signal to calculate the conduction time; a period calculation unit, used to receive the first pulse width modulation signal to calculate the period; and a memory unit, Wherein the memory unit is coupled to the conduction time calculation unit to store the conduction time, and the memory unit is coupled to the period calculation unit to store the period. The motor controller as described in item 20 of the scope of the patent application, wherein the cycle calculation unit is used to determine whether the first duty cycle is equal to 0%, and the conduction time calculation unit or the cycle calculation unit is used to determine whether the first duty cycle is equal to 0%. Period is equal to 100%. The motor controller described in item 1 of the scope of the patent application, wherein the duty cycle processing unit includes a duty cycle calculation unit, the first pulse width modulation signal further has a non-conduction time and a period, and the duty cycle calculation unit Including: a non-conduction time calculation unit, used to receive the first pulse width modulation signal to calculate the non-conduction time; a period calculation unit, used to receive the first pulse width modulation signal to calculate the period; and a memory unit, wherein the memory unit is coupled to the non-conduction time calculation unit to store the non-conduction time, and the memory unit is coupled to the period computing unit to store the period. The motor controller as described in item 22 of the scope of the patent application, wherein the non-conduction time calculation unit or the period calculation unit is used to determine whether the first duty cycle is equal to 0%, and the cycle calculation unit is used to determine whether the first duty cycle Period is equal to 100%. The motor controller as described in item 1 of the scope of the patent application, wherein the duty cycle processing unit includes a duty cycle calculation unit, and the duty cycle calculation unit includes a charging unit, and the charging unit is used to determine whether the first duty cycle is equal to 0% or 100%. The motor controller as described in item 24 of the scope of patent application, wherein the charging unit charges a component according to the first pulse width modulation signal, and the duty cycle calculation unit determines whether the first component is based on a parameter value of the component Duty cycle is equal to 0% or 100%. The motor controller as described in item 1 of the scope of the patent application, wherein the duty cycle processing unit includes a duty cycle calculation unit, and the duty cycle calculation unit includes a discharge unit, and the discharge unit is used to determine whether the first duty cycle is equal to 0% or 100%. The motor controller as described in item 26 of the scope of patent application, wherein the discharge unit discharges a component according to the first pulse width modulation signal, and the duty cycle calculation unit determines whether the first component is based on a parameter value of the component Duty cycle is equal to 0% or 100%. The motor controller described in item 1 of the scope of the patent application, wherein the duty cycle processing unit includes a duty cycle calculation unit, the duty cycle calculation unit includes a specific application calculation unit, and the specific application calculation unit is used to determine whether the first A duty cycle is equal to 0% or 100%. The motor controller as described in claim 1 of the patent application, wherein the first signal has the first duty cycle. The motor controller as described in claim 29 of the patent application, wherein the first duty cycle is represented by an N-bit value, where N is a positive integer greater than 1. The motor controller as described in claim 30, wherein N is 8. The motor controller as described in claim 29, wherein the first signal is an M-shaped wave signal. The motor controller as described in item 29 of the scope of the patent application, wherein the motor controller further includes a soft switching processing unit, the soft switching processing unit generates a second signal to the pulse width modulation processing unit, and the second signal has a second duty cycle. The motor controller as described in claim 33, wherein the second duty cycle gradually decreases with time. The motor controller as described in claim 33, wherein the second duty cycle increases gradually with time. The motor controller as described in claim 33 of the patent application, wherein the pulse width modulation processing unit includes a multiplication unit, and the multiplication unit is used to generate a third signal according to the first signal and the second signal , the third signal has a modulation duty cycle. The motor controller as described in claim 36, wherein the third signal is an M-shaped wave signal. The motor controller as described in item 36 of the scope of patent application, wherein the pulse width modulation processing unit further includes: a comparison unit; and a triangular wave generation unit for generating a fourth signal to the comparison unit, wherein the comparison The unit receives the third signal and the fourth signal, and compares the third signal with the fourth signal to generate the second PWM signal to the control unit. The motor controller as described in claim 38, wherein the fourth signal is a triangular wave signal or a sawtooth wave signal. The motor controller as described in claim 38, wherein the fourth signal is a constant frequency signal. The motor controller as described in claim 38, wherein the comparison unit is a digital comparator. The motor controller described in item 1 of the scope of the patent application, wherein when the motor controller is in a soft switching driving mode, the motor controller achieves a current wave shaping function when switching phases. The motor controller as described in item 1 of the scope of the patent application, wherein the motor controller is applied to a fan motor system. The motor controller as described in claim 1 of the patent application, wherein the motor controller is applied to a single-phase motor or a multi-phase motor. The motor controller as described in item 1 of the scope of the patent application, wherein the motor controller makes the motor reach a target speed by capturing the first duty cycle. The motor controller as described in item 1 of the scope of the patent application, wherein when a power supply voltage changes, the rotational speed of the motor remains constant. The motor controller as described in claim 1 of the patent application, wherein when a temperature changes, the rotational speed of the motor remains constant. The motor controller as described in claim 1 of the patent application, wherein the motor controller makes the motor rotate stably and the rotation speed of the motor does not deviate.

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