TWI792030B - Composite circuit protection device - Google Patents

Abstract

A composite circuit protection device includes a positive temperature coefficient (PTC) element, a piezoresistor, a first conductive lead and a second conductive lead. The PTC element includes a PTC layer having two opposite PTC surfaces, a first electrode layer and a second electrode layer having surface areas smaller than the respective PTC surface areas. The first conductive lead and the second conductive lead are respectively connected to the PTC element and the piezoresistor. The piezoresistor includes a piezoresistor layer having two opposing resistor surfaces, a third electrode layer and a fourth electrode layer having surface areas smaller than the respective resistor surface areas. The composite circuit protection device of the invention has excellent tolerance, and the PTC element can protect the piezoresistor from being burnt under the presence of overcurrent and overvoltage.

Description

Composite circuit protection device

The present invention relates to a composite circuit protection device, in particular to a composite circuit protection device comprising a positive temperature coefficient (positive temperature coefficient, PTC) element and a voltage-dependent resistor (VDR), At least one of the electrodes has a reduced surface area.

Referring to FIG. 1 , a conventional composite circuit protection device includes a positive temperature coefficient (PTC) element 12 , a varistor (VDR) 13 , a first conductive lead 14 and a second conductive lead 15 . The PTC element 12 includes a PTC layer 121, a first electrode layer 122 and a second electrode layer 123, and the first electrode layer 122 and the second electrode layer 123 respectively have two opposite surfaces connected to the PTC layer 121 respectively. One of the electrode surfaces, and the area of the electrode surface is equal to the area of the two opposite surfaces of the PTC layer 121 . The VDR 13 includes a piezoresistor layer 131, a third electrode layer 132 and a fourth electrode layer 133. The third electrode layer 132 and the fourth electrode layer 133 respectively have two electrodes connected to the piezoresistor layer 131 The electrode surface of one of the two opposite surfaces, and the area of the electrode surface is equal to the area of the two opposite surfaces of the piezoresistor layer 131. The first conductive lead 14 and the second conductive lead 15 are respectively connected to the first electrode layer 122 and the third electrode layer 132 .

Electrical characteristics (such as operating current and high-voltage surge endurance) are important factors affecting the occurrence of power surges in composite circuit protection devices. When the operating current of the composite circuit protection device is increased by increasing the thickness or area of the PTC element 12 , it is more susceptible to damage from power surges. On the other hand, when the high voltage tolerance of the overcurrent protection device is increased by reducing the thickness or area of the PTC element 12 , it is not necessarily less susceptible to power surge damage.

Although the combination of the PTC element 12 and the VDR 13 can provide over-current (over-current) and over-voltage (over-voltage) protection to the combined composite circuit protection device, the VDR 13 can only withstand short-term power surges (such as 0.001 seconds). That is to say, if the surge time exceeds a cut-off time interval, the VDR 13 will be burnt or damaged due to over-current or over-voltage, resulting in permanent loss of function of the composite circuit protection device.

Therefore, the purpose of the present invention is to provide a composite circuit protection device that can overcome at least one of the above-mentioned disadvantages of the prior art.

Therefore, the composite circuit protection device of the present invention includes a positive temperature coefficient (PTC) element, a piezoresistor, a first conductive lead and a second conductive lead. The PTC element includes a PTC layer, a first electrode layer and a second electrode layer. The PTC layer has two opposite PTC surfaces. The first electrode layer and the second electrode layer have two opposite surfaces respectively connected to the PTC layer. An electrode surface of one of the PTC surfaces. The piezoresistor includes a piezoresistor layer, a third electrode layer and a fourth electrode layer, the piezoresistor layer has two opposite resistor surfaces, the third electrode layer has a One of the two opposite resistor surfaces of the piezoresistor layer and the electrode surface between one of the two opposite resistor surfaces of the piezoresistor layer and the second electrode layer of the PTC element, the fourth electrode layer There is an electrode surface connected to the other of the two opposing resistor surfaces of the piezoresistor layer. The first conductive lead is connected to the first electrode layer, and the second conductive lead is connected to one of the third electrode layer and the fourth electrode layer of the piezoresistor. The area of the electrode surfaces of the first electrode layer and the second electrode layer is smaller than the area of the respective PTC surface, or the area of the electrode surfaces of the third electrode layer and the fourth electrode layer is smaller than the area of the respective resistor surface.

The effect of the present invention is that: the composite circuit protection device of the present invention has excellent tolerance and reliability, and the PTC element can protect the piezoresistor from being burnt under the presence of overcurrent and overvoltage.

Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same numerals.

2 and 3, the first embodiment of the composite circuit protection device of the present invention includes a positive temperature coefficient (PTC) element 2, a piezoresistor 3, a first conductive lead 4 and a second conductive lead 5.

The PTC element 2 includes a PTC layer 21, a first electrode layer 22 and a second electrode layer 23, the PTC layer 21 has two opposite PTC surfaces 211, the first electrode layer 22 and the second electrode layer 23 have their own The electrode surfaces 221, 231 of one of the two opposite PTC surfaces 211 of the PTC layer 21 are connected.

The piezoresistor 3 includes a piezoresistor layer 31 , a third electrode layer 32 and a fourth electrode layer 33 , and the piezoresistor layer 31 has two opposite resistor surfaces 311 .

The third electrode layer 32 has one of the two opposite resistor surfaces 311 connected to the piezoresistor layer 31 through solder and is disposed on one of the two opposite resistor surfaces 311 of the piezoresistor layer 31 and the electrode surface 321 between the second electrode layer 23 of the PTC element 2 . The fourth electrode layer 33 has an electrode surface 331 connected to the other of the two opposite resistor surfaces 311 of the piezoresistor layer 31 through solder.

The first conductive lead 4 is connected to the first electrode layer 22 . The second conductive lead 5 is connected to one of the third electrode layer 32 and the fourth electrode layer 33 of the piezoresistor 3 . In this embodiment, the second conductive lead 5 is connected and disposed between the second electrode layer 23 and the third electrode layer 32 .

The area of the electrode surfaces 221, 231 of the first electrode layer 22 and the second electrode layer 23 is smaller than the area of the respective PTC surface 211. The area of the electrode surfaces 321, 331 of the third electrode layer 32 and the fourth electrode layer 33 is smaller than the area of the respective resistor surface 311.

In some embodiments of the present invention, the area of the electrode surfaces 221, 231 of the first electrode layer 22 and the second electrode layer 23 is between 70% and 90% of the area of the respective PTC surface 211.

In some embodiments of the present invention, the area of the electrode surfaces 321, 331 of the third electrode layer 32 and the fourth electrode layer 33 is between 70% and 90% of the area of the respective resistor surface 311.

The PTC element 2 has a rated voltage ranging from 40% to 200% of the varistor voltage measured by the piezoresistor 3 at 1 mA. In some embodiments of the present invention, the PTC element 2 has a rated voltage ranging from 45% to 100% of the varistor voltage measured by the varistor 3 at 1 mA. In some embodiments of the present invention, the PTC element 2 has a rated voltage ranging from 45% to 70% of the varistor voltage measured by the varistor 3 at 1 mA.

According to the present invention, the PTC element 2 trips before the piezoresistor 3 burns out under an overcurrent and a voltage greater than the piezoresistor voltage of the piezoresistor 3 . In other words, in the presence of the overcurrent and the voltage greater than the varistor voltage of the piezoresistor 3, the PTC element 2 quickly jumps to a high resistance state so that the overcurrent is restricted from flowing through The piezoresistor 3 thus protects the piezoresistor 3 from being burned, and the composite circuit protection device can thus be reused.

Herein, the terms "burn out", "spark" and "ignite" are used interchangeably and refer to the loss of function of the varistor, which usually occurs above 180°C.

In some specific embodiments of the present invention, the PTC element 2 trips within 1 μs to 100 s under an overcurrent greater than 0.1 A and a voltage greater than the varistor voltage of the varistor 3 . In some embodiments of the present invention, the PTC element 2 trips within 10 μs to 10 s under an overcurrent greater than 0.1 A and a voltage greater than the varistor voltage of the varistor 3 . In some embodiments of the present invention, the PTC element 2 trips within 0.1 ms to 1 s under an overcurrent greater than 0.1 A and a voltage greater than the varistor voltage of the varistor 3 .

In some specific embodiments of the present invention, the PTC element 2 trips within 1 ms to 10 s under an overcurrent greater than 0.5 A and a voltage greater than the varistor voltage of the varistor 3 . In some embodiments of the present invention, the PTC element 2 trips within 1 ms to 1 s under an overcurrent greater than 0.5 A and a voltage greater than the varistor voltage of the varistor 3 .

In some embodiments of the present invention, the PTC element 2 trips within 1 ms to 1 s under an overcurrent greater than 10 A and a voltage greater than the varistor voltage of the varistor 3 . In some specific embodiments of the present invention, the PTC element 2 trips within 1 ms to 0.1 s under an overcurrent greater than 10 A and a voltage greater than the varistor voltage of the varistor 3 .

The PTC element 2 can be formed with a first hole 210 . In this embodiment, the first hole 210 is formed in the PTC layer 21 . The PTC layer 21 of the PTC element 2 has a rim 212 which defines the boundary of the PTC layer 21 and interconnects two opposite PTC surfaces 211 of the PTC layer 21 . The first hole 210 is spaced from the peripheral edge 212 of the PTC layer 21 , and has an effective volume capable of accommodating thermal expansion of the PTC layer 21 when the temperature rises, so as to avoid unwanted structural deformation of the PTC layer 21 .

In some embodiments of the present invention, the first hole 210 runs through at least one of the two opposite PTC surfaces 211 of the PTC layer 21 . In some embodiments of the present invention, the first hole 210 also penetrates at least one of the first electrode layer 22 and the second electrode layer 23 . In this embodiment, the first hole 210 penetrates the two opposite PTC surfaces 211 of the PTC layer 21 and the first electrode layer 22 and the second electrode layer 23 to form a through hole. In some embodiments of the present invention, the first hole 210 extends along a line passing through the geometric center of the PTC layer 21 and crossing the two opposite PTC surfaces 211 . The first hole 210 is defined by a hole-defining wall having a cross-section parallel to the PTC surface 211 of the PTC layer 21 . The cross-section of the hole-defining wall may be circular, square, elliptical, triangular, cross-shaped, etc.

According to the present invention, the PTC element 2 can be a polymer PTC (PPTC) element, and the PTC layer 21 can be a PTC polymer layer. The PTC polymer layer includes a polymer base material and conductive filler dispersed in the polymer base material. The piezoresistor layer 31 can be made of metal oxide material. The polymer substrate can be prepared from a polymer composition containing a non-grafted olefin-based polymer. In some embodiments of the present invention, the non-grafted olefinic polymer is high density polyethylene (HDPE). In some embodiments of the present invention, the polymer composition further includes a grafted olefin-based polymer. In some embodiments of the present invention, the grafted olefinic polymer is a carboxylic anhydride-grafted olefinic polymer. The conductive filler suitable for the present invention is selected from carbon black powder, metal powder, conductive ceramic powder or a combination thereof, but not limited thereto.

The piezoresistor 3 can form a second hole 310 in the piezoresistor layer 31 . In this embodiment, the piezoresistor layer 31 of the piezoresistor 3 has a peripheral edge 312, which defines the boundary of the piezoresistor layer 31 and is opposite to the two sides of the piezoresistor layer 31. The resistor surfaces 311 are interconnected. The second hole 310 is spaced apart from the periphery 312 of the piezoresistor layer 31 .

In some embodiments of the present invention, the second hole 310 penetrates at least one of the two opposite resistor surfaces 311 of the piezoresistor layer 31 . In some embodiments of the present invention, the second hole 310 also penetrates at least one of the third electrode layer 32 and the fourth electrode layer 33 . In this embodiment, the second hole 310 penetrates through two opposite resistor surfaces 311 of the piezoresistor layer 31 and the third electrode layer 32 and the fourth electrode layer 33 to form a through hole.

According to the present invention, the first conductive lead 4 has a connecting portion 41 and a free portion 42 , and the second conductive lead 5 has a connecting portion 51 and a free portion 52 . The connecting portion 41 of the first conductive lead 4 is connected to the outer surface of the first electrode layer 22 by a solder, and the free portion 42 of the first conductive lead 4 extends out of the first electrode layer 22 from the connecting portion 41 Pin holes (not shown) for insertion into a circuit board or a circuit device. In this embodiment, the connecting portion 51 of the second conductive lead 5 is connected by a solder and is arranged between the second electrode layer 23 and the third electrode layer 32, and the free portion of the second conductive lead 5 52 extends from the connecting portion 51 to the second electrode layer 23 and the third electrode layer 32 for insertion into pin holes (not shown) of a circuit board or a circuit device.

Referring to Fig. 4 and Fig. 5, the second embodiment of the composite circuit protection device of the present invention is similar to the first embodiment, the difference is that in the second embodiment, the connecting portion 51 of the second conductive lead 5 is connected by A solder is connected to the outer surface of the fourth electrode layer 33, and the free portion 52 of the second conductive lead 5 extends out of the fourth electrode layer 33 from the connection portion 51 for insertion into a circuit board or a circuit device. Foot holes (not shown). In addition, the second embodiment further includes a packaging material 7 , and the packaging material 7 packages the PTC element 2 , the piezoresistor 3 , a part of the first conductive lead 4 and a part of the second conductive lead 5 . The free portion 42 of the first conductive lead 4 and the free portion 52 of the second conductive lead 5 are exposed outside the packaging material 7 . In some specific embodiments of the present invention, the packaging material 7 is made of epoxy resin.

Referring to Fig. 6, the third embodiment of the composite circuit protection device of the present invention is similar to the second embodiment, the difference is that the third embodiment also includes a third conductive lead 6, and the third conductive lead 6 is connected and arranged between the second electrode layer 23 and the third electrode layer 32 . The third conductive lead 6 has a connecting portion 61 and a free portion 62 . The connecting portion 61 of the third conductive lead 6 is connected to the second electrode layer 23 and the third electrode layer 32, and the free portion 62 of the third conductive lead 6 extends from the connecting portion 61 to the second electrode layer 23 and the third electrode layer 32. The third electrode layer 32 is used for inserting into pin holes (not shown) of a circuit board or a circuit device.

In this embodiment, the packaging material 7 packages the PTC element 2 , the piezoresistor 3 , a part of the first conductive lead 4 , a part of the second conductive lead 5 and a part of the third conductive lead 6 . The free portion 42 of the first conductive lead 4 , the free portion 52 of the second conductive lead 5 and a part of the free portion 62 of the third conductive lead 6 are exposed outside the packaging material 7 .

The present invention will be further described with reference to the following examples, but it should be understood that these examples are for illustrative purposes only, and should not be construed as limitations on the implementation of the present invention.

Example

＜Example 1 (E1) >

10 g of HDPE (purchased from Taiwan Plastic Industry Co., Ltd., product model: HDPE9002) was used as a non-grafted olefin polymer, and 10 g of HDPE grafted with maleic anhydride (purchased from DuPont, product model: MB100D) was used as Olefin-based polymer grafted with carboxylic anhydride, 15 g carbon black powder (available from Columbian Chemicals, product model: Raven 430UB) as conductive filler, 15 g magnesium hydroxide (available from Martin Marietta Company, product model: MagChem® MH 10).

The above ingredients were mixed in a mixer (brand: Brabender), and the ingredients were mixed for 10 min at a temperature of 200°C and a stirring speed of 30 rpm.

The above-mentioned obtained ingredient mixture was placed in a mold, and hot-pressed for 4 minutes at a hot-pressing temperature of 200° C. and a hot-pressing pressure of 80 kg/cm ² to form a PTC polymer layer sheet. Take the sheet out of the mold, and make its two opposite PTC surfaces contact with two pieces of copper foil (respectively as the first electrode layer and the second electrode layer), and carry out hot pressing at 200°C and 80 kg/cm ² 4 min to form a PPTC element with a thickness of 2.2 mm. Then, the PPTC element was cut into several circular chips (chips, hereinafter referred to as PPTC chips) with a diameter of 14.5 mm (area about 165.1 mm ² ), and irradiated with Co-60 γ-rays at a total radiation dose of 150 kGy per chip. A small piece of PPTC.

A circular metal-oxide varistor (metal-oxide varistor, MOV, purchased from Ceramate Technical Company, product model: 20D361K, hereinafter referred to as MOV) includes a varistor layer and two electrode layers (respectively as the first three electrode layer and the fourth electrode layer), the piezoresistor layer has two opposite resistor surfaces (both are 20.0 mm in diameter, and the area is about 314.2 mm ² ), the electrode layers are respectively connected to the piezoresistor layer of two opposite resistor surfaces. The MOV is etched to remove part of the periphery of the electrode layers, so that each third electrode layer and each fourth electrode layer form a circular electrode layer with a diameter of 18.9 mm (area is about 280.6 mm ² ), That is, the electrode coverage of the etched MOV is about 89%, that is, the area of each third electrode layer and each fourth electrode layer (280.6 mm ² ) is about 89% of the area of the respective resistor surfaces (314.2 mm 2 ). mm ² ).

Solder the first conductive lead and the second conductive lead on the two copper foils of each PPTC chip, and then weld the etched MOV to one of the two copper foils to form an E1 composite circuit protection device.

According to the safety standard UL 1434 of Underwriter Laboratories for thermistor-type devices, the holding current (hold current, i.e. the maximum current value during normal operation) and the trip current (trip current, i.e. The minimum current value required for the PPTC element to reach a high resistance state), the rated voltage (that is, the voltage applicable to the PPTC element when it is working), and the withstand voltage (withstand voltage, that is, the maximum voltage that will not cause the PPTC element to fail or be damaged). In addition, before the etching process, the varistor voltage (that is, the voltage at which the MOV triggers work) and the clamping voltage (clamping voltage) of the MOV element were measured according to Underwriter Laboratories' safety standard UL 1449 for transient voltage surge suppressors. , that is, the MOV can provide a limited maximum voltage). The property measurement results of PPTC flakes and MOV are shown in Table 1, respectively. 【Table 1】 holding current Trip current Rated voltage withstand voltage PPTC 0.08A 0.16A 250V 250V Varistor voltage ^a Clamping voltage ^b MOV 360V 595V a: Measured at 1 mA. b: Measured under pulse waveform (t _p ) 8/20 μs and pulse current (I _p ) 2.5 A.

<Example 2 and 3 (E2 and E3) >

The process conditions of the composite circuit protection devices of E2 and E3 are similar to those of E1, the difference is that before the PPTC chips are irradiated with gamma rays, the PPTC chips of E2 and E3 are etched to remove part of the first electrode layer and the second electrode layer. The periphery of the two electrode layers makes each first electrode layer and each second electrode layer form a circular electrode layer with a diameter of 13.7 mm (area is about 147.4 mm ² ), which is the electrode coverage of the etched PPTC chip. About 89%, that is, the area of each first electrode layer and each second electrode layer (147.4 mm ² ) is about 89% of the area of the respective PTC surface (165.1 mm ² ). In addition, the MOV in E2 was not etched, that is, the electrode coverage of its MOV was 100%.

<Example 4 to 12 (E4-E12) >

The process conditions of the composite circuit protection devices of E4-E6, E7-E9, and E10-E12 are similar to those of E1-E3 respectively, the difference is that the PPTC chip is formed with the first through hole and/or the MOV is formed with the second through hole (as shown in Table 2), each first through-hole and each second through-hole are defined by a hole-defining wall with a circular cross-section (diameter 1.5 mm, circular area 1.77 mm ² ).

In E4-E6, after gamma-ray irradiation, a first perforation was punched in the central portion of the PPTC platelet. In E7-E9, a second through-hole was drilled in the central part of the MOV before the copper foil was soldered on. In E10-E12, a first through-hole was drilled in the central portion of the PPTC die and a second through-hole was drilled in the central portion of the MOV (as shown in FIG. 3 ).

＜Comparative example 1 to 4 (CE1-CE4) >

The process conditions of the circuit protection devices of CE1-CE4 are similar to those of E2, E3, E8, and E9 respectively. The difference is that CE1-CE4 do not contain PPTC chips.

＜Comparative example 5 to 8 (CE5-CE8) >

The process conditions of the circuit protection devices of CE5-CE8 are similar to those of E1, E3, E4, and E6 respectively. The difference is that none of CE5-CE8 contain MOV.

＜Comparative example 9 to 12 (CE9-CE12) >

The process conditions of CE9-CE12 composite circuit protection devices are similar to those of E1, E4, E7, and E10. The difference is that the electrode coverage of CE9-CE12 MOVs is 100%.

The structure of the (composite) circuit protection devices of E1-E12 and CE1-CE12 is shown in Table 2. 【Table 2】 (Composite) circuit protection device PPTC chip MOV Electrode coverage first piercing Electrode coverage second piercing E1 100% -- 89% -- E2 89% -- 100% -- E3 89% -- 89% -- E4 100% have 89% -- E5 89% have 100% -- E6 89% have 89% -- E7 100% -- 89% have E8 89% -- 100% have E9 89% -- 89% have E10 100% have 89% have E11 89% have 100% have E12 89% have 89% have CE1 -- -- 100% -- CE2 -- -- 89% -- CE3 -- -- 100% have CE4 -- -- 89% have CE5 100% -- -- -- CE6 89% -- -- -- CE7 100% have -- -- CE8 89% have -- -- CE9 100% -- 100% -- CE10 100% have 100% -- CE11 100% -- 100% have CE12 100% have 100% have "--" indicates no such component.

Performance Testing

[ Surge Immunity Test (Surge immunity test)]

For E1-E12 and CE1-CE12 (composite) circuit protection devices, take 10 samples as test samples for surge immunity test.

The surge immunity test of each test sample is to be connected first under the voltage of the varistor voltage (600 V _ac or 700 V _ac ) greater than MOV and the current of 0.5 A or the overcurrent of the PPTC chip (ie 10 A) The first conductive lead and the second conductive lead are tested in a manner of closing after 60 seconds. If both the PPTC chip and the MOV are not burned or damaged, the test sample has passed the surge immunity test, and the average value of the time for the PPTC chip to trip (if there is a trip) is recorded. If the PPTC chip or MOV burns, the test sample is burnt, and the average time to burn is recorded. The results are shown in Table 3 respectively. 【table 3】 600V/0.5A 600V/10A 700V/0.5A 700V/10A result time(s) result time(s) result time(s) result time(s) E1 pass 2.950 pass 0.255 pass 1.850 pass 0.190 E2 pass 2.900 pass 0.240 pass 1.815 pass 0.185 E3 pass 2.875 pass 0.235 pass 1.810 pass 0.180 E4 pass 2.850 pass 0.230 pass 1.800 pass 0.175 E5 pass 2.840 pass 0.225 pass 1.795 pass 0.170 E6 pass 2.825 pass 0.220 pass 1.780 pass 0.160 E7 pass 2.820 pass 0.230 pass 1.775 pass 0.160 E8 pass 2.815 pass 0.220 pass 1.700 pass 0.155 E9 pass 2.805 pass 0.215 pass 1.695 pass 0.150 E10 pass 2.650 pass 0.195 pass 1.550 pass 0.140 E11 pass 2.600 pass 0.190 pass 1.455 pass 0.130 E12 pass 2.515 pass 0.185 pass 1.405 pass 0.115 CE1 MOV burned 5.175 MOV burned 0.965 MOV burned 4.985 MOV burned 0.865 CE2 MOV burned 5.170 MOV burned 0.950 MOV burned 4.975 MOV burned 0.855 CE3 MOV burned 5.125 MOV burned 0.950 MOV burned 4.800 MOV burned 0.855 CE4 MOV burned 5.110 MOV burned 0.935 MOV burned 4.750 MOV burned 0.840 CE5 PPTC burned 9.175 PPTC burned 0.285 PPTC burned 9.170 PPTC burned 0.280 CE6 PPTC burned 9.170 PPTC burned 0.275 PPTC burned 9.165 PPTC burned 0.270 CE7 PPTC burned 9.165 PPTC burned 0.275 PPTC burned 9.150 PPTC burned 0.255 CE8 PPTC burned 9.160 PPTC burned 0.265 PPTC burned 9.145 PPTC burned 0.250 CE9 MOV burned 3.550 PPTC burned 0.795 MOV burned 3.330 PPTC burned 0.765 CE10 MOV burned 3.355 PPTC burned 0.770 MOV burned 3.250 PPTC burned 0.760 CE11 MOV burned 3.400 PPTC burned 0.775 MOV burned 3.125 PPTC burned 0.750 CE12 MOV burned 3.300 PPTC burned 0.755 MOV burned 3.050 PPTC burned 0.735

The results in Table 3 show that the test samples of CE1-CE4 containing only MOVs burned within 5.2 s under an overcurrent of 0.5 A and a voltage of at least 1.6 times the varistor voltage of MOV (general MOV can withstand 1.2 times its varistor voltage Voltage), or burned within 1.0 s under overcurrent and overvoltage of 10 A, and the damage cannot be repaired. In addition, CE5-CE8 test samples containing only PPTC chips burned down under an overcurrent of 0.5 A or 10 A.

Although the test samples of CE9-CE12 contained PPTC chips and MOVs, the electrode coverage of the PPTC chips and MOVs was 100%, and the PPTC chips and MOVs were burned under the overcurrent and overvoltage of 0.5 A or 10 A, respectively.

Conversely, all test samples from E1-E12 containing combinations of PPTC chips and MOVs (where the PPTC chips and/or MOVs had less than 90% electrode coverage) passed the surge immunity test without burning, showing that the PPTC chips and/or MOVs The area reduction of the electrode layer can effectively prevent the circuit protection device from being damaged.

In addition, compared with E1-E3, E4-E12 test samples with PPTC chips and/or MOVs formed with perforations have improved heat transfer, which can further shorten the time for PPTC chips to trip and prevent overcurrent from flowing through MOVs, so Protect its MOV from being burned. In other words, in the test samples of E1-E12, the PPTC die was tripped before the MOV was burnt out under an overcurrent and a voltage greater than the varistor voltage of the MOV.

In summary, by controlling the area of each electrode layer of the PTC element to be smaller than the area of the respective PTC surface, and/or controlling the area of each electrode layer of the piezoresistor to be smaller than the area of the respective resistor surface In the presence of the overcurrent and the overvoltage, the PTC element quickly jumps to a high resistance state to protect the piezoresistor from being burned due to an undesired arc. The composite circuit of the present invention The protective device can thus be used repeatedly, showing its excellent tolerance and reliability, so the purpose of the present invention can be achieved indeed.

But what is described above is only an embodiment of the present invention, and should not limit the scope of the present invention. All simple equivalent changes and modifications made according to the patent scope of the present invention and the content of the patent specification are still within the scope of the present invention. Within the scope covered by the patent of the present invention.

12: PTC element 121: PTC layer 122: the first electrode layer 123: Second electrode layer 13: Varistor 131: Varistor layer 132: The third electrode layer 133: The fourth electrode layer 14: First conductive lead 15: Second conductive lead 2: PTC element 21: PTC layer 210: The first hole 211: PTC surface 212: Perimeter 22: The first electrode layer 221: electrode surface 23: Second electrode layer 231: electrode surface 3: Varistor 31: Varistor layer 310: second hole 311: Resistor surface 312: Perimeter 32: The third electrode layer 321: electrode surface 33: The fourth electrode layer 331: electrode surface 4: The first conductive lead 41: Connecting part 42: Ministry of Freedom 5: Second conductive lead 51: Connecting part 52: Ministry of Freedom 6: The third conductive lead 61: Connecting part 62: Ministry of Freedom 7: Encapsulation material

Other features and effects of the present invention will be clearly presented in the implementation manner with reference to the drawings, wherein: [Figure 1] is a schematic diagram of an existing composite circuit protection device; [Fig. 2] is a schematic diagram of the first specific embodiment of the composite circuit protection device of the present invention; [Fig. 3] is a schematic cross-sectional view of the first specific embodiment; [Fig. 4] is a schematic diagram of the second specific embodiment of the composite circuit protection device of the present invention; [Fig. 5] is a schematic cross-sectional view of the second specific embodiment; [ Fig. 6 ] is a schematic cross-sectional view of the third embodiment of the composite circuit protection device of the present invention.

2: PTC element

21: PTC layer

210: The first hole

211: PTC surface

22: The first electrode layer

221: electrode surface

23: Second electrode layer

231: electrode surface

3: Varistor

31: Varistor layer

310: second hole

311: Resistor surface

32: The third electrode layer

321: electrode surface

33: The fourth electrode layer

331: electrode surface

4: The first conductive lead

41: Connecting part

42: Ministry of Freedom

5: Second conductive lead

51: Connecting part

52: Ministry of Freedom

Claims (20)

A composite circuit protection device, comprising: a PTC element, including: a PTC layer having two opposite PTC surfaces, and a first electrode layer and a second electrode layer respectively having two opposite PTC surfaces respectively connected to the PTC layer the electrode surface of one of them; a piezoresistor comprising: a piezoresistor layer having two opposite resistor surfaces, a third electrode layer having two opposite resistors connected to the piezoresistor layer One of the device surfaces and the electrode surface disposed between one of the two opposite resistor surfaces of the piezoresistor layer and the second electrode layer of the PTC element, and a fourth electrode layer having a connection with the an electrode surface of the other of the two opposite resistor surfaces of the varistor layer; a first conductive lead connected to the first electrode layer; and a second conductive lead connected to the first electrode layer of the varistor. One of the three electrode layers and the fourth electrode layer, wherein the area of the electrode surfaces of the first electrode layer and the second electrode layer is smaller than the area of the respective PTC surface, or the area of the third electrode layer and the fourth electrode layer The surface area of the electrodes is smaller than that of the respective resistor surfaces, and the PTC element trips within 1 μs to 100 s under an overcurrent greater than 0.1A and a voltage greater than the varistor voltage of the varistor. The composite circuit protection device as claimed in claim 1, wherein the area of the electrode surfaces of the first electrode layer and the second electrode layer is between 70% and 90% of the area of the respective PTC surfaces. The composite circuit protection device as claimed in claim 1, wherein the area of the electrode surfaces of the third electrode layer and the fourth electrode layer is between 70% and 90% of the area of the respective resistor surfaces. The composite circuit protection device as claimed in claim 1, wherein the rated voltage of the PTC element is between 45% and 200% of the varistor voltage measured by the varistor at 1 mA. The composite circuit protection device as claimed in claim 1, wherein the rated voltage of the PTC element is between 45% and 100% of the varistor voltage measured by the varistor at 1 mA. The composite circuit protection device as claimed in claim 1, wherein the rated voltage of the PTC element is between 45% and 70% of the varistor voltage measured by the varistor at 1mA. The composite circuit protection device according to claim 1, wherein the PTC element trips within 1ms to 10s under an overcurrent greater than 0.5A and a voltage greater than the varistor voltage of the varistor . The composite circuit protection device as claimed in claim 1, wherein the PTC element trips within 1ms to 1s under an overcurrent greater than 10A and a voltage greater than the varistor voltage of the varistor. The composite circuit protection device as claimed in claim 1, wherein the PTC element has a first hole formed in the PTC layer. The composite circuit protection device as claimed in claim 9, wherein the PTC layer of the PTC element has a periphery, the periphery defines the boundary of the PTC layer and is interconnected with two opposite PTC surfaces of the PTC layer, the first Holes are spaced from the periphery of the PTC layer. The composite circuit protection device as claimed in claim 9, wherein the first hole penetrates at least one of the two PTC opposite surfaces of the PTC layer. The composite circuit protection device as claimed in claim 11, wherein the first hole also penetrates at least one of the first electrode layer and the second electrode layer. The composite circuit protection device as claimed in claim 1, wherein a second hole is formed in the piezoresistor. The composite circuit protection device according to claim 1, further comprising a third conductive lead, the second conductive lead is connected to the fourth electrode layer, and the third conductive lead is connected and arranged between the second electrode layer and the Between the third electrode layer. The composite circuit protection device as claimed in claim 1, wherein the piezoresistor has a second hole formed in the piezoresistor layer. The composite circuit protection device as claimed in claim 15, wherein the piezoresistor layer of the piezoresistor has a peripheral edge that defines the boundary of the piezoresistor layer and is connected to the piezoresistor layer Two opposite resistor surfaces are interconnected, and the second hole is spaced from the periphery of the piezoresistor layer. The composite circuit protection device as claimed in claim 15, wherein the second hole penetrates at least one of the two opposite resistor surfaces of the piezoresistor layer. The composite circuit protection device as claimed in claim 17, wherein the second hole also penetrates at least one of the third electrode layer and the fourth electrode layer. The composite circuit protection device as claimed in claim 1, wherein the PTC element is a polymer PTC element, and the PTC layer is a PTC polymer layer. The composite circuit protection device according to claim 1 further includes a packaging material, the packaging material packages the PTC element, the piezoresistor, a part of the first conductive lead and a part of the second conductive lead.

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