CN113629660A

CN113629660A - Composite circuit protection device

Info

Publication number: CN113629660A
Application number: CN202010381456.2A
Authority: CN
Inventors: 陈继圣; 江长鸿
Original assignee: Fuzetec Technology Co Ltd
Current assignee: Fuzetec Technology Co Ltd
Priority date: 2020-05-08
Filing date: 2020-05-08
Publication date: 2021-11-09

Abstract

A composite circuit protection device comprises a first Positive Temperature Coefficient (PTC) element, a second PTC element, a piezoresistor, a first conductive lead, a second conductive lead and a third conductive lead. The first PTC element comprises a first PTC layer, a first electrode layer and a second electrode layer, wherein the first electrode layer and the second electrode layer are respectively arranged on two opposite surfaces of the first PTC layer. The second PTC element comprises a second PTC layer, a third electrode layer and a fourth electrode layer, wherein the third electrode layer and the fourth electrode layer are respectively arranged on two opposite surfaces of the second PTC layer. The piezoresistor is connected to the second electrode layer and the third electrode layer. The first conductive lead is connected to the first electrode layer, the second conductive lead is connected to the piezoresistor, and the third conductive lead is connected to the fourth electrode layer. The composite circuit protection device has excellent tolerance and can protect the piezoresistors clamped between the two PTC elements from being burnt in the presence of over-current and over-voltage.

Description

Composite circuit protection device

Technical Field

The present invention relates to a composite circuit protection device, and more particularly, to a composite circuit protection device including a voltage-dependent resistor (VDR or varistor) sandwiched between two Positive Temperature Coefficient (PTC) elements.

Background

US 8,508,328B 1 describes an interposed Polymeric Positive Temperature Coefficient (PPTC) overcurrent protection device, see figure 1, which comprises two electrodes 30, solder (solder material), electrically

conductive leads

50,60 respectively connected to the electrodes 30, and a PTC polymer substrate 20 laminated between the electrodes 30. The PTC polymer substrate 20 has a cavity 40 formed therein, the cavity 40 having an effective volume to accommodate thermal expansion of the PTC polymer substrate 20 when the temperature increases.

Electrical characteristics, such as operating current (operating current) and high-voltage surge withstand (high-voltage surge) are important factors that affect the occurrence of a power surge in a PPTC overcurrent protection device. For example, increasing the thickness or area of the PTC polymer substrate 20 increases the operating current of the PPTC overcurrent protection device, which is more susceptible to electrical surges. On the other hand, reducing the thickness or area of the PTC polymer substrate 20 increases the high voltage withstand of the PPTC overcurrent protection device, which is not necessarily less susceptible to electrical surges.

Although a voltage-dependent resistor (VDR) may be incorporated with the PPTC overcurrent protection device to impart overcurrent and overvoltage (over-voltage) protection to the combined composite circuit protection device, the VDR can only withstand power surges briefly (e.g., 0.001 seconds). That is, if the surge time interval exceeds the cut-off time interval, the VDR will be burned or damaged by the over-current and over-voltage, so that the composite circuit protection device will lose its function permanently.

Disclosure of Invention

The present invention is directed to a composite circuit protection device that overcomes at least one of the above-mentioned shortcomings of the prior art.

The composite circuit protection device comprises a first Positive Temperature Coefficient (PTC) element, a second PTC element, a piezoresistor, a first conductive lead, a second conductive lead and a third conductive lead. The first PTC element comprises a first PTC layer, a first electrode layer and a second electrode layer, wherein the first PTC layer is provided with two opposite surfaces, and the first electrode layer and the second electrode layer are respectively arranged on the two opposite surfaces of the first PTC layer. The second PTC element comprises a second PTC layer, a third electrode layer and a fourth electrode layer, wherein the second PTC layer is provided with two opposite surfaces, and the third electrode layer and the fourth electrode layer are respectively arranged on the two opposite surfaces of the second PTC layer. The piezoresistor is connected to the second electrode layer of the first PTC element and the third electrode layer of the second PTC element. The first conductive lead is connected to the first electrode layer of the first PTC element. The second conductive lead is connected to the piezoresistor. The third conductive lead is connected to the fourth electrode layer of the second PTC element.

The invention has the beneficial effects that: the composite circuit protection device has excellent tolerance and reliability, and can protect the piezoresistors clamped between the two PTC elements from being burnt in the presence of over-current and over-voltage.

Drawings

Other features and effects of the present invention will be apparent from the embodiments with reference to the accompanying drawings, in which:

figure 1 is a schematic diagram of a prior art plug-in PPTC overcurrent protection device;

FIG. 2 is a schematic diagram of a composite circuit protection device according to a first embodiment of the invention;

FIG. 3 is a schematic cross-sectional view of the first embodiment;

FIG. 4 is a schematic diagram of a composite circuit protection device according to a second embodiment of the present invention;

FIG. 5 is a schematic cross-sectional view of the second embodiment;

FIG. 6 is a schematic cross-sectional view of a composite circuit protection device according to a third embodiment of the present invention;

FIG. 7 is a schematic diagram of a composite circuit protection device according to a fourth embodiment of the present invention; and

fig. 8 is a schematic cross-sectional view of the fourth embodiment.

Detailed Description

Before the present invention is described in detail, it should be noted that in the following description, like elements are represented by like reference numerals.

Referring to fig. 2 and 3, the first embodiment of the composite circuit protection device of the present invention includes a first Positive Temperature Coefficient (PTC) element 2, a varistor 3, a second PTC element 4, a first conductive lead 5, a second conductive lead 6, and a third conductive lead 7.

The first PTC element 2 includes a first PTC layer 21, a first electrode layer 22 and a second electrode layer 23, the first PTC layer 21 has two opposite surfaces 211, and the first electrode layer 22 and the second electrode layer 23 are respectively disposed on the two opposite surfaces 211 of the first PTC layer 21.

The second PTC element 4 includes a second PTC layer 41, a third electrode layer 42 and a fourth electrode layer 43, the second PTC layer 41 has two opposite surfaces 411, and the third electrode layer 42 and the fourth electrode layer 43 are respectively disposed on the two opposite surfaces 411 of the second PTC layer 41.

The varistor 3 is connected to the second electrode layer 23 of the first PTC element 2 and the third electrode layer 42 of the second PTC element 4 by solder.

The first conductive lead 5 is connected to the first electrode layer 22 of the first PTC element 2. The second conductive lead 6 is connected to the varistor 3. The third conductive lead 7 is connected to the fourth electrode layer 43 of the second PTC element 4.

In some embodiments of the invention, the first PTC element 2 has a rated voltage (rated voltage) between 40% and 200% of the varistor voltage (varistor voltage) of the varistor 3 measured at 1 mA. In some embodiments of the invention, the first PTC element 2 has a rated voltage of between 110% and 200% of the varistor voltage of the varistor 3 measured at 1 mA.

According to the present invention, the first PTC element 2 or the second PTC element 4 is at an overcurrent and a voltage larger than the varistor voltage of the varistor 3 to trip before the varistor 3 burns out. In other words, in the presence of the overcurrent and the voltage greater than the varistor voltage of the varistor 3, the first PTC device 2 or the second PTC device 4 is rapidly tripped to a high resistance state, so that the overcurrent is restricted from flowing through the varistor 3, thereby protecting the varistor 3 from being burned out, and the hybrid circuit protection device is thus reused.

In this context, the terms "burn", "spark" and "fire" are used interchangeably and refer to the loss of function of the varistor 3, which typically occurs above 180 ℃.

In some embodiments of the present invention, the first PTC element 2 or the second PTC element 4 trips within 10 μ s to 10s at an overcurrent and a voltage greater than the voltage-dependent voltage of the voltage-dependent resistor 3. In some embodiments of the present invention, the first PTC element 2 or the second PTC element 4 trips within 1ms to 10s at an overcurrent of not less than 0.5A and a voltage greater than the varistor voltage of the varistor 3. In some embodiments of the present invention, the first PTC element 2 or the second PTC element 4 trips within 1ms to 1s at an overcurrent of not less than 10A and a voltage greater than the varistor voltage of the varistor 3.

The first PTC element 2 may be formed with a first hole 210. In this embodiment, the first hole 210 is formed in the first PTC layer 21. The first PTC layer 21 of the first PTC element 2 has a peripheral edge 212, which peripheral edge 212 defines the boundary of the first PTC layer 21 and interconnects with two opposite surfaces 211 of the first PTC layer 21. The first hole 210 is spaced from the periphery 212 of the first PTC layer 21 and has an effective volume to accommodate thermal expansion of the first PTC layer 21 at elevated temperatures to prevent undesirable structural deformation of the first PTC layer 21.

In some embodiments of the present invention, the first hole 210 extends through at least one of two opposing surfaces 211 of the first PTC layer 21. In some embodiments of the present invention, the first hole 210 further penetrates at least one of the first electrode layer 22 and the second electrode layer 23. In this embodiment, the first hole 210 penetrates through two opposite surfaces 211 of the first PTC layer 21 and the first and

second electrode layers

22 and 23 to form a through hole. In some embodiments of the present invention, the first hole 210 extends along a line passing through the geometric center of the first PTC layer 21 and across the two opposing surfaces 211. The first hole 210 is defined by a first hole defining wall having a cross section parallel to the surface 211 of the first PTC layer 21. The first aperture defining wall may have a circular, square, oval, triangular, cross-shaped cross-section, etc.

The second PTC device 4 may be formed with a second hole 410. In this embodiment, the second hole 410 is formed in the second PTC layer 41. The second PTC layer 41 of the second PTC element 4 has a peripheral edge 412, which peripheral edge 412 defines the boundary of the second PTC layer 41 and interconnects with two opposite surfaces 411 of the second PTC layer 41. The second hole 410 is spaced apart from the periphery 412 of the second PTC layer 41 and has an effective volume to accommodate thermal expansion of the second PTC layer 41 at elevated temperatures to prevent undesirable structural deformation of the second PTC layer 41.

In some embodiments of the invention, the second hole 410 extends through at least one of two opposing surfaces 411 of the second PTC layer 41. In some embodiments of the present invention, the second hole 410 further penetrates at least one of the third electrode layer 42 and the fourth electrode layer 43. In this embodiment, the second hole 410 penetrates through two opposite surfaces 411 of the second PTC layer 41 and the third and

fourth electrode layers

42 and 43 to form a through hole. In some embodiments of the invention, the second aperture 410 extends along a line passing through the geometric center of the second PTC layer 41 and across the two opposing surfaces 411. The second aperture 410 is defined by a second aperture defining wall having a cross-section parallel to the surface 411 of the second PTC layer 41. The second aperture defining wall may be circular, square, oval, triangular, cross-shaped, etc. in cross-section.

According to the present invention, the first PTC element 2 and the second PTC element 4 can both be polymer PTC (pptc) elements, and the first PTC layer 21 and the second PTC layer 41 can both be PTC polymer layers. The PTC polymer layer includes a polymer base material and a conductive filler dispersed in the polymer base material. The polymer substrate may be made from a polymer composition containing a non-grafted olefin-based polymer. In certain embodiments of the invention, the non-grafted olefin-based polymer is High Density Polyethylene (HDPE). In certain embodiments of the present invention, the polymer composition further comprises a grafted olefin-based polymer. In certain embodiments of the present invention, the grafted olefin-based polymer is an olefin-based polymer grafted with a carboxylic acid anhydride. The conductive filler suitable for use in the present invention is selected from carbon black (carbon black) powder, metal powder, conductive ceramic powder, or a combination thereof, but is not limited thereto.

The piezoresistor 3 can include a piezoresistor layer 31, a fifth electrode layer 32, and a sixth electrode layer 33. The piezoresistor layer 31 has two opposite surfaces 311, and the fifth electrode layer 32 and the sixth electrode layer 33 are respectively disposed on the two opposite surfaces 311 of the piezoresistor layer 31. The second conductive lead 5 can be connected to the fifth electrode layer 32 or the sixth electrode layer 33 of the piezoresistor 3. In some embodiments of the present invention, the varistor layer 31 is made of a metal oxide material.

In this embodiment, the fifth electrode layer 32 is connected to the second electrode layer 23 of the first PTC element 2. The second conductive lead 6 is connected and disposed between the sixth electrode layer 33 of the varistor 3 and the third electrode layer 42 of the second PTC element 4.

The piezoresistor 3 can have a third hole 310 formed in the piezoresistor layer 31. In this particular embodiment, the varistor layer 31 of the varistor 3 has a periphery 312, the periphery 312 defining the boundary of the varistor layer 31 and interconnecting the two opposite surfaces 311 of the varistor layer 31. The third hole 310 is spaced from the perimeter 312 of the varistor layer 31.

In some embodiments of the present invention, the third hole 310 extends through at least one of two opposite surfaces 311 of the varistor layer 31. In some embodiments of the present invention, the third hole 310 further penetrates at least one of the fifth electrode layer 32 and the sixth electrode layer 33. In the present embodiment, the third hole 310 penetrates through two opposite surfaces 311 of the piezoresistor layer 31, the fifth electrode layer 32 and the sixth electrode layer 33 to form a through hole.

The first conductive lead 5 may have a first connection portion 51 and a first free portion 52, the second conductive lead 6 may have a second connection portion 61 and a second free portion 62, and the third conductive lead 7 may have a third connection portion 71 and a third free portion 72.

In this embodiment, the first connection portion 51 of the first conductive lead 5 is connected to the outer surface of the first electrode layer 22 of the first PTC device 2 by solder, and the first free portion 52 of the first conductive lead 5 extends out of the first electrode layer 22 from the first connection portion 51 for being inserted into a pin hole (not shown) of a circuit board or a circuit device.

The second connection portion 61 of the second conductive lead 6 is connected by solder and disposed between the sixth electrode layer 33 and the third electrode layer 42, and the second free portion 62 of the second conductive lead 6 extends from the second connection portion 61 to the sixth electrode layer 33 and the third electrode layer 42 for being inserted into a pin hole (not shown) of a circuit board or a circuit device.

The third connecting portion 71 of the third conductive lead 7 is connected to the outer surface of the fourth electrode layer 43 of the second PTC device 4 by solder, and the third free portion 72 of the third conductive lead 7 extends out of the fourth electrode layer 43 from the third connecting portion 71 for inserting into a pin hole (not shown) of a circuit board or a circuit device.

Referring to fig. 4 and 5, a second embodiment of the composite circuit protection device of the present invention is similar to the first embodiment, and the difference is that the second embodiment further includes an encapsulant 8, and the encapsulant 8 encapsulates the first PTC device 2, the varistor 3, the second PTC device 4, a portion of the first conductive lead 5, a portion of the second conductive lead 6, and a portion of the third conductive lead 7. The first free portion 52 of the first conductive lead 5, the second free portion 62 of the second conductive lead 6, and the third free portion 72 of the third conductive lead 7 are exposed outside the encapsulant 8. In some embodiments of the present invention, the encapsulant 8 is made of epoxy resin.

Referring to fig. 6, a third embodiment of the composite circuit protection device of the present invention is similar to the second embodiment, except that the third embodiment further comprises a third PTC device 9 (or another varistor 9) connected to the third conductive lead 7. The third PTC element 9 (or the further piezoresistor 9) comprises a third PTC layer 91 (or a further piezoresistor layer 91), the third PTC layer 91 (or the further piezoresistor layer 91) having two opposite surfaces 911, a seventh electrode layer 92 and an eighth electrode layer 93, the seventh electrode layer 92 and the eighth electrode layer 93 being respectively disposed at the two opposite surfaces 911. The third conductive lead 7 is connected to and disposed between the fourth electrode layer 43 and the seventh electrode layer 92. The encapsulant 8 also encapsulates the third PTC layer 91 (or the further varistor layer 91). The third PTC layer 91 (or the another piezoresistor layer 91) may be formed with a fourth hole (not shown).

Referring to fig. 7 and 8, a fourth embodiment of the composite circuit protection device of the present invention is similar to the third embodiment, and the difference is that the fourth embodiment further includes a fourth conductive lead 10, the fourth conductive lead 10 is connected to the eighth electrode layer 93, and the fourth conductive lead 10 has a fourth connection portion 101 and a fourth free portion 102. The fourth connecting portion 101 of the fourth conductive lead 10 is connected to the outer surface of the eighth electrode layer 93, and the fourth free portion 102 of the fourth conductive lead 10 extends out of the eighth electrode layer 93 from the fourth connecting portion 101 for being inserted into a pin hole (not shown) of a circuit board or a circuit device. In addition, the packaging material 8 packages the first PTC element 2, the varistor 3, the second PTC element 4, the third PTC element 9 (or the another varistor 9), part of the first conductive lead 5, part of the second conductive lead 6, part of the third conductive lead 7, and part of the fourth conductive lead 10. The first free portion 52 of the first conductive lead 5, the second free portion 62 of the second conductive lead 6, the third free portion 72 of the third conductive lead 7, and the fourth free portion 102 of the fourth conductive lead 10 are exposed outside the encapsulant 8.

The invention will be further described in the following examples, but it should be understood that these examples are for illustrative purposes only and are not to be construed as limiting the practice of the invention.

Examples

< example 1(E1) >

22g of high-density polyethylene (HDPE) (available from Taiwan plastics industry Co., Ltd., product No. HDPE9002) as a non-grafted olefin-based polymer, 22g of maleic anhydride-grafted HDPE (available from DuPont, product No. MB100D) as an olefin-based polymer grafted with carboxylic anhydride, and 56g of carbon black powder (available from Columbian Chemicals, product No. Raven 430UB) as a conductive filler.

The above three ingredients were mixed in a mixer (Brander), and the ingredients were mixed at a temperature of 200 ℃ and a stirring speed of 30rpm for 10min to obtain a first ingredient mixture.

Further, 21g of HDPE grafted with maleic anhydride, 58g of carbon black powder were mixed and compounded under the same conditions as described above to obtain a second compounded mixture.

Respectively placing the obtained first mixture and second mixture in a mold, and hot pressing at 200 deg.C and 80kg/cm²Is hot pressed for 4min to form a first PTC polymer layer sheet and a second PTC polymer layer sheet, respectively. After the two sheets were removed from the mold, the first PTC polymer layer sheet was placed between two copper foils (as the first electrode layer and the second electrode layer, respectively), and the second PTC polymer layer sheet was placed between two copper foils (as the third electrode layer and the fourth electrode layer, respectively), at 200 ℃ and 80kg/cm²And hot-pressing for 4min to form a first PPTC element and a second PPTC element with the thickness of 0.42mm respectively. After the first PPTC element was cut into a plurality of circular chips (chip, hereinafter PPTC-1) having a diameter of 6.4mm and the second PPTC element was cut into a plurality of chips (chip, hereinafter PPTC-2) having a diameter of 9.5mm × 11.5mm, each chip was irradiated with Co-60 γ -ray at a total dose of 150 kGy.

A second conductive lead is soldered to one side of a metal oxide varistor (MOV, available from Ceramate Technical, model number: 07D270K), one of the copper foils of PPTC-1 and one of the copper foils of PPTC-2 are soldered to the side of the MOV to which the second conductive lead is soldered and to the opposite side of the non-soldered second conductive lead (i.e., the MOV is sandwiched between PPTC-1 and PPTC-2), the first conductive lead is soldered to the copper foil of PPTC-1 opposite the MOV, and a third conductive lead is soldered to one of the copper foils of E1 to form the composite circuit protection device of E1.

The holding current (hold current, i.e., maximum current value in normal operation), the trip current (trip current, i.e., minimum current value required for the PPTC element to reach a high resistance state), the rated voltage (i.e., voltage applied when the PPTC element is operated), and the withstand voltage (i.e., maximum voltage that does not cause failure or damage to the PPTC element) were measured for each of the PPTC-1 and PPTC-2 according to the safety standard UL 1434, 1998 for thermistor-type devices (thermal-type devices) by Underwriter Laboratories. In addition, the voltage-dependent voltage (i.e., the voltage at which the MOV is triggered to operate) and the clamping voltage (i.e., the maximum voltage at which the MOV can provide a limit) of the MOV element are measured according to the safety standards UL 1449, 2014 of Underwriter Laboratories for transient voltage surge suppressors (transient voltage supply suppressors). Property measurements of PPTC-1, PPTC-2, and MOV are shown in Table 1, respectively.

TABLE 1

a: measured at 1 mA.

b: in the pulse waveform (t)_p)8/20 μ s and pulse current (I)_p) Measured under 2.5A.

< examples 2 to 8(E2-E8) >

The process conditions for the composite circuit protection device of E2-E8 are similar to those of E1, except that PPTC-1 is formed with first through holes and/or PPTC-2 is formed with second through holes and/or MOV is formed with third through holes (as shown in Table 2), and each of the first through holes, the second through holes and the third through holes has a circular cross section (diameter is 1.5mm, and circular area is 1.77 mm)²) The aperture of (a) is defined by the wall.

Specifically, in E2, after gamma irradiation, a first perforation was drilled in the central portion of PPTC-1. In E3, a third through hole was drilled in the central portion of the MOV before soldering to PPTC-1 and PPTC-2. In E4, a first through hole was drilled in the central portion of PPTC-1 and a third through hole was drilled in the central portion of the MOV. In E5, a second perforation was drilled in the central portion of PPTC-2 after gamma irradiation. In E6, a first perforation was drilled in the central portion of PPTC-1 and a second perforation was drilled in the central portion of PPTC-2. In E7, a third through hole was drilled in the central portion of the MOV and a second through hole was drilled in the central portion of PPTC-2. In E8, a first through hole was drilled in the central portion of PPTC-1 and a third through hole was drilled in the central portion of MOV and a second through hole was drilled in the central portion of PPTC-2 (as shown in figure 3).

< comparative examples 1 to 2(CE1-CE2) >

The process conditions for the circuit protection devices of CE1 and CE2 were similar to those of E1 and E2, respectively, with the difference that CE1 and CE2 contained no MOV and PPTC-2, and the first and second conductive leads were soldered to the two copper foils of PPTC-1, respectively.

< comparative examples 3 to 4(CE3-CE4) >

The process conditions for the circuit protection devices of CE3 and CE4 are similar to E1 and E3, respectively, with the difference that no PPTC-1 and PPTC-2 are present in CE3 and CE4, and the first and second conductive leads are soldered to opposite surfaces of the MOV, respectively.

< comparative examples 5 to 6(CE5-CE6) >

The process conditions for the circuit protection devices of CE5 and CE6 were similar to those of E1 and E5, respectively, with the difference that CE5 and CE6 did not contain PPTC-1 and MOV, and the first and second conductive leads were soldered to the two pieces of copper foil of PPTC-2, respectively.

< comparative examples 7 to 10(CE7-CE10) >

The process conditions for the composite circuit protection device of CE7-CE10 are similar to E1, E5, E3, and E7, respectively, with the difference that no PPTC-1 is present in CE7-CE10, and the first and second conductive leads are soldered to opposite surfaces of the MOV, and the third conductive lead is soldered to one of the copper foils of PPTC-2.

The overall structure of the (hybrid) circuit protection devices of E1-E8 and CE1-CE10 is shown in Table 2.

TABLE 2

"- -" indicates the absence of such an element.

Performance testing

[ Hold Current test ]

10 test samples were taken for each of the (composite) circuit protection devices of E1-E8 and CE1-CE10, and a holding current test was performed to determine the maximum holding current of the test samples.

The holding current test is carried out at 25 ℃ under 16V_dcWhile remaining untripped (trip), measurements were made for 15 minutes for each test sample. The test results are shown in Table 3, respectively.

[ trip Time test (Time-to-trip test) ]

10 of each of the (combined) circuit protection devices of E1-E8 and CE1-CE10 were taken as test samples, and trip time tests were performed to determine trip times of the test samples.

The trip time test is carried out at 25 ℃ and 16V_dcThe trip time of each test sample was measured with the dc voltage of (1) and the trip current of (8.5A). The test results are shown in Table 3, respectively.

TABLE 3

"N/A" means not applicable.

The results in Table 3 show that the test samples from E1-E8 were at 16V_dcThe average maximum holding current at (B) was between 6.0A and 6.5A, higher than that of test samples of CE1-CE2 and CE5-CE 10.

[ Surge impact immunity test ]

10 test samples were taken for each of the compound circuit protection devices of E1-E8 and CE1-CE10, and a surge-impact immunity test was performed.

The surge impact immunity test is carried out at a constant voltage (38V)_dcAnd 44V_dcVoltage-dependent voltage greater than MOV) and constant current (0.5A and 10A) were turned on for 60 seconds before turning off the first and second conductive leads. If neither the PPTC die nor the MOV burns out or is damaged, the test specimen passes the surge immunity test and the average value of the time that the PPTC die trips (if any) is recorded. If a PPTC chip or MOV burns out, the test sample is burnt out and the average of the time it takes for burning out to occur is recorded. The results are shown in Table 4, respectively.

TABLE 4

Table 4 results show that test samples of CE3-CE4 containing MOVs alone burn out within 5s at currents of 0.5A and voltages of at least 1.4 times the voltage-dependent voltage of the MOV (generally MOVs can withstand 1.2 times their voltage-dependent voltage), or within 2.5s at over-currents and over-voltages of 10A, and the damage cannot be repaired. The test specimens of CE1-CE2 containing only PPTC-1 and of CE5-CE6 containing only PPTC-2 were burned at an overcurrent of 10A. Whereas test samples of CE7-CE10 containing MOV and PPTC-2 also burned under overvoltage.

In contrast, all test specimens of E1-E8 containing combinations of PPTC-1, MOV, and PPTC-2 (where PPTC-1 is rated at approximately 111% of the voltage to which the MOV is subjected at 1 mA) passed the surge-impact immunity test without burning. In addition, the PPTC die and/or MOV of E2-E8, compared to E1, formed with perforations, increased heat transfer, further reducing the time to trip the PPTC die and preventing overcurrent from flowing through the MOV, thus protecting the MOV from burning. In other words, in the test samples of E1-E8, the PPTC die was exposed to an overcurrent and a voltage greater than the voltage-sensitive voltage of the MOV to trip before the MOV burns out.

In summary, since the PTC device can be rapidly tripped to a high resistance state in the presence of overcurrent and overvoltage, the present invention can protect the varistor from being burned out by overcurrent by connecting the varistor to two PTC devices, and thus the composite type circuit protection device of the present invention can be repeatedly used without damage to exhibit excellent durability and reliability, thereby achieving the object of the present invention.

The above description is only an example of the present invention, and the scope of the present invention should not be limited thereby, and the invention is still within the scope of the present invention by simple equivalent changes and modifications made according to the claims and the contents of the specification.

Claims

1. A kind of hybrid circuit protection device, characterized by: which comprises the following steps:

a first PTC element comprising:

a first PTC layer having two opposite surfaces, and

a first electrode layer and a second electrode layer respectively arranged on two opposite surfaces of the first PTC layer;

a second PTC element comprising:

a second PTC layer having two opposite surfaces, and

a third electrode layer and a fourth electrode layer respectively arranged on two opposite surfaces of the second PTC layer;

a varistor connected to the second electrode layer of the first PTC element and the third electrode layer of the second PTC element;

a first conductive lead connected to the first electrode layer of the first PTC element;

a second conductive lead connected to the piezoresistor; and

and a third conductive lead connected to the fourth electrode layer of the second PTC element.

2. The composite circuit protection device of claim 1, wherein: the first PTC element has a rated voltage between 40% and 200% of the varistor voltage measured at 1 mA.

3. The composite circuit protection device of claim 2, wherein: the first PTC element has a rated voltage between 110% and 200% of the varistor voltage measured at 1 mA.

4. The composite circuit protection device of claim 1, wherein: the first PTC element or the second PTC element is at an overcurrent and a voltage larger than the varistor voltage of the varistor to trip before the varistor burns out.

5. The composite circuit protection device of claim 1, wherein: the first PTC element or the second PTC element is in over-current and voltage larger than the voltage-sensitive voltage of the voltage-sensitive resistor and trips within 10 mu s to 10 s.

6. The composite circuit protection device of claim 1, wherein: the first PTC element or the second PTC element trips within 1ms to 10s at an overcurrent of not less than 0.5A and a voltage greater than the varistor voltage of the varistor.

7. The composite circuit protection device of claim 1, wherein: the first PTC element or the second PTC element trips within 1ms to 1s at an overcurrent of not less than 10A and a voltage greater than the varistor voltage of the varistor.

8. The composite circuit protection device of claim 1, wherein: the first PTC element has a first hole formed in the first PTC layer.

9. The composite circuit protection device of claim 8, wherein: the first PTC layer of the first PTC element has a periphery defining a boundary of the first PTC layer and interconnecting two opposing surfaces of the first PTC layer, and the first hole is spaced apart from the periphery of the first PTC layer.

10. The composite circuit protection device of claim 8, wherein: the first hole penetrates through at least one of two opposite surfaces of the first PTC layer.

11. The composite circuit protection device of claim 10, wherein: the first hole also penetrates through at least one of the first electrode layer and the second electrode layer.

12. The composite circuit protection device of claim 8, wherein: the second PTC element has a second hole formed in the second PTC layer.

13. The composite circuit protection device of claim 12, wherein: the second PTC layer of the second PTC element has a periphery defining a boundary of the second PTC layer and interconnecting two opposing surfaces of the second PTC layer, and the second hole is spaced apart from the periphery of the second PTC layer.

14. The composite circuit protection device of claim 12, wherein: the second hole penetrates through at least one of two opposite surfaces of the second PTC layer.

15. The composite circuit protection device of claim 14, wherein: the second hole also penetrates through at least one of the third electrode layer and the fourth electrode layer.

16. The composite circuit protection device of claim 1, wherein: the varistor includes:

a varistor layer having two opposing surfaces;

a fifth electrode layer disposed on one of two opposite surfaces of the varistor layer and connected to the second electrode layer of the first PTC element; and

a sixth electrode layer disposed on the other of the two opposite surfaces of the piezoresistor layer,

wherein the second conductive lead is connected to the fifth electrode layer or the sixth electrode layer of the piezoresistor.

17. The composite circuit protection device of claim 16, wherein: the piezoresistor has a third hole formed in the piezoresistor layer.

18. The composite circuit protection device of claim 17, wherein: the piezoresistor layer of the piezoresistor has a periphery defining a boundary of the piezoresistor layer and interconnecting two opposing surfaces of the piezoresistor layer, and the third hole is spaced apart from the periphery of the piezoresistor layer.

19. The composite circuit protection device of claim 18, wherein: the third via extends through at least one of two opposing surfaces of the varistor layer.

20. The composite circuit protection device of claim 19, wherein: the third hole also penetrates through at least one of the fifth electrode layer and the sixth electrode layer.

21. The composite circuit protection device of claim 1, wherein: the first PTC element and the second PTC element are both polymer PTC elements, and the first PTC layer and the second PTC layer are both PTC polymer layers.

22. The composite circuit protection device of claim 1, wherein: the packaging material is used for packaging the first PTC element, the piezoresistor, the second PTC element, part of the first conductive lead, part of the second conductive lead and part of the third conductive lead.

23. The composite circuit protection device of claim 1, wherein: a third PTC element or another varistor is also included and connected to the third electrically conductive lead.

24. The composite circuit protection device of claim 23, wherein: and a fourth conductive lead connected to a surface of the third PTC element or the another varistor opposite the third conductive lead.