TWI791691B - Communication system, communication device, application processor and network address translation method of communication system - Google Patents

Abstract

A communication system configured to perform an address translation and a method of translating an address of the communication system are provided. The communication system configured to transceive a packet through a network includes a modem circuit configured to modulate the packet into a transmission signal to be transmitted to the network and demodulate a receiving signal from the network into the packet, and an address translation circuit configured to translate a network address of the packet, wherein the address translation circuit includes an embedded memory configured to receive a header of the packet from an external memory in which the packet is stored and store the header, a first translator configured to translate a format of the header, and a second translator configured to translate an address included in the header.

Description

Communication system, communication device, application processor and communication system traditional network address translation method [CROSS-REFERENCE TO RELATED APPLICATIONS]

This U.S. non-provisional application asserts Korean Patent Application No. 10-2017-0159685 filed with the Korean Intellectual Property Office (KIPO) on November 27, 2017 and filed on October 10, 2018 The benefit of priority of Korean Patent Application No. 10-2018-0120606 filed with the Korean Intellectual Property Office, the disclosures of both of which are incorporated herein by reference in their entirety.

Various exemplary embodiments of the inventive concept are related to a communication system, and more particularly, to a hardware structure of a communication system configured to perform network address translation for data communication, a communication device, A method of translating network addresses and/or its non-transitory computer-readable medium.

A communication device or communication system used for data communication can utilize network address forwarding Switching technology communicates with network or communication devices with different address systems. The network address translation technology may include a customer-side translator (CLAT) and a network address translation (NAT). The client converter can be a technology for converting an IPv4 address to an IPv6 address or converting an IPv6 address to an IPv4 address so that the host can freely communicate with the IPv4 host or the IPv6 host via the IPv6 network. Network address translation may refer to sending and receiving network traffic by a router or equivalent networking device, and rewriting by the router the port number of the transport protocol of the Internet protocol (IP) packet and the source Internet protocol (IP) IP) address and destination IP address technology. When performing NAT, since the IP packet is changed, the checksum of the IP header or the IP header must be updated.

Various exemplary embodiments of inventive concepts provide a communication system configured to efficiently perform address translation, a communication device, an address translation method of a communication system, and/or a non-transitory computer readable medium thereof.

According to an aspect of at least one example embodiment of the inventive concept, there is provided a communication system configured to transmit and receive at least one packet via a network. The communication system includes modem circuitry configured to modulate the at least one packet into a transmission signal for transmission to the network, and demodulate a signal received from the network into the at least one packet; and an address translation circuit configured to translate the network address of the at least one packet, converting the network address of the at least one packet includes: from an external memory in which the at least one packet is stored The body receives the header of the at least one packet, stores the header of the at least one packet in an embedded memory, converts the format of the header of the at least one packet, and converts the at least one packet An address included in the header of a packet.

According to another aspect of at least one exemplary embodiment of the inventive concept, there is provided a communication device comprising: a memory; a communication processor configured to convert a network bit of a first packet received via a network address, and storing a second packet including the converted network address in the memory; and an application processor configured to receive the second packet from the memory, drive an application program, And process the second packet.

According to another aspect of at least one exemplary embodiment of the inventive concept, there is provided an application processor including a communication function. The application processor includes: at least one processor configured to execute an application program; memory configured to be accessed by the at least one processor; and address translation circuitry configured to translate converting a network address included in a first header of at least one packet into an address system conforming to the application, and storing a second header including the converted network address in the memory body.

According to another aspect of at least one exemplary embodiment of the inventive concept, a network address translation method of a communication system is provided. The method includes storing, by at least one processor, a first Internet Protocol (IP) packet received via a network in a first memory, the first IP packet including a header and network bits address; using the at least one processor to copy the header of the first IP packet stored in the first memory to the at least one processor using the at least one processor to convert the network address included in the first IP packet; and storing a second IP packet using the at least one processor , the second IP packet includes the header and the converted IP address.

10, 10a: communication device

11: First filter

12: IP Converter

13: First IP header checksum calculator

20: Network

21: Second filter

22: Address converter

23: IP header check and calculator

24:TCP header checksum calculator

30: Electronic device

31: IP header check and calculator

32:TCP Header Checksum Calculator

40:Server

50: Other electronic devices

60: LAN

100: communication processor/shared processor

100a: communication processor

110: Processor

120, 120a: address conversion circuit

121, 121a: first converter

122, 122a: second converter

123: local memory

123a: Header check and calculator

130: Random Access Memory (RAM)

140: DMA controller

150: modem

160: memory interface

170: busbar

200, 200a: application processor

201: Operating system (OS)

202, 202a: Applications

203, 203a: drive

204a: Header Converter

210: central processing unit (CPU)

220: random access memory (RAM)

230: DMA controller

240: modem

245: Radio frequency (RF) chip

250: Address conversion circuit

260: memory controller

270: busbar

300: Memory

310, 310a: first memory

320, 320a: second memory

330, 330a: the third memory

400: input/output (I/O) components

500:DMA controller

600: busbar

AP: application processor

AR1: Area 1

AR2: Second Area

AR3: the third area

CP: communication processor

D, D': Destination IP address

DT: data

H1: IP header

H1_IPv4: IPv4 header

H1_IPv6: IPv6 header

H2: TCP header

H2_TCP: TCP header

HD: header

HD0, HD1, HDN-1, HDs: header

IHL: IP Header Length

NHD: header

NHD0, NHD1, NHDN-1, NHDs: Changed headers

NPK0, NPK1, NPKN-1: IP packet

PK: IP packet

PK0, PK1, PKN-1, PK0a, PK1a, PKN-1a: IP packets

PL: Payload

PL0, PL1, PLN-1, PLs: payload

S, S': source IP address

S11, S12, S13, S14, S15: Operation

S21, S22, S23, S24, S25, S26, S27: Operation

S110, S120, S130, S140, S150: Operation

S210, S220, S230, S240, S250: Operation

TT: Transition table

ToS: type of service

PRA: private IP address

PUA: Public IP address

Various exemplary embodiments of the inventive concepts will be more clearly understood from the following detailed description when read in conjunction with the accompanying drawing figures.

FIG. 1 is a block diagram of a communication device according to at least one example embodiment.

FIG. 2 is a diagram illustrating an operation of an address conversion circuit according to at least one example embodiment.

3 is a diagram of a structure of an Internet Protocol (IP) packet, according to at least one example embodiment.

4A and 4B illustrate an IP header of an IP packet, according to some example embodiments.

FIG. 5 illustrates a transmission control protocol (TCP) header of an IP packet, according to at least one example embodiment.

6A is a block diagram of an implementation example of a first translator of an address translation circuit in accordance with at least one example embodiment.

FIG. 6B is a flowchart of a method of operating the first converter of FIG. 6A , according to at least one example embodiment.

7A is a block diagram of an implementation example of a second translator of an address translation circuit in accordance with at least one example embodiment.

FIG. 7B is a flowchart of a method of operating the second converter of FIG. 7A , according to at least one example embodiment.

FIG. 8 illustrates a conversion table according to at least one exemplary embodiment.

9A and 9B are diagrams illustrating a method of converting an IP address of a second translator, according to at least one exemplary embodiment.

FIG. 10 is a block diagram of an address translation circuit according to at least one example embodiment.

Figure 11 is a block diagram of a communications processor, according to at least one example embodiment.

FIG. 12 is a block diagram of a communication device according to at least one example embodiment.

FIG. 13A illustrates the movement of IP packets in a communication device according to at least one example embodiment.

FIG. 13B illustrates movement of IP packets in a communication device according to at least one example embodiment.

FIG. 14 is a block diagram of an application processor according to at least one example embodiment.

FIG. 1 is a block diagram of a communication device 10 according to at least one example embodiment.

Referring to FIG. 1 , the communication device 10 may be an electronic device configured to perform data communication with at least one other electronic device. For example, the communication device 10 can be a smart phone, a tablet personal computer (PC), a laptop, a drone, a digital camera, a wearable computer, an Internet of Things (IoT) device, Vehicle driving device, virtual reality device, augmented reality device device and/or one of various other smart devices. In addition, the communication device 10 may be one of various electronic devices configured to perform data communication with external electronic devices via a wired/wireless network.

Referring to FIG. 1 , the communication device 10 may include a communication processor (communication processor, CP) 100, an application processor (application processor, AP) 200 and/or a memory 300, but is not limited thereto. In addition, the communication device 10 may further include other hardware and/or software components, such as a display module and/or an input/output (I/O) module.

The application processor 200 can drive (for example, execute) an operating system (operating system, OS) 201 and/or various application programs 202 of the communication device 10 to control multiple hardware and/or software components connected to the application processor 200 , and process and calculate various data including multimedia data. In at least one exemplary embodiment, the application processor 200 may be implemented by a system-on-chip (SoC), FPGA, multi-core processor, multi-processor system, and the like.

The communication processor 100 can transceive (eg, transmit and/or receive) data during communication with other electronic devices connected via a network. During the process of sending and receiving data, the communication processor 100 can transmit data to the application processor 200 and receive data from the application processor 200 . When the communication device 10 receives data via the network, for example, when the communication device 10 performs a data download operation, the communication processor 100 can transmit the received data to the application processor 200, and the application processor 200 can perform data processing operations, Such as data calculation and storage operations. On the contrary, when the communication device 10 transmits data via the network, for example, when the communication device 10 performs a data upload operation, the application processor The 200 can transmit the data to be uploaded to the communication processor 100, and the communication processor 100 can then transmit the data via the network. For example, when the communication device 10 performs a video streaming operation, the communication processor 100 can transmit the received data to the application processor 200, and the application processor 200 can process the data received from the communication processor 100 and display it on the screen The processed data is displayed on the screen. According to at least one exemplary embodiment, the communication processor 100 and the application processor 200 may be implemented by a single processor. In addition, according to some exemplary embodiments, the communication processor 100 and/or the application processor 200 may be implemented by two or more processors.

The memory 300 can store instructions or data received from the application processor 200 and/or the communication processor 100 or generated by the application processor 200, but is not limited thereto. The memory 300 can be implemented by volatile memory such as dynamic random access memory (DRAM), static random access memory (SRAM) and the like. However, exemplary embodiments of the inventive concept are not limited thereto, and the memory 300 may include non-volatile memory such as flash memory, magnetic random access memory (magnetic RAM, MRAM), ferroelectric random access memory Memory (ferroelectric RAM, FeRAM), phase-change random access memory (phase-change RAM, PRAM) and/or resistive random access memory (resistive RAM, ReRAM), etc. The memory 300 may refer to a memory chip included in the communication device 10 or a memory module including a plurality of memory chips and/or memory devices.

As described above, since data is frequently transmitted and received between the communication processor 100 and the application processor 200, the memory 300 can be used as a communication-processable The shared memory accessed by the processor 100 and the application processor 200 operates. The communication processor 100 and the application processor 200 can transmit and receive data through the memory 300 .

In at least one exemplary embodiment, the memory 300 may include a first area AR1, a second area AR2, and a third area AR3, etc., but is not limited thereto, and in other exemplary embodiments, may have a larger number or fewer zones. In at least one exemplary embodiment, the first area AR1 , the second area AR2 and the third area AR3 may be areas that can be physically and/or logically separated from each other in the memory chip and/or the memory module. In at least one exemplary embodiment, the first area AR1 , the second area AR2 and the third area AR3 may be memory devices that can be physically distinguished from each other in the communication device 10 .

According to at least one exemplary embodiment, the first area AR1 may be a dedicated area of the communication processor 100 which is exclusively used by the communication processor 100 . The second area AR2 can be shared between the communication processor 100 and the application processor 200 . For example, the second area AR2 may be a shared area for inter-processor communication (IPC) between the communication processor 100 and the application processor 200 . The third area AR3 may be a dedicated area of the application processor 200 which is exclusively used by the application processor 200 . However, exemplary embodiments are not limited thereto, and various regions of the memory 300 may be arranged in other configurations/relationships.

Meanwhile, in the communication device 10 according to at least one example embodiment, the communication processor 100 may include an address conversion circuit 120 . The address conversion circuit 120 can be implemented by hardware circuitry or a combination of hardware circuitry and software. The address conversion circuit 120 can determine whether it is desired and/or necessary to convert the network address of the data sent and received via the network. road address. If it is determined that it is desired and/or necessary to convert the network address of the data, the address conversion circuit 120 may convert the network address of the data based on the network address conversion technology.

Data may be transmitted and/or received as a type of Internet Protocol (IP) packet, and address translation circuitry 120 may translate the network address of the IP packet (e.g., may convert the and/or or the network address associated with the IP packet, etc.). The address translation circuit 120 can convert the destination address of the IP packet received via the network into an address suitable for the address system of the application program 202 and/or convert the source address of the IP packet to be transmitted via the network into The address of the addressing system applicable to the network.

In at least one exemplary embodiment, the address translation circuit 120 may support both client-side translation (CLAT) and network address translation (NAT), which are network address translation techniques. The client converter can be used to convert the IPv4 header of the IP packet into the IPv6 header of the IP packet and/or convert the IPv6 header into the IP header format conversion technology of the IPv4 header, so that the communication device 10 can pass A network based on a specific Internet protocol (for example, IPv6 or IPv4, etc.) can freely communicate with other communication devices. Network address translation may be used to convert private IP addresses (and/or internal IP addresses associated with private networks, LANs, intranets, etc.) to public IP addresses (and/or Global IP address, such as an IP address that can be accessed across the Internet by the Internet, etc.) or conversely, an IP address conversion technology that converts a public IP address into a private IP address. The IP address value and port number of the source address and/or destination address can be changed according to NAT.

For example, address translation circuitry 120 may write (and/or copy) IP packets with translated network addresses (eg, destination addresses, etc.) to memory The second zone AR2 of 300, but not limited to that. The application processor 200 can access the second area AR2 of the memory 300 and process the IP packet based on the converted network address. During the operation of processing the IP packet of the application processor 200, the IP packet may be copied to the third area AR3 of the memory 300, but not limited thereto.

In addition, according to some exemplary embodiments, when the application processor 200 provides an IP packet, the IP packet may be stored in the second area AR2 of the memory 300, and the address translation circuit 120 may be transferred from the second area AR2 of the memory 300. Area 2 AR2 reads the IP packet and converts the network address of the IP packet. The IP packet with the converted network address can be stored in the dedicated memory of the communication processor 100 (eg, the first area AR1 of the memory 300 ), but is not limited thereto.

As mentioned above, when the communication processor 100 transmits IP packets to the application processor 200 and/or receives IP packets from the application processor 200, since the hardware-based address translation circuit 120 performs network address translation, the application The processor 200 may not need to perform additional operations for NAT. Therefore, the load of the application processor 200 can be reduced, and the times of writing (and/or copying) the IP packet to the memory 300 or reading the IP packet from the memory 300 can be reduced.

FIG. 2 is a diagram illustrating the operation of the address conversion circuit 120 according to at least one example embodiment. Assume that the IP packet is received from the network, that is, the address translation circuit 120 is the receiving path.

Referring to FIG. 2 , the address conversion circuit 120 may include a first converter 121 , a second converter 122 and/or a local memory 123 , but is not limited thereto.

IP packets transmitted and received over the network can include headers and payloads (payload) etc. For example, the first IP packet PK0 may include a first header HD0 and a first payload PL0. The header may include a network address (hereinafter referred to as IP address) and control information, and the payload may include data.

The IP packets PK0 to PKN-1 received via the network can be stored in the first memory 310, wherein N is a natural number. For example, the first memory 310 can be the first area AR1 of the memory 300 shown in FIG. 1 , that is, the dedicated area of the communication processor 100 and the like.

The headers HDs of the IP packets PK1 to PKN-1 stored in the first memory 310 can be read, and the read headers HDs can be stored in the local memory 123 . In at least one exemplary embodiment, the address translation circuit 120 can read the header from the first memory 310 based on the address and length information of the header HDs, for example, in a direct memory access (DMA) manner. HDs, and store the header HDs in the local memory 123, the address and length information is obtained based on the descriptor information indicating where the IP packets PK0 to PKN-1 are stored in the first memory 310 .

The local memory 123 can be implemented by SRAM or register. However, exemplary embodiments of the inventive concepts are not limited thereto, and the local memory 123 may be implemented by various memories. The local memory 123 can also be called a local buffer. Although FIG. 2 illustrates an example in which the local memory 123 is included in the address conversion circuit 120, exemplary embodiments of inventive concepts are not limited thereto. In another exemplary embodiment, the local memory 123 can be an embedded memory of the communication processor (refer to 100 in FIG. 1 ), and can also be provided separately from the address conversion circuit 120. Memory.

The first converter 121 and the second converter 122 can access the local memory 123 and convert the IP addresses of the headers HD0 to HDN-1 stored in the local memory 123 . The first converter 121 can function as a pre-processor, and the second converter 122 can function as a post-processor. The first converter 121 may operate before the second converter 122, and the second converter 122 may operate after the operation of the first converter 121 is completed.

The first converter 121 can change (and/or convert, generate a new header, etc.) the header format of the IP packet and change the IP version of the IP packet. The first converter 121 can read the headers HD0 to HDN-1 from the local memory 123 and determine, for example, whether it is desired and/or necessary to change the IP version of each of the headers HD0 to HDN-1. When it is desired and/or necessary to change the IP version, the first converter 121 can convert the header to another IP version (eg, another IP protocol version, such as IPv4, IPv6, etc.), for example, by changing the format of the header to another IP version. The formats of the headers HD0 to HDN-1 are converted into formats, and the IP version is changed to another IP version. The header may include various fields (eg, a plurality of fields), and when changing the format of the header, the first converter 121 may change at least some of the fields of the header.

In at least one exemplary embodiment, the first converter 121 can support the CLAT function and convert the Internet protocol version 4 (Internet protocol version 4, IPv4) header format included in the header of the IP packet into an Internet Internet protocol version 6 (Internet protocol version 6, IPv6) header format and/or convert the IPv6 header format into the IPv4 header format. Changed headers can be stored again in the local domain memory 123. For example, when the network supports the IPv6 address system and the host (for example, the application program 202 in FIG. 1, etc.) The IPv6 address included in the header of the IP packet is converted into an IPv4 address.

The second translator 122 can perform IP address translation. The second converter 122 can read headers such as HD0 to HDN-1 (or headers changed by the first converter 121) from the local memory 123, and determine whether it is desired and/or necessary to convert the header HD0 to the IP address of each of HDN-1. When it is desired and/or necessary to convert the IP address of each of the headers HD0 to HDN-1, the second converter 122 can change the address value of the transport protocol in the IP address (e.g., indicating the source bit address and/or the value of the destination address) and port number (for example, port number of Transmission Control Protocol (TCP) or User Datagram Protocol (user datagram protocol, UDP) etc.).

In at least one exemplary embodiment, the second translator 122 can support a NAT function and translate the public IP address into the private IP address and/or convert the private IP address into the public IP address. For example, when the communication device 10 performs tethering and/or operates as a router, the second converter 122 can convert the public IP address of the IP packet received via the network into a private IP address. The changed header can be stored in the local memory 123 again.

The headers HD0 to HDN-1 may be changed by changing (e.g. converting, generating new headers, etc.) the IP version of the first converter 121 and/or by changing the IP address value of the second converter 122, And the changed headers (eg, NHD0 to NHDN-1 (or NHDs)) can be stored (and/or copied) in the second memory 320 . raise For example, the second memory 320 may be a shared area between the second area AR2 of the memory 300 shown in FIG. 1 (ie, the shared processor 100 , etc.) and the application processor 200 . In at least one exemplary embodiment, the changed header NHDs can be read from the local memory 123 and stored in the second memory 320 , for example, by DMA. Meanwhile, the payloads of the IP packets PK0 to PKN-1 (eg, PL0 to PLN-1 (or PLs)) can be read from the first memory 310 and stored in the second memory 320 in a DMA manner. Therefore, the IP packets PK0a to PKN-1a with the converted IP addresses can be stored in the second memory 320 . The application processor 200 can access the second memory 320 and process the IP packets PKs (ie, IP packets PK0a to PKN-1a) with translated addresses.

Although at least one exemplary embodiment has been described assuming that the address translation circuit 120 is a receive path, when the address translation circuit 120 is a transmit path, the operations of the first translator 121 and the second translator 122 may be similar to the first translator 120. The above operations of the converter 121 and the second converter 122 . However, when the address conversion circuit 120 is the transmission path, the header of the IP packet stored in the second memory 320 by the application processor 200 can be read from the second memory 320 and stored in the local memory 123 , and the first converter 121 and the second converter 122 can change the IP addresses respectively included in the header. In this case, the second converter 122 can function as a pre-processor. After the operation of the second converter 122 is completed, the first converter 121 can operate as a post-processor. After the IP packet with the converted address is stored in the first memory 310, the IP packet can be transmitted to other devices via the network.

Figure 3 is a structure of an IP packet PK according to at least one exemplary embodiment schema.

Referring to FIG. 3 , according to at least one exemplary embodiment, the IP packet PK may include a header HD and/or a payload PL, etc., but is not limited thereto. The header HD may include an IP header H1 and/or a TCP header H2 (or UDP header, etc.), and the payload PL may include data DT provided to and/or generated by the application. In FIG. 2 , the IP header H1 and the TCP header H2 of the IP packet PK can be stored in the local memory 123 . The first converter 121 can change the IP header H1 to change the IP version, and the IP header H1 and the TCP header H2 can be changed so that the second converter 122 can convert the IP address.

4A and 4B illustrate an IP header of an IP packet, according to some example embodiments. Figure 4A shows the header of an IPv4 packet, and Figure 4B shows the basic header of an IPv6 packet.

Referring to FIG. 4A, the header H1_IPv4 of the IPv4 packet (hereinafter referred to as the IPv4 header) may include a version, an IP header length IHL, a service type ToS, a total length, an identifier, a flag (flag), a segment offset ( fragment offset), time-to-live, protocol, header checksum, source address, destination address, options, and corresponding fields for padding, but not limited to. Each of the source address and the destination address can have a length of 32 bits, but is not limited to, and the length of options and padding can be variable.

With reference to Fig. 4B, the basic header H1_IPv6 (hereinafter referred to as IPv6 header) of IPv6 packet can include for version, traffic category, flow label (flow label), payload length, next header, hop limit (hop limit) , source address, and destination address corresponding fields for , but not limited to. Each of the source and destination addresses can have a length of 128 bits, but are not limited to this.

4A and 4B, the IPv4 header H1_IPv4 may include twelve basic fields and two optional fields, and the IPv6 header H1_IPv6 may include eight basic fields, but not limited thereto. However, in addition to the basic header (ie, the IPv6 header H1_IPv6), the IPv6 packet may further include an extended header. In the IPv6 header H1_IPv6, the next header field may refer to the type of the next header, etc. A header that may be indicated in the next header may be an IPv6 extension header or a TCP (or UDP, etc.) header, which is an upper layer header. When the extension header is not used, the TCP (or UDP, etc.) header can be located in the next header.

The IPv4 header H1_IPv4 and the IPv6 header H1_IPv6 may equally include fields for version, source and destination addresses, and the like. However, as described above, the length (i.e., 128 bits) of each of the source and destination addresses of the IPv6 header H1_IPv6 may be each of the source and destination addresses of the IPv4 header H1_IPv4 four times the length of the previous one (ie, 32 bits).

When converting the IPv4 header H1_IPv4 into the IPv6 header H1_IPv6, the IP header length IHL, identifier, flag, fragment offset, header checksum, options, and fields for filling etc., and may add fields for flow labels. Conversely, when converting the IPv6 header H1_IPv6 to the IPv4 header H1_IPv4, the fields for the flow number can be deleted, and the fields for the IP header length IHL, identifier, flag, fragment offset, header Fields for checksums, options, fills, etc. Fields of IPv4 header H1_IPv4 for Type of Service, Total Length, Protocol, Time To Live and IPv6 header H1_IPv6 for traffic The fields of category, payload length, next header, and hop limit are interchangeable with each other.

The first converter 121 of the address conversion circuit 120 explained with reference to FIG. 2 can convert the IPv4 header H1_IPv4 into the IPv6 header H1_IPv6, or convert the IPv6 header H1_IPv6 into the IPv4 header H1_IPv4.

Figure 5 illustrates a TCP header of an IP packet, according to at least one example embodiment.

Referring to FIG. 5, the TCP header H2_TCP may include a source port, a destination port, a sequence number, an acknowledgment number (acknowledgment number), a data offset, a reserved field "Reserved", a 6-bit flag, Corresponding fields for window size, TCP checksum, urgent pointer, options and/or padding, etc. Similar to the TCP header H2_TCP, the UDP header as the transport protocol may include corresponding fields for source port, destination port, UDP length and/or UDP checksum, and so on.

The second translator 122 of the address translation circuit 120 explained with reference to FIG. 2 can change the source and/or destination address values of the IP headers (for example, the IPv4 header H1_IPv4 or the IPv6 header H1_IPv6) of FIGS. 4A and 4B and Source and/or destination port numbers of the TCP header H2_TCP (or UDP header, etc.) and convert private IP addresses to public IP addresses and/or vice versa site.

FIG. 6A is a block diagram of an implementation example of the first converter 121 of the address conversion circuit 120 according to at least one exemplary embodiment, and FIG. 6B is an operation of the first converter of FIG. 6A according to at least one exemplary embodiment. 121 is a flowchart of the method. A case where the first converter 121 converts the IPv6 header into the IPv4 header will be explained as an example.

Referring to FIG. 6A , the first converter 121 may include a first filter 11 , an IP converter 12 and/or a first IP header checksum calculator 13 and the like. In at least one exemplary embodiment, the first filter 11 of the first converter 121 , the IP converter 12 and/or the IP header checksum calculator 13 may be implemented by hardware logic circuits, but is not limited thereto.

6A and 6B, the first converter 121 can read the header HD stored in the local memory 123 (S110). The first converter 121 can sequentially read the headers HD0 to HDN-1. As described above with reference to FIG. 3 , the header HD may include an IP header H1 and a TCP header H2 . In operation S110 , the first converter 121 may read the IP header H1 from the local memory 123 . The first converter 121 may perform header format conversion on the read header HD.

The first filter 11 may analyze the read header HD and determine whether IP version conversion is desired and/or necessary ( S120 ). The first filter 11 may determine the IP version of the header HD based on desired and/or predetermined filter settings (e.g., desired and/or default fields), and determine whether it is desired and/or necessary to change Header format for header HD. For example, the first filter 11 can confirm the version field of the header HD, and determine that the header HD is an IPv6 header. The first filter 11 can determine whether the IPv6 header is to be converted into an IPv4 header based on expected and/or preset different fields (eg, traffic class and/or destination address, etc.). For example, if it is determined based on the destination address that the IP packet is provided to an application configured to support IPv4, the first filter 11 may determine that it is desirable and/or necessary to convert the header format of the header HD.

If the first filter 11 determines that IP version conversion is desired and/or necessary, the IP converter 12 may change the IP header format of the header HD (S130). To change the IP header format, the IP converter 12 may select the fields to be changed and change the selected fields. The IP converter 12 can be based on, for example, stateless Internet protocol/Internet control message protocol (Internet protocol/Internet control message protocol, IP/ICMP) conversion (SSIT), network address translation-protocol conversion (network address translation) -protocol translation (NAT-PT) and/or bump-in-the-stack (BIS) to perform IP header format conversion.

Subsequently, the IP header checksum calculator 13 may update the IP header checksum (S140). In operation S130, since the IP header format is changed, the first IP header checksum calculator 13 may calculate the IP header checksum based on the IP header H1 having the changed format, and update the IP header checksum based on the calculated value. IP header checksum.

For example, when an IPv6 header is converted into an IPv4 header, the first IP header checksum calculator 13 may calculate the IP header checksum and provide the calculated value to the header checksum column of the IPv4 header bit. Therefore, the IP header checksum can be updated, and IP header format conversion, that is, IP version conversion can be completed.

The first converter 121 may store the header NHD with the changed header format in the local memory 123 (S150). For example, the first converter 121 can store the header NHD converted from the IPv6 header into the IPv4 header in the local memory 123 .

In operation S120, if the first filter 11 determines that IP version conversion is not desired and/or unnecessary, header format conversion for the header HD may be ended. Can Then, header format conversion including the above operations S110 to S150 is performed on the headers HD0 to HDN-1 stored in the local memory 123 . Although FIG. 6A shows a situation in which the IPv6 headers HD0 to HDN-1 of the local memory 123 are converted into new IPv4 headers NHD0 to NHDN-1, exemplary embodiments of the inventive concept are not limited thereto. As described above, the headers HD0 to HDN-1 may be converted as needed, and some of the headers HD0 to HDN-1 may not be converted.

The converted headers HD0 to HDN-1 stored in the local memory 123 can be copied to the first memory (see 310 in FIG. 2 ) and/or the second memory (see 310 in FIG. 2 ) in a DMA manner. 320). In addition, IP address translation may be performed on the converted headers HD0 to HDN-1 by the second translator (see 122 in FIG. 2 ).

FIG. 7A is a block diagram of an implementation example of the second converter 122 of the address conversion circuit 120 according to at least one exemplary embodiment, and FIG. 7B is an operation of the second converter of FIG. 7A according to at least one exemplary embodiment. 122. Flowchart of the method.

7A, the second converter 122 may include a second filter 21, an address converter 22, an IP header checksum calculator 23 and/or a TCP header checksum calculator 24, etc., but is not limited thereto. The second filter 21 , the address converter 22 , the IP header checksum calculator 23 and the TCP header checksum calculator 24 can be implemented by hardware logic circuits, but is not limited thereto. In at least one exemplary embodiment, the IP header checksum calculator 23 and the TCP header checksum calculator 24 may be implemented by one header checksum calculator circuit, but not limited thereto.

7A and 7B, the second converter 122 can read and store in the local Header HD in memory 123 (S210). The second converter 122 can sequentially read the headers HD0 to HDN-1. As described above with reference to FIG. 3A , the header HD may include the IP header H1 and the TCP header H2 and the like. In operation S210 , the second converter 122 may read the IP header H1 and the TCP header H2 from the local memory 123 .

The second converter 122 may perform the operations described below and convert the IP address included in the read header HD. The second converter 122 can convert the public IP address of the IP packet received via the network into a private IP address and/or convert the IP packet to be transmitted via the network (ie, the IP packet provided by the application processor) Convert your private IP address to a public IP address for your network.

The second filter 21 may analyze the read header HD and determine whether it is desired and/or necessary to perform IP address conversion (eg, conversion of address values, etc.) ( S220 ). The second filter 21 may filter the header HD based on desired and/or predetermined filter settings, and determine whether IP address translation is desired and/or necessary. In at least one example embodiment, a source address and/or a destination address of an IP address may be included in a filter setting. For example, when the source address of an IP packet to be transmitted over a network is not included in the public IP address field (e.g., IP address range and/or subnet mask) used for the network, the The second filter 21 may determine that IP address translation is desired and/or necessary. In another example, when the local IP address area (eg, IP address range and/or subnet mask) provided by the communication device 10 of FIG. 1 does not include the IP packet received via the network In case of destination address, the second filter 21 may determine that IP address translation is desired and/or necessary.

If the second filter 21 determines that it is desirable and/or necessary to perform IP address forwarding If it is changed, the address converter 22 can change the address value and port number included in the header HD (S230). As described with reference to FIGS. 4A-5 , in the fields for the source address and/or destination address of an IP header (eg, the IPv4 header H1_IPv4 of FIG. 4A or the IPv6 header H1_IPv6 of FIG. 4B ), An address value is included, and a port number may be included in the field for source port or destination port of a TCP header or UDP header (eg, TCP header H2_TCP of FIG. 5 ). The address translator 22 can change the source address value and source port number and/or change the destination address value and destination port number. Therefore, the address translator 22 can translate the public IP address into the private IP address and/or convert the private IP address into the public IP address. The address translator 22 can store the relationship between the IP address and the translated IP address in the translation table, that is, the relationship between the private IP address and the public IP address.

FIG. 8 illustrates a conversion table TT according to at least one exemplary embodiment.

Referring to FIG. 8 , the translation table TT may include a public IP address PUA and a private IP address PRA that may correspond to each other. For example, a private IP address PRA with address value "10.0.0.2" and port number "3327" may correspond to a public IP address PUA with address value "135.26.32.7" and port number "5003" . The private IP address PRA with address value "10.0.0.3" and port number "3327" may correspond to the public IP address PUA with address value "135.26.32.7" and port number "5002". Address translator 22 may generate and use translation table TT during IP address translation.

Referring back to FIGS. 7A and 7B , the IP header checksum calculator 23 may update the IP header checksum, and the TCP header checksum calculator 24 may update the TCP header checksum (or UDP header checksum, etc.) ( S240). However, when the header HD is an IPv6 header, updating of the IP header checksum may not be performed.

In operation S230, since the address value is changed, the IP header checksum calculator 23 may calculate the IP header checksum based on the IP header including the changed address value, and update the IP header checksum based on the calculated value. header checksum. Also, in operation S230, since the port number is changed, the TCP header checksum calculator 24 may calculate the TCP header checksum based on the TCP header including the changed port number, and update the TCP header checksum based on the calculated value. header checksum. Therefore, IP conversion can be completed.

The second converter 122 may store the header NHD with the changed IP address value in the local memory 123 (S250). For example, the second translator 122 may again change the IP address value from the public IP address to the header NHD of the private IP address or the IP address value from the private IP address to the public IP address instead. The header NHD is stored in the local memory 123 .

Meanwhile, in operation S220, if the second filter 21 determines that the IP address translation is not desired and/or unnecessary, the IP address translation of the header HD may be ended. The IP address translation including the above operations S210 to S250 (ie, header translation) may be performed sequentially (or in parallel) on the headers HD0 to HDN-1 stored in the local memory 123 . Although FIG. 7A shows a situation in which the headers HD0 to HDN-1 of the local memory 123 are converted into new headers HD0 to HDN-1 with converted IP addresses, exemplary embodiments of the inventive concepts are not That's all. As described above, the headers HD0 to HDN-1 may be converted as needed, and some of the headers HD0 to HDN-1 may not be converted.

The headers HD0 to HDN-1 stored in the local memory 123 can be stored in the first memory (refer to 310 in FIG. 2 ) and/or the second memory (refer to FIG. 2 320 in ) and/or the first converter (refer to 121 in FIG. 1 ) may perform header format conversion on the headers HD0 to HDN-1 stored in the local memory 123 .

9A and 9B are diagrams illustrating a method of converting an IP address of a second translator according to some exemplary embodiments. FIG. 9A shows the translation of the private IP address to the public IP address in the transmission path, and FIG. 9B shows the translation of the received public IP address to the private IP address in the reception path.

Referring to FIG. 9A, the source IP address S of the IP packet received from the host may be a private IP address with address value "10.0.0.2" and port number "3327", and the destination IP address D may be with Public IP address with address value "128.119.40.186" and port number "80". When the source IP address S does not correspond to the public IP address area (eg, IP address range and/or subnet mask) provided by the specific network, the second converter 122 (eg, the second converter The address translator of 122 (refer to 22 in FIG. 7A ) may perform an IP address translation operation of converting the source IP address S into a public IP address.

The second converter 122 can change the address value "10.0.0.2" and the port number "3327" of the source IP address S to the address value "135.26.32.7" and the port number "5003" respectively, and change the source IP address S The address S is converted to a public IP address. The private IP address and the corresponding public IP address can be stored in the translation table TT. The IP packet with the converted source IP address S' and destination IP address D can be transmitted to the destination (eg, a server or another electronic device, etc.) via the network.

9B, the source IP address S of the IP packet received from the network can be a public IP address with address value "128.119.40.186" and port number "80", and the destination IP address D can be with Address value "135.26.32.7" and port number "5003" public IP address. When the destination IP address D does not correspond to the private IP address area (for example, IP address range and/or subnet mask) provided by the local area network, the second converter 122 can perform the conversion of the public IP address to An IP address translation operation that translates an IP address into a private IP address.

The second converter 122 can refer to the translation table TT to change the address value "135.26.32.7" and the port number "5003" of the destination IP address D into the address value "10.0.0.2" and the port number "3327", respectively, And convert the destination IP address D into the source IP address. The IP packet with the translated destination IP address D' and source IP address S can be transmitted to the host.

FIG. 10 is a block diagram of an address conversion circuit 120a according to at least one example embodiment.

Referring to FIG. 10 , the address conversion circuit 120a may include a local memory 123 , a first converter 121a , a second converter 122a and/or a header checksum calculator 123a , etc., but is not limited thereto.

The first converter 121a may include the first filter 11 and/or the IP converter 12 and the like. Operations of the first filter 11 and the IP converter 12 of the first converter 121 a may be the same as those of the first filter 11 and the IP converter 12 shown in FIG. 6A . In addition, the second converter 122a may include a second filter 21 and/or an address converter 22 and the like. Operations of the second filter 21 and the address converter 22 of the second converter 122 a may be the same as those of the second filter 21 and the address converter 22 shown in FIG. 7A .

The header checksum calculator 123a may update the header check when the first converter 121a converts the format of the IP header and/or when the second converter 122a converts the IP address and.

The header checksum calculator 123a may include an IP header checksum calculator 31 and/or a TCP header checksum calculator 32 and the like. When the first converter 121a converts the format of the IP header, the IP header checksum calculator 31 may calculate the IP header checksum based on the converted IP header having the format, and update the TCP header checksum .

In addition, when the second converter 122a converts the IP address, the IP header checksum calculator 31 may update the IP header checksum based on the IP header including the changed address value, and the TCP header checksum calculates Controller 32 may calculate a TCP header checksum based on the TCP header including the changed port number and update the TCP header checksum.

In at least one exemplary embodiment, each of the first converter 121a and the second converter 122a of the address conversion circuit 120a may not include a header checksum calculator, but an additional header checksum calculator 123a The header checksum may be calculated during header format conversion by the first converter 121a and during IP address conversion by the second converter 122a, but exemplary embodiments are not limited thereto.

FIG. 11 is a block diagram of a communications processor 100a, according to at least one example embodiment.

11, the communication processor 100a may include at least one processor 110, random access memory (RAM) 130, modem 150, address conversion circuit 120, DMA controller 140 and/or memory interface 160, etc., but Exemplary embodiments are not limited thereto. In addition, the communication processor 100a may further include other components. In at least one exemplary embodiment, the communication processor 100a may be implemented by a single chipset, but is not limited thereto. The components of the communication processor 100a can be transmitted via the bus 170 and receive information.

The processor 110 can control all operations of the communication processor 100a and can be implemented by a central processing unit (CPU), a microprocessor (MP) or a digital signal processor (DSP). In at least one exemplary embodiment, the processor 110 may be implemented by a multi-core processor (eg, a dual-core processor or a quad-core processor), or may be multi-processors.

The RAM 130 can be used as operating memory, buffer memory and/or cache memory, etc. For example, software or firmware for controlling the communication processor 100 a can be loaded into the RAM 130 . RAM 130 may be implemented by volatile memory (eg, DRAM and SRAM, etc.) and/or resistive memory (eg, PRAM, MRAM, FeRAM, ReRAM, etc.).

The modem 150 can convert IP packets into signals suitable for transmission over the network and/or convert signals received over the network into IP packets. The modem 150 can encode and modulate the IP packets and convert the IP packets into transmission signals. In addition, the modem 150 can demodulate and decode received signals received via the network and convert the received signals into IP packets. Modem 150 may amplify and filter the signal and communicate with a radio frequency (RF) chip configured to convert the frequency of the signal. The RF chip can transmit transmission signals to the network and/or receive signals from the network through the antenna.

The memory interface 160 can transmit data to the memory 300 and/or read data from the memory 300 under the control of the processor 110 and/or the DMA controller 140 , but it is not limited thereto.

The memory 300 may be implemented by a device (eg, a memory chip or a memory module, etc.) other than the communication processor (eg, a communication chip) 100a. However, exemplary embodiments of inventive concepts are not limited thereto. In at least one exemplary embodiment, the memory 300 may be an embedded memory of the communication processor 100a. IP packets received via the modem 150 or to be received via the modem 150 can be stored in the memory 300 . In at least one exemplary embodiment, the communication processor 100 a and the application processor (refer to 200 in FIG. 1 ) can access the memory 300 . The memory 300 may include a dedicated area of the communication processor 100 a , a shared area, and a dedicated area of the application processor 200 .

The DMA controller 140 can support data transfer between components of the communication processor 100 a and control data transfer between components of the communication processor 100 a directly without the intervention of the processor 110 . In at least one exemplary embodiment, the DMA controller 140 can transmit the header of the IP packet stored in the memory 300 to the address conversion circuit 120 and/or transmit the header converted by the address conversion circuit 120 to the memory Body 300. In addition, the DMA controller 140 can transfer the payload of the IP packet in multiple areas of the memory 300 (eg, the dedicated area of the communication processor 100a, the shared area, and the dedicated area of the application processor 200).

The address conversion circuit 120 can convert the network addresses of the IP packets transmitted and received via the network. The address conversion circuits 120 and 120a described with reference to FIG. 2 and FIG. 10 can be applied to the communication processor 100a.

The address conversion circuit 120 can receive the header of the IP packet stored in the memory 300 and convert the network address included in the header through the control of the DMA controller 140 . The address conversion circuit 120 can convert the format of the header (ie, IP version) Or perform IP address translation.

When the address translation circuit 120 operates as a receive path, the address translation circuit 120 may convert the format of the header and then perform IP address translation. When the address conversion circuit 120 operates as a transmission path, the address conversion circuit 120 may perform IP address conversion and then convert the format of the header. The address conversion circuit 120 can store the converted header in the shared area of the memory 300 (or memory shared with the application processor) and/or convert the converted header under the control of the DMA controller 140 Stored in the dedicated area of the communication processor 100a. For example, when the address conversion circuit 120 operates as a receiving path, the address conversion circuit 120 can store the converted header in the shared area of the memory 300 so that the application processor can use the converted header. When the address conversion circuit 120 operates as a transmission path, the address conversion circuit 120 can store the converted header in the dedicated area of the communication processor 100a included in the memory 300, so that it is provided by the application processor and The IP packet including the converted header can be transmitted to the network via the modem 150 .

As mentioned above, before the IP packet received from the network is provided to the application processor (refer to 200 in FIG. 1 ), the address conversion circuit 120 of the communication processor 100a can convert the network address of the IP packet. In addition, before the IP packet provided by the application processor 200 is transmitted to the network, the address conversion circuit 120 of the communication processor 100a can convert the network address of the IP packet.

FIG. 12 is a block diagram of a communication device 10a according to at least one example embodiment.

Referring to FIG. 12, the communication device 10a can be connected via a network (for example, global network) 20 transmits data (eg, IP packets) to and receives data (eg, IP packets) from at least one electronic device 30 and/or server 40 , etc. The communication device 10a can also function as a router. The communication device 10a can transmit the IP packet received through the network 20 to another electronic device 50 through the local area network. In addition, the communication device 10 a can transmit the IP packets received from other electronic devices 50 to the electronic device 30 or the server 40 via the network 20 .

The communication device 10 a may include a communication processor 100 , an application processor 200 , a memory 300 , an input/output (I/O) device 400 and/or a DMA controller 500 , etc., but is not limited thereto. In addition, the communication device 10a may further include other components. The components of the communication device 10 a can transmit and receive data through the bus 600 .

The input/output element 400 can provide a user interface and include an input unit (eg, a touchpad, a keypad, and/or input buttons, etc.) and/or an output unit (eg, a display and a speaker, etc.).

The DMA controller 500 can support data transfer between components of the communication device 10 a and control data transfer between components of the communication device 10 a directly without the intervention of the application processor 200 . In at least one exemplary embodiment, the DMA controller 500 can control IP packets to be transmitted among the communication processor 100 , the application processor 200 and the memory 300 . In addition, the DMA controller 500 can transfer the header of the IP packet stored in the memory 300 to the address conversion circuit 120 of the communication processor 100 and/or convert the header converted by the address conversion circuit 120 to the memory 300 . In at least one example embodiment, each of the communication processor 100 and the application processor 200 may include a DMA controller.

The network address of the IP packet received via the network 20 can be converted, and the IP packet including the converted network address can be stored in the memory 300 . The communication processor 100 can convert the network address of the IP packet into an address system that can be recognized by the application program 202 of the application processor 200 or other electronic devices 50 . The application processor 200 can read the IP packet including the translated network address from the memory 300, and the application program 202 can process the IP packet. In addition, other electronic devices 50 can process the IP packets including the converted network addresses via the local area network 60 .

In addition, the communication processor 100 can convert the network address of the IP packet provided by the application processor 200 and/or other electronic devices 50 into an address system conforming to the network 20, and include the converted network address The IP packets are transmitted to the network 20 .

In the communication device 10a according to at least one exemplary embodiment, the communication processor 100 can convert the network address so that the application processor 200 does not need to perform additional network address conversion. Therefore, the processing and/or memory load of the application processor 200 can be reduced and/or can be made more efficient, and the performance of the communication device 10a is improved.

FIG. 13A illustrates the movement of IP packets in a communication device according to at least one example embodiment. FIG. 13B shows the movement of IP packets in the communication device according to the comparative example. 13A and 13B illustrate the movement of IP packets received from the network in the hardware area (eg, communication processor CP) and software area (eg, application processor AP).

Referring to FIG. 13A, the IP packets can be received via the network (S11), and the received IP packets PK0 to PKN-1 can be stored in the first memory 310 of the hardware area. middle.

The address conversion circuit 120 can convert the network address of the IP packet (S12). As described with reference to FIGS. 2 to 9B , the address translation circuit 120 can receive the header of the IP packet and convert the header format or the IP address. The address conversion circuit 120 can copy (or store) the IP packets (for example, IP packets NPK0 to NPKN-1) including the converted network addresses to the second memory 320 (for example, a shared memory) (or copy or stored in the second memory 320) (S13).

Subsequently, the IP packets NPK0 to NPKN-1 can be processed by the software domain. The driver 203 can copy the IP packets NPK0 to NPKN-1 stored in the second memory 320 to the socket buffer ( S14 ). For example, the socket buffer can be a part of the third memory 330 dedicated to the application processor AP.

The application 202 can read the IP packets NPK0 to NPKN-1 from the socket buffer (S15).

Referring to FIG. 13B , the IP packets may be received via the network (S21), and the received IP packets PK0 to PKN-1 may be stored in the first memory 310a of the hardware area. The IP packets PK0 to PKN-1 may be copied to the second memory 320a (eg, shared memory) (S22).

Thereafter, the IP packets PK0 to PKN-1 can be processed by the software domain. The driver 203a can copy the IP packets PK0 to PKN-1 stored in the second memory 320a to the socket buffer (S23). For example, the socket buffer can be a part of the third memory 330a dedicated to the application processor AP, but it is not limited thereto. Meanwhile, the addressing system of IP packets PK0 to PKN-1 may not conform to the address system configured to process IP packets PK0 Addressing system to application 202a of PKN-1. Therefore, the header converter 204a (eg, a resident program) can read the IP packets PK0 to PKN-1 from the socket buffer (S24) and/or convert the network addresses of the IP packets PK0 to PKN-1 (S25). The header converter 204a and/or the driver 203a may re-copy the IP packets NPK0 to NPKN-1 with the converted network addresses to the socket buffer (S26). Then, the application 202a can read the IP packets NPK0 to NPKN-1 from the socket buffer (S27).

When comparing the movement of an IP packet in the communication device shown in FIG. 13A according to at least one exemplary embodiment with the movement of an IP packet in the communication device shown in FIG. 13B according to a comparative example, according to at least one example In the communication device of the exemplary embodiment, the hardware-based address translation circuit 120 can perform network address translation in advance, so that the application processor AP does not need to perform address translation. Therefore, the processing and/or memory load of the application processor AP can be reduced. In addition, the number of times the IP packet is copied to the memory can be reduced, thereby increasing the processing speed of the IP packet.

FIG. 14 is a block diagram of an application processor 200a according to at least one exemplary embodiment.

Since the functions of the modem are integrated in the application processor 200a, the application processor 200a shown in FIG. 14 can be called ModAP.

14, the application processor 200a may be implemented by a system chip (system-on-chip, SoC), and may include a central processing unit (CPU) 210, a random access memory (RAM) 220, a DMA controller 230, a modem 240 , the address conversion circuit 250 and/or the memory controller 260 and so on. In addition, the application processor 200a may further include other components, such as a power management unit, a display controller and/or a sensor detector etc. The components of the system chip can transmit and receive data via the bus 270 .

The CPU 210 may control all operations of the application processor 200a. The CPU 210 can process and/or execute at least one program (eg, computer-readable instructions, etc.) and/or data stored in the RAM (or ROM) 220, and control operations of components of the application processor 200a. In at least one exemplary embodiment, the CPU 210 may be implemented by a multi-core processor, a plurality of interconnected processors, a distributed processing system and/or a cloud computing processing system, and the like. The multi-core processor may be a single computing component including at least two independent cores.

The RAM 220 can temporarily store programs (eg, operating systems, application programs, computer-readable instructions thereof, etc.), data or instructions. For example, the programs and/or data stored in the memory 300 can be temporarily stored in the RAM 220 under the control of the CPU 210 or the boot code. RAM 220 may be implemented by DRAM, SRAM, or the like.

The DMA controller 230 can support data transfer between components of the application processor 200 a and control data transfer between components of the application processor 200 a directly without the intervention of the CPU 210 .

In order to perform wired and/or wireless communication, the modem 240 can adjust the data to be transmitted according to the wired and/or wireless environment and store the received data again. The modem 240 can perform digital communication with the RF chip 245, but is not limited thereto.

The RF chip 245 can convert the high-frequency signal received through the antenna into a low-frequency signal, and transmit the converted low-frequency signal to the modem 240 . In addition, the RF chip 245 can convert the low frequency signal received from the modem 240 into a high frequency signal and transmit the converted high frequency signal to the wireless network through the antenna. In addition, the RF chip 245 can be used for The signal is amplified and/or filtered.

In addition, the operations of the modem 240 , the address conversion circuit 250 and the memory controller 260 may be the same or similar to those of the modem 150 , the address conversion circuit 120 and the memory interface 160 shown in FIG. 11 . Therefore, it will not be described in detail.

As described above, the application processor 200a according to at least one example embodiment may include some components (eg, the modem 240 and the address conversion circuit 250 ) configured to perform communication functions. In this case, since the address translation circuit 250 performs network address translation in advance, the CPU 210 may not need to perform address translation. The load of the CPU 210 can be reduced, and the number of times the IP packet is copied to the memory 300 can be reduced, and thus the processing speed of the IP packet can be increased. Therefore, the performance of the application processor 200a can be improved.

While the inventive concepts have been particularly shown and described with reference to various exemplary embodiments thereof, it should be understood that various changes in form and details could be made without departing from the spirit and scope of the following claims.

10: Communication device

100: communication processor/shared processor

120: Address conversion circuit

200: application processor

201: Operating system (OS)

202: Application

300: Memory

AP: application processor

AR1: Area 1

AR2: Second Area

AR3: the third area

CP: communication processor

Claims (23)

A communication system configured to transmit and receive at least one packet via a network, the communication system comprising: a modem circuit configured to convert the at least one packet into a transmission signal for transmission to the network, and transmit from the The signal demodulation received by the network becomes the at least one packet; and the address conversion circuit is configured to convert the network address of the at least one packet, and the conversion of the network address of the at least one packet includes : receiving the header of the at least one packet from the external memory in which the at least one packet is stored, and storing the header of the at least one packet in the embedded memory, converting the at least one packet format of the header, and converting an address included in the header of the at least one packet. In the communication system described in item 1 of the scope of the patent application, the address conversion circuit includes a first converter circuit and a second converter circuit. The communication system according to claim 1, wherein the address translation circuit is further configured to convert the header of the at least one packet from the first version according to a version of the Internet Protocol (IP) The format is changed to a second format according to another version of the internet protocol. The communication system as described in item 1 of the scope of the patent application, wherein the address translation circuit is further configured to convert the Internet protocol (IP) of the at least one packet into Addresses are converted from public Internet Protocol addresses to private Internet Protocol addresses, or the Internet Protocol addresses are converted from private Internet Protocol addresses to public Internet Protocol addresses. The communication system according to claim 1, wherein, in response to the address translation circuit operating as a receiving path, the address translation circuit is further configured to store the changed header in a shared memory ; and the shared memory is configured to be shared between the address translation circuit and an external application processor. The communication system as described in item 5 of the scope of the patent application, wherein the address conversion circuit is further configured to directly store the payload of the at least one packet in the shared memory without storing the payload in the embedded memory. The communication system as described in item 1 of the scope of the patent application, wherein the address conversion circuit is further configured to: judge whether format conversion is desired based on the desired first filter item; changing at least some of the plurality of fields included in the header to correspond to a target internet protocol version; and updating an internet protocol header check of the header based on the transformed format and fields. The communication system described in item 1 of the scope of the patent application, wherein the address conversion circuit is further configured as: Judging whether address translation is desired based on the desired second filter item; changing an Internet Protocol (IP) address value and port number included in the header based on a result of judging whether it is desired to perform the address translation ; and updating the IP header checksum field and the transport protocol header checksum field of the header based on the changed IP address value and the changed port number. The communication system as described in claim 1, wherein in response to the address translation circuit operating as a receiving path, the address translation circuit is further configured to preprocess the at least one packet and process the At least one packet is post-processed. The communication system described in claim 1 of the scope of the patent application, wherein in response to the operation of the address translation circuit as a transmission path, the address translation circuit is further configured to pre-process the at least one packet and process the At least one packet is post-processed. A communication device, comprising: a memory; a communication processor configured to convert a network address of a first packet received via a network, and store a second packet including the converted network address in the in the memory; and an application processor configured to receive the second packet from the memory, drive an application, and process the second packet, wherein the first packet includes a header and a payload , and the first packet stores in a first dedicated memory; the communication processor includes an internal buffer; and the communication processor is further configured to copy the header of the first packet to the internal buffer, and convert the The network address included in the header of the first packet. The communication device as described in item 11 of the scope of the patent application, wherein the communication processor further includes: an embedded memory configured to store the header of the first packet; a first address conversion circuit configured to converting an Internet Protocol (IP) version of an Internet Protocol header included in the header of the first packet; and a second address translation circuit configured to convert the header in the first packet The Internet Protocol address included in the header. The communication device according to claim 12, wherein the first address conversion circuit is further configured to convert the IPv4 header included in the header of the first packet into an IPv6 header, Or convert the IPv6 header included in the header of the first packet into an IPv4 header. The communication device as described in item 12 of the scope of patent application, wherein the second address conversion circuit is further configured to convert the public IP address included in the header of the first packet into Private Internet Protocol address. The communication device as described in claim 12 of the scope of the patent application, wherein in response to the first address conversion circuit performing an Internet protocol version conversion operation on the first packet, the second address conversion circuit is further configured paired with the first packet to perform Internet protocol address translation operations. The communication device according to claim 11, wherein the application processor is further configured to copy the second packet stored in the memory to a second dedicated memory. An application processor including a communication function, the application processor comprising: at least one processor configured to execute an application program; a memory configured to be accessed by the at least one processor; and an address translation circuit, configured to convert a network address included in a first header of at least one packet received from the network into an address system conforming to the application, and to include the converted network address The second header is stored in the memory, wherein the address conversion circuit includes a buffer configured to receive the first header of the at least one packet and store the first header header; and the address conversion circuit is further configured to convert the format of the first header; and convert the address included in the first header. The application processor of claim 17, wherein the address translation circuit is further configured to update the IP header checksum of the at least one packet. A network address translation method for a communication system, the method comprising: using at least one processor to receive a first Internet protocol address via the network The (IP) packet is stored in a first memory, and the first Internet Protocol packet includes a header and a network address; the at least one processor is used to store the first memory in the first memory Copying the header of the first IP packet into an internal buffer of the at least one processor; converting the network included in the first IP packet using the at least one processor and storing a second IP packet including the header and the converted IP address with the at least one processor. The method according to claim 19, wherein converting the network address includes: converting the current format of the header into a second format; and converting the current Internet address included in the header The protocol address is converted to a second Internet Protocol address. The method according to claim 20, wherein converting the current format of the header includes: judging whether it is desired to convert the current format of the header based on a first filter setting; resulting in converting the format of an IP header of the header from a first format according to one version of IP to a second format according to another version of IP; and A checksum of the internet protocol header is updated. The method of claim 20, wherein converting the current IP address included in the header includes: determining whether conversion of the current IP address is desired based on a second filter setting address; change the address value of the Internet Protocol header included in the header and the port number of the Transport Protocol header included in the header based on the result of the judgment; and update the Internet A checksum of an internet protocol header and a checksum of said transport protocol header. The method according to claim 19, further comprising: using the at least one processor to copy the second internet protocol packet to the socket buffer; and using the at least one processor to execute the application program and Process the second IP packet.

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