TW201926975A - Communication system, communication device, application processor and network address translation method of communication system - Google Patents

Abstract

A communication system configured to perform an address translation and a method of translating an address of the communication system are provided. The communication system configured to transceive a packet through a network includes a modem circuit configured to modulate the packet into a transmission signal to be transmitted to the network and demodulate a receiving signal from the network into the packet, and an address translation circuit configured to translate a network address of the packet, wherein the address translation circuit includes an embedded memory configured to receive a header of the packet from an external memory in which the packet is stored and store the header, a first translator configured to translate a format of the header, and a second translator configured to translate an address included in the header.

Description

Communication system, communication device, application processor, and network address conversion method of communication system

Various exemplary embodiments of the inventive concept relate to a communication system, and more particularly to a hardware structure, a communication device, and a communication system configured to perform network address translation for data communication, A method of converting a network address and/or its non-transitory computer readable medium.

A communication device or communication system for data communication can communicate with a network or communication device having a different address system using network address translation technology. Network address translation techniques may include a customer-side translator (CLAT) and a network address translation (NAT). The client converter can be a technology for converting an IPv4 address to an IPv6 address or converting an IPv6 address to an IPv4 address so that the host can freely communicate with the IPv4 host or IPv6 host via the IPv6 network. Network address translation can refer to the nickname of the transmission protocol for the transmission and reception of network traffic by a router or equivalent networking device, and the Internet protocol (IP) packet is rewritten by the router, and the source Internet Protocol ( IP) address and the technology of the destination IP address. When performing network address translation, since the Internet Protocol (IP) packet is changed, the checksum of the Internet Protocol (IP) header or transport protocol header must be updated.

Various exemplary embodiments of the inventive concept provide a communication system configured to efficiently perform address translation, a communication device, an address conversion method of a communication system, and/or a non-transitory computer readable medium thereof.

In accordance with an aspect of at least one exemplary embodiment of the inventive concept, a communication system is provided that is configured to transceive at least one packet via a network. The communication system includes: a data machine circuit configured to convert the at least one packet into a transmission signal for transmission to the network, and demodulate a signal received from the network into the at least one packet; And an address translation circuit configured to convert the network address of the at least one packet, and converting the network address of the at least one packet includes: receiving an external memory from the at least one packet a header of the at least one packet, and storing the header of the at least one packet in an embedded memory, converting a format of the header of the at least one packet, and converting the at least one packet The address included in the header.

According to another aspect of at least one exemplary embodiment of the inventive concept, a communication device is provided, the communication device comprising: a memory; a communication processor configured to convert a network bit of a first packet received via a network Addressing, and storing, in the memory, a second packet including the converted network address; and an application processor configured to receive the second packet from the memory, to drive an application, And processing the second packet.

According to another aspect of at least one exemplary embodiment of the inventive concept, an application processor including a communication function is provided. The application processor includes: at least one processor configured to execute an application; a memory configured to be accessed by the at least one processor; and an address translation circuit configured to receive from the network Converting a network address included in a first header of at least one packet into an address system conforming to the application, and storing a second header including the converted network address in the memory In the body.

According to another aspect of at least one exemplary embodiment of the inventive concept, a network address translation method of a communication system is provided. The method includes storing, by using at least one processor, a first Internet Protocol (IP) packet received via a network, the first Internet Protocol packet including a header and a network bit Copying, by the at least one processor, the header of the first Internet Protocol packet stored in the first memory to an internal buffer of the at least one processor; Translating, by the at least one processor, the network address included in the first internet protocol packet; and storing, by the at least one processor, a second internet protocol packet, the second internet The protocol packet includes the header and the converted network address.

FIG. 1 is a block diagram of a communication device 10 in accordance with at least one example embodiment.

Referring to Figure 1, communication device 10 can be an electronic device configured to perform data communication with at least one other electronic device. For example, the communication device 10 can be a smart phone, a tablet personal computer (PC), a laptop, a drone, a digital camera, a wearable computer, an Internet of Things (IoT) device, One of a vehicle drive device, a virtual reality device, an augmented reality device, and/or various other smart devices. Additionally, communication device 10 can be one of a variety of electronic devices configured to perform data communication with external electronic devices via a wired/wireless network.

Referring to FIG. 1, the communication device 10 may include, but is not limited to, a communication processor (CP) 100, an application processor (AP) 200, and/or a memory 300. In addition, the communication device 10 may further include other hardware and/or software components, such as a display module and/or an input/output (I/O) module.

The application processor 200 can drive (eg, execute) an operating system (OS) 201 of the communication device 10 and/or various applications 202 to control a plurality of hardware and/or software components connected to the application processor 200. And process and calculate various materials including multimedia materials. In at least one example embodiment, application processor 200 may be implemented by a system-on-chip (SoC), an FPGA, a multi-core processor, a multi-processor system, or the like.

The communications processor 100 can transceive (e.g., transmit and/or receive) data during communications with other electronic devices connected via the network. In the data transceiving process, the communication processor 100 can transmit the data to the application processor 200 and receive the data from the application processor 200. When the communication device 10 receives data via the network, for example, when the communication device 10 performs a data download operation, the communication processor 100 can transmit the received data to the application processor 200, and the application processor 200 can perform a data processing operation, For example, data calculation and storage operations. In contrast, when the communication device 10 transmits data via the network, for example, when the communication device 10 performs a data upload operation, the application processor 200 can transmit the data to be uploaded to the communication processor 100, and the communication processor 100 can then pass through the network. Road transmission data. For example, when the communication device 10 performs a video streaming operation, the communication processor 100 can transmit the received data to the application processor 200, and the application processor 200 can process the data received from the communication processor 100 and display it on the screen. The processed data is displayed on it. According to at least one example embodiment, communication processor 100 and application processor 200 may be implemented in a single processor. Additionally, communication processor 100 and/or application processor 200 may be implemented in two or more processors, in accordance with some example embodiments.

The memory 300 can store instructions or materials received by the application processor 200 and/or the communication processor 100 or generated by the application processor 200, but is not limited thereto. The memory 300 can be implemented by a volatile memory such as a dynamic random access memory (DRAM) or a static random access memory (SRAM). However, the exemplary embodiments of the inventive concept are not limited thereto, and the memory 300 may include non-volatile memory such as a flash memory, a magnetic random access memory (MRAM), and a ferroelectric random memory. Take memory (ferroelectric RAM, FeRAM), phase-change RAM (PRAM) and/or resistive random access memory (ReRAM). The memory 300 may refer to a memory chip included in the communication device 10 or a memory module including a plurality of memory chips and/or memory devices.

As described above, since the data is frequently transmitted and received between the communication processor 100 and the application processor 200, the memory 300 can operate as a shared memory accessible by the communication processor 100 and the application processor 200. The communication processor 100 and the application processor 200 can transmit and receive data via the memory 300.

In at least one exemplary embodiment, the memory 300 may include the first area AR1, the second area AR2, and the third area AR3, etc., but is not limited thereto, and may have a larger number in other exemplary embodiments. Or a smaller number of zones. In at least one exemplary embodiment, the first region AR1, the second region AR2, and the third region AR3 may be regions that are physically and/or logically separated from each other in the memory chip and/or the memory module. In at least one exemplary embodiment, the first zone AR1, the second zone AR2, and the third zone AR3 may be memory devices that are physically distinguishable from each other in the communication device 10.

According to at least one exemplary embodiment, the first area AR1 may be a dedicated area of the communication processor 100, which is exclusively used by the communication processor 100. The second zone AR2 can be shared between the communication processor 100 and the application processor 200. For example, the second area AR2 may be a shared area for inter-processor communication (IPC) between the communication processor 100 and the application processor 200. The third zone AR3 may be a dedicated zone of the application processor 200 that is used exclusively by the application processor 200. However, the exemplary embodiments are not limited thereto, and various regions of the memory 300 may be arranged in other configurations/relationships.

Meanwhile, in the communication device 10 according to at least one exemplary embodiment, the communication processor 100 may include an address conversion circuit 120. The address conversion circuit 120 can be implemented by a hardware circuit system or a combination of a hardware circuit system and a software. The address translation circuit 120 can determine whether it is desirable and/or necessary to convert the network address of the data transceived via the network. If it is determined that a network address is desired and/or necessary to convert the data, the address translation circuitry 120 can convert the network address of the data based on the network address translation technique.

The data can be transmitted and/or received as a type of Internet Protocol (IP) packet, and the address translation circuitry 120 can translate the network address of the IP packet (eg, included in the convertible IP packet and/or Or the network address associated with the IP packet, etc.). The address translation circuit 120 can convert the destination address of the IP packet received via the network into an address suitable for the address system of the application 202 and/or convert the source address of the IP packet to be transmitted via the network into The address of the address system applicable to the network.

In at least one exemplary embodiment, address translation circuitry 120 can support both a client translator (CLAT) and a network address translation (NAT) as a network address translation technique. The client converter may be an IP header format conversion technique for converting an IPv4 header of an IP packet into an IPv6 header of an IP packet and/or an IPv6 header to an IPv4 header, so that the communication device 10 can be Networks based on specific Internet protocols (eg, IPv6 or IPv4, etc.) are free to communicate with other communication devices. Network address translation can be used to translate private IP addresses (and/or internal IP addresses associated with private networks, LANs, internal networks, etc.) into public IP addresses (and/or A global IP address, such as an IP address that can be accessed across the Internet by the Internet, or the like, or an IP address translation technique that converts a public IP address to a private IP address. The IP address value and nickname of the source and/or destination address can be changed according to the network address translation.

For example, the address translation circuitry 120 can write (and/or copy) an IP packet having a translated network address (eg, a destination address, etc.) to the second region AR2 of the memory 300, but not Limited to this. The application processor 200 can access the second region AR2 of the memory 300 and process the IP packet based on the translated network address. During the operation of processing the IP packet of the application processor 200, the IP packet may be copied to the third area AR3 of the memory 300, but is not limited thereto.

Moreover, according to some exemplary embodiments, when the application processor 200 provides an IP packet, the IP packet may be stored in the second area AR2 of the memory 300, and the address conversion circuit 120 may be the first from the memory 300. The second zone AR2 reads the IP packet and translates the network address of the IP packet. The IP packet having the converted network address can be stored in dedicated memory of the communication processor 100 (e.g., the first area AR1 of the memory 300), but is not limited thereto.

As described above, when the communication processor 100 transmits the IP packet to the application processor 200 and/or receives the IP packet from the application processor 200, since the hardware-based address conversion circuit 120 performs network address translation, the application Processor 200 may not need to perform additional operations for network address translation. Therefore, the load of the application processor 200 can be reduced, and the number of times the IP packet is written (and/or copied) to the memory 300 or the IP packet is read from the memory 300 can be reduced.

FIG. 2 is a diagram showing the operation of the address translation circuit 120 in accordance with at least one example embodiment. It is assumed that an IP packet is received from the network, that is, the address conversion circuit 120 is a reception path.

Referring to FIG. 2, the address conversion circuit 120 may include the first converter 121, the second converter 122, and/or the local memory 123, but is not limited thereto.

IP packets transmitted and received via the network may include headers, payloads, and the like. For example, the first IP packet PK0 may include a first header HD0 and a first payload PL0. The header may include a network address (hereinafter referred to as an IP address) and control information, and the payload may include data.

The IP packets PK0 to PKN-1 received via the network may be stored in the first memory 310, where N is a natural number. For example, the first memory 310 can be the first area AR1 of the memory 300 shown in FIG. 1, that is, the dedicated area of the communication processor 100, and the like.

The header HDs of the IP packets PK1 to PKN-1 stored in the first memory 310 can be read, and the read header HDs can be stored in the local memory 123. In at least one exemplary embodiment, the address translation circuit 120 can read the header from the first memory 310 based on the address and length information of the header HDs, for example, in a direct memory access (DMA) manner. HDs, and the header HDs are stored in the local memory 123, and the address and length information is obtained based on descriptor information indicating the locations where the IP packets PK0 to PKN-1 are stored in the first memory 310. .

The local memory 123 can be implemented by a static random access memory or a scratchpad. However, exemplary embodiments of the inventive concept are not limited thereto, and the local memory 123 may be implemented by various memories. Local memory 123 may also be referred to as a local buffer. Although FIG. 2 shows an example in which the local memory 123 is included in the address conversion circuit 120, the exemplary embodiments of the inventive concept are not limited thereto. In another exemplary embodiment, the local memory 123 may be an embedded memory of a communication processor (refer to 100 in FIG. 1), and may also be a memory separately provided from the address conversion circuit 120.

The first converter 121 and the second converter 122 can access the local memory 123 and convert the IP addresses of the headers HD0 to HDN-1 stored in the local memory 123. The first converter 121 can operate as a pre-processor and the second converter 122 can operate as a post-processor. The first converter 121 can operate before the second converter 122, and the second converter 122 can operate after the operation of the first converter 121 is completed.

The first converter 121 can change (and/or convert, generate a new header, etc.) the header format of the IP packet and change the IP version of the IP packet. The first converter 121 can read the headers HD0 to HDN-1 from the local area memory 123 and determine, for example, whether it is desirable and/or necessary to change the IP version of each of the headers HD0 to HDN-1. When it is desired and/or necessary to change the IP version, the first converter 121 may, for example, change the format of the header to another IP version (eg, another IP protocol version, such as IPv4, IPv6, etc.) The format of the header HD0 to HDN-1 is converted into a format, and the IP version is changed to another IP version. The header may include various fields (eg, multiple fields), and when changing the header format, the first converter 121 may change at least some of the fields of the header.

In at least one exemplary embodiment, the first converter 121 can support the CLAT function and convert the Internet Protocol version 4 (IPv4) header format included in the header of the IP packet into the Internet. The Internet Protocol version 6, IPv6 header format and/or the IPv6 header format is converted to the IPv4 header format. The changed header can be stored again in the local memory 123. For example, when the network supports the IPv6 address system and the host (eg, the application 202 in FIG. 1) that utilizes the IP packet received via the network supports the IPv4 address, the first converter 121 can The IPv6 address included in the header of the IP packet is converted to an IPv4 address.

The second converter 122 can perform IP address translation. The second converter 122 can read a header such as HD0 to HDN-1 (or a header changed by the first converter 121) from the local area memory 123, and determine whether it is desired and/or necessary to convert the header HD0. IP address to each of HDN-1. When it is desired and/or necessary to convert the IP address of each of the headers HD0 to HDN-1, the second converter 122 may change the address value of the transport protocol in the IP address (eg, indicating the source bit) The value of the address and/or destination address) and the apostrophe (for example, the nickname of the Transmission Control Protocol (TCP) or the user datagram protocol (UDP)).

In at least one exemplary embodiment, the second converter 122 can support the NAT function and convert the public IP address to a private IP address and/or convert the private IP address to a public IP address. For example, when the communication device 10 performs tethering and/or operates as a router, the second converter 122 can convert the public IP address of the IP packet received via the network into a private IP address. The changed header can be stored again in the local memory 123.

The headers HD0 to HDN-1 may be changed by changing (eg, converting, generating a new header, etc.) the IP version of the first converter 121 and/or by changing the IP address value of the second converter 122, And the altered headers (eg, NHD0 to NHDN-1 (or NHDs)) can be stored (and/or copied) into the second memory 320. For example, the second memory 320 may be a shared area between the second area AR2 of the memory 300 shown in FIG. 1 (ie, the shared processor 100 and the like) and the application processor 200. In at least one exemplary embodiment, the changed header NHDs can be read from the local area memory 123, for example, in a DMA manner, and stored in the second memory 320. Meanwhile, the payloads of the IP packets PK0 to PKN-1 (for example, PL0 to PLN-1 (or PLs)) can be read from the first memory 310 in the DMA mode and stored in the second memory 320. Therefore, the IP packets PK0a to PKN-1a having the converted IP addresses can be stored in the second memory 320. The application processor 200 can access the second memory 320 and process the IP packets PK0a to PKN-1a having the translated addresses.

Although the pseudo-location conversion circuit 120 has been described as at least one exemplary embodiment of the receive path, when the address translation circuit 120 is a transmission path, the operations of the first converter 121 and the second converter 122 may be similar to the first The above operations of the converter 121 and the second converter 122. However, when the address conversion circuit 120 is a transmission path, the header of the IP packet stored in the second memory 320 by the application processor 200 can be read from the second memory 320 and stored in the local memory 123. And the first converter 121 and the second converter 122 can change IP addresses respectively included in the header. In this case, the second converter 122 can operate as a pre-processor. After the operation of the second converter 122 is completed, the first converter 121 can operate as a post processor. After the IP packet having the translated address is stored in the first memory 310, the IP packet can be transmitted to other devices via the network.

FIG. 3 is a diagram of a structure of an IP packet PK in accordance with at least one example embodiment.

Referring to FIG. 3, according to at least one exemplary embodiment, the IP packet PK may include, but is not limited to, a header HD and/or a payload PL and the like. The header HD may include an IP header H1 and/or a TCP header H2 (or a UDP header, etc.), and the payload PL may include a data DT that is provided to the application and/or generated by the application. In FIG. 2, the IP header H1 and the TCP header H2 of the IP packet PK may be stored in the local memory 123. The first converter 121 can change the IP header H1 to change the IP version, and the IP header H1 and the TCP header H2 can be changed such that the second converter 122 can convert the IP address.

4A and 4B illustrate IP headers of IP packets, in accordance with some example embodiments. Figure 4A shows the header of an IPv4 packet, and Figure 4B shows the basic header of an IPv6 packet.

Referring to FIG. 4A, the header H1_IPv4 of an IPv4 packet (hereinafter referred to as an IPv4 header) may include a version, an IP header length IHL, a service type ToS, a total length, an identifier, a flag, a fragment offset ( The corresponding fields of fragment offset), time-to-live, protocol, header checksum, source address, destination address, options, and padding are, but are not limited to, this. Each of the source address and the destination address may have a length of 32 bits, but is not limited thereto, and the length of the options and padding may be variable.

Referring to FIG. 4B, the basic header H1_IPv6 of an IPv6 packet (hereinafter referred to as an IPv6 header) may include a version, a traffic class, a flow label, a payload length, a next header, and a hop limit. , the source address, and the corresponding field of the destination address, but not limited to this. Each of the source address and the destination address may have a length of 128 bits, but is not limited thereto.

4A and 4B, the IPv4 header H1_IPv4 may include twelve basic fields and two optional fields, and the IPv6 header H1_IPv6 may include eight basic fields, but is not limited thereto. However, in addition to the basic header (ie, IPv6 header H1_IPv6), the IPv6 packet may further include an extension header. In the IPv6 header H1_IPv6, the next header field may refer to the type of the next header, and the like. The header that can be indicated in the next header can be an IPv6 extension header or a TCP (or UDP, etc.) header, which is an upper header. When the extension header is not used, the TCP (or UDP, etc.) header can be in the next header.

The IPv4 header H1_IPv4 and the IPv6 header H1_IPv6 may equally include fields for version, source address, destination address, and the like. However, as described above, the source address of the IPv6 header H1_IPv6 and the length of each of the destination addresses (ie, 128 bits) may be the source address of the IPv4 header H1_IPv4 and each of the destination addresses. Four times the length of the person (ie, 32 bits).

When converting the IPv4 header H1_IPv4 to the IPv6 header H1_IPv6, the IP header length IHL, identifier, flag, fragment offset, header checksum, and options included in the IPv4 header H1_IPv4 may be deleted. Fill in fields such as fields, and add fields for stream labels. Conversely, when converting the IPv6 header H1_IPv6 to the IPv4 header H1_IPv4, the field for the stream label can be deleted and can be added for the IP header length IHL, identifier, flag, fragment offset, header Check the fields for and, options, and padding. The fields for the service type ToS, the total length, the agreement, the time-to-live of the IPv4 header H1_IPv4 and the fields for the traffic class, the payload length, the next header, and the hop limit of the IPv6 header H1_IPv6 can be converted from each other.

The first converter 121 of the address translation circuit 120 explained with reference to FIG. 2 may convert the IPv4 header H1_IPv4 into an IPv6 header H1_IPv6 or convert the IPv6 header H1_IPv6 into an IPv4 header H1_IPv4.

FIG. 5 illustrates a TCP header of an IP packet in accordance with at least one example embodiment.

Referring to FIG. 5, the TCP header H2_TCP may include a source port, a destination port, a sequence number, an acknowledgement number, a data offset, a reserved field "Reserved", a 6-bit flag, Corresponding fields for window size, TCP checksum, urgent pointer, options, and/or padding. Similar to the TCP header H2_TCP, the UDP header as a transport protocol may include corresponding fields for source, destination, UDP length, and/or UDP checksum, and the like.

The second converter 122 of the address translation circuit 120 illustrated with reference to FIG. 2 may change the source and/or destination address values of the IP header (eg, IPv4 header H1_IPv4 or IPv6 header H1_IPv6) of FIGS. 4A and 4B and The source and/or destination nickname of the TCP header H2_TCP (or UDP header, etc.), and convert the private IP address to a public IP address and/or conversely convert the public IP address to a private IP address site.

FIG. 6A is a block diagram of an implementation example of a first converter 121 of the address translation circuit 120, and FIG. 6B is a first converter operating the FIG. 6A, in accordance with at least one exemplary embodiment, in accordance with at least one example embodiment. Flow chart of the method of 121. A case in which the first converter 121 converts the IPv6 header into an IPv4 header will be explained as an example.

Referring to FIG. 6A, the first converter 121 may include a first filter 11, an IP converter 12, and/or a first IP header checksum calculator 13, and the like. In at least one exemplary embodiment, the first filter 11, the IP translator 12, and/or the IP header collation and calculator 13 of the first converter 121 may be implemented by hardware logic circuitry, but are not limited thereto.

Referring to FIGS. 6A and 6B, the first converter 121 can read the header HD stored in the local memory 123 (S110). The first converter 121 can sequentially read the headers HD0 to HDN-1. As described above with reference to FIG. 3, the header HD may include an IP header H1 and a TCP header H2. In operation S110, the first converter 121 can read the IP header H1 from the local area memory 123. The first converter 121 can perform header format conversion on the read header HD.

The first filter 11 can analyze the read header HD and judge whether it is desirable and/or necessary to perform IP version conversion (S120). The first filter 11 can determine the IP version of the header HD based on desired and/or predetermined filter settings (eg, desired and/or preset fields) and determine if it is desirable and/or necessary to change The header format of the header HD. For example, the first filter 11 can confirm the version field of the header HD and determine that the header HD is an IPv6 header. The first filter 11 can determine whether the IPv6 header is to be converted to an IPv4 header based on the desired and/or preset different fields (eg, traffic class and/or destination address, etc.). For example, if it is determined based on the destination address that the IP packet is provided to an application configured to support IPv4, the first filter 11 may determine a header format that is expected and/or necessary to convert the header HD.

If the first filter 11 determines that it is desired and/or necessary for IP version conversion, the IP converter 12 may change the IP header format of the header HD (S130). To change the IP header format, IP translator 12 can select the field to be changed and change the selected field. The IP switcher 12 can be based on, for example, a stateless internet protocol/Internet control message protocol (IP/ICMP) conversion (SSIT), a network address translation-a protocol conversion (network address translation). -protocol translation, NAT-PT) and/or bump-in-the-stack (BIS) methods perform IP header format conversion.

Subsequently, the IP header checksum calculator 13 can update the IP header checksum (S140). In operation S130, since the IP header format is changed, the first IP header collation and calculator 13 may calculate an IP header checksum based on the IP header H1 having the changed format, and update based on the calculated value. IP header checksum.

For example, when the IPv6 header is converted to an IPv4 header, the first IP header checksum calculator 13 can calculate the IP header checksum and provide the calculated value to the header check and column of the IPv4 header. Bit. Therefore, the IP header checksum can be updated, and the IP header format conversion, that is, the IP version conversion can be completed.

The first converter 121 may store the header NHD having the changed header format in the local memory 123 (S150). For example, the first converter 121 can store the header NHD converted from the IPv6 header to the IPv4 header in the local memory 123.

In operation S120, if the first filter 11 determines that an IP version conversion is undesirable and/or unnecessary, the header format conversion to the header HD may be ended. The header format conversion including the above-described operations S110 to S150 can be subsequently performed on the headers HD0 to HDN-1 stored in the local memory 123. Although FIG. 6A shows a case in which the IPv6 headers HD0 to HDN-1 of the local area memory 123 are converted into new IPv4 headers NHD0 to NHDN-1, the exemplary embodiments of the inventive concept are not limited thereto. As described above, the headers HD0 to HDN-1 can be converted as needed, and some of the headers HD0 to HDN-1 may not be converted.

The converted headers HD0 to HDN-1 stored in the local memory 123 can be copied to the first memory (see 310 in FIG. 2) and/or the second memory in a DMA manner (see FIG. 2 320). In addition, IP address translation can be performed on the converted headers HD0 to HDN-1 by the second converter (see 122 in Fig. 2).

FIG. 7A is a block diagram of an implementation example of a second converter 122 of the address translation circuit 120, and FIG. 7B is a second converter of the operation of FIG. 7A, in accordance with at least one exemplary embodiment, in accordance with at least one example embodiment. Flow chart of the method of 122.

Referring to FIG. 7A, the second converter 122 may include, but is not limited to, the second filter 21, the address converter 22, the IP header collation and the calculator 23, and/or the TCP header collation and the calculator 24, and the like. The second filter 21, the address translator 22, the IP header checksum calculator 23, and the TCP header checksum calculator 24 may be implemented using hardware logic circuits, but are not limited thereto. In at least one exemplary embodiment, the IP header checksum calculator 23 and the TCP header checksum calculator 24 may be implemented by a header check and calculation circuit, but are not limited thereto.

Referring to FIGS. 7A and 7B, the second converter 122 can read the header HD stored in the local memory 123 (S210). The second converter 122 can sequentially read the headers HD0 to HDN-1. As described above with reference to FIG. 3A, the header HD may include an IP header H1, a TCP header H2, and the like. In operation S210, the second converter 122 may read the IP header H1, the TCP header H2, and the like from the local area memory 123.

The second converter 122 can perform the operations described below and convert the IP address included in the read header HD. The second converter 122 can convert the public IP address of the IP packet received via the network into a private IP address and/or an IP packet to be transmitted via the network (ie, an IP packet provided by the application processor) The private IP address is translated into a public IP address for the network.

The second filter 21 can analyze the read header HD and judge whether it is desired and/or necessary to perform IP address conversion (for example, conversion of an address value or the like) (S220). The second filter 21 may filter the header HD based on the desired and/or predetermined filter settings and determine if IP address translation is desired and/or necessary. In at least one exemplary embodiment, a source address and/or a destination address of an IP address may be included in the filter settings. For example, when the source address of an IP packet to be transmitted over the network is not included in a public IP address area (eg, IP address range and/or subnet mask) for the network, The second filter 21 can determine the desired and/or necessary IP address translation. In another example, IP packets received over the network are not included in the local IP address region (eg, IP address range and/or subnet mask) provided by communication device 10 of FIG. At the destination address, the second filter 21 can determine the desired and/or necessary IP address translation.

If the second filter 21 determines that it is desired and/or necessary to perform IP address translation, the address translator 22 can change the address value and the nickname included in the header HD (S230). As described with reference to Figures 4A through 5, in the fields of the source and/or destination addresses for the IP header (e.g., IPv4 header H1_IPv4 of Figure 4A or IPv6 header H1_IPv6 of Figure 4B) The address value is included, and an apostrophe may be included in the field of the source or destination for the TCP header or UDP header (eg, TCP header H2_TCP of Figure 5). The address translator 22 can change the source address value and source nickname and/or change the destination address value and destination nickname. Thus, address translator 22 can convert the public IP address to a private IP address and/or convert the private IP address to a public IP address. The address translator 22 may store the relationship between the IP address and the translated IP address in the translation table, i.e., the relationship between the private IP address and the public IP address.

FIG. 8 illustrates a conversion table TT in accordance with at least one example embodiment.

Referring to FIG. 8, the conversion table TT may include a public IP address PUA and a private IP address PRA that may correspond to each other. For example, a private IP address PRA having an address value of "10.0.0.2" and an nickname "3327" may correspond to a public IP address PUA having an address value of "135.26.32.7" and an nickname "5003". . The private IP address PRA having the address value "10.0.0.3" and the nickname "3327" may correspond to the public IP address PUA having the address value "135.26.32.7" and the nickname "5002". The address translator 22 can generate and use the conversion table TT during IP address translation.

Referring back to FIGS. 7A and 7B, the IP header checksum calculator 23 may update the IP header checksum, and the TCP header checksum calculator 24 may update the TCP header checksum (or UDP header checksum, etc.) ( S240). However, when the header HD is an IPv6 header, the update of the IP header checksum may not be performed.

In operation S230, since the address value is changed, the IP header collation and calculator 23 may calculate the IP header checksum based on the IP header including the changed address value, and update the IP standard based on the calculated value. Head check and. Further, in operation S230, since the apostrophe is changed, the TCP header collation and calculator 24 may calculate the TCP header checksum based on the TCP header including the changed apostrophe, and update the TCP flag based on the calculated value. Head check and. Therefore, IP conversion can be completed.

The second converter 122 may store the header NHD having the changed IP address value in the local memory 123 (S250). For example, the second converter 122 can again change the IP address value from the public IP address to the header of the private IP address. The NMD or IP address value is reversed from the private IP address to the public IP address. The header NHD is stored in the local memory 123.

Meanwhile, in operation S220, if the second filter 21 determines that the IP address conversion is undesired and/or unnecessary, the IP address conversion to the header HD may be ended. The IP address conversion (i.e., header conversion) including the above operations S210 to S250 can be sequentially performed (or performed in parallel) on the headers HD0 to HDN-1 stored in the local memory 123. Although FIG. 7A shows a case in which the headers HD0 to HDN-1 of the local memory 123 are converted into new headers HD0 to HDN-1 having converted IP addresses, an exemplary embodiment of the inventive concept is not Limited to this. As described above, the headers HD0 to HDN-1 can be converted as needed, and some of the headers HD0 to HDN-1 may not be converted.

The headers HD0 to HDN-1 stored in the local memory 123 can be stored in the first memory (refer to 310 in FIG. 2) and/or the second memory (refer to 320 in FIG. 2) and/or Alternatively, the header format conversion may be performed on the headers HD0 to HDN-1 stored in the local memory 123 by the first converter (refer to 121 in FIG. 1).

9A and 9B are diagrams illustrating a method of converting an IP address of a second converter, in accordance with some example embodiments. Figure 9A shows the conversion of the private IP address into a public IP address in the transmission path, and Figure 9B shows the conversion of the received public IP address into a private IP address in the receive path.

Referring to FIG. 9A, the source IP address S of the IP packet received from the host may be a private IP address having an address value of "10.0.0.2" and an nickname "3327", and the destination IP address D may have The address value "128.119.40.186" and the public IP address of the nickname "80". The second converter 122 (eg, the second converter) when the source IP address S does not correspond to a common IP address area (eg, IP address range and/or subnet mask) provided by a particular network An address translator of 122 (refer to 22 in FIG. 7A) can perform an IP address translation operation of converting the source IP address S into a public IP address.

The second converter 122 can change the address value "10.0.0.2" of the source IP address S and the nickname "3327" to the address value "135.26.32.7" and the nickname "5003", respectively, and the source IP bit. The address S is converted to a public IP address. The private IP address and its corresponding public IP address can be stored in the conversion table TT. An IP packet having a translated source IP address S' and a destination IP address D can be transmitted to a destination (e.g., a server or another electronic device, etc.) via the network.

Referring to FIG. 9B, the source IP address S of the IP packet received from the network may be a public IP address having an address value of "128.119.40.186" and an nickname "80", and the destination IP address D may have The address value "135.26.32.7" and the public IP address of the nickname "5003". When the destination IP address D does not correspond to a private IP address area (eg, IP address range and/or subnet mask) provided by the local area network, the second converter 122 may perform the common IP bit. The IP address translation operation is translated into a private IP address.

The second converter 122 can change the address value "135.26.32.7" of the destination IP address D and the nickname "5003" to the address value "10.0.0.2" and the nickname "3327", respectively, with reference to the conversion table TT. The destination IP address D is converted to a source IP address. The IP packet with the translated destination IP address D' and the source IP address S can be transmitted to the host.

FIG. 10 is a block diagram of an address translation circuit 120a in accordance with at least one exemplary embodiment.

Referring to FIG. 10, the address conversion circuit 120a may include, but is not limited to, the local area memory 123, the first converter 121a, the second converter 122a, and/or the header collation and the calculator 123a.

The first converter 121a may include a first filter 11 and/or an IP converter 12 and the like. The operations of the first filter 11 and the IP converter 12 of the first converter 121a may be the same as those of the first filter 11 and the IP converter 12 shown in FIG. 6A. Further, the second converter 122a may include a second filter 21 and/or an address converter 22 and the like. The operation of the second filter 21 of the second converter 122a and the address converter 22 may be the same as the operation of the second filter 21 and the address converter 22 shown in FIG. 7A.

When the first converter 121a converts the format of the IP header and/or when the second converter 122a converts the IP address, the header checksum calculator 123a may update the header checksum.

The header checksum calculator 123a may include an IP header check and calculator 31 and/or TCP header checksum calculator 32 and the like. When the first converter 121a converts the format of the IP header, the IP header checksum calculator 31 can calculate the IP header checksum based on the converted IP header having the format, and update the TCP header checksum and .

Furthermore, when the second converter 122a converts the IP address, the IP header checksum calculator 31 can update the IP header checksum based on the IP header including the changed address value, and the TCP header checksum is calculated. The processor 32 may calculate the TCP header checksum and update the TCP header checksum based on the TCP header including the changed apostrophe.

In at least one exemplary embodiment, each of the first converter 121a and the second converter 122a of the address translation circuit 120a may not include a header check and a calculator, but an additional header check and calculator 123a The header checksum may be calculated during the header format conversion of the first converter 121a and during the IP address translation of the second converter 122a, but the exemplary embodiments are not limited thereto.

FIG. 11 is a block diagram of a communication processor 100a in accordance with at least one example embodiment.

Referring to FIG. 11, the communication processor 100a may include at least one processor 110, a random access memory (RAM) 130, a data machine 150, an address conversion circuit 120, a DMA controller 140, and/or a memory interface 160, etc., but The exemplary embodiments are not limited thereto. Further, the communication processor 100a may further include other components. In at least one exemplary embodiment, communication processor 100a may be implemented by a single chipset, but is not limited thereto. The components of communication processor 100a can transmit and receive data via bus bar 170.

The processor 110 can control all operations of the communication processor 100a and can be implemented by a central processing unit (CPU), a microprocessor (MP), or a digital signal processor (DSP). In at least one example embodiment, processor 110 may be implemented by a multi-core processor (eg, a dual-core processor or a quad-core processor) or may be a multi-processor.

The RAM 130 can be used as an operation memory, a buffer memory, and/or a cache memory or the like. For example, a software or firmware for controlling the communication processor 100a can be loaded to the RAM 130. The RAM 130 may be implemented by volatile memory (eg, DRAM and SRAM, etc.) and/or resistive memory (eg, PRAM, MRAM, FeRAM, ReRAM, etc.).

The data machine 150 can convert the IP packet into a signal suitable for transmission via the network and/or convert the signal received via the network into an IP packet. The data machine 150 can encode and modulate the IP packet and convert the IP packet into a transmission signal. In addition, the data machine 150 can demodulate and decode the received signal received via the network and convert the received signal into an IP packet. The data machine 150 can amplify and filter the signal and communicate with a radio frequency (RF) chip configured to convert the frequency of the signal. The RF chip can transmit the transmission signal to the network via the antenna and/or receive the received signal from the network.

The memory interface 160 can transfer data to and/or from the memory 300 by the control of the processor 110 and/or the DMA controller 140, but is not limited thereto.

The memory 300 can be implemented by a device other than a communication processor (e.g., communication chip) 100a (e.g., a memory chip or a memory module, etc.). However, exemplary embodiments of the inventive concept are not limited thereto. In at least one exemplary embodiment, memory 300 can be an embedded memory of communication processor 100a. IP packets received via data machine 150 or to be received via data machine 150 may be stored in memory 300. In at least one exemplary embodiment, the communication processor 100a and the application processor (refer to 200 in FIG. 1) can access the memory 300. The memory 300 can include a dedicated area of the communication processor 100a, a shared area, and a dedicated area of the application processor 200.

The DMA controller 140 can support data transfer between components of the communications processor 100a and control the transfer of data directly between components of the communications processor 100a without the intervention of the processor 110. In at least one exemplary embodiment, the DMA controller 140 may transmit the header of the IP packet stored in the memory 300 to the address translation circuit 120 and/or transmit the header converted by the address translation circuit 120 to the memory. Body 300. In addition, the DMA controller 140 can transmit the payload of the IP packet in a plurality of areas of the memory 300 (eg, a dedicated area of the communication processor 100a, a shared area, and a dedicated area of the application processor 200).

The address translation circuit 120 can convert the network address of the IP packet transmitted and received via the network. The address conversion circuits 120 and 120a explained with reference to FIGS. 2 and 10 can be applied to the communication processor 100a.

The address conversion circuit 120 can receive the header of the IP packet stored in the memory 300 by the control of the DMA controller 140 and convert the network address included in the header. The address translation circuit 120 can convert the format of the header (i.e., the IP version) or perform IP address translation.

When the address conversion circuit 120 operates as a reception path, the address conversion circuit 120 can convert the format of the header and then perform IP address translation. When the address translation circuit 120 operates as a transmission path, the address conversion circuit 120 can perform IP address translation and then convert the format of the header. The address translation circuit 120 can store the converted header in the shared area of the memory 300 (or the memory shared with the application processor) and/or convert the header by the control of the DMA controller 140. It is stored in a dedicated area of the communication processor 100a. For example, when the address translation circuitry 120 operates as a receive path, the address translation circuitry 120 can store the converted headers in a shared area of the memory 300 such that the application processor can use the converted headers. When the address translation circuit 120 operates as a transmission path, the address conversion circuit 120 can store the converted header in a dedicated area of the communication processor 100a included in the memory 300 so that it is provided by the application processor and The IP packet including the converted header can be transmitted to the network via the data machine 150.

As described above, the address translation circuit 120 of the communication processor 100a can convert the network address of the IP packet before the IP packet received from the network is supplied to the application processor (refer to 200 in FIG. 1). In addition, the address translation circuit 120 of the communication processor 100a can convert the network address of the IP packet before the IP packet provided by the application processor 200 is transmitted to the network.

FIG. 12 is a block diagram of a communication device 10a in accordance with at least one example embodiment.

Referring to FIG. 12, the communication device 10a can transmit data (eg, IP packets) to at least one electronic device 30 and/or server 40 and the like via at least one electronic device 30 and/or via a network (eg, global network) 20. Or the server 40 or the like receives the data (for example, an IP packet). The communication device 10a can also operate as a router. The communication device 10a can transmit the IP packet received via the network 20 to another electronic device 50 via a local area network path. In addition, the communication device 10a can transmit the IP packets received from the other electronic devices 50 to the electronic device 30 or the server 40 via the network 20.

The communication device 10a may include, but is not limited to, the communication processor 100, the application processor 200, the memory 300, the input/output (I/O) component 400, and/or the DMA controller 500, and the like. Further, the communication device 10a may further include other components. The components of the communication device 10a can transmit and receive data via the bus bar 600.

The input/output component 400 can provide a user interface and include an input unit (eg, a touchpad, a keypad, and/or an input button, etc.) and/or an output unit (eg, a display and a speaker, etc.).

The DMA controller 500 can support data transfer between components of the communication device 10a and control the transfer of data directly between components of the communication device 10a without the intervention of the application processor 200. In at least one exemplary embodiment, DMA controller 500 can control the transmission of IP packets between communication processor 100, application processor 200, and memory 300. In addition, the DMA controller 500 can transmit the header of the IP packet stored in the memory 300 to the address conversion circuit 120 of the communication processor 100 and/or convert the header converted by the address conversion circuit 120 to the memory 300. . In at least one example embodiment, each of communication processor 100 and application processor 200 can include a DMA controller.

The network address of the IP packet received via the network 20 can be converted, and the IP packet including the converted network address can be stored in the memory 300. The communications processor 100 can translate the network address of the IP packet into an address system that is identifiable by the application 202 of the application processor 200 or other electronic device 50. The application processor 200 can read an IP packet including the converted network address from the memory 300, and the application 202 can process the IP packet. Additionally, other electronic devices 50 may process IP packets including translated network addresses via local area network path 60.

In addition, the communication processor 100 can convert the network address of the IP packet provided by the application processor 200 and/or other electronic device 50 into an address system conforming to the network 20, and will include the converted network address. The IP packet is transmitted to the network 20.

In communication device 10a in accordance with at least one example embodiment, communication processor 100 may convert the network address such that application processor 200 may not need to perform additional network address translation. Therefore, the processing and/or memory load of the application processor 200 can be reduced and/or can become more efficient, and the performance of the communication device 10a is improved.

Figure 13A illustrates the movement of an IP packet in a communication device in accordance with at least one example embodiment. Fig. 13B shows the movement of the IP packet in the communication device according to the comparative example. 13A and 13B illustrate the movement of an IP packet received from the network in a hardware area (e.g., communication processor CP) and a software area (e.g., application processor AP).

Referring to FIG. 13A, an IP packet can be received via the network (S11), and the received IP packets PK0 to PKN-1 can be stored in the first memory 310 of the hardware area.

The address conversion circuit 120 can convert the network address of the IP packet (S12). As described with reference to Figures 2 through 9B, the address translation circuitry 120 can receive the header of the IP packet and convert the header format or IP address. Address translation circuitry 120 may copy (or store) IP packets (eg, IP packets NPK0 through NPKN-1) including the translated network address to second memory 320 (eg, shared memory) (or copy) Or stored in the second memory 320) (S13).

The IP packets NPK0 to NPKN-1 can then be processed by the software area. The driver 203 can copy the IP packets NPK0 to NPKN-1 stored in the second memory 320 to the socket buffer (S14). For example, the socket buffer can be part of the third memory 330 that is dedicated to the application processor AP.

The application 202 can read the IP packets NPK0 to NPKN-1 from the socket buffer (S15).

Referring to FIG. 13B, an IP packet can be received via the network (S21), and the received IP packets PK0 to PKN-1 can be stored in the first memory 310a of the hardware area. The IP packets PK0 to PKN-1 may be copied to the second memory 320a (for example, shared memory) (S22).

Thereafter, the IP packets PK0 to PKN-1 can be processed by the software area. The drive 203a can copy the IP packets PK0 to PKN-1 stored in the second memory 320a to the socket buffer (S23). For example, the socket buffer may be part of the third memory 330a dedicated to the application processor AP, but is not limited thereto. Meanwhile, the address systems of the IP packets PK0 to PKN-1 may not conform to the address system of the application 202a configured to process the IP packets PK0 to PKN-1. Thus, the header converter 204a (e.g., resident program) can read the IP packets PK0 through PKN-1 (S24) from the socket buffer and/or convert the network addresses of the IP packets PK0 through PKN-1 (S25). The header converter 204a and/or the driver 203a may recopy the IP packets NPK0 to NPKN-1 having the converted network address to the socket buffer (S26). Subsequently, the application 202a can read the IP packets NPK0 to NPKN-1 from the socket buffer (S27).

In comparing the movement of the IP packet in the communication device shown in FIG. 13A according to at least one exemplary embodiment with the movement of the IP packet in the communication device shown in FIG. 13B according to the comparative example, in accordance with at least one example In the communication device of the embodiment, the hardware-based address conversion circuit 120 can perform network address translation in advance so that the application processor AP does not need to perform address conversion. Therefore, the processing and/or memory load of the application processor AP can be reduced. In addition, the number of times an IP packet is copied to the memory can be reduced, thereby increasing the processing speed of the IP packet.

FIG. 14 is a block diagram of an application processor 200a in accordance with at least one example embodiment.

Since the functions of the data machine are integrated in the application processor 200a, the application processor 200a shown in FIG. 14 can be referred to as a ModAP.

Referring to FIG. 14, the application processor 200a may be implemented by a system-on-chip (SoC), and may include a central processing unit (CPU) 210, a random access memory (RAM) 220, a DMA controller 230, and a data machine. 240, address conversion circuit 250 and/or memory controller 260, and the like. In addition, the application processor 200a may further include other components such as a power management unit, a display controller, and/or a sensor. The components of the system wafer can transmit and receive data via bus 270.

The CPU 210 can control all operations of the application processor 200a. The CPU 210 can process and/or execute at least one program (e.g., computer readable instructions, etc.) and/or material stored in the RAM (or ROM) 220 and control the operation of the components of the application processor 200a. In at least one example embodiment, CPU 210 may be implemented by a multi-core processor, a plurality of interconnected processors, a distributed processing system, and/or a cloud computing processing system, or the like. The multi-core processor can be a single computing component that includes at least two separate cores.

The RAM 220 can temporarily store programs (eg, operating systems, applications, their computer readable instructions, etc.), materials, or instructions. For example, the programs and/or data stored in the memory 300 can be temporarily stored in the RAM 220 by the control of the CPU 210 or the boot code. The RAM 220 can be implemented by DRAM, SRAM, or the like.

The DMA controller 230 can support data transfer between components of the application processor 200a and control the transfer of data directly between components of the application processor 200a without the intervention of the CPU 210.

To perform wired and/or wireless communication, the data machine 240 can change the data to be transmitted in accordance with the wired and/or wireless environment and store the received data again. The data machine 240 can perform digital communication with the RF chip 245, but is not limited thereto.

The RF chip 245 can convert the high frequency signal received via the antenna into a low frequency signal and transmit the converted low frequency signal to the data machine 240. In addition, the RF chip 245 can convert the low frequency signal received from the data machine 240 into a high frequency signal and transmit the converted high frequency signal to the wireless network via the antenna. In addition, RF chip 245 can amplify and/or filter the signal.

In addition, the operations of the data machine 240, the address conversion circuit 250, and the memory controller 260 may be the same as or similar to the operations of the data machine 150, the address conversion circuit 120, and the memory interface 160 shown in FIG. Therefore, it will not be repeated.

As described above, the application processor 200a in accordance with at least one example embodiment may include some components (eg, data machine 240 and address translation circuitry 250) that are configured to perform communication functions. In this case, since the address conversion circuit 250 performs network address conversion in advance, the CPU 210 may not need to perform address conversion. The load of the CPU 210 can be lowered, and the number of times the IP packet is copied to the memory 300 can be reduced, and thus the processing speed of the IP packet can be increased. Therefore, the performance of the application processor 200a can be improved.

While the invention has been particularly shown and described with reference to the embodiments of the present invention, it is understood that various changes in form and detail may be made without departing from the spirit and scope of the invention.

10, 10a‧‧‧ communication device

11‧‧‧First filter

12‧‧‧IP converter

13‧‧‧First IP Header Check and Calculator

20‧‧‧Network

21‧‧‧Second filter

22‧‧‧ Address Converter

23‧‧‧IP header check and calculator

24‧‧‧TCP header check and calculator

30‧‧‧Electronic devices

31‧‧‧IP header check and calculator

32‧‧‧TCP header check and calculator

40‧‧‧Server

50‧‧‧Other electronic devices

60‧‧‧LAN Road

100‧‧‧Communication Processor/Common Processor

100a‧‧‧Communication processor

110‧‧‧ processor

120, 120a‧‧‧ address conversion circuit

121, 121a‧‧‧ first converter

122, 122a‧‧‧ second converter

123‧‧‧ local memory

123a‧‧ Header Check and Calculator

130‧‧‧ Random Access Memory (RAM)

140‧‧‧DMA controller

150‧‧‧Data machine

160‧‧‧ memory interface

170‧‧‧ busbar

200, 200a‧‧‧ application processor

201‧‧‧Operating System (OS)

202, 202a‧‧‧Application

203, 203a‧‧‧ drive

204a‧‧‧head converter

210‧‧‧Central Processing Unit (CPU)

220‧‧‧ Random Access Memory (RAM)

230‧‧‧DMA controller

240‧‧‧Data machine

245‧‧‧RF (RF) wafer

250‧‧‧ address conversion circuit

260‧‧‧ memory controller

270‧‧ ‧ busbar

300‧‧‧ memory

310, 310a‧‧‧ first memory

320, 320a‧‧‧ second memory

330, 330a‧‧‧ third memory

400‧‧‧Input/Output (I/O) components

500‧‧‧DMA controller

600‧‧‧ busbar

AP‧‧‧Application Processor

AR1‧‧‧First District

AR2‧‧‧Second District

AR3‧‧‧ Third District

CP‧‧‧Communication Processor

D, D’‧‧‧ destination IP address

DT‧‧‧Information

H1‧‧‧IP header

H1_IPv4‧‧‧IPv4 header

H1_IPv6‧‧‧IPv6 header

H2‧‧‧TCP header

H2_TCP‧‧‧TCP header

HD‧‧‧ heading

HD0, HD1, HDN-1, HDs‧‧‧ headers

IHL‧‧‧IP header length

NHD‧‧‧ heading

NHD0, NHD1, NHDN-1, NHDs‧‧‧ altered headers

NPK0, NPK1, NPKN-1‧‧‧ IP packets

PK‧‧‧IP packet

PK0, PK1, PKN-1, PK0a, PK1a, PKN-1a‧‧‧ IP packets

PL‧‧‧ payload

PL0, PL1, PLN-1, PLs‧‧‧ payload

S, S’‧‧‧ source IP address

S11, S12, S13, S14, S15‧‧‧ operations

S21, S22, S23, S24, S25, S26, S27‧‧ operation

S110, S120, S130, S140, S150‧‧‧ operations

S210, S220, S230, S240, S250‧‧‧ operations

TT‧‧‧ conversion table

ToS‧‧‧ Service Type

PRA‧‧‧ private IP address

PUA‧‧‧ public IP address

Various exemplary embodiments of the inventive concept will be more clearly understood from the following detailed description.

FIG. 1 is a block diagram of a communication device in accordance with at least one example embodiment.

2 is a diagram showing the operation of an address translation circuit in accordance with at least one example embodiment.

3 is a diagram of the structure of an Internet Protocol (IP) packet, in accordance with at least one example embodiment.

4A and 4B illustrate IP headers of IP packets, in accordance with some example embodiments.

FIG. 5 illustrates a transmission control protocol (TCP) header of an IP packet in accordance with at least one example embodiment.

FIG. 6A is a block diagram of an implementation example of a first converter of an address translation circuit in accordance with at least one example embodiment.

FIG. 6B is a flowchart of a method of operating the first converter of FIG. 6A, in accordance with at least one example embodiment.

FIG. 7A is a block diagram of an implementation example of a second converter of an address translation circuit in accordance with at least one example embodiment.

FIG. 7B is a flowchart of a method of operating the second converter of FIG. 7A, in accordance with at least one example embodiment.

FIG. 8 illustrates a conversion table in accordance with at least one example embodiment.

9A and 9B are diagrams illustrating a method of converting an IP address of a second converter, in accordance with at least one example embodiment.

FIG. 10 is a block diagram of an address translation circuit in accordance with at least one example embodiment.

11 is a block diagram of a communication processor in accordance with at least one example embodiment.

Figure 12 is a block diagram of a communication device in accordance with at least one example embodiment.

Figure 13A illustrates the movement of an IP packet in a communication device in accordance with at least one example embodiment.

Figure 13B illustrates the movement of an IP packet in a communication device in accordance with at least one example embodiment.

Figure 14 is a block diagram of an application processor in accordance with at least one example embodiment.

Claims (25)

A communication system configured to transceive at least one packet via a network, the communication system comprising: a modem circuit configured to transform the at least one packet into a transmission signal for transmission to the network, and Demodulating the signal received from the network into the at least one packet; a address conversion circuit configured to convert a network address of the at least one packet, and converting the network address of the at least one packet includes: Receiving, from the external memory in which the at least one packet is stored, a header of the at least one packet, and storing the header of the at least one packet in the embedded memory, Converting a format of the header of the at least one packet, and Translating the address included in the header of the at least one packet. The communication system of claim 1, wherein the address conversion circuit comprises a first converter circuit and a second converter circuit. The communication system of claim 1, wherein the address conversion circuit is further configured to: self-reference the header of the at least one packet from a version of a version according to an Internet Protocol (IP) The format is changed to a second format according to another version of the internet protocol. The communication system of claim 1, wherein the address conversion circuit is further configured to convert the Internet Protocol (IP) address of the at least one packet from a public internet protocol address to A private internet protocol address, or a translation of the Internet Protocol address self-service internet protocol address into a public internet protocol address. For example, the communication system described in claim 1 of the patent scope, wherein Depending on the address conversion circuit operating as a receive path, the address translation circuit is further configured to store the changed header in shared memory; The shared memory is configured to be shared between the address translation circuitry and an external application processor. The communication system of claim 5, wherein the address conversion circuit is further configured to store the payload of the at least one packet directly in the shared memory without storing the payload In the embedded memory. The communication system of claim 1, wherein the address conversion circuit is further configured to: Determining whether a format conversion is desired based on the expected first filter item; Changing at least some of the plurality of fields included in the header to correspond to a target internet protocol version in response to the desired format conversion; and The internet protocol header check and field of the header are updated based on the converted format. The communication system of claim 1, wherein the address conversion circuit is further configured to: Determining whether an address conversion is desired based on the expected second filter item; Changing an internet protocol (IP) address value and an apostrophe included in the header based on a result of determining whether the address conversion is desired; and The internet protocol header check and field of the header and the transport protocol header check and field are updated based on the changed internet protocol address value and the changed apostrophe. The communication system of claim 1, wherein the address conversion circuit is further configured to preprocess the at least one packet and to operate according to the address conversion circuit operating as a receiving path At least one packet is post-processed. The communication system of claim 1, wherein the address conversion circuit is further configured to preprocess the at least one packet and to operate according to the address conversion circuit operating as a transmission path At least one packet is post-processed. A communication device comprising: Memory; a communications processor configured to convert a network address of the first packet received via the network and to store a second packet including the converted network address in the memory; An application processor configured to receive the second packet from the memory, drive an application, and process the second packet. The communication device according to claim 11, wherein The first packet includes a header and a payload, and the first packet is stored in the first dedicated memory; The communication processor includes an internal buffer; The communication processor is further configured to copy the header of the first packet to the internal buffer and convert the network address included in the header of the first packet . The communication device of claim 11, wherein the communication processor further comprises: An embedded memory configured to store a header of the first packet; a first address translation circuit configured to convert an Internet Protocol (IP) version of an internet protocol header included in the header of the first packet; A second address translation circuit configured to translate an internet protocol address included in the header of the first packet. The communication device of claim 13, wherein the first address conversion circuit is further configured to convert an IPv4 header included in the header of the first packet into an IPv6 header. Or converting the IPv6 header included in the header of the first packet into an IPv4 header. The communication device of claim 13, wherein the second address conversion circuit is further configured to convert a public internet protocol address included in the header of the first packet into Private internet protocol address. The communication device of claim 13, wherein the second address conversion circuit is further configured according to the first address conversion circuit performing an internet protocol version conversion operation on the first packet. The first packet is paired to perform an internet protocol address translation operation. The communication device of claim 11, wherein the application processor is further configured to copy the second packet stored in the memory to a second dedicated memory. An application processor includes a communication function, and the application processor includes: At least one processor configured to execute an application; a memory configured to be accessed by the at least one processor; An address translation circuit configured to convert a network address included in a first header of at least one packet received from the network into an address system conforming to the application, and to include the converted A second header of the network address is stored in the memory. An application processor as described in claim 18, wherein The address translation circuit includes a buffer configured to receive the first header of the at least one packet and store the first header; The address translation circuit is further configured to convert the format of the first header; Converting the address included in the first header. The application processor of claim 19, wherein the address translation circuit is further configured to update an Internet Protocol Header Checksum of the first packet. A network address translation method for a communication system, the method comprising: And storing, by the at least one processor, a first Internet Protocol (IP) packet received via the network, where the first Internet Protocol packet includes a header and a network address; Copying, by the at least one processor, the header of the first internet protocol packet stored in the first memory to an internal buffer of the at least one processor; Converting, by the at least one processor, the network address included in the first internet protocol packet; The second internet protocol packet is stored by the at least one processor, the second internet protocol packet including the header and the translated network address. The method of claim 21, wherein converting the network address comprises: Converting the current format of the header to a second format; Converting the current internet protocol address included in the header to a second internet protocol address. The method of claim 22, wherein converting the current format of the header comprises: Determining whether it is desired to convert the current format of the header based on the first filter setting; Converting, from the result of the determination, the format of the Internet Protocol Header of the header from a first format according to a version of the Internet Protocol to a second format according to another version of the Internet Protocol ;as well as Update the checksum of the Internet Protocol header. The method of claim 22, wherein converting the internet protocol address included in the header comprises: Determining whether it is desired to convert the internet protocol address based on the second filter setting; Changing an address value of an internet protocol header included in the header and an apostrophe of a transport protocol header included in the header based on a result of the determining; Updating the checksum of the Internet Protocol header and the checksum of the transport protocol header. For example, the method described in claim 21 of the patent scope further includes: Copying the second internet protocol packet to the socket buffer with the at least one processor; Executing an application with the at least one processor and processing the second internet protocol packet.