TWI791324B - Input and output circuit for wafer on wafer technology, and chip device using thereof - Google Patents

Abstract

An input and output circuit and a chip device are provided in the present disclosure. The input and output circuit includes multiple groups of first connection node groups, multiple groups of second connection node groups, multiple groups of connection structure groups, multiple input and output circuits, and a multiplex circuit. Multiple groups of first connection node groups and multiple groups of second connection node groups are disposed correspondingly. The multiple connection structure groups are arranged between the multiple first connection node groups and the multiple second connection node groups. The multiplex circuit utilizes a part or all of the first connection node groups, the second connection node groups, and the connection structure groups for signal transmission based on transmission states of the first connection node group, the second connection node group, and the connection structure group.

Description

Input and output circuits of wafer-to-wafer technology and chip devices using the same

The invention relates to an input and output circuit and a chip device, in particular to an input and output circuit and a chip device with high yield.

The demand for wafer on wafer and chip level circuits design is gradually increasing in today's semiconductor manufacturing process. As shown in FIG. 1 , the first circuit 2 and the second circuit 3 can be stacked through the input and output circuit 1 and disposed on the substrate SB. However, the wafer stacking process or the input and output circuit design of the chip-level circuit will affect the yield of the final product.

Therefore, how to provide a high-yield input and output circuit and chip device to overcome the above-mentioned defects has become one of the important issues to be solved by this business.

The technical problem to be solved by the present invention is to provide an input and output circuit suitable for connecting a first circuit and a second circuit, and the input and output circuit is arranged between the first circuit and the Between the second circuits, the input and output circuits include: multiple sets of first connection node groups, the multiple sets of first connection node groups are arranged on one side of the first circuit; multiple sets of second connection node groups, The multiple sets of second connection node groups are arranged on one side of the second circuit, the multiple sets of first connection node groups are set correspondingly to the multiple sets of second connection node groups, and each set of the first connection node groups A connection node group corresponds to one set of the second connection node group; multiple sets of connection structure groups are set between the multiple first connection node groups and the multiple second connection node groups; and a plurality of input An output driving circuit, each of the input and output driving circuits is electrically connected to a set of the first connection node group; a multiplexing circuit is connected to the plurality of input and output driving circuits; wherein, the multiplexing circuit according to the A transmission state of each of the plurality of first connection node groups, the plurality of second connection node groups, and the connection structure groups, using a part or all of the plurality of first connection node groups, the plurality of second connection node groups The two connection node groups and the connection structure group perform signal transmission.

The present invention also discloses a chip device, comprising: a first circuit, including a control circuit; a second circuit; and an input and output circuit, including: a plurality of first connection node groups; a plurality of second connection node groups ; A plurality of connection structure groups, the plurality of connection structure groups are respectively connected to the plurality of first connection node groups and the plurality of second connection node groups; a plurality of input and output drive circuits, arranged in the first circuit wherein, each of the input-output driving circuits is electrically connected to a group of the first connection node groups; and a multiplexing circuit is connected to the plurality of input-output driving circuits; wherein, the control circuit is electrically connected to the Multiplexing circuit; wherein, one connection structure group is set between each first connection node group and the corresponding second connection node group, and the plurality of first connection node groups are set in the first On one side of the circuit, the plurality of second connection node groups are arranged on one side of the second circuit, and the plurality of first connection node groups are set correspondingly to the plurality of second connection node groups; wherein, the The multiplexing circuit uses a part or all of the multiple sets of first connection nodes according to a transmission state of each of the multiple sets of first connection node groups, the multiple sets of second connection node groups, and the connection structure group group, the plurality of second connection node groups and the connection structure group perform signal transmission.

One of the beneficial effects of the present invention is that the input and output circuits and the chip device provided by the present invention can use multiplexing circuits to select connection nodes, connection structures or auxiliary connection nodes capable of normal transmission, instead of connections in abnormal transmission states. Nodes, connection structures, or auxiliary connection nodes to effectively improve the utilization rate of the connection circuits between wafer circuits, and thus improve the yield rate of chip devices.

In order to further understand the features and technical content of the present invention, please refer to the following detailed description and drawings related to the present invention. However, the provided drawings are only for reference and description, and are not intended to limit the present invention.

The following is an illustration of the implementation of the "input and output circuits and chip device" disclosed by the present invention through specific specific embodiments. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various modifications and changes can be made to the details in this specification based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only for simple illustration, and are not drawn according to the actual size, which is stated in advance. The following embodiments will further describe the relevant technical content of the present invention in detail, but the disclosed content is not intended to limit the protection scope of the present invention. In addition, the term "or" used herein may include any one or a combination of more of the associated listed items depending on the actual situation.

[first embodiment]

Please refer to FIG. 2 and FIG. 3 . FIG. 2 is a schematic diagram of the input and output circuits of the first embodiment of the present invention. FIG. 3 is another schematic diagram of the input and output circuits of the first embodiment of the present invention.

In this embodiment, an input and output circuit 1 is provided, which is suitable for connecting a first circuit 2 and a second circuit 3 . The input and output circuit 1 is arranged between the first circuit 2 and the second circuit 3 .

The input and output circuit 1 includes a plurality of first connection node groups 11 , a plurality of second connection node groups 12 , a plurality of connection structure groups 13 , a plurality of input and output driving circuits 14 and a multiplexing circuit 15 .

The first circuit 2 further includes a control circuit 21 and a storage circuit 22 . The control circuit 21 is electrically connected to the storage circuit 22 .

A plurality of first connection node groups 11 are arranged on one side of the first circuit 2 . A plurality of second connection node groups 12 are provided on one side of the second circuit 3 . Multiple sets of first connection node groups 11 and multiple sets of second connection node groups 12 are set correspondingly. Each set of first connection node groups 11 is correspondingly provided with a set of second connection node groups 12 . Multiple sets of connection structure groups 13 are arranged between multiple sets of first connection node groups 11 and multiple sets of second connection node groups 12 .

A plurality of input-output driving circuits 14 are arranged in the first circuit, and each input-output driving circuit 14 is electrically connected to a group of first connection node groups 11 . The multiplexing circuit 15 is connected to a plurality of input/output drive circuits 14 .

The multiplexing circuit 15 utilizes a part or all of the first connection node groups 11, the multiple groups The second connection node group 12 and the connection structure group 13 perform signal transmission.

That is, the control circuit 21 of the first circuit 2 is electrically connected to the multiplexing circuit 15 . The control circuit 21 provides a multiplexing control signal to the multiplexing circuit 15 according to the respective transmission states of the multiple first connecting node groups 11 , the multiple second connecting node groups 12 and the connecting structure group 13 . That is, the multiplexing circuit 15 receives the multiplexing control signal and opens or closes a plurality of connection channels of the multiplexing circuit 15 according to the multiplexing control signal, so as to utilize a part or all of the multiple first connection node groups 11, multiple A second connection node group 12 and a connection structure group 13 are used for signal transmission. The multiplexing circuit 15 includes a plurality of connection channels, which can be turned on and off by receiving the multiplexing control signal from the control circuit 21 . In addition, the control circuit 21 can also provide control signals to a plurality of input and output driving circuits 14 through the link channels opened by the multiplexing circuit 15 , so as to transmit the control signals to the second circuit 3 . That is, according to a transmission state of each of the multiple first connection node groups 11, the multiple second connection node groups 12, and the connection structure group 13, the control circuit 21 will send a multiplexing control signal to the multiplexing circuit 15 to utilize multiplexing The working circuit 15 closes one or more groups of first connection node groups 11, one or more groups of second connection node groups 12 and one or more groups of connection nodes in an abnormal transmission state. One or more corresponding input and output drive circuits 14 of the structure group 13 are used to turn on multiple sets of first connection node groups 11, multiple sets of second connection node groups 12 and multiple sets of connection structure groups 13 corresponding to the normal transmission state. Multiple sets of input and output drive circuits 14 for signal transmission.

That is, as shown in Figure 2, the first connection node group 11, the second connection node group 12 and the connection structure group 13 at the top are in the abnormal transmission state (NG state), and now the multiplexing circuit 15 can adjust other The first connection node group 11 , the second connection node group 12 and the connection structure group 13 replace the uppermost first connection node group 11 , the second connection node group 12 and the connection structure group 13 in the abnormal transmission state to transmit control signals.

As shown in FIG. 1 , each first connection node group 11 includes a first connection node 11A. Each second connection node group 12 includes one second connection node 12A. Each connecting structure group 13 includes a connecting structure 13A.

Furthermore, as shown in FIG. 3 , the first connection node group 11 includes a plurality of first connection nodes A, and the plurality of first connection nodes 11A of the first connection node group 11 are connected to each other. The second connection node group 12 includes a plurality of second connection nodes 12A, and the plurality of second connection nodes 12A of the second connection node group 12 are connected to each other. The connection structure group 13 includes a plurality of connection structures 13A.

As shown in FIG. 2 , in this embodiment, each input-output driving circuit 14 includes an output terminal. An impedance R is electrically connected to the output terminal of the input-output driving circuit 21 . As a voltage regulation impedance when outputting a control signal, it is generally called a pull-down impedance (pull low resistor). In other embodiments, the impedance R may not be set.

In this embodiment, the multiple input and output driving circuits 14 may be connected to a control circuit 21 or a logic circuit (not shown in the figure), which is not limited in the present invention. The second circuit 3 may include a plurality of memory circuits 31 , a control circuit or an application circuit, which are not limited in the present invention. That is, the circuits connected to the plurality of second connection nodes 12A provided in the second circuit 3 are not limited in any way.

That is, when the first circuit 2 and the second circuit 3 are stacked, they will be aligned and then connected: for example, wafer bonding (wafer bonding), wire bonding (wire bonding), so that the first circuit 2 Stacked setup with second circuit 3. When the circuit is aligned, the accuracy is very important. The distance between the first circuit 2 and the second circuit 3 will affect the yield rate of the input and output circuit 1 connecting the first circuit 2 and the second circuit 3 . In this embodiment, the connection structure 13A may be, for example, a wafer bonding structure or a wire bonding structure.

In this embodiment, the storage circuit 22 of the first circuit 2 is used for storing a channel state of the multiplexing circuit 15 . In electronic technology, the multiplexing circuit 15 may be a multiplexer (Data Selector) or a multiplexer (multiplexer, MUX). The multiplexing circuit 15 can respectively provide a channel for outputting from a plurality of analog or digital input signals.

In this embodiment, the first circuit 2 and the second circuit 3 may be a wafer-level circuit (wafer), a chip-level circuit (chip), or a general-scale circuit. The input and output driving circuit 21 is a CMOS IO logic.

The number of multiplexing circuits 15 can be adjusted according to actual needs, and the number of input and output drive circuits 14 can also be adjusted according to actual needs, which is not limited in the present invention. The storage circuit 22 is a flash memory, a read-only memory, a programmable read-only memory, an electrically rewritable read-only memory, an erasable programmable read-only memory or an electrically erasable Scalable read-only memory.

[Second embodiment]

Please refer to FIG. 4 . FIG. 4 is a schematic diagram of the input and output circuits of the second embodiment of the present invention.

Similarly, the structure of the input and output circuit 1 is similar to that of the input and output circuit 1', the main difference is that the input and output circuit 1' also includes a first auxiliary connection node 16, a second auxiliary connection node 17 and an auxiliary Connection structure 18.

The first auxiliary connection node 16 is arranged on one side of the first circuit 2 . The second auxiliary connection node 17 is provided on one side of the second circuit 3 . The first auxiliary connection node 16 and the second auxiliary connection node 17 are set correspondingly. The auxiliary connection structure 18 is disposed between the first auxiliary connection node 16 and the second auxiliary connection node 17 and connects the first auxiliary connection node 16 and the second auxiliary connection node 17 .

In this embodiment, the first auxiliary connection node 16 is also electrically connected to an I/O control circuit 14 , and the I/O control circuit 14 connected to the first auxiliary connection node 16 is also connected to the multiplexing circuit 15 .

Therefore, when one of the first connection node groups 11 of the plurality of first connection node groups 11, one of the corresponding plurality of second connection node groups 12 of the second connection node group 12 and the correspondingly set connection structure group are In an abnormal transmission state, the multiplexing circuit 15 can select the first auxiliary connection node 16 and the second auxiliary connection node 17 to transmit the first connection node group 11 and the corresponding second connection node in the abnormal transmission state A control signal for group 12.

In addition, at this time, the multiplexing circuit 15 can also adjust the other first connection node group 11, the second connection node group 12 and the connection structure group 13 to replace the first connection node group 11 and the second connection node group 12 in the abnormal transmission state. And connect the structure group 13 to transmit the control signal.

[Third embodiment]

Please refer to FIG. 5 and FIG. 6. FIG. 5 is a schematic diagram of a wafer device according to a third embodiment of the present invention. FIG. 6 is another schematic diagram of a wafer device according to a third embodiment of the present invention.

In this embodiment, a wafer device C1 is provided. The chip device C1 includes an input and output circuit C11, a first circuit C12 and a second circuit C13.

The first circuit C12 includes a control circuit C121.

The input and output circuit C11 includes a plurality of first connection node groups C111, a plurality of second connection node groups C112, a plurality of connection structure groups C113, a plurality of input and output driving circuits C114 and a multiplexing circuit C115.

Multiple sets of connection structure groups C113 are respectively connected to multiple sets of first connection node groups C111 and multiple sets of second connection node groups C112.

A plurality of input and output driving circuits C114 are disposed on one side of the plurality of first connection node groups C111.

An input-output driving circuit C114 is electrically connected to a set of first connection node groups C111.

The multiplexing circuit C115 is connected to multiple input and output driving circuits C114. The control circuit C121 is electrically connected to the multiplexing circuit C115.

A connection structure group C113 is provided between each first connection node group C111 and the corresponding second connection node group C112. A plurality of first connection node groups C111 are provided on one side of the first circuit C12. A plurality of second connection node groups are arranged on one side of the second circuit C13. Multiple sets of first connection node groups C111 are set corresponding to multiple sets of second connection node groups C112.

The multiplexing circuit C115 utilizes part or all of the multiple first connection node groups C111, the multiple second connection node groups C111, the multiple The second connection node group C112 and the connection structure group C113 perform signal transmission. The multiplexing circuit C115 includes multiple connection channels, which can be turned on and off by receiving a multiplexing control signal from the control circuit C121. That is, the multiplexing circuit C115 receives the multiplexing control signal and opens or closes multiple connection channels of the multiplexing circuit C115 according to the multiplexing control signal, so as to use part or all of the multiple sets of first connection node groups C111, multiple The second connection node group C112 and the connection structure group C113 perform signal transmission. In addition, the control circuit C121 provides control signals to a plurality of input and output drive circuits C114 through the connection channels opened by the multiplexing circuit C115, so as to transmit the control signals to the second circuit C13. That is, according to a transmission state of each of the multiple first connection node groups C111, the multiple second connection node groups C112, and the connection structure group C113, the control circuit C121 will send a multiplexing control signal to the multiplexing circuit C115 to utilize multiplexing Working circuit C115, close one or more groups of first connection node groups C111, one or more groups of second connection node groups C112 and one or more groups of nodes in abnormal transmission state One or more input/output drive circuits C114 corresponding to the connection structure group C113 are used to turn on multiple first connection node groups C111, multiple second connection node groups C112 and multiple connection structure groups C113 in the normal transmission state The corresponding multiple sets of input and output drive circuits C114 perform signal transmission.

That is, as shown in FIG. 4, the first connection node group C111, the second connection node group C112 and the connection structure group C113 at the top are in an abnormal transmission state (NG state), and at this moment the multiplexing circuit C115 can adjust other The first connection node group C111, the second connection node group C112 and the connection structure group C113 replace the uppermost abnormal transmission state first connection node group C111, second connection node group C112 and connection structure group C113 to transmit control signals.

As shown in FIG. 4 , each first connection node group C111 includes a first connection node C111A. Each second connection node group C112 includes a second connection node C112A. Each connection structure group C113 includes a connection structure C113A.

As shown in FIG. 5 , in this embodiment, a group of connection structure groups C113 is set between each group of first connection node groups C111 and a corresponding group of second connection node groups C112 . The first connection node group C111 includes a plurality of first connection nodes C111A. The plurality of first connection nodes C111A of the first connection node group C111 are connected to each other. The second connection node group C112 includes a plurality of second connection nodes C112A. The plurality of second connection nodes C112A of the second connection node group C112 are connected to each other. The connection structure group C113 includes a plurality of connection structures C113A.

In this embodiment, the first circuit C12 and the second circuit C13 may be a wafer-level circuit (wafer), a chip-level circuit (chip), or a general-scale circuit. The input and output driving circuit C114 is a CMOS IO logic.

In this embodiment, the I/O driving circuit C114 includes an output terminal. The output terminal of the input-output driving circuit C114 is electrically connected to an impedance R.

As shown in FIG. 1 , in this embodiment, each input-output driving circuit C114 includes an output terminal. An impedance R is electrically connected to the output terminal of the I/O driving circuit C114. As a voltage regulation impedance when outputting a control signal, it is generally called a pull-down impedance (pull low resistor). In other embodiments, the impedance R may not be set.

In this embodiment, the connection structure C113A of the connection structure group C113 is a wafer bonding structure (wafer bonding) or a wire bonding structure (wire bonding).

That is, when the first circuit C12 and the second circuit C13 are performing the stacking process, they will be connected after alignment: for example, wafer bonding (wafer bonding), wire bonding (wire bonding), so as to carry out the first circuit C12 Stacked setup with second circuit C13. When the circuit is aligned, the accuracy is very important. The distance between the first circuit C12 and the second circuit C13 will affect the yield rate of the input and output circuit C11 connecting the first circuit C12 and the second circuit C13. In this embodiment, the connection structure C113A may be, for example, a wafer bonding structure or a wire bonding structure.

That is, when the first circuit C12 and the second circuit C13 are performing the stacking process, they will be connected after alignment: for example, wafer bonding (wafer bonding), wire bonding (wire bonding), so as to carry out the first circuit C12 Stacked setup with second circuit C13. When the circuit is aligned, the accuracy is very important. The distance between the first circuit C12 and the second circuit C13 will affect the yield rate of the input and output circuit 1 connecting the first circuit C12 and the second circuit C13. In this embodiment, the connection structure C113A may be, for example, a wafer bonding structure or a wire bonding structure.

In addition, the number of the first circuit C12 and the second circuit C13 of the chip device C1 can also be adjusted according to actual needs, and the number of input and output circuits can be adjusted according to actual needs. The storage circuit C122 is a flash memory, a read-only memory, a programmable read-only memory, an electrically rewritable read-only memory, an erasable programmable read-only memory, or an electrically erasable Scalable read-only memory.

[Fourth embodiment]

Please refer to FIG. 7 . FIG. 7 is a schematic diagram of a wafer device according to a fourth embodiment of the present invention.

The main structure of the chip device C1' of this embodiment is similar to that of the chip device C1 of the third embodiment, the main difference is that the chip device C1' also includes a first auxiliary connection node C116', a second auxiliary connection node C117' and a Auxiliary connection structure C118'.

The first auxiliary connection node C116' is provided at one side of the first circuit C12'. The second auxiliary connection node C117' is provided at one side of the second circuit C13'. The first auxiliary connection node C116' and the second auxiliary connection node C117' are set correspondingly. The auxiliary connection structure C118' is disposed between the first auxiliary connection node C116' and the second auxiliary connection node C117', and connects the first auxiliary connection node C116' and the second auxiliary connection node C117'.

Among them, when one of the first connection node groups C111' of the multiple first connection node groups C111', one of the corresponding second connection node groups C112' of the multiple second connection node groups C112' and the correspondingly set connection structure The group C113' is in an abnormal transmission state, the multiplexing circuit C115' can connect the first auxiliary connection node C116' and the second auxiliary connection node C117 to the first connection node group C111' and the corresponding The second connection node group C112' is used to transmit a control signal of the first connection node group C111' and the corresponding second connection node group C112' in the abnormal transmission state.

In addition, at this time, the multiplexing circuit C115' can also adjust the other first connection node group C111', the second connection node group C112' and the connection structure group C113 to replace the uppermost abnormal transmission state first connection node group C111', The second connection node group C112' and the connection structure group C113' are used to transmit control signals.

The first circuit C12' also includes a storage circuit C122'. The control circuit C121' is electrically connected to the storage circuit C122'. A channel state of the multiplexing circuit C115' is stored in the storage circuit C122'. In electronic technology, the multiplexing circuit C115 may be a multiplexer (Data Selector) or a multiplexer (multiplexer, MUX). The multiplexing circuit C115 can respectively provide a channel for output from multiple analog or digital input signals.

Wherein, when each first connection node group C111' includes multiple first connection nodes C111A', the multiple first connection nodes C111A' of the first connection node group C111' are connected to each other. When each second connection node group C112' includes a plurality of second connection nodes C112A', the plurality of second connection nodes C112A' of the second connection node group C112' are connected to each other.

Similarly, in this embodiment, each input-output driving circuit C114' includes an output terminal. An impedance R is electrically connected to the output terminal of the input-output driving circuit C114'. As a voltage regulation impedance when outputting a control signal, it is generally called a pull-down impedance (pull low resistor). In other embodiments, the impedance R may not be set.

In this embodiment, multiple input and output drive circuits C114' can be connected to a control circuit 21 or a logic circuit (not shown in the figure), which is not limited in the present invention. The second circuit C13' may include a plurality of memory circuits C131', a control circuit or an application circuit, which are not limited in the present invention. That is, the circuits connected to the plurality of second connection nodes C112A' provided in the second circuit C13' are not limited in any way. In addition, the number of the first circuit C12 and the second circuit C13 of the chip device C1 can also be adjusted according to actual needs, and the number of input and output circuits can be adjusted according to actual needs.

[Advantageous Effects of Embodiment]

One of the beneficial effects of the present invention is that the input and output circuits and the chip device provided by the present invention can use the multiplexing circuit to close the connection node, connection structure or auxiliary connection node of abnormal transmission, and use the connection node of normal transmission state , connection structure or auxiliary connection node, so as to effectively improve the utilization rate of the connection circuit between the wafer circuits, and also improve the performance of the circuit or the chip device.

The content disclosed above is only a preferred feasible embodiment of the present invention, and does not therefore limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made by using the description and drawings of the present invention are included in the application of the present invention. within the scope of the patent.

1,1',C11,C11': Input and output circuits 2,2',C12,C12': the first circuit 3,3',C13,C13': the second circuit 11,11',C111,C111': the first connection node group 12,12',C112,C112': the second connection node group 13,13',C113,C113': connection structure group 14, 14', C114, C114': input and output drive circuit 15, 15', C115, C115': multiplexing circuit 21,21’, C121, C121’: control circuit 22,22', C122, C122': storage circuit R: Impedance 31, 31’, C131, C131’: memory circuit 16', C116': the first auxiliary connection node 17', C117': the second auxiliary connection node 18', C118': Auxiliary connection structure C1, C1': wafer device 11A, 11A', C111A, C111A': the first connection node 12A, 12A', C112A, C112A': the second connection node 13A, 13A’, C113A, C113A’: connection structure SB: Substrate

FIG. 1 is a schematic diagram of stacking multiple circuits through input and output circuits.

FIG. 2 is a schematic diagram of the input and output circuits of the first embodiment of the present invention.

FIG. 3 is another schematic diagram of the input and output circuits of the first embodiment of the present invention.

FIG. 4 is a schematic diagram of the input and output circuits of the second embodiment of the present invention.

FIG. 5 is a schematic diagram of a wafer device according to a third embodiment of the present invention.

FIG. 6 is another schematic diagram of a wafer device according to a third embodiment of the present invention.

FIG. 7 is a schematic diagram of a wafer device according to a fourth embodiment of the present invention.

1: Input and output circuit

2: The first circuit

3: The second circuit

11: The first connection node group

12: The second connection node group

13: Connection structure group

14: Input and output drive circuit

15: Multiplexing circuit

21: Control circuit

22: storage circuit

R: Impedance

31:Memory circuit

11A: first connection node

12A: the second connection node

13A: Connection structure

Claims (10)

An input and output circuit is suitable for connecting a first circuit and a second circuit, the input and output circuit is arranged between the first circuit and the second circuit, the input and output circuit includes: a plurality of first connection node groups, the plurality of first connection node groups being arranged on one side of the first circuit; Multiple sets of second connection node groups, the multiple sets of second connection node groups are arranged on one side of the second circuit, the multiple sets of first connection node groups and the multiple sets of second connection node groups are set correspondingly Yes, each set of the first connection node group corresponds to a set of the second connection node group; Multiple sets of connection structure groups are arranged between the multiple sets of first connection node groups and the multiple sets of second connection node groups; a plurality of input-output driving circuits, each of which is electrically connected to a group of the first connection node groups; and A multiplexing circuit, connecting the multiple input and output drive circuits; Wherein, according to a transmission state of each of the plurality of first connection node groups, the plurality of second connection node groups, and the connection structure groups, the multiplexing circuit selects part or all of the plurality of first connection node groups A connection node group, the plurality of second connection node groups and the connection structure group perform signal transmission. The input and output circuit according to claim 1, wherein the first circuit further includes a control circuit, the control circuit is electrically connected to the multiplexing circuit, and the control circuit The respective transmission states of the node group, the plurality of second connection node groups, and the connection structure groups provide a control signal to the multiplexing circuit, and the multiplexing circuit receives the control signal and according to the control signals to open or close a plurality of connection channels of the multiplexing circuit, so as to utilize a part or all of the plurality of first connection node groups, the plurality of second connection node groups and the connection structure group for signal transmission. The input and output circuit according to claim 2, wherein a group of connection structures is set between each group of the first connection node group and a corresponding group of the second connection node group, and the first A connection node group includes one or more first connection nodes, and when the first connection node group includes the plurality of first connection nodes, the plurality of first connection nodes of the first connection node group connected to each other, the second connection node group includes one or more second connection nodes, when the second connection node group includes the plurality of second connection nodes, the second connection node group A plurality of second connection nodes are connected to each other, and the group of connection structures includes a plurality of connection structures. The input and output circuit as described in claim 2, further comprising: a first auxiliary connection node arranged on one side of the first circuit; a second auxiliary connection node arranged on one side of the second circuit, the first auxiliary connection node and the second auxiliary connection node are correspondingly arranged; and An auxiliary connection structure, respectively arranged between the first auxiliary connection node and the second auxiliary connection node, and connecting the first auxiliary connection node and the second auxiliary connection node; Wherein, when one of the plurality of first connection node groups, the corresponding plurality of second connection node groups, and the corresponding set of connection structure groups are in an abnormal transmission state, the multiplexing The circuit selects the first auxiliary connection node and the second auxiliary connection node to transmit a control signal of the first connection node group and the corresponding second connection node group in the abnormal transmission state . The input and output circuit as described in claim 2, wherein the first circuit further includes a storage circuit, the control circuit is electrically connected to the storage circuit, and a channel state of the multiplexing circuit is stored in the storage in the circuit. A wafer device comprising: a first circuit including a control circuit; a second circuit; and 1. Input and output circuits, including: a plurality of first connection node groups; a plurality of second connection node groups; A plurality of connection structure groups, the plurality of connection structure groups are respectively connected to the plurality of first connection node groups and the plurality of second connection node groups; A plurality of input-output driving circuits, arranged in the first circuit, each of the input-output driving circuits is electrically connected to a set of the first connection node group; and A multiplexing circuit, connecting the multiple input and output drive circuits; Wherein, the control circuit is electrically connected to the multiplexing circuit; Wherein, one connection structure group is arranged between each first connection node group and the corresponding second connection node group, and the plurality of first connection node groups are arranged on one side of the first circuit , the plurality of second connection node groups are arranged on one side of the second circuit, and the plurality of first connection node groups are correspondingly arranged with the plurality of second connection node groups; Wherein, according to a transmission state of each of the plurality of first connection node groups, the plurality of second connection node groups, and the connection structure groups, using the multiplexing circuit to close the connection in the abnormal transmission state One or more of the plurality of first connection node groups, one or more of the plurality of second connection node groups, and one or more of the corresponding one or more of the plurality of connection structure groups The input-output drive circuit is used to turn on the multiple sets of first connection node groups, the multiple sets of second connection node groups and the multiple sets of input and output corresponding to the multiple sets of connection structure groups in the normal transmission state The driving circuit performs signal transmission. The chip device according to claim 6, wherein the first circuit further includes a control circuit, the control circuit is electrically connected to the multiplexing circuit, and the control circuit according to the plurality of first connection node groups , the respective transmission states of the plurality of second connection node groups and the connection structure groups, provide a control signal to the multiplexing circuit, and the multiplexing circuit receives the control signal and according to the control signal To open or close a plurality of connection channels of the multiplexing circuit, to use part or all of the plurality of first connection node groups, the plurality of second connection node groups and the connection structure group for signal transmission. The chip device according to claim 6, wherein a group of connection structures is set between each group of the first connection node group and a corresponding group of the second connection node group, and the first connection The node group includes one or more first connection nodes, and when the first connection node group includes the first connection nodes, the plurality of first connection nodes in the first connection node group are connected to each other, so The second connection node group includes one or more second connection nodes, and when the second connection node group includes the second connection node, the plurality of second connection nodes in the second connection node group connected to each other, the connection structure group includes one or more connection structures. The wafer device as described in claim 6, further comprising: a first auxiliary connection node arranged on one side of the first circuit; a second auxiliary connection node arranged on one side of the second circuit, the first auxiliary connection node and the second auxiliary connection node are correspondingly arranged; and An auxiliary connection structure, respectively arranged between the first auxiliary connection node and the second auxiliary connection node, and connecting the first auxiliary connection node and the second auxiliary connection node; Wherein, when one of the plurality of first connection node groups, the corresponding plurality of second connection node groups, and the corresponding set of connection structure groups are in an abnormal transmission state, the multiplexing The circuit selects the first auxiliary connection node and the second auxiliary connection node to transmit a control signal of the first connection node group and the corresponding second connection node group in the abnormal transmission state . The chip device according to claim 6, wherein the first circuit further includes a storage circuit, the control circuit is electrically connected to the storage circuit, and a channel state of the multiplexing circuit is stored in the storage circuit .

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