TWI807494B - Input and output circuit for wafer on wafer technology, and chip device using thereof - Google Patents

Abstract

An input and output circuit and a chip device are provided in the present disclosure. The input and output circuit includes multiple groups of first connection node groups, multiple groups of second connection node groups, and multiple groups of connection structure groups, multiple input and output circuits. Multiple groups of first connection node groups and multiple groups of second connection node groups are disposed correspondingly. The multiple connection structure groups are arranged between the multiple first connection node groups and the multiple second connection node groups. When one or more of the multiple transmission signals are not correctly transmitted to the first circuit, the second control circuit adjusts the output volume of the transmission signal of the second input/output drive circuit by gradually increasing or decreasing by a predetermined output volume interval to adjust the output volume of the transmission signal.

Description

Input and output circuits of wafer-to-wafer technology and chip devices using it

The invention relates to an input and output circuit and a chip device, in particular to an input and output circuit and a chip device with high yield.

The demand for wafer on wafer and chip level circuits design is gradually increasing in today's semiconductor manufacturing process. As shown in FIG. 1 , the first circuit 2 and the second circuit 3 can be stacked through the input and output circuit 1 and disposed on the substrate SB. However, the wafer stacking process or the input and output circuit design of the chip-level circuit will affect the yield of the final product.

Therefore, how to provide a high-yield input and output circuit and chip device to overcome the above-mentioned defects has become one of the important issues to be solved by this business.

The technical problem to be solved by the present invention is to provide an input and output circuit for the deficiencies of the prior art, which is suitable for connecting a first circuit and a second circuit. The connection node groups and the plurality of second connection node groups are set correspondingly, and each group of the first connection node groups is correspondingly provided with a group of the second connection node groups; multiple sets of connection structure groups are arranged between the plurality of first connection node groups and the plurality of second connection node groups; a plurality of first input-output drive circuits, each of the first input-output drive circuits is electrically connected to a group of the first connection node groups, and the first control circuit is connected to the plurality of first input-output drive circuits; The plurality of second input-output drive circuits; wherein the plurality of first input-output drive circuits receive a plurality of transmission signals sent from the second circuit, and provide the plurality of transmission signals to the first control circuit. When one or more of the plurality of transmission signals is not correctly transmitted to the first circuit, the second control circuit adjusts the output size of the transmission signal of the corresponding second input-output drive circuit that fails to transmit the transmission signal correctly. The second control circuit adjusts the output size of the transmission signal of the second input-output drive circuit. Or decrease to adjust the output size of the transmission signal.

The invention also discloses an input and output circuit, which is suitable for connecting a first circuit and a second circuit, the input and output circuit is arranged between the first circuit and the second circuit, the first circuit includes a first control circuit, the second circuit includes a second control circuit, the input and output circuit includes: multiple first connection node groups, the multiple first connection node groups are arranged on one side of the first circuit; multiple second connection node groups, the multiple second connection node groups are arranged on one side of the second circuit, the multiple first connection node groups and the multiple second connection node groups Each group of the first connection node groups is correspondingly provided with a group of the second connection node groups; multiple groups of connection structures are arranged between the multiple groups of the first connection node groups and the multiple groups of the second connection node groups; a plurality of first input-output drive circuits, each of the first input-output drive circuits is electrically connected to a group of the first connection node groups, and the first control circuit is connected to the plurality of first input-output drive circuits; A plurality of first input-output drive circuits receive a plurality of transmission signals sent from the second circuit, and provide the plurality of transmission signals to the first control circuit. When one or more of the plurality of transmission signals is not correctly transmitted to the first circuit, the second control circuit provides a notification signal through a communication path to notify the first control circuit to adjust the corresponding first input-output drive circuit to adjust the signal detection interval to detect the transmission signal. The communication path is set between the first circuit and the second circuit.

The present invention also discloses a chip device, comprising: a first circuit, including a first control circuit and a first storage circuit, the first control circuit is electrically connected to the first storage circuit; a second circuit; and an input and output circuit, including: a plurality of first connection node groups; a plurality of second connection node groups; a plurality of connection structure groups, the plurality of connection structure groups are respectively connected to the plurality of first connection node groups and the plurality of second connection node groups; The output driver circuit receives a plurality of transmission signals sent from the second circuit, and provides the plurality of transmission signals to the first control circuit. When one or more of the plurality of transmission signals is not correctly transmitted to the first circuit, the second control circuit adjusts the output size of the transmission signal of the corresponding second input-output driver circuit. The second control circuit adjusts the output size of the transmission signal of the second input-output driver circuit.

The present invention also discloses a chip device, comprising: a first circuit, including a first control circuit and a first storage circuit, the first control circuit is electrically connected to the first storage circuit; a second circuit; and an input and output circuit, including: a plurality of first connection node groups; a plurality of second connection node groups; a plurality of connection structure groups, the plurality of connection structure groups are respectively connected to the plurality of first connection node groups and the plurality of second connection node groups; The plurality of first input-output drive circuits receive a plurality of transmission signals sent from the second circuit, and provide the plurality of transmission signals to the first control circuit. When one or more of the plurality of transmission signals is not correctly transmitted to the first circuit, the second control circuit provides a notification signal through a communication path to notify the first control circuit to adjust the corresponding first input-output drive circuit to adjust the signal detection interval to detect the transmission signal. The communication path is set between the first circuit and the second circuit.

One of the beneficial effects of the present invention is that the input and output circuits and the chip device provided by the present invention can effectively improve the utilization rate of the connection circuit between the wafer circuits by adjusting the first predetermined signal detection interval of the first circuit or the second predetermined signal detection interval of the second circuit, and thus improve the use efficiency of the circuit and the chip device.

In order to further understand the features and technical content of the present invention, please refer to the following detailed description and drawings related to the present invention. However, the provided drawings are only for reference and description, and are not intended to limit the present invention.

The following is an illustration of the implementation of the "input and output circuits and chip device" disclosed by the present invention through specific specific embodiments. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various modifications and changes can be made to the details in this specification based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only for simple illustration, and are not drawn according to the actual size, which is stated in advance. The following embodiments will further describe the relevant technical content of the present invention in detail, but the disclosed content is not intended to limit the protection scope of the present invention. In addition, the term "or" used herein may include any one or a combination of more of the associated listed items depending on the actual situation.

[first embodiment]

Please refer to FIG. 2 and FIG. 3 . FIG. 2 is a schematic diagram of the input and output circuits of the first embodiment of the present invention. FIG. 3 is another schematic diagram of the input and output circuits of the first embodiment of the present invention.

In this embodiment, an input and output circuit 1 is provided, which is suitable for connecting a first circuit 2 and a second circuit 3 . The input and output circuit 1 is arranged between the first circuit 2 and the second circuit 3 .

The input and output circuit 1 includes a plurality of first connection node groups 11 , a plurality of second connection node groups 12 , a plurality of connection structure groups 13 , a plurality of first input and output driving circuits 14 , and a plurality of second input and output driving circuits 15 . The first connection node group 11 is provided on one side of the first circuit 2 . The second connection node group 12 is provided on one side of the second circuit 3 . Each first connection node group 11 is set corresponding to the second connection node group 12 .

The first circuit 2 further includes a first control circuit 21 and a first storage circuit 22 . The first control circuit 21 is electrically connected to the first storage circuit 22 . The second circuit 3 further includes a second control circuit 31 and a second storage circuit 32 . The second control circuit 31 is electrically connected to the second storage circuit 32 .

The first control circuit 21 is electrically connected to a plurality of first input-output driving circuits 14 .

The second control circuit 31 is electrically connected to the plurality of second input and output driving circuits 15 .

The plurality of first input-output driving circuits 14 are respectively electrically connected to the plurality of first connection node groups 11 .

The plurality of second input-output driving circuits 15 are respectively electrically connected to the plurality of second connection node groups 12 . The plurality of connection structure groups 13 are respectively arranged between the plurality of first connection node groups 11 and the plurality of second connection node groups 12 .

Wherein, a plurality of first input-output driving circuits 14 receive transmission signals sent from the second circuit 3 and provide a plurality of transmission signals to the first control circuit 21 .

The first control circuit 21 adjusts a predetermined signal detection interval to detect multiple transmission signals to generate multiple adjusted signal detection intervals corresponding to multiple connection structure groups 13, and the first control circuit 21 performs signal detection according to the multiple adjusted signal detection intervals.

That is, each input-output driving circuit 14 receives the transmission signal transmitted from the second circuit 3 . However, when each transmission signal passes through the first connection node group 11, the connection structure group 13 and the second connection node group 12 on the respective transmission paths, due to the transmission status of the first connection node group 11, the connection structure group 13 and the second connection node group 12, signal distortion or signal strength reduction will occur (as shown in FIG. 2 and FIG. 3 ). The first control circuit 21 performs signal detection on each received transmission signal according to the first predetermined signal detection interval, so as to determine that the received transmission signal is a normal signal.

When the transmission signals received by the plurality of input and output driving circuits 14 have signal distortion or signal strength reduction, the first control circuit 21 will detect a signal upper limit value, a signal lower limit value or a combination thereof of the received transmission signals to adjust the first predetermined signal detection interval to generate an adjusted first signal detection interval.

The transmission states of the first connection node group 11 , the connection structure group 13 and the second connection node group 12 corresponding to each input-output driving circuit 14 are not necessarily the same. Therefore, each of the first connection node group 11 , the connection structure group 13 , the second connection node group 12 and the corresponding input/output driving circuit 14 each includes an adjusted first predetermined signal detection interval. The first control circuit 21 detects each transmission signal according to the adjusted first predetermined signal detection interval corresponding to each input and output driving circuit 14 . The adjusted first predetermined signal detection interval corresponding to each input and output driving circuit 14 is stored in the first storage circuit 22 .

The first control circuit 21 adjusts the first predetermined signal detection interval in the following ways:

The first predetermined signal detection interval includes a first predetermined signal upper limit and a second predetermined signal upper limit.

The first way is to adjust the first predetermined signal upper limit value of the first predetermined signal detection interval according to the signal upper limit value of the transmission signal.

When the signal upper limit of the transmission signal is lower than the first predetermined signal upper limit of the first predetermined signal detection interval, the first control circuit 21 may lower the first predetermined signal upper limit of the first predetermined signal detection interval to detect a lower signal upper limit of the transmission signal.

When the signal upper limit of the transmission signal is much higher than the first predetermined signal upper limit of the first predetermined signal detection interval, the first control circuit 21 can increase the first predetermined signal upper limit of the first predetermined signal detection interval to detect a higher signal upper limit of the transmission signal.

The second method is to adjust the first predetermined signal lower limit value of the first predetermined signal detection interval according to the signal lower limit value of the transmission signal.

When the signal lower limit value of the transmission signal is much smaller than the first predetermined signal lower limit value of the first predetermined signal detection interval, the first control circuit 21 can adjust the first predetermined signal lower limit value of the first predetermined signal detection interval to be smaller, so as to detect a smaller signal lower limit value of the transmission signal.

When the signal lower limit value of the transmission signal is much higher than the first predetermined signal lower limit value of the first predetermined signal detection interval, the first control circuit 21 can increase the first predetermined signal lower limit value of the first predetermined signal detection interval to detect a higher signal lower limit value of the transmission signal.

The third method is to adjust the first predetermined signal upper limit and the first predetermined signal lower limit of the first predetermined signal detection interval according to the signal upper limit and the signal lower limit of the transmission signal.

That is, as shown in FIG. 2 , the first control circuit 21 can adjust the first predetermined signal upper limit and the first predetermined signal lower limit in the first predetermined signal detection interval to detect the transmission signal.

In addition, the first control circuit 21 can adjust the upper limit value of the first predetermined signal and the lower limit value of the first predetermined signal according to a unit adjustment interval, and adjust the unit adjustment interval once each time. The first predetermined signal upper limit and the first predetermined signal lower limit of the first predetermined signal detection interval can also be directly adjusted according to the signal upper limit and signal lower limit of the transmission signal to generate an adjusted first predetermined signal detection interval. The adjusted first predetermined signal detection interval includes the adjusted first adjusted upper limit of signal detection and the first adjusted lower limit of signal detection.

Similarly, the second circuit 3 can also receive the transmission signal sent by the first circuit 2 . That is, the multiple second I/O driving circuits 15 can receive the transmission signals sent by the multiple first I/O driving circuits 14 disposed on the first circuit 2 . The plurality of second input-output driving circuits 15 provide the received transmission signals to the second control circuit 31 .

During the initialization process, the second control circuit 31 adjusts a second predetermined signal detection interval and detects a plurality of transmission signals to generate a plurality of second adjusted signal detection intervals corresponding to a plurality of connection structure groups 13, and the second control circuit 31 performs signal detection according to the plurality of adjusted signal detection intervals.

That is, each second input-output driving circuit 15 receives the transmission signal transmitted from the first circuit 2 . However, when each transmission signal passes through the first connection node group 11, the connection structure group 13 and the second connection node group 12 on the respective transmission paths, due to the transmission status of the first connection node group 11, the connection structure group 13 and the second connection node group 12, signal distortion or signal strength reduction will occur (as shown in FIG. 2 and FIG. 3 ). The second control circuit 31 performs signal detection on each received transmission signal according to the first predetermined signal detection interval, so as to determine that the received transmission signal is a normal signal.

When the transmission signals received by the plurality of second input and output driving circuits 15 have signal distortion or signal intensity reduction, the second control circuit 31 will detect a signal upper limit value, a signal lower limit value or a combination of the received transmission signals to adjust the second predetermined signal detection interval to generate an adjusted second predetermined signal detection interval.

Since the transmission states of the first connection node group 11 , the connection structure group 13 and the second connection node group 12 corresponding to each second input-output driving circuit 15 are not necessarily the same. Therefore, each of the first connection node group 11 , the connection structure group 13 , the second connection node group 12 and the corresponding second input-output driving circuit 15 each includes an adjusted second predetermined signal detection interval. The second control circuit 31 detects each transmission signal according to the adjusted second predetermined signal detection interval corresponding to each second input-output driving circuit 15 . The adjusted second predetermined signal detection interval corresponding to each second input-output driving circuit 15 will be stored in the second storage circuit 32 .

As shown in FIG. 2 , each first connection node group 11 includes a first connection node 11A. Each second connection node group 12 includes one second connection node 12A. Each connecting structure group 13 includes a connecting structure 13A.

Furthermore, as shown in FIG. 3 , the first connection node group 11 includes a plurality of first connection nodes A, and the plurality of first connection nodes 11A of the first connection node group 11 are connected to each other. The second connection node group 12 includes a plurality of second connection nodes 12A, and the plurality of second connection nodes 12A of the second connection node group 12 are connected to each other. The connection structure group 13 includes a plurality of connection structures 13A.

As shown in FIG. 2 , in this embodiment, each input-output driving circuit 14 includes an output terminal. An impedance R is electrically connected to the output terminal of the input-output driving circuit 21 . As a voltage regulation impedance when outputting a control signal, it is generally called a pull-down impedance (pull low resistor). In other embodiments, the impedance R may not be set.

In this embodiment, the multiple input and output driving circuits 14 can be connected to a control circuit 21 or a logic circuit (not shown in the figure), which is not limited in the present invention. The second circuit 3 may include a plurality of memory circuits 31 , a control circuit or an application circuit, which are not limited in the present invention. That is, the circuits connected to the plurality of second connection nodes 12A provided in the second circuit 3 are not limited in any way.

That is, when the first circuit 2 and the second circuit 3 are stacked, they will be aligned and then connected: for example, wafer bonding (wafer bonding), wire bonding (wire bonding), so as to perform the stacking arrangement of the first circuit 2 and the second circuit 3 . When the circuit is aligned, the accuracy is very important. The distance between the first circuit 2 and the second circuit 3 will affect the yield rate of the input and output circuit 1 connecting the first circuit 2 and the second circuit 3 . In this embodiment, the connection structure 13A can be, for example, a pin header structure, a wafer bonding structure (wafer bonding) or a wire bonding structure (wire bonding).

In this embodiment, the first circuit 2 and the second circuit 3 may be a wafer-level circuit (wafer), a chip-level circuit (chip), or a general-scale circuit. The input and output driving circuit 21 is a CMOS IO logic.

The first storage circuit 22 and the second storage circuit 32 are a flash memory, a read-only memory, a programmable read-only memory, an electrically rewritable read-only memory, an erasable programmable read-only memory or an electrically erasable programmable read-only memory.

[Second embodiment]

Please refer to FIG. 4 and FIG. 5 . FIG. 4 is a schematic diagram of a wafer device according to a second embodiment of the present invention. FIG. 5 is another schematic view of the wafer device according to the second embodiment of the present invention.

In this embodiment, a wafer device C1 is provided. The chip device C1 includes an input and output circuit C11, a first circuit C12 and a second circuit C13.

The input and output circuit C11 is suitable for connecting a first circuit C12 and a second circuit C13. The input and output circuit C11 is provided between the first circuit C12 and the second circuit C13.

The input and output circuit C11 includes a plurality of first connection node groups C111, a plurality of second connection node groups C112, a plurality of connection structure groups C113, a plurality of first input and output driving circuits C114, and a plurality of second input and output driving circuits C115. The first connection node group C111 is provided on one side of the first circuit C12. The second connection node group C112 is provided on one side of the second circuit C13. Each first connection node group C111 is set correspondingly to the second connection node group C112.

The first circuit C12 further includes a first control circuit C121 and a first storage circuit C122. The first control circuit C121 is electrically connected to the first storage circuit C122. The second circuit C13 further includes a second control circuit C131 and a second storage circuit C132. The second control circuit C131 is electrically connected to the second storage circuit C132.

The first control circuit C121 is electrically connected to a plurality of first input-output driving circuits C114.

The second control circuit C131 is electrically connected to a plurality of second input-output driving circuits C115.

The plurality of first input and output driving circuits C114 are electrically connected to the plurality of first connection node groups C111 respectively.

The plurality of second input and output driving circuits C115 are electrically connected to the plurality of second connection node groups C112 respectively. The plurality of connection structure groups C113 are respectively arranged between the plurality of first connection node groups C111 and the plurality of second connection node groups C112.

Wherein, a plurality of first input and output driving circuits C114 receive transmission signals sent from the second circuit C13, and provide a plurality of transmission signals to the first control circuit C121.

The first control circuit C121 adjusts a predetermined signal detection interval and detects a plurality of transmission signals to generate a plurality of adjusted signal detection intervals corresponding to a plurality of connection structure groups C113, and the first control circuit 21 performs signal detection according to the plurality of adjusted signal detection intervals.

That is, each input-output driving circuit C114 receives the transmission signal transmitted from the second circuit 3 . However, when each transmission signal passes through the first connection node group C111, the connection structure group C113, and the second connection node group C112 on the respective transmission paths, signal distortion or signal strength reduction will occur due to the transmission status of the first connection node group C111, the connection structure group C113, and the second connection node group C112 (as shown in FIG. 4 ). The first control circuit C121 performs signal detection on each received transmission signal according to the first predetermined signal detection interval, so as to determine that the received transmission signal is a normal signal.

When the transmission signals received by the multiple input and output driving circuits C114 have signal distortion or signal strength decrease, the first control circuit C121 detects a signal upper limit, a signal lower limit or a combination thereof of the received transmission signals to adjust the first predetermined signal detection interval to generate an adjusted first signal detection interval.

The transmission states of the first connection node group C111 , the connection structure group C113 and the second connection node group C112 corresponding to each input-output driving circuit C114 are not necessarily the same. Therefore, each of the first connection node group C111 , the connection structure group C113 , the second connection node group C112 and the corresponding input/output driving circuit C114 each includes an adjusted first predetermined signal detection interval. The first control circuit C121 detects each transmission signal according to the adjusted first predetermined signal detection interval corresponding to each input and output driving circuit C114 . The adjusted first predetermined signal detection interval corresponding to each input and output driving circuit C114 is stored in the first storage circuit C122. As shown in FIG. 4 , the transmission signal S1 and the transmission signal S2 are detected using different adjustment signal detection intervals.

The first control circuit C121 adjusts the first predetermined signal detection interval in the following ways:

The first predetermined signal detection interval includes a first signal detection upper limit and a first signal detection lower limit.

The first way is to adjust the first signal detection upper limit of the first predetermined signal detection interval according to the signal upper limit of the transmission signal.

When the signal upper limit of the transmission signal is lower than the first signal detection upper limit of the first predetermined signal detection interval, the first control circuit C121 can lower the first signal detection upper limit of the first predetermined signal detection interval to detect a lower signal upper limit of the transmission signal.

When the signal upper limit of the transmission signal is much higher than the first signal detection upper limit of the first predetermined signal detection interval, the first control circuit C121 can increase the first signal detection upper limit of the first predetermined signal detection interval to detect a higher signal upper limit of the transmission signal.

The second way is to adjust the first signal detection lower limit value of the first predetermined signal detection interval according to the signal lower limit value of the transmission signal.

When the signal lower limit value of the transmission signal is much smaller than the first signal detection lower limit value of the first predetermined signal detection interval, the first control circuit C121 can adjust the first signal detection lower limit value of the first predetermined signal detection interval to be smaller, so as to detect a smaller signal lower limit value of the transmission signal.

When the signal lower limit of the transmission signal is much higher than the first signal detection lower limit of the first predetermined signal detection interval, the first control circuit C121 can increase the first signal detection lower limit of the first predetermined signal detection interval to detect a higher signal lower limit of the transmission signal.

The third method is to adjust the first signal detection upper limit and the first signal detection lower limit of the first predetermined signal detection interval according to the signal upper limit and the signal lower limit of the transmission signal.

That is, as shown in FIG. 4 , the first control circuit C121 can adjust the first signal detection upper limit and the first signal detection lower limit of the first predetermined signal detection interval to detect the transmission signal.

In addition, the first control circuit C121 can adjust the first signal detection upper limit value and the first signal detection lower limit value according to a unit adjustment interval, and the unit adjustment interval is adjusted each time. The first signal detection upper limit and the first signal detection lower limit of the first predetermined signal detection interval can also be directly adjusted according to the signal upper limit and signal lower limit of the transmission signal to generate an adjusted first adjusted signal detection interval. The adjusted first adjusted signal detection interval includes the adjusted first adjusted signal detection upper limit and the first adjusted signal detection lower limit.

Similarly, the second circuit C13 can also receive the transmission signal sent by the first circuit C12. That is, the plurality of second input-output driving circuits C115 can receive the transmission signals sent by the plurality of first input-output driving circuits C114 disposed in the first circuit C12. The plurality of second input-output driving circuits C115 provide the received transmission signals to the second control circuit C131.

During the initialization process, the second control circuit C131 adjusts a second predetermined signal detection interval and a plurality of transmission signals for detection to generate a plurality of second adjusted signal detection intervals corresponding to the plurality of connection structure groups C113, and the second control circuit C131 performs signal detection according to the plurality of adjusted signal detection intervals.

That is, each second input-output driving circuit C115 receives the transmission signal transmitted from the first circuit C12. However, when each transmission signal passes through the first connection node group C111, the connection structure group C113, and the second connection node group C112 on the respective transmission paths, signal distortion or signal strength reduction will occur due to the transmission status of the first connection node group C111, the connection structure group C113, and the second connection node group C112 (as shown in FIG. 4 and FIG. 5 ). The second control circuit C131 performs signal detection on each received transmission signal according to the first predetermined signal detection interval, so as to determine that the received transmission signal is a normal signal.

When the transmission signals received by the plurality of second input and output driving circuits C115 have signal distortion or signal intensity reduction, the second control circuit C131 detects a signal upper limit, a signal lower limit or a combination thereof of the received transmission signals to adjust the second predetermined signal detection interval to generate an adjusted second predetermined signal detection interval.

The transmission states of the first connection node group C111 , the connection structure group C113 and the second connection node group C112 corresponding to each second input-output driving circuit C115 are not necessarily the same. Therefore, each of the first connection node group C111 , the connection structure group C113 , the second connection node group C112 and the corresponding second input-output driving circuit C115 each includes an adjusted second predetermined signal detection interval. The second control circuit C131 detects each transmission signal according to the adjusted second predetermined signal detection interval corresponding to each second input-output driving circuit C115. The adjusted second predetermined signal detection interval corresponding to each second input-output driving circuit C115 will be stored in the second storage circuit C132.

As shown in FIG. 4 , each first connection node group C111 includes a first connection node C111A. Each second connection node group C112 includes a second connection node C112A. Each connection structure group C113 includes a connection structure C113A.

Furthermore, as shown in FIG. 5 , the first connection node group C111 includes a plurality of first connection nodes C111A, and the plurality of first connection nodes C111A of the first connection node group C111 are connected to each other. The second connection node group C112 includes a plurality of second connection nodes C112A, and the plurality of second connection nodes C112A of the second connection node group C112 are connected to each other. The connection structure group C113 includes a plurality of connection structures C113A.

As shown in FIG. 4 , in this embodiment, each input-output driving circuit C114 includes an output terminal. An impedance R is electrically connected to the output terminal of the input-output driving circuit C121. As a voltage regulation impedance when outputting a control signal, it is generally called a pull-down impedance (pull low resistor). In other embodiments, the impedance R may not be set.

In this embodiment, the multiple input and output driving circuits C114 may be connected to a control circuit C121 or a logic circuit (not shown in the figure), which is not limited in the present invention. The second circuit C13 may include a plurality of memory circuits C131, a control circuit or an application circuit, which are not limited in the present invention. That is, the circuits connected to the plurality of second connection nodes C112A provided in the second circuit 3 are not limited in any way.

That is, when the first circuit C12 and the second circuit C13 are performing the stacking process, they will be connected after alignment: such as wafer bonding (wafer bonding), wire bonding (wire bonding), so as to perform the stacking arrangement of the first circuit C12 and the second circuit C13. When the circuit is aligned, the accuracy is very important. The distance between the first circuit C12 and the second circuit C13 will affect the yield rate of the input and output circuit 1 connecting the first circuit C12 and the second circuit C13. In this embodiment, the connecting structure C113A may be, for example, a pin header structure, a wafer bonding structure (wafer bonding) or a wire bonding structure (wire bonding).

In this embodiment, the first circuit C12 and the second circuit C13 may be a wafer-level circuit (wafer), a chip-level circuit (chip), or a general-scale circuit. The input and output driving circuit C121 is a CMOS IO logic.

The first storage circuit C122 and the second storage circuit C132 are a flash memory, a read-only memory, a programmable read-only memory, an electrically rewritable read-only memory, an erasable programmable read-only memory or an electrically erasable programmable read-only memory.

[Third embodiment]

Please refer to FIG. 6 . FIG. 6 is a schematic diagram of a wafer device according to a third embodiment of the present invention.

The chip device C3 and the input and output circuit C31 of this embodiment are similar to the chip device C1 and the input and output circuit C11 of the second embodiment, and the main difference is the control action of the first input and output driving circuit C314 and the second input and output driving circuit C315 in the first control circuit C321 and the second control circuit C331.

In this embodiment, the plurality of first input and output driving circuits C314 receive the plurality of transmission signals sent from the second circuit C315, and provide the plurality of transmission signals to the first control circuit C321. When one or more of the transmission signals are not correctly transmitted to the first control circuit C321, the second control circuit C331 adjusts the output level of the corresponding second input-output driving circuit C315 to adjust the output size of the transmission signal.

For example, the way the second control circuit C331 adjusts the output size of the transmission signal of the second input-output driving circuit C315 may be to gradually increase or decrease the output size in a predetermined range to adjust the output size of the transmission signal. Similarly, the output size of the transmission signal adjusted by the second control circuit C331 of the second input-output driving circuit C315 can be stored in the second storage circuit C332.

In other embodiments, the second control circuit C331 can also directly increase or decrease a larger output size range.

In this embodiment, the first control circuit C321 of the first circuit C32 is connected to the second control circuit C331 of the second circuit C33 through a communication path CP1. The communication path CP1 is set between the first circuit C32 and the second circuit C33.

[Fourth embodiment]

Please refer to FIG. 7 . FIG. 7 is a schematic diagram of a wafer device according to a fourth embodiment of the present invention.

The chip device C5 and the input and output circuit C51 in this embodiment are similar to the chip device C1 and the input and output circuit C11 in the second embodiment, the main difference is the control action of the first input and output driving circuit C514 and the second input and output driving circuit C515 in the first control circuit C521 and the second control circuit C531.

In this embodiment, the plurality of first input-output driving circuits C514 receive the plurality of transmission signals sent from the second circuit C53, and provide the plurality of transmission signals to the first control circuit C521. When one or more of the plurality of transmission signals cannot be correctly transmitted to the first control circuit C521 of the first circuit C52, the second control circuit C531 will notify the first control circuit C521 to adjust the corresponding first input-output driving circuit C514 to adjust the signal detection interval through the communication path CP2 to detect the transmission signal. That is, the first control circuit C521 can adjust the size of the first predetermined signal detection interval similarly to the first embodiment.

In this embodiment, the first control circuit C521 of the first circuit C52 is connected to the second control circuit C531 of the second circuit C53 through a communication path CP2. The communication path CP2 is set between the first circuit C52 and the second circuit C53.

[Advantageous Effects of Embodiment]

One of the beneficial effects of the present invention is that the input and output circuits and the chip device provided by the present invention can effectively improve the utilization rate of the connection circuit between the wafer circuits by adjusting the first predetermined signal detection interval of the first circuit or the second predetermined signal detection interval of the second circuit, and thus improve the use efficiency of the circuit and the chip device.

The content disclosed above is only a preferred feasible embodiment of the present invention, and does not limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made by using the description and drawings of the present invention are included in the scope of the patent application of the present invention.

C1: wafer device 1, C11: input and output circuit 2, C12: the first circuit 3, C13: Second circuit 11, C111: The first connection node group 12, C112: Second connection node group 13, C113: Connection structure group 14, C114: the first input and output drive circuit 15, C115: the first input and output drive circuit 21, C121: the first control circuit 22, C122: the first storage circuit R: Impedance 31, C131: Second control circuit 32, C132: Second storage circuit 11A, C111A: first connection node 12A, C112A: Second connection node 13A, C113A: connection structure SB: Substrate

FIG. 1 is a schematic diagram of stacking multiple circuits through input and output circuits.

FIG. 2 is a schematic diagram of the input and output circuits of the first embodiment of the present invention.

FIG. 3 is another schematic diagram of the input and output circuits of the first embodiment of the present invention.

FIG. 4 is a schematic diagram of a wafer device according to a second embodiment of the present invention.

FIG. 5 is another schematic view of the wafer device according to the second embodiment of the present invention.

FIG. 6 is a schematic diagram of a wafer device according to a third embodiment of the present invention.

FIG. 7 is a schematic diagram of a wafer device according to a fourth embodiment of the present invention.

1: Input and output circuit 2: The first circuit 3: The second circuit 11: The first connection node group 12: The second connection node group 13: Connection structure group 14: The first input and output drive circuit 15: The first input and output drive circuit 21: The first control circuit 22: the first storage circuit R: Impedance 31: Second control circuit 32: the second storage circuit 11A: first connection node 12A: the second connection node 13A: Connection structure

Claims (10)

An input and output circuit, suitable for connecting a first circuit and a second circuit, the input and output circuit is arranged between the first circuit and the second circuit, the first circuit includes a first control circuit, the second circuit includes a second control circuit, the input and output circuit includes: multiple sets of first connection node groups, the multiple sets of first connection node groups are arranged on one side of the first circuit; Each group of the first connection node groups is correspondingly provided with a group of the second connection node groups; multiple groups of connection structures are arranged between the multiple groups of the first connection node groups and the multiple groups of the second connection node groups; a plurality of first input-output drive circuits, each of the first input-output drive circuits is electrically connected to a group of the first connection node groups, and the first control circuit is connected to the plurality of first input-output drive circuits; a plurality of second input-output drive circuits, each of the second input-output drive circuits is electrically connected to a group of the second connection node groups, and the second control circuit is connected to the plurality of second input-output drive circuits; The driving circuit receives multiple transmission signals sent from the second circuit, and provides the multiple transmission signals to the first control circuit. When one or more of the multiple transmission signals cannot be correctly transmitted to the first circuit, the second control circuit adjusts the output size of the transmission signal of the corresponding second input-output drive circuit that fails to transmit the transmission signal correctly. The second control circuit adjusts the output size of the transmission signal of the second input-output drive circuit. An input and output circuit, suitable for connecting a first circuit and a second circuit, the input and output circuit is arranged between the first circuit and the second circuit, the first circuit includes a first control circuit, the second circuit includes a second control circuit, the input and output circuit includes: multiple sets of first connection node groups, the multiple sets of first connection node groups are arranged on one side of the first circuit; Each group of the first connection node groups is correspondingly provided with a group of the second connection node groups; multiple groups of connection structures are arranged between the multiple groups of the first connection node groups and the multiple groups of the second connection node groups; a plurality of first input-output drive circuits, each of the first input-output drive circuits is electrically connected to a group of the first connection node groups, and the first control circuit is connected to the plurality of first input-output drive circuits; a plurality of second input-output drive circuits, each of the second input-output drive circuits is electrically connected to a group of the second connection node groups, and the second control circuit is connected to the plurality of second input-output drive circuits; The driving circuit receives multiple transmission signals sent from the second circuit, and provides the multiple transmission signals to the first control circuit. When one or more of the multiple transmission signals cannot be correctly transmitted to the first circuit, the second control circuit provides a notification signal through a communication path to notify the first control circuit to adjust the corresponding first input and output drive circuit to adjust the signal detection interval to detect the transmission signal. The communication path is set between the first circuit and the second circuit. The input and output circuit as described in claim 2, wherein each of the transmission signals includes a signal upper limit value and a signal lower limit value, a first predetermined signal detection The detection interval includes a first signal detection upper limit and a first signal detection lower limit, and the first control circuit adjusts the first signal detection upper limit to generate a first adjustment signal detection upper limit of a first adjustment signal detection interval. The input and output circuit according to claim 2, wherein each of the transmission signals includes a signal upper limit and a signal lower limit, a first predetermined signal detection interval includes a first signal detection upper limit and a first signal detection lower limit, and the first control circuit adjusts the first signal detection lower limit to generate a first adjusted signal detection lower limit of the first adjusted predetermined signal detection interval. The input and output circuit according to claim 2, wherein each of the transmission signals includes a signal upper limit and a signal lower limit, and a first predetermined signal detection interval includes a first predetermined signal upper limit and a first predetermined signal lower limit, and the first control circuit adjusts the first predetermined signal upper limit and the first predetermined signal lower limit in the first predetermined signal detection interval to generate a first adjusted signal detection upper limit and a first adjusted signal detection lower limit in the first adjusted signal detection interval. The input and output circuit according to claim 2, wherein the second circuit further includes a second storage circuit, the second control circuit is electrically connected to the second storage circuit, the input and output circuit further includes a plurality of second input and output driving circuits, the plurality of second input and output driving circuits are respectively electrically connected to the plurality of second connection node groups, and the plurality of second input and output driving circuits are electrically connected to the second control circuit; wherein the plurality of second input and output driving circuits receive a plurality of transmission signals sent from the first circuit, and provide the plurality of transmission signals to the second control circuit to generate corresponding connections A plurality of second adjustment signal detection intervals are configured, and then, the second control circuit performs signal detection according to the plurality of second adjustment signal detection intervals. A chip device, comprising: a first circuit, including a first control circuit and a first storage circuit, the first control circuit is electrically connected to the first storage circuit; a second circuit, including a second control circuit and a plurality of second input-output driving circuits, the second control circuit is connected to the plurality of second input-output driving circuits; and an input and output circuit, including: a plurality of first connection node groups; a plurality of second connection node groups; Each of the first input-output drive circuits is electrically connected to a set of first connection node groups, and each of the second input-output drive circuits is electrically connected to a set of second connection node groups; wherein, the plurality of first input-output drive circuits receive multiple transmission signals sent from the second circuit, and provide the multiple transmission signals to the first control circuit. The output size of the transmission signal is gradually increased or decreased in a predetermined output size interval to adjust the output size of the transmission signal. A chip device, comprising: a first circuit including a first control circuit and a first storage circuit, the first control circuit electrically connected to the first storage circuit; a second circuit including a second control circuit; and an input and output circuit including: A plurality of first connection node groups; a plurality of second connection node groups; a plurality of connection structure groups, the plurality of connection structure groups are respectively connected to the plurality of first connection node groups and the plurality of second connection node groups; and a plurality of first input-output drive circuits, each of which is electrically connected to a set of the first connection node groups; wherein, the plurality of first input-output drive circuits receive a plurality of transmission signals sent from the second circuit, and provide the plurality of transmission signals to the first control circuit, when one or more of the plurality of transmission signals is not correctly transmitted to the first circuit, The second control circuit of the second circuit provides a notification signal through a communication path to notify the first control circuit to adjust the corresponding first input-output drive circuit to adjust the signal detection interval to detect the transmission signal, and the communication path is set between the first circuit and the second circuit. The chip device according to claim 8, wherein each of the transmission signals includes a signal upper limit and a signal lower limit, a first predetermined signal detection interval includes a first signal detection upper limit and a first signal detection lower limit, the first control circuit adjusts the first signal detection upper limit to generate a first adjusted signal detection upper limit in a first adjusted signal detection interval, or the first control circuit adjusts the first signal detection lower limit to generate a first adjusted signal detection lower limit in the first adjusted predetermined signal detection interval. The chip device according to claim 8, wherein each of the transmission signals includes a signal upper limit and a signal lower limit, and a first predetermined signal detection interval includes a first predetermined signal upper limit and a first predetermined signal lower limit, and the first control circuit adjusts the first predetermined signal upper limit and the first predetermined signal lower limit in the first predetermined signal detection interval to generate a first adjusted signal detection upper limit and a first adjusted signal detection interval. Adjust the signal detection lower limit.

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