TWI790780B - Timing control method using pulse frequency modulation, timing controller and display device - Google Patents

Abstract

A timing control method is disclosed. The timing control method includes calculating a plurality of charging/discharging times corresponding to a plurality of display pixels according to a target voltage and a plurality of RC time constants, and generating a control signal according to a processing time and the plurality of RC time constants.

Description

Timing control method using pulse frequency modulation, timing controller and display

The present invention refers to a timing control method, a timing controller and a display using pulse frequency modulation, especially a timing controlling method, a timing controller and a display using control signals with multiple charging and discharging times.

With the advancement of liquid crystal display (Liquid Crystal Display, LCD) panel technology, the demand for high-end LCD panels in the consumer market is also increasing. The current high-end LCD panel refers to a large-size panel that can support high frame rate (Frame Rate), high color depth, and high resolution; for example, the frame rate (Frame Rate) is 120Hz, and the color depth is 10 bits (ie It can display 1024 grayscale colors) and Ultra High Definition Television (UHDTV) with a resolution of 8K (7680*4320 square pixels).

However, when the size of the LCD panel increases, the signal path between the driver and the display pixels increases, and the load impedance seen by the driver also increases, causing the remote load to require a higher charge to reach the target voltage. In practical applications, the brightness of the display pixels located near the end of the signal path is higher, while the brightness of the display pixels located at the end of the signal path is lower, resulting in uneven brightness of the LCD panel, resulting in poor visual performance. Therefore, how to improve the uneven brightness of the LCD panel has become one of the important issues in this field.

An object of the present invention is to provide a timing control method, including calculating multiple charging and discharging times according to a target voltage and multiple RC time constants; and generating a control signal according to a processing time and the multiple charging and discharging times.

Another object of the present invention is to provide a timing controller for a display device, including a processor; and a memory, coupled to the processor, for storing a program code, the program code is used to instruct the The processor executes the control method as described above. Wherein the timing controller executes the above timing control method to generate the control signal to a source driver of the display device.

Another object of the present invention is to provide a display device, which includes a display panel, a source driver, a gate driver, and the above-mentioned timing controller. The display panel includes a plurality of display pixels as described above. The source driver is coupled to the display panel for generating a plurality of source driving signals to the display panel. The gate driver is coupled to the display panel and used for generating a plurality of gate driving signals to the display panel. The timing controller is coupled to the source driver and the gate driver; wherein the timing controller generates the above-mentioned control signal to the source driver, so that the source driver generates a plurality of source electrodes according to the control signal drive signals to the display panel.

Different from the traditional control signal with only a single charge and discharge time, the timing control method and its timing controller of the present invention use control signals with multiple charge and discharge times or multiple pulse frequencies to adapt to the loads located at different positions in the signal path. The required charge and discharge capacity. In this way, since a plurality of display pixels can be charged and discharged to a target voltage within a plurality of charge and discharge times, the timing control method and timing controller of the present invention can improve the uneven brightness of the LCD panel.

FIG. 1 is a partial schematic diagram of a display device (display) 1 according to an embodiment of the present invention. The display device 1 includes a timing controller (Timing Controller) 10 , a source driver (Source Driver) 11 , a gate driver (Gate Driver) 12 and a display panel 13 . The timing controller 10 is coupled to the source driver 11 and the gate driver 12 for generating a control signal SC to the source driver 11 and a control signal GC to the gate driver 12 . The source driver 11 is coupled to the display panel 13 for generating a plurality of source driving signals S1 . . . S5 to the display panel 13 according to the control signal SC. The gate driver 12 is coupled to the display panel 13 for generating a plurality of gate driving signals G1 . . . G4 to the display panel 13 according to the control signal GC. The partial circuit structure of the display panel 13 is shown in FIG. 1 , and includes a plurality of display pixels PX, a plurality of source lines and a plurality of gate lines. The plurality of display pixels PX are arranged in a matrix along the X and Y directions. Each display pixel PX includes a switch (such as a transistor) and a light emitting unit CLC; the light emitting unit CLC is coupled between the switch and a system voltage VCOM. In other embodiments, the display panel 13 may be a panel with a resolution of m*n square pixels, including m*n display pixels PX, m gate lines and n source lines, where m and n are greater than A positive integer of zero.

A plurality of source lines are connected to sources of switches of a plurality of display pixels PX, and are used to transmit a plurality of source driving signals S1 . . . S5 . A plurality of gate lines are connected to gates of switches of a plurality of display pixels PX, and are used to respectively transmit a plurality of gate driving signals G1 . . . G4 to turn on a plurality of display pixels PX respectively. For example, as shown in FIG. 1, when the gate drive signal G1 turns on five display pixels PX connected to the same gate line, the source driver 11 can sequentially input source drive signals S1...S5 to the same gate line. The five display pixels PX on the gate line charge and discharge the five light emitting cells CLC in sequence. There are four nodes N1 , N2 , N3 and N4 connecting the source line for transmitting the source driving signal S3 and the four display pixels PX.

2 is a schematic diagram of the control signal SC2, the target voltages VH, VL, the near-end node voltage N12, and the far-end node voltage N42 versus time. The timing controller 10 in FIG. 1 can generate the control signal SC2 to the source driver 11 so that the source driver 11 generates the source driving signal S3. Assume that the near-end node voltage N12 is the voltage of the source driving signal S3 input to the node N1, and the far-end node voltage N42 is the voltage of the source driving signal S3 input to the node N4. In the control signal SC2 , the update time of each display pixel PX is T, where TA is the processing time of the source driver 11 , and TB is the charge and discharge time of the display pixel PX. In operation, during the processing time TA, when the source driver 11 detects a rising edge (Rising Edge) of the control signal SC2 , the source driver 11 performs digital-analog conversion to generate the source driving signal S3 . Then, within the charging and discharging time TB, the source driving signal S3 charges and discharges the display pixel PX, for example, charging from the target voltage VL to the target voltage VH, or discharging from the target voltage VH to the target voltage VL.

It can be seen from Figure 2 that the near-end node voltage N12 takes a short time to charge from the target voltage VL to the target voltage VH, while the far-end node voltage N42 takes a long time to charge from the target voltage VL to the target voltage VH; the discharge time also has similar results . Since the load impedance will increase with the length of the signal path, compared with the near-end display pixels PX, the far-end display pixels PX need a larger charging amount. In order to solve the problem of low brightness of the display pixel PX at the end of the signal path, the traditional method is to prolong the charging and discharging time TB, but the applicant noticed that this method will not only prolong the working time of the source driver 11 but also cause its own power failure. power consumption and temperature rise, and it is impossible to exactly solve the problem of the difference between the near-end and far-end charging and discharging.

3 is a schematic diagram of another control signal SC3, target voltages VH, VL, another near-end node voltage N13, and another far-end node voltage N43 versus time. The updating time of the control signal SC3 in FIG. 3 is 1/2*T, the processing time is TA, and the charging and discharging time is TC, wherein 1/2*T=TA+TC. Comparing Figure 3 with Figure 2, it can be seen that under the premise that the processing time TA remains unchanged, the charging and discharging time is shortened to TC, although the near-end node voltage N13 can be charged to the target voltage VH within the charging and discharging time TC (or by discharge to the target voltage VL), but the remote node voltage N43 cannot be charged to the target voltage VH (or discharged to the target voltage VL) within the charging and discharging time TC, which leads to uneven brightness of the LCD panel . In practical applications, when the update rate is increased, the time for display pixels to charge and discharge is shortened; for example, the update rate is increased from 60 Hz to 120 Hz, which reduces the update time by half and makes the uneven brightness of the LCD panel become obvious. .

4 is a schematic diagram of another control signal SC4, target voltages VH, VL, another near-end node voltage N14, and another far-end node voltage N44 versus time. The updating time of the control signal SC4 in FIG. 4 is 1/2*T, the processing time is 1/2*TA, and the charging and discharging time is TD, wherein 1/2*T=1/2*TA+TD. Comparing Figure 4 and Figure 3, it can be seen that under the premise that the update time is 1/2*T, the processing time is shortened to 1/2*TA. Although the remote node voltage N44 is closer to the target voltage VH, it still cannot It is charged to the target voltage VH (or discharged to the target voltage VL) within the charge and discharge time TD.

5 is a schematic diagram of voltage versus time of control signals, target voltages VH, VL, and multiple node voltages D1 , D2 , D3 , D4 according to an embodiment of the present invention. In the embodiment of the present invention, the control signal has multiple updating times T1, T2, T3, T4, the processing time is Ta, and the multiple charging and discharging times are Tb1, Tb2, Tb3, Tb4. In the embodiment of the present invention, the i-th update time can be expressed as the following function (1): Ti=Ta+Tbi (1); Wherein, 1≦i≦m, m is the number of display pixels PX connected to the same source line (equal to the number of gate lines). In one embodiment, the distance between the i-th display pixel PX and the source driver 11 is proportional to the size of i, and the size of i is proportional to the charging and discharging time; that is, the farther the i-th display pixel PX is from the source driver 11 Display pixels PX, the longer the charging time, so Tbi<Tb(i+1).

（2）； 其中，VC(t)是對應於多個顯示像素PX（或發光單元CLC）的多個即時充電電壓，t是充電時間，τ是RC時間常數，Vo是充電電壓的絕對值∣VH-VL∣。 Further, the following function (2) describes the relationship between the charging capacitance of the resistance-capacitance (RC) circuit over time:

(2); Among them, VC(t) is a plurality of instantaneous charging voltages corresponding to a plurality of display pixels PX (or light-emitting unit CLC), t is the charging time, τ is the RC time constant, and Vo is the absolute value of the charging voltage∣ VH-VL∣.

（3）； 其中，VR(t)是對應於多條源極線的訊號路徑（即，電阻負載）的即時放電電壓，t是充電時間，τ是RC時間常數，Vo是放電電壓的絕對值∣VH-VL∣。 The following function (3) describes the relationship between the discharge of the resistive load of the RC circuit over time:

(3); where VR(t) is the instantaneous discharge voltage corresponding to the signal path of multiple source lines (i.e., resistive load), t is the charging time, τ is the RC time constant, and Vo is the absolute value of the discharge voltage ∣VH-VL∣.

Through experimental measurement or simulation estimation, the RC time constant at any position in the signal path of the source line (that is, the resistive load) can be obtained, and the charging voltage Vo is a known |VH-VL|, so it can be calculated according to the function (2 ) or (3) deduce the capacitive charge time t or the resistive load discharge time t. For example, assuming that one source line is connected to m display pixels PX1...PXm, m RC time constants τ1...τm corresponding to m display pixels PX1...PXm can be obtained through experimental measurement or simulation estimation, and the charging voltage Vo is the known |VH-VL|, so m charging and discharging times Tb1...Tbm can be deduced according to the function (2). It should be noted that for a display screen with a resolution of m*n, the sum of the m charging and discharging times Tb1...Tbm shall not be greater than the update time of one source line of the entire screen, so as to meet the refresh rate of the screen display (Refresh Rate).

As shown in Fig. 5, the node voltage D1 at node N1 is charged to the target voltage VH within the charging and discharging time Tb1, the node voltage D2 at the node N2 is discharged to the target voltage VL within the charging and discharging time Tb2, and the node N3 at the node N3 The node voltage D3 is charged to the target voltage VH within the charging and discharging time Tb3, and the node voltage D4 at the node N4 is discharged to the target voltage VL within the charging and discharging time Tb4. Therefore, the display pixels PX located at different positions of the signal path can be charged and discharged to the target voltage VH or VL, so that the image brightness of the LCD panel is uniform and the visual performance is good.

In short, unlike the traditional control signal which only has a single charging and discharging time, the control signal of the present invention has multiple charging and discharging times to meet the needs of loads located in different positions of the signal path (ie, m display pixels PX1...PXm) charge and discharge capacity. From another perspective, the traditional control signal only has a single duty cycle or a single pulse frequency; in contrast, the control signal of the present invention has multiple duty cycles or multiple pulse frequencies. In this way, since the m display pixels PX1 . . . PXm can be charged and discharged to the target voltage VH or VL within m charging and discharging times Tb1 .

FIG. 6 is a schematic diagram of voltage versus time of target voltages VH, VL, multiple node voltages D1 , D2 , D3 , D4 according to an embodiment of the present invention. In the application of low-power drivers, it can be seen from FIG. 6 that the voltage difference between the node voltages D1, D2, D3, D4 corresponding to multiple charging times Tb1, Tb2, Tb3, Tb4 and the target voltage VH or VL is dV. When the charging amounts of the node voltages D1, D2, D3, and D4 are the same, the corresponding display pixels PX can obtain the same charge amount. Although the node voltages D1, D2, D3, and D4 have not reached the predetermined target voltages, as long as Moderately adjusting the brightness of the backlight of the LCD panel can make up for the difference in display brightness, and can also make the brightness of the picture of the LCD panel uniform, and the visual performance is good. Accordingly, the charging voltage Vo of the function (2) can be expressed as (∣VH-VL|-dV).

FIG. 7 is a flowchart of a timing control process according to an embodiment of the present invention. The timing controller 10 includes a processor; and a memory coupled to the processor for storing a program code. The timing control flow in FIG. 7 can be compiled into the program code, which is used to instruct the processor of the timing controller 10 to execute related steps to generate the control signal SC to the source driver 11 . The timing control flow includes the following steps.

Step 71 : Calculate a plurality of charging and discharging times according to a target voltage and a plurality of RC time constants.

Step 72: Generate a control signal according to a processing time and a plurality of charging and discharging times corresponding to a plurality of display pixels.

In step 71 , the timing controller 10 calculates a plurality of charging and discharging times Tb1 . . . Tbm according to the target voltages VH, VL and a plurality of RC time constants τ1 . . . τm. For example, the timing controller 10 calculates the charging voltage Vo as |VH-VL| according to the target voltages VH and VL, and then deduces a plurality of charging and discharging times Tb1 . . . Tbm according to the function (2). In step 72 , the timing controller 10 generates a control signal SC according to the processing time Ta and a plurality of charging and discharging times Tb1 . . . Tbm. Therefore, through the timing control flow shown in FIG. 7 of the present invention, the timing controller 10 can generate the control signal SC with multiple duty cycles or multiple pulse frequencies, so that the brightness of the screen of the LCD panel is uniform and the visual performance is good.

It should be noted that the control signal GC for the gate driver 12 should also have multiple duty cycles or multiple pulse frequencies to cooperate with the control signal SC of the source driver 11, so that multiple display pixels PX can operate at an appropriate timing. is turned on or off. Specifically, since the refresh times T1 . . . Tm of the m display pixels PX are different, the control signal GC used for the gate driver 12 must turn on the m gate channels at a corresponding timing. In addition, the gate driver 12 also faces the similar problem that the signal path increases and the load impedance increases. The remote switch (transistor) needs a higher conduction voltage to be turned on, so the switch characteristics should be considered to adjust the gate driver. 12 control signal GC.

To sum up, unlike the traditional control signal which only has a single charging and discharging time, the timing control method and timing controller of the present invention use control signals with multiple charging and discharging times or multiple pulse frequencies to adapt to the signal path The charge and discharge capacity required by the load at different locations. In this way, since a plurality of display pixels can be charged and discharged to a target voltage within a plurality of charge and discharge times, the timing control method and timing controller of the present invention can improve the uneven brightness of the LCD panel.

The present invention has been described by the above-mentioned related embodiments, but the above-mentioned embodiments are only examples for implementing the present invention. It must be pointed out that the disclosed embodiments do not limit the scope of the present invention. On the contrary, modifications and equivalent arrangements included in the spirit and scope of the patent claims are included in the scope of the present invention.

1: Display device 10: Timing controller 11: Source driver 12: Gate driver 13: Display panel 71, 72: Steps CLC: light emitting unit D1, D2, D3, D4: Node voltage dV: voltage difference GC, SC, SC2, SC3, SC4: control signal G1...G4: gate drive signal N1, N2, N3, N4: nodes N12, N13, N14: near-end node voltage N42, N43, N44: remote node voltage PX: display pixels S1...S5: Source drive signal T, T1, T2, T3, T4: update time TA, Ta: processing time TB, TC, TD, Tb1, Tb2, Tb3, Tb4: charge and discharge time VCOM: system voltage VH, VL: target voltage X, Y: direction

FIG. 1 is a partial schematic diagram of a display device (display) according to an embodiment of the present invention. FIG. 2 is a schematic diagram of voltage versus time of a control signal, a target voltage, a near-end node voltage, and a far-end node voltage. 3 is a schematic diagram of another control signal, a target voltage, another near-end node voltage, and another far-end node voltage versus time. 4 is a schematic diagram of another control signal, a target voltage, another near-end node voltage, and another far-end node voltage versus time. FIG. 5 is a schematic diagram of a control signal, a target voltage, and a plurality of node voltages versus time according to an embodiment of the present invention. FIG. 6 is a schematic diagram of a target voltage and a plurality of node voltages versus time according to an embodiment of the present invention. FIG. 7 is a flowchart of a timing control process according to an embodiment of the present invention.

71, 72: Steps

Claims (6)

A timing control method, comprising: calculating a plurality of charging and discharging times corresponding to a plurality of display pixels according to a target voltage and a plurality of RC time constants; and generating a control signal according to a processing time and the plurality of charging and discharging times; Wherein according to the target voltage and the plurality of RC time constants, the step of calculating the plurality of charging and discharging times includes: according to a function, a plurality of instantaneous charging voltages corresponding to the plurality of display pixels, the plurality of RC time constants, a charging voltage, calculating the multiple charging and discharging times, wherein the function is expressed as follows: VC ( t )= V ₀ (1- e ^-t/τ ); wherein VC(t) is the multiple corresponding to the multiple display pixels One of the instant charging voltages, t is one of the multiple charging and discharging times, τ is one of the multiple RC time constants, Vo is the charging voltage. The timing control method as described in Claim 1, wherein the control signal has a plurality of update times, and the i-th update time in the plurality of update times is expressed as follows: Ti=Ta+Tbi; wherein, 1≦i≦m, Tbi<Tb(i+1), Ta is the processing time, and Tbi is the ith charging and discharging time among the plurality of charging and discharging times. The timing control method as described in claim 1, wherein according to the target voltage and the multiple RC time constants, the step of calculating the multiple charging and discharging times includes: calculating the time between a first target voltage and a second target voltage an absolute value to calculate the charging voltage. The timing control method as described in claim 1, wherein according to the target voltage and the multiple RC time constants, the step of calculating the multiple charging and discharging times includes: calculating the time between a first target voltage and a second target voltage An absolute value, calculating the difference between the absolute value and a voltage difference to calculate the charging voltage. A timing controller for a display device, comprising: a processor; and a memory, coupled to the processor, for storing a program code, and the program code is used to instruct the processor to execute the request item 1 To the timing control method described in any one of Claim 4. A display device, comprising: a display panel, including a plurality of display pixels as described in Claim 1; a source driver, coupled to the display panel, for generating a plurality of source driving signals to the display panel; a gate driver, coupled to the display panel, for generating a plurality of gate drive signals to the display panel; and a timing controller as described in claim 5, coupled to the source driver and the gate driver; Wherein the timing controller generates the control signal as described in claim 1 to the source driver, so that the source driver generates the plurality of source drive signals to the display panel according to the control signal.

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