TWI789462B - Radio frequency integrated circuit supporting carrier aggregation, wireless communication device including the same and non-transitory processor readable storage medium - Google Patents

Abstract

A radio frequency (RF) integrated circuit is provided. The RF integrated circuit supports carrier aggregation and includes first receiving circuits and a first shared phase locked loop circuit that provides a first frequency signal of a first frequency to the first receiving circuits. One of the first receiving circuits includes an analog to digital converter (ADC) and a digital conversion circuit. The ADC converts an RF signal received by the one of the first receiving circuits to a digital signal by using the first frequency signal. The digital conversion circuit generates a digital baseband signal by performing frequency down conversion on the digital signal.

Description

Radio frequency integrated circuit supporting carrier aggregation, its wireless communication device and non-transitory processor-readable storage medium [CROSS-REFERENCE TO RELATED APPLICATIONS]

This application claims the priority of Korean Patent Application No. 10-2017-0159682 and No. 10-2018-0083140 filed at the Korea Intellectual Property Office on November 27, 2017 and July 17, 2018, respectively. The disclosures of each of said Korean patent applications are hereby incorporated by reference in their entirety.

Apparatuses, devices and articles of manufacture according to the present disclosure relate to radio frequency (RF) integrated circuits supporting carrier aggregation, and more particularly to radio frequency integrated circuits for transmitting and receiving radio frequency signals.

The wireless communication device can modulate the data and transmit the radio frequency (RF) signal to the wireless communication network by loading a radio frequency (RF) signal on a certain carrier. In addition, the wireless communication device can receive radio frequency signals from the wireless communication network, and The received RF signal is amplified, and the amplified RF signal is demodulated. To transmit and receive more data, wireless communication devices can support carrier aggregation, that is, send and receive radio frequency signals modulated into multiple carriers.

One aspect of the present invention is to provide a radio frequency (RF) integrated circuit and a wireless communication device including the radio frequency integrated circuit. The power consumption efficiency is high.

According to an aspect of the exemplary embodiments, there is provided a radio frequency (RF) integrated circuit configured to support carrier aggregation, the radio frequency integrated circuit including: a plurality of first receiving circuits; and a first shared phase-locked loop circuit , configured to provide a first frequency signal of a first frequency to the plurality of first receiving circuits, wherein one of the plurality of first receiving circuits includes: an analog to digital converter (analog to digital converter, ADC) configured to convert the radio frequency signal received by the one of the plurality of first receiving circuits into a digital signal using the first frequency signal; and a digital conversion circuit configured to convert the radio frequency signal by the The digital signal is down-converted to generate a digital baseband signal.

According to another aspect of the exemplary embodiment, there is provided a wireless communication device configured to support carrier aggregation, the wireless communication device includes a radio frequency (RF) integrated circuit and a modem, and the radio frequency integrated circuit includes: a receiving circuit configured to receive radio frequency signals; and a shared phase-locked loop circuit configured to provide a frequency signal of a specific frequency to the plurality of receiving circuits for analog-to-digital conversion Alternatively, the modem is configured to provide a digital reference signal to the RF IC for downconverting the RF signal.

According to another aspect of the exemplary embodiments, there is provided a non-transitory processor-readable storage medium including commands to be executed by a processor in a wireless communication device, the wireless communication device including a plurality of receiving circuits, The plurality of receiving circuits share a phase-locked loop circuit, and the command, when executed by the processor, is configured to provide a digital reference signal to the plurality of receiving circuits for use based on and determined by the processor. Down-converting the radio frequency (RF) signal to the channel corresponding to the radio frequency (RF) signal received by the plurality of receiving circuits, and providing the plurality of receiving circuits with a frequency band group corresponding to the radio frequency signal A signal that adjusts the sampling rate when a receiving circuit performs an analog-to-digital conversion.

10: Wireless communication system

100, 200, 300, 500, 600: wireless communication device

110, 112: base station

114: Broadcast station

120: System controller

130: Satellite

210_1: main antenna

210_2: Auxiliary antenna

230_1: the first transceiver circuit/transmitter circuit

230_2: Second transceiver circuit/transmitter circuit

232_1: The first antenna interface circuit

232_2: Second antenna interface circuit

234_1, 234_2: receiving circuit

236_1, 236_2: transmission circuit

250, 350, 550, 650: Modem

250a, 1010: memory

330_1~330_n-1, 330_n: first receiving circuit~nth receiving circuit

330G1_1~330G1_j-1, 330G1_j: the first receiving circuit

330_2, 330G2_1~330G2_k-1, 330G2_k: second receiving circuit

331_1, 331_11, 331_12: the first low noise amplifier (LNA)

331_2, 331_21, 331_22: second low noise amplifier (LNA)

331_3, 331_31, 331_32: the third low noise amplifier (LNA)

331_m: mth Low Noise Amplifier (LNA)

332_1, 332_2, 332_3~332_m: first filter~mth filter

332_1', 332_11, 332_12: Low Band (LB) Filters

332_2', 332_21, 332_22: mid-band (MB) filters

332_3', 332_31, 332_32: High Band (HB) filter

333, 333_1, 333_2: multiplexer (MUX)

334, 334_1, 334_2: Analog-to-digital converter (ADC)

334': Time-interleaved ADC (ADC_TIL)

334_1', 334_2': time-interleaved ADC (ADC_TIL)

335, 335_1, 335_2, 534, DC_CKT: digital conversion circuit

370: Shared phase-locked loop circuit (Shared_PLL)

370G1: The first Shared_PLL (Shared_PLL1)

370G1', 380': frequency divider

370G2: Second Shared_PLL (Shared_PLL2)

370G2', 570, 670: Shared_PLL

400: time-interleaved ADC

401: Splitter

402: the first ADC circuit ADC_1/the first ADC circuit/ADC circuit

403: second ADC circuit ADC_2/second ADC circuit/ADC circuit

404: the third ADC circuit ADC_3/the third ADC circuit/ADC circuit

405: fourth ADC circuit ADC_4/fourth ADC circuit/ADC circuit

406: Combiner

407: time interleaving control circuit

408:ADC drive voltage supply circuit

530_1~530_n-1, 530_n: first transmission circuit~nth transmission circuit

531: Power Amplifier (PA)

532: filter

533:Digital-to-analog converter (DAC)

630_1~630_n-1, 630_n: first transceiver circuit~nth transceiver circuit

1000: electronic device

1011: program storage device

1012: data storage device

1013: application

1014: Frequency conversion program & data type conversion program

1020: processor unit

1021: memory interface

1022: Processor

1023: peripheral device interface

1040: Input/Output Controller

1050: display

1060: input device

1090: communication processor/communication processing unit

1092: Shared PLL circuit

AN_CKT: Analog Circuit

AN_S, AN_S1, AN_S2: Analog signal

BB _IN1 : Digital baseband signal

BB _IN2 ~BB _INn-1 , BB _INn : second digital baseband signal ~ nth digital baseband signal

BB _OUT1 ~BB _OUTn-1 , BB _OUTn : first digital baseband signal ~nth digital baseband signal

BB _OUT1 (ω1): The first digital baseband signal

BB _OUT2 (ω2): The second digital baseband signal

BG1: First Band Group

BG2: Second Band Group

BG3: Third Band Group

BG4: Fourth Band Group

BGI: Band Group Information

BGI1: the first BGI

BGI2: Second BGI

D_RS1: The first digital reference signal

D_RS1’, D_RS1a, D_RS1b: digital reference signal

D_RS2: Second digital reference signal

D_RSn-1, D_RSn-1’: n-1th digital reference signal

D_RSn, D_RS’: nth digital reference signal

DEa, DEb: Digital down-frequency filter / down-frequency filter

DG_S, DG_S1, DG_S2: digital signal

DIV_F_S: The divided frequency signal

DIV_RT_CS: frequency division ratio control signal

DMa, DMb: digital mixer

F_CS: frequency control signal

F_S: frequency signal

F_S1: The first frequency signal

F_S1’: signal

F_S2: Second frequency signal

f1: first frequency

f2: second frequency

f3: third frequency

f4: fourth frequency

f5: fifth frequency

FTa, FTb: digital low-pass filter

I_BB _OUT1 : In-phase digital baseband signal

MUX_CS, MUX_CS1, MUX_CS2: multiplexer (MUX) control signal

PLL_CS: PLL control signal

Q_BB _OUT2 : Quadrature digital baseband signal

RCKT_G1: The first receiving circuit group/receiving circuit group

RCKT_G2: Second receiving circuit group/receiving circuit group

RF _IN : RF signal

RF _OUT : RF output signal

S100, S110, S120: steps

t1: the first moment

t2: the second moment

t3: the third moment

t4: the fourth moment

t5: the fifth moment

t6: the sixth moment

t7: the seventh moment

t8: the eighth moment

T _INV , TINV': specific time interval

TL_CS, TL_CS’: time interleaved control signal

TL_CS1, TL_CS1’: first time interleaving control signal

TL_CS2, TL_CS2': second time interleaving control signal

T _S : specific time period

V_CS: voltage supply control signal

V _DD : driving voltage

ω1: first channel

ω2: second channel

Exemplary embodiments will be more clearly understood by reading the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings: FIG. communication system.

2A to 2D and FIGS. 3A and 3B are diagrams for explaining techniques for carrier aggregation (CA) according to an exemplary embodiment.

FIG. 4 is a block diagram illustrating a wireless communication device according to an exemplary embodiment.

FIG. 5 is a block diagram illustrating a connection relationship between a plurality of receiving circuits of a wireless communication device according to an exemplary embodiment.

6A to 6C are diagrams illustrating a receiving circuit and a shared lock according to an exemplary embodiment Diagram of the connection structure between phase loop circuits.

FIG. 7 is a block diagram of the first receiving circuit shown in FIG. 5 according to an exemplary embodiment.

8A and 8B are diagrams illustrating an implementation example of a time-interleaved analog-to-digital converter (ADC) capable of time interleaving, according to an exemplary embodiment.

9A and 9B are diagrams for explaining detailed operations of the time-interleaved ADC shown in FIGS. 8A and 8B according to an exemplary embodiment.

10A and 10B are block diagrams of an example implementation of a wireless communication device including a frequency divider, according to an exemplary embodiment.

11A and FIG. 11B are diagrams for explaining the operation of a receiving circuit and a data machine when performing an inter-band carrier aggregation operation (inter-CA operation) according to an exemplary embodiment, and FIG. 11C is an ADC operation in which the receiving circuit A flowchart of an exemplary embodiment of sequentially adjusting the sampling rate in FIG.

12A and 12B are block diagrams illustrating an implementation example of a wireless communication device in which each of the receiving circuits includes a frequency divider, according to an exemplary embodiment.

13 is a block diagram showing an implementation example in which a transmission circuit of a wireless communication device shares a PLL circuit according to an exemplary embodiment.

FIG. 14 is a block diagram showing an implementation example in which a transceiving circuit of a wireless communication device shares a PLL circuit according to an exemplary embodiment.

FIG. 15 is a block diagram illustrating an electronic device supporting a communication function including a beamforming function according to an exemplary embodiment.

Generally speaking, a wireless communication device used to support carrier aggregation may include a radio frequency integrated circuit (or radio frequency front-end module), where the radio frequency integrated circuit includes a plurality of receiving circuits (or receivers) for receiving radio frequency signals and transmitting radio frequency signals multiple transmission circuits (or transmitters).

Each of the receiving circuits may separately have a hardware configuration of a local oscillator, which generates a frequency signal for down-converting the radio frequency signal. Due to this configuration, it is difficult to reduce the design area of the receiving circuit, and since the wireless communication device requires a large number of local oscillators, the local oscillators consume a lot of power, and it is difficult to control the area when the wireless communication device performs communication operations. Efficient use of electricity.

Hereinafter, exemplary embodiments are explained in detail with reference to the accompanying drawings.

FIG. 1 shows a wireless communication device 100 performing wireless communication operations and a wireless communication system 10 including the wireless communication device 100 .

Referring to FIG. 1, the wireless communication system 10 may be a long term evolution (long term evolution, LTE) system, a code division multiple access (code division multiple access, CDMA) system, a global system for mobile communication (global system for mobile communication, GSM) system , and any one of a wireless local area network (wireless local area network, WLAN) system and the like. In addition, the CDMA system can also be implemented using various versions of CDMA such as: wideband CDMA (wideband CDMA, WCDMA), time division synchronous CDMA (time division synchronous CDMA, TD-SCDMA) and CDMA2000.

The wireless communication system 10 may include at least two base stations (base stations) 110 and 112 and a system controller 120 . However, the exemplary embodiment is not limited thereto, and the wireless communication system 10 may include multiple base stations and multiple network entities. The wireless communication device 100 may be called user equipment (user equipment, UE), mobile station (mobile station, MS), mobile terminal (mobile terminal, MT), user terminal (user terminal, UT), subscriber station (subscriber) station, SS), mobile devices, etc. The base stations 110 and 112 can be referred to as fixed stations that communicate with the wireless communication device 100 and/or other base stations, and the base stations 110 and 112 can communicate with the wireless communication device 100 and/or other base stations to send and receive information including control Radio frequency (RF) signals for information. Each of the base stations 110 and 112 may be called a Node B, an evolved Node B (evolved Node B, eNB), a base transceiver system (BTS), an access point (access point, AP), etc. .

The wireless communication device 100 can communicate with the wireless communication system 10 and can receive signals from the broadcasting station 114 . In addition, the wireless communication device 100 can receive signals from satellites 130 of a global navigation satellite system (GNSS). The wireless communication device 100 may support radio technologies for wireless communication (eg, LTE, CDMA2000, WCDMA, TD-SCDMA, GSM, 802.11, etc.).

The wireless communication device 100 can utilize multiple carriers to support carrier aggregation for performing transceiving operations. The wireless communication device 100 can perform wireless communication with the wireless communication system 10 in low frequency band, middle frequency band and high frequency band. Each of the low frequency band, the mid frequency band and the high frequency band may be referred to as a frequency band group, and each frequency band group may include a plurality of frequency bands. Frequency band groups can be based on communication standards or communication infrastructure It can be determined in different ways, and the frequency band group can be determined more finely or roughly than the above-mentioned low frequency band, middle frequency band and high frequency band. That is, the low frequency band, mid frequency band, and high frequency band are just examples. In addition, the bandwidth of the frequency bands included in each frequency band group may vary according to communication standards or communication infrastructure.

For example, in LTE, one frequency band may cover a maximum of about 20 megahertz (MHz). Carrier aggregation (hereinafter referred to as CA) can be classified into intra-band CA (intra-band CA) and inter-band CA (inter-band CA). Intra-band CA may refer to performing wireless communication operations using multiple carriers in the same frequency band, and inter-band CA may refer to performing wireless communication operations using multiple carriers in different frequency bands.

The radio frequency integrated circuit of the wireless communication device 100 according to the exemplary embodiment may include a plurality of receiving circuits for receiving radio frequency signals, and at least two receiving circuits in the receiving circuits may share a phase-locked loop circuit, the phase-locked loop circuit The loop circuit generates a frequency signal for analog-to-digital conversion operation on the radio frequency signal. In addition, each receiving circuit may include a digital conversion circuit for down-converting the radio frequency signal (i.e., performing down-conversion on the radio frequency signal), and the digital conversion circuit may receive the radio frequency signal converted into a digital signal and perform down-conversion on the radio frequency signal . The digital conversion circuit can receive a digital reference signal for performing down-conversion from a modem (modem) of the wireless communication device 100 .

In addition, the radio frequency integrated circuit of the wireless communication device 100 may include a plurality of transmission circuits for transmitting radio frequency signals, and at least two transmission circuits in the transmission circuits may share a phase-locked loop circuit, and the phase-locked loop circuit generates Frequency signal for digital-to-analog conversion operation on radio frequency signals. In addition, each of the transmit circuits can A digital conversion circuit for up-converting the radio frequency signal (ie, performing up-conversion on the radio frequency signal) is included, and the digital conversion circuit can receive a digital baseband signal from the modem and perform up-conversion on the digital baseband signal. The digital conversion circuit can receive the digital reference signal for performing up-conversion from the modem of the wireless communication device 100 .

In addition, the receiving circuit and the transmitting circuit of the radio frequency integrated circuit of the wireless communication device 100 may be implemented to share a PLL circuit, and a specific exemplary embodiment of sharing the PLL circuit will be described with reference to FIG. 6A and so on.

FIG. 2A to FIG. 2D and FIG. 3A and FIG. 3B are diagrams for explaining carrier aggregation technology.

Figure 2A is an example diagram of continuous in-band CA. Referring to FIG. 2A , the wireless communication device 100 in FIG. 1 can utilize four consecutive carriers in the same frequency band in the low frequency band to transmit and receive signals.

FIG. 2B is an example diagram of discontinuous in-band CA. Referring to FIG. 2A , the wireless communication device 100 can utilize four consecutive carriers in the same frequency band in the low frequency band to transmit and receive signals. The frequency band may include multiple frequency channels, and the four consecutive carriers may respectively correspond to different frequency channels. The degree to which the carriers are spaced apart from each other may be, for example, about 5 megahertz, about 10 megahertz, or another amount.

FIG. 2C is an example diagram of inter-band CA in the same band group. Referring to FIG. 2C, the wireless communication device 100 can perform signal processing using four carriers corresponding to channels in two frequency bands (ie, low frequency band 1 and low frequency band 2) included in the same frequency band group (ie, low frequency band). send and receive.

FIG. 2D is an example diagram of inter-band CA in different frequency band groups. Reference picture 2D, the wireless communication device 100 can transmit and receive signals using four carriers corresponding to channels in different frequency band groups. Two carriers may correspond to channels in any one of the frequency bands included in the low frequency band, and the other two carriers may correspond to channels in any one of the frequency bands included in the middle frequency band.

The CAs shown in FIGS. 2A-2D are not limited to these examples, and the wireless communication device 100 can support various CA combinations of frequency bands or frequency band groups. In addition, the CAs shown in FIGS. 2A to 2D show four carriers, but the specific number of carriers is not limited and may be smaller or larger than the four carriers shown in the figures.

Referring to FIG. 3A, a new technique for CA has emerged that combines and operates multiple frequency bands at one or more base stations to meet the need for increased bit rates. As one of the mobile networks, LTE can achieve a data transmission speed of approximately 100 megabits per second (Mbps), and thus, can transmit and receive large-capacity video smoothly in a wireless environment. FIG. 3A shows an example in which the data transmission speed is increased by up to about 5 times by combining five frequency bands in the LTE standard by CA technology. Since each carrier in FIG. 3A is a carrier defined by LTE, and a frequency bandwidth is defined up to about 20 MHz in the LTE standard, the wireless communication device 100 according to the exemplary embodiment can increase the data rate Increased to a maximum bandwidth of approximately 100 MHz.

Although FIG. 3A shows an example in which only carriers defined by LTE are combined, exemplary embodiments are not limited thereto. As shown in FIG. 3B , carriers of different wireless communication networks can also be combined. Referring to FIG. 3B, since the frequency bands are combined by the CA technique, it is possible not only to combine the frequency bands in the LTE standard but also to Furthermore, frequency bands in the 3G standard and the wireless fidelity (Wi-fi) standard can also be combined. In a similar manner, LTE-Advanced (LTE-A) can perform much faster data transmission by employing CA technology.

FIG. 4 is a block diagram illustrating a wireless communication device 200 according to an exemplary embodiment.

Referring to FIG. 4 , the wireless communication device 200 may include a first transceiver circuit (or transceiver) 230_1 connected to the main antenna 210_1 , a second transceiver circuit 230_2 connected to the auxiliary antenna 210_2 and a modem (or baseband processor) 250 . The first transceiving circuit 230_1 may include a first antenna interface circuit 232_1 , a receiving circuit 234_1 and a transmitting circuit 236_1 . The second transceiver circuit 230_2 may include a second antenna interface circuit 232_2 , a receiving circuit 234_2 and a transmitting circuit 236_2 . In FIG. 4, each of the first transceiving circuit 230_1 and the second transceiving circuit 230_2 is shown as including one of the receiving circuits 234_1 and 234_2 and one of the transmitting circuits 236_1 and 236_2, but this is only is an exemplary embodiment. The exemplary embodiment is not limited thereto, and the first transceiver circuit 230_1 and the second transceiver circuit 230_2 may further include a plurality of receiving circuits and a plurality of transmitting circuits, respectively.

The first transceiver circuit 230_1 and the second transceiver circuit 230_2 can support multiple frequency bands, multiple radio technologies, CA, receiving diversity, multiple-input multiple-output between multiple transmit antennas and multiple receive antennas. multiple-out, MIMO) transmission, etc.

The receiving circuits 234_1 and 234_2 may include a low noise amplifier, an analog-to-digital converter (ADC) and a digital conversion circuit DC_CKT. receiving circuit 234_1 and The configuration of 234_2 can be applied to other receiving circuits included in the wireless communication device 200 . In the following, the operation of the first transceiving circuit 230_1 is explained, and the exemplary embodiment of the first transceiving circuit 230_1 can be applied to the second transceiving circuit 230_2.

To receive data, the main antenna 210_1 can receive radio frequency signals from the base stations 110 and 112 and so on. The first antenna interface circuit 232_1 can route the RF signal to the selected receiving circuit 234_1. The first antenna interface circuit 232_1 may include a duplexer, a filter circuit, an input matching circuit and the like.

The receiving circuit 234_1 according to the exemplary embodiment may filter the received radio frequency signal so that only signal components corresponding to a specific frequency band group (or specific frequency band) pass therethrough and may perform conversion of the filtered radio frequency signal into digital Signal manipulation (or analog-to-digital conversion (ADC)). In addition, the digital conversion circuit DC_CKT can receive a digital reference signal from the modem 250, and based on the received digital reference signal, can perform down-conversion on the radio frequency signal that has been converted into a digital signal. Since the receiving circuit 234_1 includes the digital conversion circuit DC_CKT, hardware configuration of a local oscillator for generating a frequency signal having a variable frequency varying according to a channel corresponding to a radio frequency signal received by the receiving circuit 234_1 may not be required. Rate. Therefore, the size of the receiving circuit 234_1 can be reduced, and thus, the design efficiency of a radio frequency integrated circuit including the receiving circuit 234_1 can be improved. The receiving circuit 234_1 can provide the digital baseband signal generated by down-conversion to the modem 250, and the modem 250 can process the digital baseband signal to generate a data signal.

In addition, in some exemplary embodiments, the plurality of receiving circuits in the first transceiver circuit 230_1 including the receiving circuit 234_1 may share a PLL circuit. road. In some exemplary embodiments, the PLL circuit can generate a frequency signal for analog-to-digital conversion and provide the generated frequency signal to the plurality of receiving circuits sharing the PLL circuit. Since the receiving circuits sharing the PLL circuit jointly receive the frequency signal with the same frequency, the frequency division operation of the frequency signal can be used so that each of the receiving circuits can obtain the frequency signal with the target frequency. In some exemplary embodiments, the modem 250 can control the frequency division operation of the frequency signal of the phase-locked loop circuit so that each of the receiving circuits can obtain a frequency signal with a target frequency, and the receiving circuit can use An analog-to-digital conversion operation is performed on the frequency signal of the target frequency. Detailed exemplary embodiments on this issue are subsequently set forth with reference to FIGS. 8A-8C , 10 , 13 , and so on.

In some exemplary embodiments, the plurality of receiving circuits 234_2 in the second transceiving circuit 230_2 may share a phase-locked loop circuit different from the phase-locked loop circuit shared by the plurality of receiving circuits 234_1 in the first transceiving circuit 230_1 . In other words, the wireless communication device 200 may be implemented with a structure in which the first transceiver circuit 230_1 and the second transceiver circuit 230_2 each share its own different phase-locked loop circuit. In another exemplary embodiment, the plurality of receiving circuits 234_1 in the first transceiving circuit 230_1 and the plurality of receiving circuits 234_2 in the second transceiving circuit 230_2 may share one phase locked loop circuit. In other words, the wireless communication device 200 can be implemented with a structure in which the first transceiver circuit 230_1 and the second transceiver circuit 230_2 share a phase-locked loop circuit. In addition, a plurality of receiving circuits in the first transceiver circuit 230_1 and the second transceiver circuit 230_2 may be grouped and the receiving circuits in the group share different phase-locked loop circuits. However, the above exemplary embodiment It is merely exemplary, and exemplary embodiments of the receiving circuits 234_1 and 234_2 sharing the PLL circuit can be implemented in various ways.

The transmission circuits 236_1 and 236_2 may include power amplifiers, digital-to-analog converters (digital to analog converters, DACs) and digital conversion circuits (not shown). The configurations of the transmission circuits 236_1 and 236_2 can be applied to other transmission circuits included in the wireless communication device 200 .

The digital conversion circuit of the transmission circuit 236_1 can receive the digital reference signal and the digital baseband signal from the modem 250 and perform up-conversion on the digital baseband signal based on the digital reference signal. After that, the DAC of the transmitting circuit 236_1 can convert the digital baseband signal of the RF band into a digital RF signal, and the power amplifier of the transmitting circuit 236_1 can amplify the RF signal to have a proper output power level. The transmitting circuit 236_1 can provide the amplified RF signal to the main antenna 210_1 through the first antenna interface circuit 232_1, and the main antenna 210_1 can transmit the amplified RF signal to the base stations 110 and 112 and so on.

An exemplary embodiment similar to the exemplary embodiment in which the receiving circuit 234_1 and the receiving circuit 234_2 share a PLL circuit can also be applied to the transmitting circuits 236_1 and 236_2, and the PLL circuit shared by the transmitting circuit 236_1 and the transmitting circuit 236_2 It may be the same as or different from the PLL circuit shared by the receiving circuit 234_1 and the receiving circuit 234_2. Hereinafter, a PLL circuit shared by a plurality of reception circuits or a plurality of transmission circuits may be referred to as a shared PLL circuit.

The modem 250 can generate data signals by demodulating the baseband signals received from the transceiver circuits 230_1 and 230_2 and modulate the data signals by The generated baseband signal is provided to the transceiver circuits 230_1 and 230_2. In addition, the modem 250 can generate digital reference signals for down-conversion or up-conversion of the transceiver circuits 230_1 and 230_2 and provide the generated digital reference signals to the transceiver circuits 230_1 and 230_2. The modem 250 can control the frequency division operation of the frequency signal shared by the PLL circuit so that each of the receiving circuits 234_1 and 234_2 or the transmitting circuits 236_1 and 236_2 acquires a frequency signal with a target frequency. The data engine 250 may include a memory 250 a, and the memory 250 a may store instructions defined to perform the above-mentioned operations of the data engine 250 . The modem 250 may perform operations of the modem 250 according to the exemplary embodiment by executing instructions stored in the memory 250a.

FIG. 5 is a block diagram illustrating a connection relationship among a plurality of receiving circuits of a wireless communication device 300 according to an exemplary embodiment.

Referring to FIG. 5 , the wireless communication device 300 may include a first receiving circuit 330_1 to an nth receiving circuit 330_n, a modem 350 and a shared phase-locked loop circuit (Shared_PLL) 370 . The first receiving circuit 330_1 may include a first low noise amplifier (low noise amplifier, LNA) 331_1 to an mth low noise amplifier 331_m, a first filter 332_1 to an mth filter 332_m, a multiplexer (multiplexer, MUX) 333 , ADC 334 and digital conversion circuit 335 , and the configuration of the first receiving circuit 330_1 can be applied to the second receiving circuit 330_2 to the nth receiving circuit 330_n. The radio frequency signal RF _IN can be transmitted via a carrier in at least one frequency band, and at least one of the first to nth receiving circuits 330_1 to 330_n can be selected according to the CA type (ie, intra-band CA or inter-band CA) to Receive radio frequency signal RF _IN .

In some exemplary embodiments, Shared_PLL 370 may include a VCO Oscillator and frequency multiplier (frequency multiplier) and can generate a frequency signal with a specific frequency. The frequency of the clock signal generated by the Shared_PLL 370 can be controlled by the modem 350 through the PLL control signal PLL_CS. The Shared_PLL 370 may be implemented as a local oscillator according to an exemplary embodiment, and may have a structure in which the first to nth reception circuits 330_1 to 330_n share one local oscillator.

The first LNA 331_1 and the first filter 332_1 may constitute a path for receiving a signal component transmitted by a carrier corresponding to one frequency band group among the signal components of the radio frequency signal. In addition, to support the inter-band CA described with reference to FIG. 2C , the first LNA 331_1 and the first filter 332_1 may constitute a path for receiving a signal component transmitted by a carrier corresponding to one frequency band of the signal components of the radio frequency signal. In other words, a path capable of receiving a radio frequency signal RF _IN corresponding to each frequency band group (or each frequency band) can be constructed through the first LNA 331_1 to the mth LNA 331_m and the first filter 332_1 to the mth filter 332_m, and The MUX 333 may receive a multiplexer control signal MUX_CS from the modem 350 and perform a CA operation by selecting one of the multiple paths based on the received multiplexer control signal MUX_CS. In other words, the first receiving circuit 330_1 can receive one frequency band among the plurality of frequency band groups through the configuration of the first LNA 331_1 to the mth LNA 331_m, the first filter 332_1 to the mth filter 332_m, and the MUX 333 The radio frequency signal RF _IN corresponding to the group. The first filter 332_1 to the mth filter 332_m may be implemented to pass only components of the radio frequency signal RF _IN corresponding to a specific frequency band group. However, the exemplary embodiment is not limited thereto, and the first to mth filters 332_1 to 332_m may selectively filter the radio frequency signal RF _IN to support CA. For example, filters can have various passbands.

The ADC 334 can receive a frequency signal F_S with a specific frequency from the Shared_PLL 370 . The Shared_PLL 370 can provide the same frequency signal F_S to the first receiving circuit 330_1 to the nth receiving circuit 330_n. In other words, the first receiving circuit 330_1 to the nth receiving circuit 330_n may be implemented to share one Shared_PLL 370 . The ADC 334 can receive the radio frequency signal RF _IN which has passed through the selected path from the MUX 333 and can perform analog-to-digital conversion based on the frequency signal F_S.

The digital conversion circuit 335 can down-convert the radio frequency signal RF _IN converted into a digital signal based on the first digital reference signal D_RS1 received from the modem 350 . In other words, the digital conversion circuit 335 can perform the operation of converting the RF band signal into a baseband signal. The first digital reference signal D_RS1 can vary according to the channel corresponding to the radio frequency signal RF _IN . For example, further referring to FIG. 2A , the first digital reference signal D_RS1 in the case where the radio frequency signal RF _IN corresponds to a channel in the high frequency band may be different from the first digital reference signal D_RS1 in the case where the radio frequency signal RF _IN corresponds to a channel in the low frequency band. A digital reference signal D_RS1.

The digital conversion circuit 335 may provide the modem 350 with the first digital baseband signal BB _OUT1 generated as a result of performing down-conversion, and the modem 350 may process (or demodulate) the first digital baseband signal BB _OUT1 and Generate data signal. The above configuration of the first receiving circuit 330_1 may be applied to the second receiving circuit 330_2 to the nth receiving circuit 330_n. In other words, the modem 350 can provide the second digital reference signal D_RS2 to the nth digital reference signal D_RSn to the second receiving circuit 330_2 to the nth receiving circuit 330_n respectively, and can transmit from the second receiving circuit 330_2 to the nth receiving circuit 330_n respectively. Receive the second digital baseband signal BB _OUT2 to the nth digital baseband signal BB _OUTn .

The first receiving circuit 330_1 to the nth receiving circuit 330_n according to the exemplary embodiment may include a digital conversion circuit 335 which receives a digital reference signal from the modem 350 and performs down-conversion so that it is not necessary to use a local oscillator for A frequency signal varying according to a channel corresponding to the radio frequency signal RF _IN is generated. In addition, since the structure in which the first to nth reception circuits 330_1 to nth reception circuits 330_n share the Shared_PLL 370 can be applied, the size of the radio frequency integrated circuits including the first to nth reception circuits 330_1 to 330_n can be reduced, and the radio frequency product The power consumption of the body circuit can also be reduced.

6A to 6C are diagrams illustrating a connection structure between a receiving circuit and a shared PLL circuit according to an exemplary embodiment.

Referring to FIG. 6A, the radio frequency integrated circuit may include a plurality of first receiving circuits (330G1_1 to 330G1_j), a plurality of second receiving circuits (330G2_1 to 330G2_k), a first Shared_PLL (Shared_PLL1) 370G1 and a second Shared_PLL (Shared_PLL2) 370G2. The plurality of first receiving circuits (330G1_1 to 330G1_j) may be grouped into a first receiving circuit group RCKT_G1, and the plurality of second receiving circuits (330G2_1 to 330G2_k) may be grouped into a second receiving circuit group RCKT_G2 . The first receiving circuit group RCKT_G1 and the second receiving circuit group RCKT_G2 may be defined as units for grouping receiving circuits sharing one of the Shared_PLL1 370G1 and Shared_PLL2 370G2 , respectively.

In some exemplary embodiments, the first receiving circuit group RCKT_G1 may be connected to the Shared_PLL1 370G1 to receive the first frequency signal F_S1 of the first frequency. The second receiving circuit group RCKT_G2 can be connected to the Shared_PLL2 370G2 to receive the second frequency signal F_S2 of the second frequency. The first frequency of the first frequency signal F_S1 and the second frequency of the second frequency signal F_S2 may be the same as or different from each other. Although FIG. 6A shows an exemplary embodiment in which two receiving circuit groups (RCKT_G1 and RCKT_G2) are distinguished, exemplary embodiments are not limited thereto. Further implementation examples may be possible such that receive circuits are grouped into more receive circuit groups than shown in FIG. 6A and each receive circuit group may be individually connected to a shared lock phase loop circuit. That is, the number of receiving circuit groups is not particularly limited and can be more than two as shown in FIG. 6A .

In the following, an exemplary embodiment of a criterion for grouping receiving circuits into receiving circuit groups is explained with reference to FIG. 6B . Referring to FIG. 6A to FIG. 6B, the plurality of first receiving circuits (330G1_1 to 330G1_j) may have the ability to receive the first frequency band group BG1 between the first frequency f1 and the second frequency f2 and the second frequency f2 and the second frequency f2. The configuration of the first frequency signal F_S1 corresponding to the second frequency band group BG2 between the three frequencies f3, and the plurality of second receiving circuits (330G2_1 to 330G2_k) may have the ability to receive the third frequency f3 and the fourth frequency f4 The configuration of the second frequency signal F_S2 corresponding to the third frequency band group BG3 between the fourth frequency f4 and the fifth frequency f5 corresponding to the fourth frequency band group BG4. For example, the plurality of first receiving circuits (330G1_1 to 330G1_j) may include filters for receiving the first frequency signal F_S1 corresponding to the first frequency band group BG1 and the second frequency band group BG2, and the The plurality of second receiving circuits ( 330G2_1 to 330G2_k ) may include filters for receiving the second frequency signal F_S2 corresponding to the third frequency band group BG3 and the fourth frequency band group BG4 . In other words, the first frequency band group BG1 and the second frequency band group BG2 corresponding to the first frequency signal F_S1 receivable by the plurality of first receiving circuits (330G1_1 to 330G1_j) and the frequency band group BG2 that can be received by the plurality of second receiving circuits ( 330G2_1 to 330G2_k ) The third frequency band group BG3 and the fourth frequency band group BG4 corresponding to the received second frequency signal F_S2 may be different from each other. At this time, the plurality of first receiving circuits (330G1_1 to 330G1_j) may be grouped into a first receiving circuit group RCKT_G1, and the plurality of second receiving circuits (330G2_1 to 330G2_k) may be grouped into a second receiving circuit Group RCKT_G2. The frequency of the first frequency signal F_S1 received from Shared_PLL1 370G1 by the plurality of first receiving circuits (330G1_1 to 330G1_j) can be compared with the second frequency received by the plurality of second receiving circuits (330G2_1 to 330G2_k) from Shared_PLL2 370G2 The frequency of the signal F_S2 is low.

The first to fourth band groups BG1 to BG4 explained with reference to FIG. 6B are merely exemplary embodiments. There may be fewer or more frequency band groups, and receiving circuits may be grouped according to frequency band groups of frequency signals receivable by the receiving circuits. In addition, according to an exemplary embodiment, the RF IC may include a larger number of shared PLL circuits than that shown in FIG. 6A .

Referring to FIG. 6C, the radio frequency integrated circuit may include the plurality of first receiving circuits (330G1_1 to 330G1_j), the plurality of second receiving circuits (330G2_1 to 330G2_k), a frequency divider 370G1' and a Shared_PLL 370G2'. in some exemplary In an embodiment, the second receiving circuit group RCKT_G2 can be connected to the Shared_PLL 370G2 ′ to receive the second frequency signal F_S2 of a specific frequency. The first receiving circuit group RCKT_G1 can be connected to the frequency divider 370G1' to receive the signal F_S1', which is a signal obtained by frequency-dividing the second frequency signal F_S2. The frequency division ratio of the frequency divider 370G1' can be determined according to the frequency band group (or the frequency band in the frequency band group, or the channel) of the RF signal that can be received by the plurality of first receiving circuits (330G1_1 to 330G1_j). The exemplary embodiment shown in FIG. 6C is only exemplary, and there may be various implementations in which more frequency dividers are respectively connected to more receiving circuit groups.

FIG. 7 is a block diagram of the first receiving circuit 330_1 shown in FIG. 5 according to an exemplary embodiment.

7, the first receiving circuit 330_1 may include a first LNA 331_1 to a third LNA 331_3, a low band (low band, LB) filter 332_1', a medium band (medium band, MB) filter 332_2', a high frequency band ( high band (HB) filter 332_3 ′, MUX 333 , ADC 334 and digital conversion circuit 335 . The first LNA 331_1 to the third LNA 331_3 , the LB filter 332_1 ′, the MB filter 332_2 ′, the HB filter 332_3 ′, the MUX 333 and the ADC 334 may be referred to as an analog circuit AN_CKT, and the original radio frequency signal RF _IN is input to all The above analog circuit AN_CKT. The digital conversion circuit 335 may include digital mixers DMa and DMb, digital low-pass filters FTa and FTb, and digital decimation filters (digital decimation filters, DECI) DEa and DEb.

The LB filter 332_1' can pass only the signal component corresponding to the LB of the radio frequency signal RF _IN , the MB filter 332_2' can pass only the signal component corresponding to the MB of the radio frequency signal RF _IN , and the HB filter 332_3' can only pass the signal component corresponding to the MB of the radio frequency signal RF IN. Pass the signal component corresponding to HB of the radio frequency signal RF _IN . However, the exemplary embodiment is just an example, and each of the LB filter 332_1 ′, the MB filter 332_2 ′, and the HB filter 332_3 ′ may be implemented to pass only signal components corresponding to different frequency bands, and The first receiving circuit 330_1 may include more than three filters 332 . Hereinafter, for convenience of explanation, it is assumed that each of the LB filter 332_1 ′, the MB filter 332_2 ′, and the HB filter 332_3 ′ is implemented to pass only signal components corresponding to different frequency band groups. The modem 350 may provide the MUX control signal MUX_CS to the MUX 333 and control the MUX 333 such that the radio frequency signal RF _IN having passed through any one of the LB filter 332_1 ′, the MB filter 332_2 ′, and the HB filter 332_3 ′ is received by the MUX 333 . Output to ADC 334. The ADC 334 can receive the frequency signal F_S from the Shared_PLL 370 and perform sampling on the analog radio frequency signal RF _IN based on the frequency signal F_S to generate a digital radio frequency signal RF _IN .

The digital mixers DMa and DMb can respectively receive the digital reference signals D_RS1a and D_RS1b from the modem 350, and can use the digital reference signals D_RS1a and D_RS1b to divide the digital radio frequency signals into the I channel and the Q channel respectively, and generate down-converted digital signal. The resulting down-converted digital signal may be filtered by passing through corresponding digital low-pass filters FTa and FTb to remove signals generated during down-conversion. The filtered digital signal may be down-sampled by passing through the corresponding down-frequency filters DEa and DEb respectively, and thus, the in-phase digital baseband signal I_BB OUT1 and the positive-phase digital baseband signal I_BB _OUT1 including samples corresponding to the target channel may be generated, respectively. Hand digital baseband signal Q_BB _OUT2 . The modem 350 can receive the in-phase digital baseband signal I_BB _OUT1 and the quadrature digital baseband signal Q_BB _OUT2 from the digital conversion circuit 335 . The modem 350 can control the downsampling degree of the digital down-conversion filters DEa and DEb, and thus can optimize the processing operation speed of the in-phase digital baseband signal I_BB _OUT1 and the quadrature digital baseband signal Q_BB _OUT2 of the modem 350 .

The modem 350 can change the digital reference signals D_RS1a and D_RS1b according to the channel corresponding to the radio frequency signal RF _IN received by the first receiving circuit 330_1. For example, when the MUX 333 activates the path formed by the first LNA 331_1 and the LB filter 332_1′, the first receiving circuit 330_1 can receive the radio frequency signal RF _IN corresponding to LB, and the modem 350 can generate an RF signal with a specific value The digital reference signals D_RS1a and D_RS1b enable the digital conversion circuit 335 to down-convert the radio frequency signal RF _IN from the frequency channel in the LB to the base frequency. In addition, when the MUX 333 activates the path formed by the second LNA 331_2 and the MB filter 332_2′, the first receiving circuit 330_1 can receive the radio frequency signal RF _IN corresponding to the MB, and the modem 350 can generate a digital reference with a specific value The signals D_RS1a and D_RS1b enable the digital conversion circuit 335 to down-convert the radio frequency signal RF _IN from the channel in the MB to the baseband.

The configuration of the first receiving circuit 330_1 shown in FIG. 7 can be applied to other second receiving circuits 330_2 to nth receiving circuits 330_n shown in FIG. 5 .

8A and 8B are diagrams illustrating an implementation example of a time-interleaved ADC 400 capable of time-interleaving according to an exemplary embodiment.

According to an exemplary embodiment, ADC 334 shown in FIG. 7 may be implemented as time-interleaved ADC 400 shown in FIG. 8A . The time-interleaved ADC 400 may include a splitter 401, a first ADC circuit ADC_1 402, a second ADC circuit ADC_2 403, a third ADC circuit ADC_3 404 and a fourth ADC circuit ADC_4 405, a combiner 406 and a time-interleaved control circuit 407 . The time interleaving control circuit 407 can receive band group information (band group information, BGI) corresponding to the radio frequency signal RF _IN received by the first receiving circuit 330_1 from the modem 350 (refer to FIG. The time-interleaved control signals TL_CS and TL_CS′ are provided to the slicer 401 and the combiner 406 to control the sampling rate of the time-interleaved ADC 400 .

The divider 401 can receive the analog signal (or RF signal) AN_S and provide the analog signal AN_S to the first ADC circuit 402 to the fourth ADC circuit 405 with a constant time difference based on the time-interleaved control signal TL_CS. Therefore, the first ADC circuit 402 to the fourth ADC circuit 405 can receive the analog signal AN_S and the frequency signal F_S with different constant phases from the Shared_PLL 370 (refer to FIG. 7 ), and can compare the received analog signals based on the same sampling rate. The signal AN_S is digitally converted and the result of the digital conversion is provided to the combiner 406 . The combiner 406 can combine the digital conversion results from the first ADC circuit 402 to the fourth ADC circuit 405 based on the time-interleaved control signal TL_CS' and can generate a digital signal DG_S.

Since the first receiving circuit (330_1 shown in FIG. 7 ) shares the PLL circuit (370 shown in FIG. 7 ) with other receiving circuits, it may be difficult for the first receiving circuit 330_1 to obtain proper samples every time in actual ADC operation. A frequency signal with an appropriate frequency in terms of frequency. Therefore, the first receiving circuit (330_1 shown in FIG. 7) can be implemented to include the time-interleaved ADC 400 shown in FIG. 8A, thereby selectively controlling the first ADC circuit 402 to the fourth ADC circuit 405 to appropriately change the overall time The sampling rate of the ADC 400 is interleaved. For example, when the time-interleaved ADC 400 receives the frequency For the frequency signal F_S lower than the threshold frequency, the time interleaving control circuit 407 may selectively use a larger number of ADC circuits than would be used at the threshold frequency to obtain an appropriate sampling rate. When receiving a frequency signal F_S with a frequency higher than the threshold frequency, the time interleaving control circuit 407 can selectively control a number of ADC circuits smaller than the number of ADC circuits to be used at the threshold frequency to obtain an appropriate sampling rate .

However, the exemplary embodiments are merely examples. The time interleaving control circuit 407 can receive frequency band related information or channel related information corresponding to the radio frequency signal RF _IN received by the first receiving circuit 330_1 from the modem (350 shown in FIG. 7 ), and can be based on the frequency band related information or channel related information to control the sampling rate of the time-interleaved ADC 400. When the time-interleaved ADC 400 is controlled based on band-related information or channel-related information, the sampling rate can be adjusted more finely than when the time-interleaved ADC 400 is controlled based on BGI.

FIG. 8A shows an exemplary embodiment in which the time-interleaved ADC 400 includes a separate time-interleaved control circuit 407, but the exemplary embodiment is not limited thereto, and in some exemplary embodiments, the data engine (350 shown in FIG. 7 ) can be implemented to directly control the time-interleaved ADC 400. In addition, FIG. 8A shows an exemplary embodiment in which the time-interleaved ADC 400 includes four ADC circuits (ie, 402 to 405), but the exemplary embodiment is not limited thereto, and the time-interleaved ADC 400 may be implemented to include more Fewer or greater numbers of ADC circuits are shown in FIG. 8A.

Referring to FIG. 8B , compared to FIG. 8A , the time-interleaved ADC 400 may further include an ADC driving voltage supply circuit 408 . The time interleaving control circuit 407 may provide a voltage supply control signal V_CS to the ADC driving voltage supply circuit 408, the voltage supply control signal V_CS includes information about at least one ADC circuit used in ADC operation. The ADC driving voltage supply circuit 408 may provide the driving voltage V _DD to at least one of the first ADC circuit 402 to the fourth ADC circuit 405 used for ADC operation based on the voltage supply control signal V_CS, but may not provide the driving voltage V DD to the ADC not used for ADC operation. The circuit provides a driving voltage V _DD . In other words, the ADC driving voltage supply circuit 408 can only provide the driving voltage V _DD to the ADC circuit for ADC operation, thereby reducing power consumption.

9A and 9B are diagrams for explaining detailed operations of the time-interleaved ADC 400 according to an exemplary embodiment.

Referring to FIG. 9A, the time interleaving control circuit 407 can determine the sampling rate of the time interleaving ADC 400 based on the first BGI BGI1 received from the data machine (350 shown in FIG. Interleaved control signals TL_CS1 and TL_CS1'. The divider 401 can receive the analog signal AN_S1 and provide the analog signal AN_S1 with a specific time interval T _INV to the first ADC circuit 402 to the fourth ADC circuit 405 based on the first time interleaving control signal TL_CS1 . The first ADC circuit 402 to the fourth ADC circuit 405 can perform a sampling operation every specific time period Ts based on the frequency signal F_S received from the shared PLL circuit (370 shown in FIG. 7 ). Sampling results respectively generated by sampling the analog signal AN_S1 at each of the first time t1 to the eighth time t8 through the first ADC circuit 402 to the fourth ADC circuit 405 may be provided to the combiner 406, And the combiner 406 can output the digital signal DG_S1 by combining the sampling results based on the first time interleaving control signal TL_CS1 ′.

Referring to FIG. 9B, the time interleaving control circuit 407 can determine the sampling rate of the time interleaving ADC 400 based on the second BGI BGI2 received from the data engine (350 shown in FIG. Interleaving control signals TL_CS2 and TL_CS2'. The divider 401 can receive the analog signal AN_S2 and provide the analog signal AN_S2 with a specific time interval TINV′ to the first ADC circuit 402 and the third ADC circuit 404 based on the second time interleaving control signal TL_CS2 . The first ADC circuit 402 and the third ADC circuit 404 can perform a sampling operation on the analog signal AN_S2 every specific time period Ts based on the frequency signal F_S received from the shared PLL circuit (370 shown in FIG. 7 ). Sampling results respectively generated by sampling the analog signal AN_S2 at the first time t1, the third time t3, the fifth time t5 and the seventh time t7 through the first ADC circuit 402 and the third ADC circuit 404 may be provided to the combiner 406, and the combiner 406 can output the digital signal DG_S2 by combining the sampling results based on the second time-interleaved control signal TL_CS2'. Additionally, as explained above with reference to FIG. 8B , in some exemplary embodiments, the ADC drive voltage supply circuit (408 shown in FIG. 8B ) may be provided and controlled such that the drive voltage V _DD is not supplied to the second ADC circuit 403 and the fourth ADC circuit 405 . For example, the driving voltage V _DD may only be provided to the first ADC circuit 402 and the third ADC circuit 404 , and may not be provided to the second ADC circuit 403 and the fourth ADC circuit 405 indicated by hatching in FIG. 9B .

By controlling the time-interleaved ADC 400 in the manner described with reference to FIGS. 9A and 9B , the sampling rate can be properly adjusted without directly changing the frequency of the frequency signal F_S. frequency.

10A and 10B are block diagrams of an implementation example of a wireless communication device 300 including a Shared_PLL 370 for generating a frequency signal having a variable frequency, according to an exemplary embodiment.

Compared with the wireless communication device 300 shown in FIG. 5 , the wireless communication device 300 shown in FIG. 10A can receive the frequency control signal F_CS from the modem 350 . Hereinafter, content overlapping with that given with reference to FIG. 5 is omitted, and only a new configuration is explained.

Referring to FIG. 10A , the modem 350 can generate the frequency control signal F_CS based on the BGI of the radio frequency signal RF _IN received by the first receiving circuit 330_1 to the nth receiving circuit 330_n. For example, when the first receiving circuit 330_1 receives the radio frequency signal RF _IN corresponding to LB, the second receiving circuit 330_2 receives the radio frequency signal RF _IN corresponding to MB, and the third receiving circuit 330_3 receives the radio frequency signal RF corresponding to HB _IN , the modem 350 can generate the frequency control signal F_CS by determining the target frequency based on the band group of HB corresponding to the highest band group. As another example, when the first receiving circuit 330_1 receives the radio frequency signal RF _IN corresponding to LB and the second receiving circuit 330_2 receives the radio frequency signal RF _IN corresponding to MB, the modem 350 can use The frequency band group of the MB determines the target frequency to generate the frequency control signal F_CS.

The Shared_PLL 370 can receive the frequency control signal F_CS from the modem 350 and can provide the frequency signal F_S with the target frequency to the first receiving circuit 330_1 to the nth receiving circuit 330_n based on the frequency control signal F_CS. In other words, the Shared_PLL 370 can provide the first receiving circuit 330_1 to the nth receiving circuit 330_n with the frequency signal F_S having a relatively high frequency, so as to utilize the received radio frequency signal in the first receiving circuit 330_1 to the nth receiving circuit 330_n RF _IN corresponds to the receiver circuit of the highest frequency band group to perform the appropriate ADC operation.

In other exemplary embodiments, the modem 350 may generate the frequency control signal F_CS based on information about the frequency band or channel of the radio frequency signal RF _IN received by the first receiving circuit 330_1 to the nth receiving circuit 330_n, thereby more finely Adjust the frequency control signal F_CS.

Referring to FIG. 10B , each of the first to nth reception circuits 330_1 to 330_n may include an ADC implemented by the time-interleaved ADC explained with reference to FIG. 8A and the like. Hereinafter, the first receiving circuit 330_1 is explained as an example. The first receiving circuit 330_1 may include a time-interleaved ADC (ADC_TIL) 334'. As explained with reference to FIG. 10A, since the frequency of the frequency control signal F_CS is determined using the receiving circuit having the highest frequency band group corresponding to the received radio frequency signal RF _IN , the frequency of the frequency signal F_S may not be suitable for performing ADC operations. Frequency of. At this time, the modem 350 can provide the ADC_TIL 334 ′ with information about the BGI of the radio frequency signal RF _IN received by the first receiving circuit 330_1 , and the ADC_TIL 334 ′ can adjust the sampling rate based on the BGI. In another embodiment, the modem 350 may provide the ADC_TIL 334′ with band-related information or channel-related information of the radio frequency signal RF _IN received by the first receiving circuit 330_1, and the ADC_TIL 334′ may be based on the band-related information or channel-related information Adjust the sample rate. A detailed description has already been given with reference to FIG. 8A, and thus will not be repeated.

11A and FIG. 11B are diagrams for explaining the first receiving circuit 330_1 and the second receiving circuit 330_2 and the data when the inter-band CA operation is performed according to an exemplary embodiment. 11C is a flowchart of an exemplary embodiment in which the sampling rate is sequentially adjusted in the ADC operation of the receiving circuit.

Referring to FIG. 11A , the wireless communication device 300 may include a first receiving circuit 330_1 , a second receiving circuit 330_2 and a Shared_PLL 370 . The first receiving circuit 330_1 may include a first LNA 331_11 to a third LNA 331_31 , an LB filter 332_11 , an MB filter 332_21 , an HB filter 332_31 , a MUX 333_1 , an ADC 334_1 and a digital conversion circuit 335_1 . The second receiving circuit 330_2 may include a first LNA 331_12 to a third LNA 331_32, an LB filter 332_12, an MB filter 332_22, an HB filter 332_32, a MUX 333_2, an ADC 334_2 and a digital conversion circuit 335_2. Hereinafter, the first receiving circuit 330_1 and the second receiving circuit 330_2 can receive the radio frequency signal RF _IN based on the MUX control signals MUX_CS1 and MUX_CS2 received from the modem 350 respectively, and the radio frequency signal RF _IN includes the first channel ω1 and the second channel The signal component corresponding to ω2. The signal component corresponding to the first channel ω1 may be said to be transmitted via a carrier located in the first channel ω1, and the signal component corresponding to the second channel ω2 may be said to be transmitted via a carrier in the second channel ω2 signal components. Hereinafter, it is assumed that the first channel ω1 is included in the HB and the second channel ω2 is included in the LB.

The first receiving circuit 330_1 can receive the radio frequency signal RF _IN corresponding to HB, and the second receiving circuit 330_2 can receive the radio frequency signal RF _IN corresponding to LB. As described above, the modem 350 can determine the target frequency based on the frequency band group (or HB) of the radio frequency signal RF _IN received by the first receiving circuit 330_1 assigned priority, and can generate frequency control based on the determined target frequency Signal F_CS. The Shared_PLL 370 can receive the frequency control signal F_CS from the modem 350 and can generate the frequency signal F_S with the target frequency based on the frequency control signal F_CS. The Shared_PLL 370 can provide the frequency signal F_S to the ADCs 334_1 and 334_2 of the first receiving circuit 330_1 and the second receiving circuit 330_2 respectively.

The ADC 334_1 of the first receiving circuit 330_1 can use the frequency signal F_S to convert the analog radio frequency signal RF _IN including only the signal component of the first channel ω1 into a digital signal. The digital conversion circuit 335_1 of the first receiving circuit 330_1 can use the first digital reference signal D_RS1 received from the modem 350 to perform down-conversion on the digital signal. The digital conversion circuit 335_1 can extract the signal component of the first channel ω1 from the radio frequency signal RF _IN and generate the first digital baseband signal BB _OUT1 (ω1) and provide the first digital baseband signal BB _OUT1 (ω1) to the modem 350 .

The ADC 334_2 of the second receiving circuit 330_2 can use the frequency signal F_S to convert the analog radio frequency signal RF _IN including only the signal component of the second channel ω2 into a digital signal. The digital conversion circuit 335_2 of the second receiving circuit 330_2 can use the second digital reference signal D_RS2 received from the modem 350 to perform down-conversion on the digital signal. The digital conversion circuit 335_2 can extract the signal component of the second channel ω2 from the radio frequency signal RF _IN and generate the second digital baseband signal BB _OUT2 (ω2) and provide the second digital baseband signal BB _OUT2 (ω2) to the modem 350 .

Referring to FIG. 11B , the first receiving circuit 330_1 and the second receiving circuit 330_2 may include ADC_TIL 334_1 ′ and 334_2 ′. ADC_TIL 334_1' and 334_2' can receive the first BGI BGI1 and the second BGI BGI2 corresponding to the radio frequency signal RF _IN received by the first receiving circuit 330_1 and the second receiving circuit 330_2 from the modem 350, and can be based on the first BGI BGI1 and the second BGI BGI2 to adjust the sampling rate. For example, the modem 350 may provide the ADC_TIL 334_1' with the first BGI BGI1 indicating that the first receiving circuit 330_1 has received the radio frequency signal RF _IN corresponding to HB, and may provide the ADC_TIL 334_2' indicating that the second receiving circuit 330_2 has received The second BGI BGI2 of the radio frequency signal RF _IN corresponding to LB. The details of ADC-TIL 334_1 ′ and ADC-TIL 334_2 ′ have been described with reference to FIG. 8A and so on, and will not be repeated here.

Referring to FIG. 11C , a modem according to an exemplary embodiment of the inventive concept may sequentially adjust a sampling rate during an ADC operation of each of a plurality of receiving circuits. First, the modem can determine the target frequency of the frequency signal by considering the receiving circuit receiving the radio frequency signal corresponding to the highest frequency band group among the plurality of receiving circuits, and can control the generation of the frequency signal having the target frequency (S100) . Next, the modem may control time interleaving of ADCs in the receiving circuits by considering frequency band groups corresponding to radio frequency signals received by each receiving circuit ( S110 ). Therefore, the ADC included in each receiving circuit can perform an ADC operation on the analog RF signal based on an appropriate sampling rate ( S120 ).

12A and 12B are block diagrams of an implementation example of a wireless communication device 300 in which each receiving circuit includes a frequency divider, according to an exemplary embodiment.

Compared with the first receiving circuit 330_1 shown in FIG. 5 , the first receiving circuit 330_1 shown in FIG. 12A may further include a frequency divider 380'. Like the first receiving circuit 330_1, each of the second to nth receiving circuits (330_2 to 330_n shown in FIG. 5 ) may further include a frequency divider 380'. Each of the receiving circuits in the wireless communication device 300 including the first receiving circuit 330_1 shown in FIG. 12A can be separately The ground includes frequency divider 380'. In the following, the first receiving circuit 330_1 shown in FIG. 12A is described as a reference, and it can be clearly understood that the exemplary embodiment of the first receiving circuit 330_1 is also applicable to other receiving circuits sharing the Shard_PLL 370 .

The modem 350 can determine the frequency division ratio of the frequency divider 380' based on the frequency band group corresponding to the radio frequency signal RFIN received by the first receiving circuit 330_1 and can provide the frequency division ratio control signal DIV_RT_CS to the frequency divider 380'. For example, when the first receiving circuit 330_1 receives the radio frequency signal RFIN corresponding to LB, the modem 350 can determine the frequency division ratio as the first frequency division ratio. When the first receiving circuit 330_1 receives the radio frequency signal RFIN corresponding to the MB, the modem can determine the frequency division ratio as the second frequency division ratio. When the first receiving circuit 330_1 receives the radio frequency signal RFIN corresponding to HB, the modem can determine the frequency division ratio as the third frequency division ratio. The magnitude of the frequency division ratio may have the following magnitude relationship: third frequency division ratio>second frequency division ratio>first frequency division ratio. The frequency divider 380' can receive the frequency signal F_S from the Shared_PLL 370 and divide the frequency signal F_S to generate a frequency-divided frequency signal DIV_F_S. The frequency divider 380' can provide the frequency-divided frequency signal DIV_F_S to the ADC 334, and the ADC 334 can perform an ADC operation according to a sampling rate satisfying the frequency-divided frequency signal DIV_F_S.

In this way, when each of the receiving circuits is provided with a separate frequency divider, the modem 350 can provide each frequency divider with a separate frequency division ratio control signal to adjust the frequency division ratio of the frequency signal F_S An adjustment is made whereby the sampling rate of the ADC of each receiving circuit is adjusted.

In addition, as mentioned above, the modem 350 can be based on the frequency band related information or channel related information corresponding to the radio frequency signal RFIN received by the first receiving circuit 330_1 to determine the frequency division ratio of the frequency divider 380' and provide the frequency division ratio control signal DIV_RT_CS to the frequency divider 380'.

Referring to FIG. 12B, the first receiving circuit 330_1 may include a time-interleaved ADC 334_1'. The time-interleaved ADC 334_1' can receive the BGI corresponding to the radio frequency signal RFIN received by the first receiving circuit 330_1 from the modem 350 and can adjust the sampling rate based on the BGI. The detailed description on this issue has been described with reference to FIG. 8A and so on, and will not be repeated for the sake of brevity.

In addition, the modem 350 according to an exemplary embodiment may sequentially adjust the sampling rate during the ADC operation of the first receiving circuit 330_1. First, the modem 350 can determine the frequency division ratio of the frequency divider 380' by considering the frequency band group corresponding to the radio frequency signal RFIN received by the first receiving circuit 330_1 and can control the frequency signal according to the determined frequency division ratio. Frequency division operation of F_S. Next, the time interleaving of the time interleaving ADC 334_1' can be controlled by considering the frequency band group corresponding to the radio frequency signal RFIN received by the first receiving circuit 330_1. Therefore, the time-interleaved ADC 334_1' included in the first receiving circuit 330_1 can perform an ADC operation on the analog radio frequency signal RFIN based on a proper sampling rate.

FIG. 13 is a block diagram showing an implementation example in which the transmission circuit of the wireless communication device 500 shares the Shared_PLL 570 according to an exemplary embodiment.

Referring to FIG. 13 , the wireless communication device 500 may include a first transmission circuit 530_1 to an nth transmission circuit 530_n, a modem 550 and a Shared_PLL 570 . The first transmission circuit 530_1 to the nth transmission circuit 530_n can share one Shared_PLL 570 , and the first transmission circuit 530_1 to the nth transmission circuit 530_n can use the Shared_PLL 570 Receive frequency signal F_S. The first transmission circuit 530_1 may include a power amplifier (PA) 531 , a filter 532 , a DAC 533 and a digital conversion circuit 534 .

The digital conversion circuit 534 of the first transmission circuit 530_1 can receive the digital baseband signal BBIN1 and the digital reference signal D_RS1' from the modem 550, and can up-convert the digital baseband signal BBIN1 based on the digital reference signal D_RS1'. DAC 533 can convert digital RF signal into analog RF signal. The first transmitting circuit 530_1 can pass the analog RF signal through the filter 532 and the PA 531 and output the result as the RF output signal RFOUT. The above configuration of the first transmission circuit 530_1 may be applied to the second transmission circuit 530_2 to the nth transmission circuit 530_n. In other words, the modem 550 can provide the second digital reference signal D_RS2' to the nth digital reference signal D_RSn' and the second digital baseband signal BBIN2 to the nth digital baseband signal BBINn to the second transmission circuit 530_2 to the nth transmission circuit 530_2 respectively. Circuit 530_n.

In addition, as described above, the exemplary embodiment in which the wireless communication device 500 includes one frequency divider and thus the first transmission circuit 530_1 to the nth transmission circuit 530_n share one frequency divider is applicable, and in which the first transmission circuit 530_1 to Exemplary embodiments in which each of the nth transmit circuits 530_n include a separate frequency divider are also applicable.

FIG. 14 is a block diagram illustrating an implementation example in which the transceiver circuits of the wireless communication device 600 share the Shared_PLL 670 according to an exemplary embodiment.

Referring to FIG. 14 , the wireless communication device 600 may include a first transceiver circuit 630_1 to an nth transceiver circuit 630_n, a modem 650 and a Shared_PLL 670 . The first transceiver circuit 630_1 to the nth transceiver circuit 630_n can share a Shared_PLL 670, And the first transceiver circuit 630_1 to the nth transceiver circuit 630_n can receive the frequency signal F_S from the Shared_PLL 670 .

Each of the first transceiver circuit 630_1 to the nth transceiver circuit 630_n may include at least one transmission circuit and at least one reception circuit, and the transmission circuit included in each of the first transceiver circuit 630_1 to the nth transceiver circuit 630_n Shared_PLL 670 may be shared by the circuit and the receive circuit. In addition, as mentioned above, wherein the wireless communication device 600 includes a frequency divider, and therefore the exemplary embodiment in which the first transceiver circuit 630_1 to the nth transceiver circuit 630_n share one frequency divider is applicable, and wherein the first transceiver circuit 630_1 Exemplary embodiments in which each of the through nth transceiver circuits 630_n include a separate frequency divider are also applicable.

FIG. 15 is a block diagram illustrating an electronic device 1000 supporting a communication function including a beamforming function according to an exemplary embodiment.

Referring to FIG. 15 , the electronic device 1000 may include a memory 1010 , a processor unit 1020 , an input/output controller 1040 , a display 1050 , an input device 1060 and a communication processor 1090 . Here, a plurality of memories 1010 may be included. The components are as follows.

The memory 1010 may include a program storage device 1011 and a data storage device 1012. The program storage device 1011 stores programs for controlling the operation of the electronic device 1000, and the data storage device 1012 stores data generated during program execution. The data storage device 1012 may store data for the operation of the application program 1013 and the frequency conversion program & data type conversion program 1014 . The program storage device 1011 may include an application program 1013 and a frequency conversion program & data type conversion program 1014 . Here, the programs included in the program storage device 1011 may be program codes or instruction sets (sets of instructions) and can be expressed as instruction sets.

The application program 1013 may include an application program running in the electronic device 1000 . In other words, the application program 1013 may include application instructions executed by the processor 1022 . According to the concept of the present invention, the frequency conversion program & data type conversion program 1014 can control the up-conversion operation/down-conversion operation of the radio frequency signal RF _IN and control the change of the sampling rate in the ADC operation. In other words, the frequency conversion program & data type conversion program 1014 may include a receiving circuit for making the modem (or baseband processor) of the communication processing unit 1090 generate a digital reference signal and provide the generated digital reference signal to the communication processor 1090 based instructions. The frequency conversion program & data type conversion program 1014 may include instructions that serve as the basis for causing the modem of the communication processor 1090 to provide information for controlling the sampling rate when the ADC of the receiving circuit performs ADC operations. When the modem executes the frequency conversion program & data type conversion program 1014, the operations according to the above-mentioned embodiments can be performed.

The peripheral device interface 1023 can control the connection between the input/output peripheral devices of the base station and the processor 1022 and the memory interface 1021 . The processor 1022 can use at least one software program to control the base station to provide applicable services. At this time, the processor 1022 can execute at least one program stored in the memory 1010 to provide a service corresponding to the applicable program.

The input/output controller 1040 may provide an interface between the input/output devices (eg, the display 1050 and the input device 1060 ) and the peripheral device interface 1023 . The display 1050 can display status information, input characters, moving pictures, still pictures and so on. For example, display 1050 may display information about 1022 Information of the executed application program.

The input device 1060 can provide input data generated by a series of electronic devices 1000 to the processor unit 1020 via the input/output controller 1040 . At this time, the input device 1060 may include a keypad including at least one hardware button and a touch pad for sensing touch information. For example, the input device 1060 can provide touch information (eg, touch, touch movement, and touch release) sensed by the touch pad to the processor 1022 via the input/output controller 1040 .

The electronic device 1000 may include a communication processor 1090, and the communication processor 1090 performs communication functions for realizing voice communication and data communication. The communication processor 1090 may include a shared PLL circuit 1092 shared by the receiving circuit (or transmitting circuit, or transceiving circuit) explained with reference to FIG. 5 and the like. The shared PLL circuit 1092 can jointly provide frequency signals of a specific frequency to the receiving circuit (or transmitting circuit, or transceiving circuit).

Although the inventive concept has been specifically shown and described with reference to exemplary embodiments of the inventive concept, those skilled in the art should understand that, without departing from the spirit and scope of the inventive concept defined by the following patent claims , various changes in form and details can be made to it. Therefore, the true protection scope of the concept of the present invention should be determined by the technical idea of the scope of the following claims.

300‧‧‧Wireless communication system

330_1~330_n‧‧‧the first receiving circuit~the nth receiving circuit

331_1~331_m‧‧‧The first low-noise amplifier (LNA)~the mth low-noise amplifier (LNA)

332_1~332_m‧‧‧first filter~mth filter

333‧‧‧Multiplexer (MUX)

334‧‧‧Analog-to-digital converter (ADC)

335‧‧‧digital conversion circuit

350‧‧‧modem

370‧‧‧Shared phase-locked loop circuit (Shared_PLL)

BB _OUT1 ~BB _OUTn-1 , BB _OUTn ‧‧‧First digital baseband signal~nth digital baseband signal

D_RS1‧‧‧First digital reference signal

D_RSn‧‧‧nth digital reference signal

D_RSn-1‧‧‧n-1th digital reference signal

F_S‧‧‧frequency signal

PLL_CS‧‧‧PLL control signal

RF _IN ‧‧‧RF signal

MUX_CS‧‧‧multiplexer (MUX) control signal

Claims (23)

A radio frequency (RF) integrated circuit configured to support carrier aggregation, the radio frequency integrated circuit comprising: a plurality of first receive circuits configured to be connected to a first antenna; and a first shared phase-locked loop circuit, configured to provide a first frequency signal of a first frequency to the plurality of first receiving circuits, at least one of the plurality of first receiving circuits being selected based on the type of carrier aggregation to start from the first day receiving a radio frequency signal by line, wherein one of the plurality of first receiving circuits includes: an analog-to-digital converter (ADC), configured to use the first frequency signal to be transmitted by one of the plurality of first receiving circuits one converts a received radio frequency signal into a digital signal; and a digital conversion circuit configured to generate a digital baseband signal by down-converting the digital signal based on a digital reference signal according to the The channel corresponding to the radio frequency signal is changed. The radio frequency integrated circuit according to item 1 of the scope of patent application, wherein the first frequency is determined according to a frequency band group corresponding to the radio frequency signal received by one of the plurality of first receiving circuits . The radio frequency integrated circuit described in item 2 of the scope of patent application, wherein the frequency band group includes a plurality of frequency band groups corresponding to the radio frequency signal, and the first frequency is based on the plurality of frequency band groups The highest frequency band group in is determined. The radio frequency integrated circuit as described in item 1 of the scope of the patent application, wherein one of the plurality of first receiving circuits further includes a frequency divider, and the frequency divider is configured to receive the first frequency signal, The first frequency signal is frequency-divided and the frequency-divided first frequency signal is provided to the analog-to-digital converter. The radio frequency integrated circuit described in item 4 of the scope of the patent application, wherein the frequency division ratio of the frequency divider is determined according to the frequency band group corresponding to the radio frequency signal. The radio frequency integrated circuit as described in item 1 of the scope of the patent application, wherein the sampling rate of the radio frequency signal of the analog-to-digital converter is determined according to the frequency band group corresponding to the radio frequency signal. The radio frequency integrated circuit according to item 6 of the scope of patent application, wherein the analog-digital converter includes a plurality of analog-digital converter circuits, each of the plurality of analog-digital converter circuits is configured configured to receive the first frequency signal and to provide the radio frequency signal with a time difference to at least one of the plurality of analog-to-digital converter circuits based on the frequency band group corresponding to the radio frequency signal An analog-to-digital converter circuit to perform the sampling operation. The radio frequency integrated circuit as described in item 1 of the patent scope, wherein one of the plurality of first receiving circuits further includes: a first path configured to receive the radio frequency corresponding to a first frequency band group a signal; a second path configured to receive the radio frequency signal corresponding to a second frequency band group; and A multiplexer configured to selectively connect any one of the first path and the second path to the analog-to-digital converter. The radio frequency integrated circuit described in item 1 of the scope of the patent application, wherein the digital conversion circuit includes: a digital mixer configured to receive the digital reference signal and process the digital signal based on the digital reference signal down-conversion; a low-pass filter configured to filter the down-converted digital signal; and a frequency-down filter configured to down-sample the filtered digital signal and generate the digital base frequency signal. The radio frequency integrated circuit described in item 1 of the scope of the patent application further includes: a plurality of second receiving circuits; and a second shared phase-locked loop circuit configured to provide a second frequency signal of a second frequency to the A plurality of second receiving circuits. The radio frequency integrated circuit as described in item 10 of the scope of the patent application, wherein the first frequency band group corresponding to the radio frequency signals received by the plurality of first receiving circuits is related to the radio frequency signals received by the plurality of second receiving circuits The second frequency band groups corresponding to the received radio frequency signals are different from each other. The radio frequency integrated circuit described in item 1 of the scope of the patent application further includes: a plurality of second receiving circuits; and a frequency divider configured to receive the first frequency signal from the first shared phase-locked loop circuit , divide the frequency of the first frequency signal and divide the frequency-divided first frequency signal The frequency signal is provided to the plurality of second receiving circuits. The radio frequency integrated circuit described in item 1 of the scope of the patent application further includes: a plurality of transmission circuits; and a second shared phase-locked loop circuit configured to provide a second frequency signal of a second frequency to the plurality of A transmission circuit, wherein one of the plurality of transmission circuits includes: a digital conversion circuit configured to up-convert the received digital baseband signal and generate a digital output signal; and a digital-to-analog converter (DAC ), configured to convert the digital output signal into an analog signal using the second frequency signal. The radio frequency integrated circuit described in item 1 of the scope of the patent application further includes a plurality of transmission circuits, wherein the first shared phase-locked loop circuit is configured to provide the first frequency signal to the plurality of transmission circuits . A wireless communication device configured to support carrier aggregation, the wireless communication device comprising: a radio frequency (RF) integrated circuit including: a plurality of receiving circuits configured to connect to an antenna and receive radio frequency signals from the antenna; and a shared phase-locked loop circuit configured to provide a frequency signal of a specific frequency to the plurality of receiving circuits for analog-to-digital conversion; and a modem configured to provide a digital reference signal to the radio frequency integrated circuit for for down-converting the radio frequency signal, At least one of the plurality of receiving circuits is selected based on the carrier aggregation type to receive the radio frequency signal. The wireless communication device according to claim 15, wherein one of the plurality of receiving circuits includes: an analog-to-digital converter (ADC), configured to convert the received frequency signal based on the frequency signal converting the radio frequency signal into a digital signal; and a digital conversion circuit configured to down-convert the digital signal based on the digital reference signal and generate a digital baseband signal. The wireless communication device according to claim 16 of the claimed patent scope, wherein the modem is configured to receive the digital baseband signal from the digital conversion circuit and process the digital baseband signal. The wireless communication device according to claim 16, wherein the modem is configured to provide the analog-to-digital converter with frequency band group information about the frequency band group corresponding to the radio frequency signal, and the The analog-to-digital converter is configured to determine a sampling rate based on the frequency band group information, and convert the radio frequency signal into the digital signal according to the sampling rate. The wireless communication device as described in item 15 of the scope of the patent application, wherein: the radio frequency integrated circuit further includes a frequency divider, and the frequency divider is configured to receive the frequency signal from the shared phase-locked loop circuit, frequency-dividing the frequency signal and providing the frequency-divided frequency signal to the plurality of receiving circuits, and the modem is configured based on two or more frequency bands corresponding to the radio frequency signal The highest frequency band group in the group controls the division ratio of the frequency divider. The wireless communication device as described in claim 15 of the scope of the patent application, wherein: one of the plurality of receiving circuits includes a frequency divider configured to receive the frequency signal and to receive the frequency signal performing frequency division and generating a frequency-divided signal for performing the analog-to-digital conversion, and the modem is configured to control a frequency division ratio of the frequency divider based on a frequency band group corresponding to the radio frequency signal . The wireless communication device as described in item 15 of the scope of patent application, wherein the radio frequency integrated circuit further includes a plurality of transmission circuits for transmitting the radio frequency signal, and the shared phase-locked loop circuit is configured to transmit the radio frequency signal to the A plurality of transmission circuits provide the frequency signal for digital-to-analog conversion. The wireless communication device according to claim 21, wherein one of the plurality of transmission circuits includes: a digital conversion circuit configured to up-convert the digital baseband signal received by the modem and generating a digital output signal; and a digital-to-analog converter (DAC) configured to convert the digital output signal into an analog signal using the frequency signal. A non-transitory processor-readable storage medium comprising commands to be executed by a processor in a wireless communication device including a plurality of receiving circuits sharing a phase-locked loop circuit , the commands, when executed by the processor, the processor configured to provide a digital reference signal to the plurality of receiving circuits for use based on radio frequency (RF) signals received by the plurality of receiving circuits The corresponding channel down-converts the radio frequency signal and sends it to the multiple a receiving circuit providing a signal for adjusting a sampling rate when the plurality of receiving circuits perform analog-to-digital conversion based on a frequency band group corresponding to the radio frequency signal, wherein the plurality of receiving circuits are configured to be connected to an antenna, And wherein at least one of the plurality of receiving circuits is selected based on a type of carrier aggregation to receive the radio frequency signal from the antenna.

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