KR20190062138A - An radio frequency(RF) integrated circuit supporting carrier aggregation and a wireless communication apparatus including the same - Google Patents

Abstract

According to a technical aspect of the present disclosure, a radio frequency (RF) integrated circuit supporting carrier aggregation comprises: a plurality of first reception circuits; and a first shared phase locked loop circuit for providing a first frequency signal having a first frequency to the first reception circuits. Meanwhile, the first reception circuit includes an analog to digital converter (ADC) for converting a received RF signal into a digital signal using the first frequency signal, and a digital conversion circuit for performing frequency down conversion on the digital signal to generate a digital baseband signal.

Description

(RF) integrated circuit supporting carrier aggregation and a wireless communication apparatus including the same,

TECHNICAL FIELD The technical idea of the present disclosure relates to an RF integrated circuit supporting carrier aggregation and an RF integrated circuit for transmitting and receiving RF signals and a radio communication apparatus including the RF integrated circuit.

The wireless communication apparatus modulates data, and transmits the RF signal to a wireless communication network by placing it on a predetermined carrier wave. Further, the wireless communication apparatus can receive an RF signal from a wireless communication network, amplify it, and demodulate it. In order to transmit and receive more data, the radio communication apparatus can support Carrier Aggregation, that is, transmission and reception of an RF signal modulated with a multi-carrier. In general, a wireless communication device for supporting carrier aggregation may include an RF integrated circuit (or RF front-end module), wherein the RF integrated circuit includes a plurality of receiving circuits (or receivers) And a plurality of transmit circuits (or transmitters) for transmitting RF signals.

Each of the conventional receiving circuits individually has a hardware configuration of a local oscillator that generates a frequency signal necessary for frequency down conversion of the RF signal. Because of this, it has been difficult to reduce the design area of the receiving circuit, and since the wireless communication device requires a large number of local oscillators, the power consumed by the local oscillators is significant, There is a problem that it is difficult to use it efficiently.

SUMMARY OF THE INVENTION A technical problem of the present disclosure is to provide an RF integrated circuit capable of reducing the design area of an RF integrated circuit supporting carrier aggregation and efficiently consuming electric power in a communication operation and a wireless communication device including the same .

According to an aspect of the present invention, there is provided an RF (Radio Frequency) integrated circuit supporting Carrier Aggregation (CA) according to one aspect of the present disclosure, including: a plurality of first receiving circuits and a first And a first shared phase locked loop circuit that provides a first frequency signal having a frequency to the first receiving circuits, wherein the first receiving circuit receives the received RF signal as a digital signal An ADC (Analog to Digital Converter) for converting the digital signal into a digital baseband signal and a digital conversion circuit for performing a frequency down conversion on the digital signal to generate a digital baseband signal.

A wireless communication device supporting carrier wave integration according to another aspect of the present disclosure, comprising: a plurality of receiving circuits for receiving an RF signal and a frequency signal having a predetermined frequency used for analog-to- And a modem for providing the RF integrated circuit with a digital reference signal used for frequency down conversion of the RF signal.

There is provided a non-transitory processor readable storage medium comprising instructions in accordance with yet another aspect of the disclosure, the instructions being executable by a processor in a wireless communication device having a plurality of receiving circuits sharing one phase locked loop circuit The processor is configured to provide a digital reference signal required for frequency down conversion based on a frequency channel corresponding to an RF signal received by the receiving circuits to the receiving circuits and to correspond to the RF signal received by the receiving circuits And a signal for adjusting the sampling rate in the analog-to-digital converting operation of the receiving circuits is provided to the receiving circuits based on the band group of the receiving groups.

The receiving circuits according to an embodiment of the present disclosure include a digital converter circuit for receiving a digital reference signal from a modem and performing a frequency downconversion, thereby generating a local oscillator for generating a frequency signal that varies according to a band group corresponding to the RF signal. And the receiving circuits can share one phase locked loop circuit can be applied, so that the size of the RF integrated circuit having the receiving circuits can be minimized. In addition, the power consumption of the RF integrated circuit including the receiving circuits can be reduced.

1 illustrates a wireless communication device 100 that performs wireless communication operations and a wireless communication system including the same.
FIGS. 2A to 2D, FIGS. 3A and 3B are diagrams for explaining a description of CA.
4 is a block diagram of the wireless communication apparatus of FIG. 1 according to one embodiment of the present disclosure;
5 is a block diagram for explaining a connection relationship among a plurality of receiving circuits of a wireless communication apparatus.
6A to 6C are views for explaining a connection structure between receiving circuits and a shared phase locked loop circuit according to an embodiment of the present disclosure.
FIG. 7 is a specific block diagram for explaining the first receiving circuit of FIG. 5 according to an embodiment of the present disclosure; FIG.
8A and 8B are diagrams illustrating an embodiment of a time interleaving controllable time interleaving ADC 400 according to an embodiment of the present disclosure.
9A and 9B are diagrams for explaining the concrete operation of the time interleaving ADC.
10 is a block diagram illustrating an implementation of a wireless communication device including a divider in accordance with one embodiment of the present disclosure;
Figs. 11A and 11B are diagrams for explaining the operation of the receiving circuits and the modem when performing the inter-CA operation, and Fig. 11C is a flowchart showing an embodiment for adjusting the sampling rate in a step- to be.
12A and 12B are block diagrams illustrating an implementation of a wireless communication device in which each of the receiving circuits includes a divider, in accordance with one embodiment of the present disclosure.
13 is a block diagram illustrating an implementation in which the transmit circuits of a wireless communication device share a phase locked loop circuit in accordance with one embodiment of the present disclosure;
14 is a block diagram illustrating an implementation in which the transmit and receive circuits of a wireless communication device share a phase locked loop circuit in accordance with one embodiment of the present disclosure;
15 is a block diagram illustrating an electronic device supporting a communication function including a beamforming function according to an embodiment of the present disclosure;

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 illustrates a wireless communication device 100 that performs wireless communication operations and a wireless communication system including the same.

1, the wireless communication system 10 may be any of a long term evolution (LTE) system, a code division multiple access (CDMA) system, a global system for mobile communication (GSM), and a wireless local area network It can be one. The CDMA system may also be implemented in various CDMA versions, such as wideband CDMA (WCDMA), time division synchronous CDMA (TD-SCDMA), cdma2000,

The wireless communication system 10 may include at least two base stations 110 and 112 and a system controller 120. However, this is not limiting to the exemplary embodiment, and the wireless communication system 10 may include multiple base stations and multiple network entities. The wireless communication apparatus 100 may be referred to as a user equipment (UE), a mobile station (MS), a mobile terminal (MT), a user terminal (UT), a subscriber station (SS) The base stations 110 and 112 may refer to fixed stations that communicate with the wireless communication device 100 and / or other base stations and may communicate with the wireless communication device 100 and / And / or RF (Radio Frequency) signals including control information. The base stations 110 and 120 may be referred to as a Node B, an evolved Node B (eNB), a Base Transceiver System (BTS), and an Access Point (AP).

The wireless communication device 100 is capable of communicating with the wireless communication system 10 and receiving signals from the broadcast station 114. Further, the wireless communication device 100 may receive a signal from a satellite 130 of a Global Navigation Satellite System (GNSS). The wireless communication device 100 may support radio technology for wireless communication (e.g., LTE, cdma2000, WCDMA, TD-SCDMA, GSM, 802.11, etc.).

The radio communication apparatus 100 may support carrier aggregation for performing transmission and reception operations using a plurality of carriers. The wireless communication device 100 may perform wireless communication with the wireless communication system 10 in a low band, a mid band, and a high band. Each of the low band, the middle band, and the high band may be referred to as a band group, and each band group may include a plurality of frequency bands. The band group can be variably determined according to the communication standard or the communication infrastructure, and the band group can be determined more finely or roughly than the above-described low band, middle band, and high band. In addition, the bandwidth of the frequency band included in each band group may vary depending on the communication standard or communication infrastructure.

 For example, in LTE one frequency band can cover up to 20MHz. The carrier aggregation (hereinafter referred to as CA) may be classified into an intra-band CA and an inter-band CA. The intra-band CA refers to performing a radio communication operation using a plurality of carriers within the same frequency band, and the inter-band CA refers to performing a radio communication operation using a plurality of carriers within another frequency band.

The RF integrated circuit of the wireless communication device 100 according to one embodiment of the present disclosure includes a plurality of receiving circuits for receiving an RF signal and at least two of the receiving circuits are analog- One phase locked loop circuit may be shared to generate the frequency signals needed for the conversion operation. Each receiving circuit may also include a digital conversion circuit to perform a frequency down conversion of the RF signal, and the digital conversion circuit may receive the RF signal converted into the digital signal and perform frequency down conversion on the RF signal have. The digital conversion circuit may receive the digital reference signal required to perform the frequency down conversion from the modem of the wireless communication device 100.

In addition, the RF integrated circuit of the wireless communication device 100 may comprise a plurality of transmit circuits for transmitting RF signals, and at least two transmit circuits of the transmit circuits are required for the digital-to-analog conversion operation of the RF signal One phase locked loop circuit that generates a frequency signal can be shared. In addition, each of the transmit circuits may include a digital conversion circuit that performs frequency up conversion of the RF signal, and the digital conversion circuit receives the digital baseband signal from the modem and performs frequency up conversion on the digital baseband signal . The digital conversion circuit may receive a digital reference signal required to perform the frequency up conversion from the modem of the wireless communication device 100.

Further, the receiving and transmitting circuits of the RF integrated circuit of the wireless communication device 100 may be implemented to share one phase locked loop circuit, and specific embodiments sharing the phase locked loop circuit may be implemented as shown in Figures 4, 6a and the like.

FIGS. 2A to 2D, FIGS. 3A and 3B are diagrams for explaining a description of CA.

Fig. 2A is an exemplary diagram of a contiguous intraband CA; Fig. Referring to FIG. 2A, the radio communication apparatus 100 of FIG. 1 can perform transmission and reception of signals using four adjacent carriers in the same frequency band of a low-band.

2B is an exemplary diagram of a non-contiguous intraband CA. Referring to FIG. 2B, the radio communication apparatus 100 may perform transmission and reception of signals using four non-adjacent carriers within the same frequency band of a low-band. The frequency band may comprise a plurality of frequency channels, where each of the four carriers may correspond to a different frequency channel. The extent to which each carrier is spaced apart, for example, the carriers may be separated by 5 MHz, 10 MHz, or another amount, respectively.

Figure 2C is an illustration of an interband CA in the same band group. Referring to FIG. 2C, the radio communication apparatus 100 includes four frequency bands (frequency bands) corresponding to frequency channels in two frequency bands (Low-Band 1, Low-Band 2) included in the same band group To transmit and receive signals.

2D is an illustration of an interband CA in another group of bands. Referring to FIG. 2D, the radio communication apparatus 100 may perform transmission and reception of signals using four carriers corresponding to frequency channels in another band group. Specifically, the two carriers are carriers corresponding to frequency channels in one frequency band included in the low-band, and the remaining two carriers are one of the carriers included in the mid-band And carriers corresponding to frequency channels in the frequency band.

The CA shown in FIGS. 2A-2D is not limited to this example, and the wireless communication device 100 may support various combinations of CAs for a frequency band or band group.

Referring to FIG. 3A, a technique has emerged for a CA that combines and operates multiple frequency bands at one or more base stations to meet the need for increased bit rate. LTE (Long Term Evolution), which is one of the mobile network, can realize a data transmission speed of 100Mbps, so that large capacity video can be transmitted and received smoothly in a wireless environment. 3A shows an example in which the data transmission rate can be increased up to 5 times by combining five frequency bands on the LTE standard by a carrier integration technique. 3A is a carrier defined by LTE, and one frequency bandwidth is defined up to 20 MHz in the LTE standard, the radio communication apparatus 100 according to an embodiment can have a frequency bandwidth of up to 100 MHz The data rate can be improved by the bandwidth of the data transmission rate.

3A shows an example in which only carrier waves defined in LTE are combined, but the present invention is not limited thereto. As shown in FIG. 3B, carriers of different wireless communication networks can also be combined. Referring to FIG. 3B, not only LTE but also frequency bands on the 3G and Wi-fi standards can be combined together by combining the frequency bands by the carrier integration technique. In this way, LTE-A adopts carrier integration technology to enable faster data transmission.

4 is a block diagram of the wireless communication apparatus of FIG. 1 according to one embodiment of the present disclosure;

4, the radio communication apparatus 200 includes a first transmission / reception circuit (or a transceiver 230_1, a secondary antenna 210_2) connected to a primary antenna 210_1, 2 transmission / reception circuit 230_2 and a modem (or a baseband processor) 250. The first transmission / reception circuit 230_1 includes an antenna interface circuit 232_1, a reception circuit 234_1, and a transmission circuit 236_1 The second transmission / reception circuit 230_2 may include an antenna interface circuit 232_2, a reception circuit 234_2, and a transmission circuit 236_2. In FIG. 4, the transmission / reception circuits 230_1 and 230_2 One of the receiving circuits 234_1 and 234_2 and one transmitting circuit 236_1 and 236_2, but this is not limitative of the exemplary embodiment, and the transmitting and receiving circuits 230_1 and 230_2 Each further comprise a plurality of receiving circuits and a plurality of transmitting circuits .

The transmission and reception circuits 230_1 and 230_2 may be configured to transmit a plurality of frequency bands, a plurality of radio technologies, a CA, a reception diversity, a Multiple-Input Multiple-Out (MIMO) transmission between a plurality of transmission antennas and a plurality of reception antennas And so on.

The receiving circuits 234_1 and 234_2 may include a low noise amplifier (Low Noise Amplifier), an analog-to-digital converter (ADC), and a digital conversion circuit (DC_CKT). The configuration of the receiving circuits 234_1 and 234_2 may be applied to other receiving circuits provided in the wireless communication device 200. [ Hereinafter, the operation of the first transmission / reception circuit 230_1 will be described, and the embodiment of the first transmission / reception circuit 230_1 may be applied to the second transmission / reception circuit 230_2.

For data reception, the primary antenna 210_1 may receive an RF signal from a base station or the like. The antenna interface circuit 232_1 may route the RF signal to the selected receiving circuit 234_1. The antenna interface circuit 232_1 may include a duplexer, a filter circuit, and an input matching circuit.

The receiving circuit 234_1 according to an embodiment of the present disclosure can filter the received RF signal to pass only a signal component corresponding to a predetermined band group (or a predetermined frequency band), and output the filtered RF signal (Analog-to-digital conversion) can be performed. Also, the digital conversion circuit (DC_CKT) receives the digital reference signal from the modem 250, and can perform frequency down conversion on the RF signal converted into the digital signal based on the digital reference signal. Since the receiving circuit 234_1 includes the digital conversion circuit DC_CKT, the receiving circuit 234_1 is a hardware circuit of a local oscillator for generating a frequency signal having a variable frequency according to the frequency channel corresponding to the RF signal received by the receiving circuit 234_1 A configuration may be unnecessary. Therefore, the size of the receiving circuit 234_1 can be minimized, and as a result, the design efficiency of the RF integrated circuit including the receiving circuit 234_1 can be increased. The receiving circuit 234_1 may provide the digital baseband signal generated through the frequency down conversion to the modem 250 and the modem 250 may process the digital baseband signal to generate the data signal.

Further, in one embodiment, the plurality of receiving circuits in the first transmitting / receiving circuit 230_1 including the receiving circuit 234_1 may share a phase locked loop circuit. In one embodiment, the phase locked loop circuit may generate a frequency signal required for analog-to-digital conversion and provide the phase locked loop circuit to a plurality of shared receiving circuits. Since the receiving circuits sharing the phase locked loop circuit collectively receive the frequency signals having the same frequency, a dividing operation for the frequency signals may be required in order for each of the receiving circuits to acquire the frequency signal having the desired frequency have. In one embodiment, the modem 250 may control the dispense operation for the frequency signal of the phase locked loop circuit such that each of the receive circuits may acquire a frequency signal having a target frequency, An analog-to-digital conversion operation can be performed using a frequency signal having a frequency. Specific examples of this will be described in Figs. 8A to 8C, 10, 13, and the like.

In one embodiment, the phase locked loop circuits that are different from the phase locked loop circuits shared by the plurality of receiving circuits in the first transmitting and receiving circuit 230_1 can be shared by the plurality of receiving circuits in the second transmitting and receiving circuit 230_2. That is, the radio communication apparatus 200 may be implemented with a structure in which different phase-locked loop circuits are shared by the respective transmission / reception circuits 230_1 and 230_2. In another embodiment, the plurality of reception circuits in the first transmission / reception circuit 230_1 and the plurality of reception circuits in the second transmission / reception circuit 230_2 may share one phase locked loop circuit. That is, the radio communication apparatus 200 can be implemented with a structure in which the transmission / reception circuits 230_1 and 230_2 share one phase locked loop circuit. Furthermore, a plurality of receiving circuits in the transmitting / receiving circuits 230_1 and 230_2 may be grouped and each may be implemented to share a different phase locked loop circuit. However, the above embodiments are only illustrative, and the embodiments of the receiving circuits 234_1 and 234_2 sharing the phase locked loop circuit can be variously implemented.

The transmission circuits 236_1 and 236_2 may include a power amplifier, a digital-analog converter (DAC), and a digital conversion circuit (not shown). The configuration of the transmission circuits 236_1 and 236_2 may be applied to other transmission circuits in the wireless communication device 220. [

The digital conversion circuit of the transmission circuit 236_1 may receive the digital reference signal and the digital baseband signal from the modem 250 and perform the frequency up-conversion on the digital baseband signal based on the digital reference signal. Thereafter, the DAC of the transmission circuit 236_1 can convert the digital baseband signal of the RF band into a digital RF signal, and the power amplifier of the transmission circuit 236_1 can amplify the RF signal to have an appropriate output power level have. The transmitting circuit 236_1 can provide the amplified RF signal to the primary antenna 210_1 through the antenna interface circuit 232_1 and the primary antenna 210_1 can transmit the RF signal to the base station or the like.

An embodiment in which the receiving circuits 234_1 and 234_2 share a phase locked loop circuit may also be applied to the transmitting circuits 236_1 and 236_2 and may be applied to the phase locked loop circuit shared by the transmitting circuits 236_1 and 236_2, The phase locked loop circuits shared by the first and second transistors 234_1 and 234_2 may be the same or different. Hereinafter, a phase locked loop circuit shared by a plurality of receiving circuits or a plurality of transmitting circuits is referred to as a shared phase locked loop circuit.

The modem 250 generates a data signal by demodulating the baseband signal received from the transmission / reception circuits 230_1 and 230_2, or provides a baseband signal generated by modulating the data signal to the transmission / reception circuits 230_1 and 230_2 . Also, the modem 250 can generate a digital reference signal required for frequency down-conversion and frequency up-conversion of the transmission / reception circuits 230_1 and 230_2 and provide it to the transmission / reception circuits 230_1 and 230_2, So that each of the receiving circuits 234_1 and 234_2 or the transmitting circuits 236_1 and 236_2 can acquire a frequency signal having a desired target frequency. The modem 250 may include a memory 250a and instructions defined to perform the operations of the modem 250 described above may be stored in the memory 250a. The modem 250 may perform operations of the modem 250 in accordance with the embodiments of the present disclosure by executing instructions stored in the memory 250a.

5 is a block diagram for explaining a connection relationship among a plurality of receiving circuits of a wireless communication apparatus.

5, the wireless communication device 300 may include a plurality of receiving circuits 330_1 to 330_n, a modem 350, and a shared phase locked loop circuit 370. [ The first receiving circuit 330_1 may include a plurality of low noise amplifiers 331_1 to 331_m, a plurality of filters 332_1, a multiplexer 333, an ADC 334 and a digital converting circuit 335, 1 receiving circuit 330_1 may be applied to the second to the n-th receiving circuits 330_2 to 330_n. The RF signal RF _IN may be transmitted through carriers located in at least one of the band groups and at least one of the receiving circuits 330_1 to 330_n may be selected according to the CA type And can receive the RF signal RF _IN .

In one embodiment, the shared phase locked loop circuit 370 may include a voltage controlled oscillator and a frequency multiplier and may generate a frequency signal having a predetermined frequency. The frequency of the frequency signal generated by the shared phase locked loop circuit 370 may be controlled by the modem 350. The shared phase locked loop circuit 370 may be implemented as a local oscillator according to an embodiment, and a structure in which a plurality of receiving circuits 330_1 to 330_n share one local oscillator may be applied.

One low noise amplifier 331_1 and one filter 332_1 can constitute a path through which a signal component transmitted by a carrier corresponding to one band group out of the signal components of the RF signal is received. In order to support the inter-CA described in FIG. 2C, one low-noise amplifier 331_1 and one filter 332_1 are connected to a signal component transmitted by a carrier corresponding to one frequency band among the signal components of the RF signal, May be configured. That is to say, paths that can receive the RF signal RF _IN corresponding to each band group (or each frequency band) through the low-noise amplifiers 331_1 to 331_m and the filters 332_1 to 332_m And the multiplexer 333 receives the mux control signal MUX_CS from the modem 350 and selects one of the plurality of paths based on the mux control signal MUX_CS to perform the CA operation. That is, the first receiving circuit 330_1 receives the RF signal corresponding to one of the plurality of band groups through the configurations of the low-noise amplifiers 331_1 to 331_m, the filters 332_1 to 332_m and the multiplexer 333, (RF _IN ). The filters 332_1 to 332_m may be implemented to pass only components of an RF signal corresponding to a specific band group. However, the present invention is not limited thereto, and the filters 332_1 to 332_m may be designed to selectively filter RF signals to support carrier aggregation. For example, the filter can be designed to have various passbands.

The ADC 334 may receive a frequency signal F_S having a predetermined frequency from the shared phase locked loop circuit 370. [ The shared phase locked loop circuit 370 may provide the same frequency signal F_S to the plurality of receiving circuits 330_1 to 330_n. That is, the receiving circuits 330_1 to 330_n may be implemented so as to share one shared phase locked loop circuit 370. [ The ADC 334 may receive the RF signal that has passed the selected path from the multiplexer 333 and may perform analog-to-digital conversion based on the frequency signal F_S.

The digital conversion circuit 335 may perform frequency down conversion on the RF signal converted into the digital signal based on the digital reference signal D_RS1 received from the modem 350. [ That is, the digital conversion circuit 335 can perform an operation of converting the RF band signal into the baseband signal in a digital manner. The digital reference signal D_RS1 may vary depending on the frequency channel corresponding to the RF signal. For example, referring to FIG. 2A, when the RF signal corresponds to a frequency channel within a high-band and when the RF signal corresponds to a frequency channel within a low-band, The signal D_RS1 may be different.

The digital conversion circuit 335 may provide the digital baseband signal BB _OUT1 generated as a result of the frequency down conversion to the modem 350 and the modem 350 may process the digital baseband signal BB _OUT1 (Or demodulate) the data signal to generate a data signal. The configuration of the first receiving circuit 330_1 may be applied to the second to the n-th receiving circuits 330_2 to 330_n. That is, the modem 350 may provide the digital reference signals D_RS2 to D_RSn to the second to the n-th receiving circuits 330_2 to 330_n, respectively, and the second to the n-th receiving circuits 330_2 to 330_ Band signals BB _OUT2 to BB _OUTn .

On by receiving circuit (330_1 ~ 330_n) in accordance with one embodiment of the present disclosure is directed to a digital conversion circuit 335 for performing a frequency down-converted by receiving a digital reference signal from a modem (350), RF signal (RF _IN) A structure in which a local oscillator that generates a variable frequency signal according to a corresponding frequency channel is not required and reception circuits 330_1 to 330_n can share the shared phase locked loop circuit 270 can be applied, It is possible to minimize the size of the RF integrated circuit including the RF integrated circuits 330_1 to 330_n and reduce the power consumption of the RF integrated circuit.

6A to 6C are views for explaining a connection structure between receiving circuits and a shared phase locked loop circuit according to an embodiment of the present disclosure.

6A, the RF integrated circuit includes a plurality of first receiving circuits 330G1_1 to 330G1_l, a plurality of second receiving circuits 330G2_1 to 330G2_k, and shared phase locked loop circuits 370G1 and 370G2 . The first receiving circuits 330G1_1 to 330G1_l may be divided into a first receiving circuit group RCKT_G1 and the second receiving circuits 330G2_1 to 330G2_k may be divided into a second receiving circuit group RCKT_G2. The receiving circuit groups RCKT_G1 and RCKT_G2 may be defined as a unit for grouping the receiving circuits sharing one shared phase locked loop circuit 370G1 and 370G2.

In one embodiment, the first receiving circuit group RCKT_G1 may be coupled to a first shared phase locked loop circuit 370G1 to receive a first frequency signal F_S1 having a first frequency. The second receiving circuit group RCKT_G2 may be coupled to a second shared phase locked loop circuit 370G2 to receive a second frequency signal F_S2 having a second frequency. The first frequency of the first frequency signal F_S1 and the second frequency of the second frequency signal F_S2 may be the same or different. 6A shows an embodiment divided into two receiving circuit groups RCKT_G1 and RCKT_G2. However, this is not limitative of the present invention, and the receiving circuits are divided into more receiving circuit groups than in FIG. 6A And each receiving circuit group can be individually connected to a shared phase locked loop circuit, and so on.

Hereinafter, FIG. 6B illustrates an embodiment of a criterion in which the receiving circuits are grouped into a receiving circuit group. Referring to FIG. 6B, the first receiving circuits 330G1_1 to 330G1_l receive the first band group BG1 between the frequencies f1 'and f2' and the second band group BG1 between the frequencies f2 'and f3' The second receiving circuits 330G2_1 to 330G2_k have a configuration capable of receiving an RF signal corresponding to the band group BG2 and the third receiving groups BG3 and BG3 between the f3 ' and can receive an RF signal corresponding to the fourth band group BG4 between frequencies f4 'to f5'. For example, the first receiving circuits 330G1_1 to 330G1_l may include filters for receiving RF signals corresponding to the first and second band groups BG1 and BG2, and the second receiving circuits 330G2_1 To 330G2_k may include filters for receiving RF signals corresponding to the third and fourth band groups BG3 and BG4. That is, the band groups BG1 and BG2 corresponding to the RF signals receivable by the first receiving circuits 330G1_1 to 330G1_l and the band groups BG1 and BG2 corresponding to the RF signals receivable by the second receiving circuits 330G2_1 to 330G2_k, (BG3, BG4) may be different. At this time, the first receiving circuits (330G1_1 to 330G1_l) may be divided into a first receiving circuit group (RCKT_G1) and the second receiving circuits (330G2_1 to 330G2_k) may be divided into a second receiving circuit group (RCKT_G2). The first frequency signals F_S1 received by the first receiving circuits 330G1_1 to 330G1_l from the first shared phase and hold circuit 370G1 are selected such that the second receiving circuits 330G2_1 to 330G2_k are connected to the second shared phase and hold circuit 370G2 The second frequency signal F_S2 that is received from the first frequency signal F_S2.

The band groups BG1 to BG4 described in FIG. 6B are exemplary embodiments, but not limited thereto, there may be fewer or more band groups, and the receiving circuits may be grouped according to the band group of the receivable RF signals . Also, according to an embodiment, the RF integrated circuit may include a greater number of shared phase locked loop circuits than in Figure 6A.

6C, the RF integrated circuit includes first receiving circuits 330G1_1 to 330G1_l, second receiving circuits 330G2_1 to 330G2_k, a frequency divider 370G1 ', and a shared phase locked loop circuit 370G2' . In one embodiment, the second receiving circuit group RCKT_G2 may be coupled to a shared phase locked loop circuit 370G2 'to receive a frequency signal F_S2 having a predetermined frequency. The first receiving circuit group RCKT_G1 is connected to the frequency divider 370G1 'to receive the frequency-divided signal F_S1' of the frequency signal F_S2. The frequency division ratio of the frequency divider 370G1 'may be determined according to a band group (or a frequency band or a frequency channel in a band group) of the RF signals receivable by the first receiving circuits 330G1_1. The embodiment shown in FIG. 6C is merely exemplary, but not limited to, various embodiments are possible, such that more frequency dividers can be connected to more receiving circuit groups, respectively.

FIG. 7 is a specific block diagram for explaining the first receiving circuit of FIG. 5 according to an embodiment of the present disclosure; FIG.

7, the first receiving circuit 330_1 includes a plurality of low noise amplifiers 331_1 to 331_3, a plurality of filters 332_1 to 332_3, a multiplexer 333, an ADC 334, and a digital conversion circuit 335 ). The low noise amplifiers 331_1 to 331_3, the filters 332_1 to 332_3, the multiplexer 333 and the ADC 334 may be referred to as an analog circuit AN_CKT to which an analog RF signal RF _IN is inputted. Digital conversion circuit 335 may include digital mixers DMa and DMb, digital low pass filters FTa and FTb and digital decimation filters DEa and DEb.

The LB filter 332_1 can pass only the signal component corresponding to the low band in the RF signal and the MB filter 332_2 can pass only the signal component corresponding to the intermediate band in the RF signal and the HB filter 332_3 It is possible to pass only the signal component corresponding to the high band in the RF signal. This is an exemplary embodiment only, and each of the filters 332_1 to 332_3 may be implemented to pass only signal components corresponding to different frequency bands, and the first receiving circuit 330_1 may include more filters have. However, for convenience of description, it is assumed that each of the filters 332_1 to 332_3 is implemented to pass only signal components corresponding to different band groups. The modem 350 may provide a multiplexer 333 with a mux control signal MUX_CS to control the output of the RF signal through one of the filters 332_1 to 332_3 to the ADC 334. [ The ADC 334 may receive the frequency signal F_S from the shared phase locked loop circuit 370 and perform sampling on the analog RF signal based on the frequency signal F_S to generate a digital RF signal.

The digital mixers DMa and DMb receive the digital reference signals D_RS1a and D_RS1b from the modem 350 and divide the digital RF signals into I and Q channels using the digital reference signals D_RS1a and D_RS1b, The frequency down-converted digital signal can be generated. The digital signals are filtered through digital low-pass filters (FTa and FTb) in order to eliminate unnecessary signals generated during frequency down-conversion, and the filtered digital signals pass through decimation filters DEa and DEb, respectively, Digital baseband signals I_BB _OUT1, Q_BB _OUT2 may be generated that are downsampled and contain samples of the signal corresponding to the target frequency channel. The modem 350 may receive the I digital baseband signal I_BB _OUT1 and the Q digital baseband signal Q_BB _OUT2 from the digital conversion circuit 335. The modem 350 may control the degree of downsampling of the decimation filters DEa and DEb so that the processing speed of the processing of the digital baseband signals I_BB _{OUT1 and} Q_BB _OUT2 of the modem 350 is It can be optimized.

The modem 350 may change the digital reference signals D_RS1a and D_RS1b according to the frequency channel corresponding to the RF signal received by the first receiving circuit 330_1. For example, when the path composed of the first low-noise amplifier 331_1 and the LB filter 332_1 is activated by the multiplexer 333, the first receiving circuit 330_1 can receive the RF signal corresponding to the low band And the modem 350 can generate digital reference signals D_RS1a and D_RS1b having predetermined values so that the digital conversion circuit 335 can frequency downconvert the RF signal from the frequency channel in the low band to the baseband . Further, when the path composed of the second low-noise amplifier 331_1 and the MB (filter 332_2) is activated by the multiplexer 333, the second receiving circuit 330_1 can receive the RF signal corresponding to the intermediate band , The modem 350 can generate the digital reference signals D_RS1a and D_RS1b having predetermined values so that the digital conversion circuit 335 can frequency downconvert the RF signal from the frequency channel to the baseband in the middle band.

The configuration of the first receiving circuit 330_1 shown in FIG. 7 may be applied to the other receiving circuits 330_2 through 330_n shown in FIG.

8A and 8B are views for explaining an embodiment of a time interleaving controllable time interleaving ADC according to an embodiment of the present disclosure.

In accordance with one embodiment of the present disclosure, the ADC 334 of FIG. 7 may be implemented as a time-interleaved ADC 400 of FIG. 8A. The time interleaving ADC 400 may include a splitter 401, a plurality of ADC circuits 402 to 405, a combiner 406 and a time interleaving control circuit 407. The time interleaving control circuit 407 can receive the band group related information (BGI) corresponding to the RF signal received by the first receiving circuit 330_1 from the modem 350 (FIG. 7) The sampling rate of the time interleaving ADC 400 can be controlled by providing the time interleaving control signals TL_CS and TL_CS 'to the splitter 401 and the combiner 406 based on the time interleaving control signals TL_CS and TL_CS'.

The splitter 401 may provide an analog signal (or an RF signal) AN_S to the ADC circuits 402 to 405 with a certain time difference based on the time interleaving control signal TL_CS. As a result, the ADC circuits 402_405 can receive the frequency signals from the analog signal AN_S and the shared phase-locked loop circuit 370 (FIG. 7), each having a constant phase difference, An analog signal AN_S can be digitally converted and the result of the conversion can be provided to the combiner 406. [ The combiner 406 may combine the results of the digital conversion from the ADC circuits 402 to 405 based on the time interleaving control signal TL_CS 'to generate a digital signal DG_S.

Because the first receiving circuit 330_1 (FIG. 7) shares the phase locked loop circuit 370 (FIG. 7) with other receiving circuits, the first receiving circuit 330_1 It may be difficult to obtain a frequency signal having a suitable frequency every time. Accordingly, the first receiving circuit 330_1 (FIG. 7) is implemented to include the time interleaving ADC 400 of FIG. 8A, thereby selectively controlling the plurality of ADC circuits 402-405 to provide a full time interleaving ADC 400 ) Can be appropriately changed. For example, when the time interleaving ADC 400 receives a frequency signal F_S having a frequency lower than a desired frequency, the time interleaving control circuit 407 selectively utilizes a large number of ADC circuits to obtain an appropriate sampling rate And when the frequency signal F_S having a frequency higher than the desired frequency is received, the time interleaving control circuit 407 can selectively control a small number of ADC circuits to have a proper sampling rate .

The time interleaving control circuit 407 receives frequency band related information or frequency channel related information corresponding to the RF signal received by the first receiving circuit 330_1 from the modem 350 And may control the sampling rate of the time interleaving ADC 400 based on frequency band related information or frequency channel related information. In the case of controlling the time interleaving ADC 400 based on the frequency band related information or the frequency channel related information, it is possible to adjust the sampling rate more finely than the case of controlling the time interleaving ADC 400 based on the band group related information have.

8A shows an embodiment in which the time interleaving ADC 400 has a separate time interleaving control circuit 407, but this is an exemplary embodiment, and not limited thereto, that the modem 350 (FIG. 7) Lt; RTI ID = 0.0 > 400 < / RTI > 8A, the time interleaving ADC 400 is shown to include four ADC circuits 402 to 405, but this is not limitative of the exemplary embodiment, and it should be understood that fewer, or more, The number of ADC circuits may be included.

Referring to FIG. 8B, the time interleaving ADC 400 may further include an ADC driving voltage providing circuit 408 in comparison with FIG. 8A. The time interleaving control circuit 407 may provide the ADC drive voltage providing circuit 408 with a supply control signal V_CS that includes information regarding at least one ADC circuit used in ADC operation. The ADC drive voltage providing circuit 408 provides a drive voltage V _DD to at least one of the plurality of ADC circuits 402 to 405 used for ADC operation based on the supply control signal V_CS, The driving voltage (V _DD ) may not be provided to the ADC circuit not used for the ADC operation. That is, the ADC driving voltage providing circuit (V _DD ) provides the driving voltage (V _DD ) only to the ADC circuit used for the ADC operation, thereby reducing unnecessary power consumption.

9A and 9B are diagrams for explaining the concrete operation of the time interleaving ADC.

Referring to FIG. 9A, the time interleaving control circuit 407 can determine the sampling rate of the time interleaving ADC 400 based on the first band group related information BGI1 received from the modem 350 (FIG. 7) The first time interleaving control signals TL_CS1 and TL_CS1 'to the splitter 401 and the combiner 406, respectively. Splitter 401 may provide the first to the fourth place the ADC circuit (402-405) predetermined time difference (T _INV) each to an analog signal (AN_S1) based on a first time-interleaved control signals (TL_CS1) . The first to fourth ADC circuits 402 to 405 can perform a sampling operation every predetermined time period Ts based on the frequency signal F_S received from the shared phase locked loop circuit 370 (FIG. 7). A sampling result generated by sampling each of 't1' to 't8' through the first to fourth ADC circuits 402 to 405 may be provided to the combiner 406, It is possible to output the digital signal DG_S1 by combining the sampling results based on the one-time interleaving control signal TL_CS1 '.

Referring to FIG. 9B, the time interleaving control circuit 407 can determine the sampling rate of the time interleaving ADC 400 based on the second band group related information BGI2 received from the modem 350 (FIG. 7) The second time interleaving control signals TL_CS2 and TL_CS2 'to the splitter 401 and the combiner 406, respectively. Splitter 401 can leave the respective predetermined time difference (T _INV ') to the first and the 3 ADC circuit (402, 404) into two based on the time-interleaved control signals (TL_CS2) providing an analog signal (AN_S2) have. The first and third ADC circuits 402 and 404 may perform a sampling operation every predetermined time period Ts based on the frequency signal F_S received from the shared phase locked loop circuit 370 (FIG. 7). Sampling results generated by sampling the first and third ADC circuits 402 and 404 at 't1', t3 ',' t5 'and' t8 'respectively can be provided to the combiner 406, The binarizer 406 may combine the sampling results based on the second time interleaving control signal TL_CS2 'to output the digital signal DG_S2. 8B, the ADC drive voltage supply circuit 408 (FIG. 8B) can be controlled such that the drive voltage is not provided to the second and fourth ADC circuits 403 and 405. In this case, as shown in FIG.

The sampling rate can be appropriately adjusted without directly changing the frequency of the frequency signal F_S by controlling the time interleaving ADC 400 in the same manner as in Figs. 9A and 9B.

10A and 10B are block diagrams illustrating an embodiment of a wireless communication apparatus having a shared phase locked loop circuit for generating a frequency signal having a variable frequency according to an embodiment of the present disclosure.

The wireless communication device 300 of Figure 10A may receive the frequency control signal F_CS from the modem 350 as compared to the wireless communication device 300 of Figure 5. Hereinafter, the parts overlapping with those of FIG. 5 will be omitted, and a description will be given centering on the new configuration.

Referring to FIG. 10A, the modem 350 may generate a frequency control signal F_CS based on information on a band group of an RF signal RF _IN received by the receiving circuits 330_1 to 330_n. For example, the first receiving circuit 330_1 receives the RF signal corresponding to the low band, the second receiving circuit 330_2 receives the RF signal corresponding to the middle band, and the third receiving circuit 330_3 When receiving the RF signal corresponding to the high band, the modem 350 can generate the frequency control signal F_CS by determining the target frequency based on the band group of the high band corresponding to the highest band group. In another example, when the first receiving circuit 330_1 receives the RF signal corresponding to the low band and the second receiving circuit 330_2 receives the RF signal corresponding to the middle band, It is possible to generate the frequency control signal F_CS by determining the target frequency based on the band group of the middle band corresponding to the group.

The shared phase locked loop circuit 370 receives the frequency control signal F_CS from the modem 350 and supplies the frequency signal F_S having the target frequency based on the frequency control signal F_CS to the plurality of receiving circuits 330_1 To 330_n. In other words, the shared phase locked loop circuit 380 is configured such that the band group corresponding to the received RF signal among the receiving circuits 330_1 to 330_n has a relatively high frequency To the receiving circuits 330_1 to 330_n.

In another embodiment, the modem 350 generates a frequency control signal F_CS based on information about the frequency band or frequency channel of the RF signal RF _IN received by the receiving circuits 330_1 to 330_n, The frequency of the signal F_CS can be more finely adjusted.

Referring to FIG. 10B, the receiving circuits 330_1 to 330_n may each include an ADC implemented by the time interleaving ADC described in FIG. 8A and the like. Hereinafter, when the first receiving circuit 330_1 is described, the first receiving circuit 330_1 may include a time interleaving ADC 334 '. 10A, since the frequency of the frequency signal F_CS is determined by preferentially considering the reception circuit having the highest band group corresponding to the received RF signal, the frequency of the frequency signal received by the first receiving circuit 330_1 The signal F_S may not have a suitable frequency to perform the ADC operation. At this time, the modem 350 may provide the time-interleaving ADC 334 'with information on the band group of the RF signal received by the first receiving circuit 330_1, and the time interleaving ADC 334' You can adjust the sampling rate based on the information. In another embodiment, the modem 350 may provide frequency-band related information or frequency channel related information of the RF signal received by the first receiving circuit 330_1 to the time interleaving ADC 334 ' 334 'may adjust the sampling rate based on frequency band related information or frequency channel related information. The concrete contents have been described above with reference to FIG. 8A and the like, and a detailed description thereof will be omitted.

Figs. 11A and 11B are diagrams for explaining the operation of the receiving circuits and the modem when performing the inter-CA operation, and Fig. 11C is a flowchart showing an embodiment for adjusting the sampling rate in a step- to be.

Referring to FIG. 11A, the wireless communication apparatus 300 may include a first receiving circuit 330_1, a second receiving circuit 330_2, and a shared phase locked loop circuit 370. FIG. The first receiving circuit 330_1 may include a plurality of low noise amplifiers 331_11 to 331_31, a plurality of filters 332_11 to 332_31, a multiplexer 333_1, an ADC 334_1 and a digital converting circuit 335_1 . The second receiving circuit 330_2 may include a plurality of low noise amplifiers 331_12 to 331_32, a plurality of filters 332_12 to 332_32, a multiplexer 333_2, an ADC 334_2 and a digital converting circuit 335_2 . Hereinafter, the receiving circuits 330_1 and 330_2 receive a signal component corresponding to the first frequency channel? 1 and a signal component corresponding to the second frequency channel? 2 based on the mux control signals MUX_CS1 and MUX_CS2 received from the modem 350, (RF _IN ) including a signal component corresponding to the RF signal (RF _IN ). A signal component corresponding to the first frequency channel (? 1) refers to a signal component transmitted through a carrier located on the first frequency channel (? 1), and a signal component corresponding to the second frequency channel may be referred to as a signal component transmitted through a carrier wave at a frequency ([omega] 2). The following description assumes that the first frequency channel? 1 is included in the high band HB and the second frequency channel? 1 is included in the low band LB.

The first receiving circuit 330_1 receives the RF signal RF _IN corresponding to the high band HB and the second receiving circuit 330_2 receives the RF signal RF _IN corresponding to the low band LB can do. The modem 350 receives the band group (high band HB) of the RF signal RF _IN received by the first receiving circuit 330_1 with priority given to the first receiving circuit 330_1 as described above, The target frequency of the frequency signal F_S can be determined to generate the frequency control signal F_CS according to the determined target frequency. The shared phase locked loop circuit 370 may receive the frequency control signal F_CS from the modem 350 and generate a frequency signal F_S having the target frequency based on the frequency control signal F_CS. The shared phase locked loop circuit 370 may provide the frequency signal F_S to the ADCs 334_1 and 334_2 of the receiving circuits 330_1 and 330_2, respectively.

The ADC 334_1 of the first receiving circuit 330_1 can convert an analog RF signal RF _IN containing only the signal component of the first frequency channel? 1 into a digital signal using the frequency signal F_S. The digital conversion circuit 335_1 of the first receiving circuit 330_1 can perform frequency down conversion on the digital signal using the first digital reference signal D_RS1 received from the modem 350. [ The digital conversion circuit 335_1 may extract the signal component of the first frequency channel (? 1) from the RF signal (RF _IN ) to generate and provide the first digital baseband signal BB _OUT1 to the modem 350.

The ADC 334_2 of the second receiving circuit 330_2 can convert the analog RF signal RF _IN including only the signal component of the second frequency channel? 2 into a digital signal using the frequency signal F_S. The digital conversion circuit 335_2 of the second reception circuit 330_2 can perform frequency down conversion on the digital signal using the second digital reference signal D_RS2 received from the modem 350. [ Digital conversion circuit 335_2 may extract the signal component of the second frequency channel (omega 2) from the RF signal RF _IN and generate and provide the second digital baseband signal BB _OUT2 to the modem 350. [

Referring to FIG. 11B, each of the receiving circuits 330_1 and 330_2 may include time interleaving ADCs 334_1 'and 334_2'. The time interleaving ADCs 334_1 'and 334_2' receive the band group related information BGI1 and BGI2 corresponding to the RF signal RF _IN received from the modem 350 by the receiving circuits 330_1 and 330_2, The sampling rate can be adjusted based on the group related information (BGI1, BGI2). For example, the modem 350 transmits the first band group related information BGI1 indicating that the first receiving circuit 330_1 receives the RF signal RF _IN corresponding to the high band HB to the time interleaving ADC And the second band group related information BGI2 indicating that the second receiving circuit 330_2 receives the RF signal RF _IN corresponding to the low band LB to the time interleaving ADC 334_2 ' ). The details of the time interleaving ADCs 334_1 'and 334_2' are described with reference to FIG. 8A and the like, and redundant descriptions will be omitted.

Referring to FIG. 11C, a modem in accordance with one embodiment of the present disclosure may step-adjust the sampling rate during ADC operation for each of the receive circuits. First, the modem can determine the target frequency of the frequency signal in consideration of the receiving circuit that receives the RF signal corresponding to the highest band group among the plurality of receiving circuits, and control the generation of the frequency signal having the target frequency ( S100). Then, the modem can separately control the time interleaving of the ADC in the receiving circuit in consideration of the band group corresponding to the RF signal received by each receiving circuit (S110). As a result, the ADC included in each of the receiving circuits can perform the ADC operation on the analog RF signal based on the optimal sampling rate (S120).

12A and 12B are block diagrams illustrating an implementation of a wireless communication device in which each of the receiving circuits includes a divider, in accordance with one embodiment of the present disclosure.

The first receiving circuit 330_1 of FIG. 12A may further include a frequency divider 380 as compared with the first receiving circuit 330_1 of FIG. The second to n-th receiving circuits 330_2 to 330_n (FIG. 5) may further include a frequency divider such as the first receiving circuit 330_1. The receiving circuits in the wireless communication device 300 including the first receiving circuit 330_1 of Fig. 12A may each include a divider separately. Hereinafter, the description will be made on the basis of the first receiving circuit 330_1 shown in Fig. 12A, and the embodiment of the first receiving circuit 330_1 will be described also with respect to other receiving circuits sharing the shared phase locked loop circuit 370 It is clear that it can be applied.

The modem 350 can determine the division ratio of the frequency divider 380 based on the band group corresponding to the RF signal received by the first receiving circuit 330_1 and outputs the frequency division ratio control signal DIV_RT_CS ). ≪ / RTI > For example, when the first receiving circuit 330_1 receives an RF signal corresponding to the low band (LB), the modem 350 determines the frequency division ratio as a first frequency division ratio, and the first receiving circuit 330_1 When the RF signal corresponding to the intermediate band (MB) is received, the frequency division ratio is determined as the second frequency division ratio. When the first reception circuit (330_1) receives the RF signal corresponding to the high frequency band (HB) Can be determined as the third division ratio. The size of the dispense ratio can have the following size relationship (third dispense ratio> second dispense ratio> first dispense ratio). The frequency divider 380 may receive the frequency signal F_S from the shared phase locked loop circuit 370 and divide the frequency signal F_S to produce a frequency divided signal DIV_F_S. The divider 380 may provide the divided frequency signal DIV_F_S to the ADC 334 and the ADC 334 may perform the ADC operation according to the sampling rate corresponding to the frequency divided signal DIV_F_S .

As such, when the receive circuits are each individually provided with a divider, the modem 350 provides a separate divider ratio control signal for each divider to adjust the division ratio for the frequency signal F_S, The ADC's sampling rate can be adjusted.

In addition, as described above, the modem 350 can determine the frequency division ratio of the frequency divider 380 based on frequency band related information or frequency channel related information corresponding to the RF signal received by the first receiving circuit 330_1 And may provide dividing ratio control signal DIV_RT_CS to divider 380. [

Referring to FIG. 12B, the first receiving circuit 330_1 may include a time interleaving ADC 334_1 '. The time interleaving ADC 334_1 'receives the band group related information (BGI) corresponding to the RF signal (RF _IN ) received by the first receiving circuit 330_1 from the modem 350 and outputs the band group related information (BGI) The sampling rate can be adjusted. A detailed description thereof has been described with reference to FIG. 8A and the like, and redundant description is omitted.

Further, the modem 350 according to one embodiment of the present disclosure can step-adjust the sampling rate during ADC operation for the first receiving circuit 330_1. First, the modem 350 can determine the frequency division ratio of the frequency divider 380 in consideration of the band group corresponding to the RF signal received by the first receiving circuit 330_1, and determines the frequency signal F_S according to the determined frequency division ratio. Can be controlled. Thereafter, the time interleaving of the time interleaving ADC 334_1 'can be controlled in consideration of the band group corresponding to the RF signal received by the first receiving circuit 330_1. As a result, the time interleaving ADC 334_1 'included in the first receiving circuit 330_1 can perform the ADC operation on the analog RF signal based on the optimal sampling rate.

13 is a block diagram illustrating an implementation in which the transmit circuits of a wireless communication device share a phase locked loop circuit in accordance with one embodiment of the present disclosure;

13, the wireless communication device 400 may include transmitting circuits 430_1 through 430_n, a modem 450, and a shared phase locked loop circuit 470. [ The transmitting circuits 430_1 to 430_n may share one shared phase locked loop circuit 470 and the transmitting circuits 430_1 to 430_n from the shared phase locked loop circuit 470 receive the frequency signal F_S can do. The first transmission circuit 430_1 may include a power amplifier 431, a filter 432, a DAC (Digital Analog Converter) 433, and a digital conversion circuit 434.

The digital conversion circuit 434 is a digital baseband signal (BB _IN1) and a digital reference signal (D_RS1 ') receiving the digital reference signal (D_RS1' based on) from the modem 450 of the first transmission circuit (430_1) To perform frequency up conversion on the digital baseband signal (BB _IN1 ). The DAC 433 can convert the converted digital RF signal into an analog RF signal. The first transmission circuit 430_1 can output the analog RF signal as the RF output signal RF _OUT through the filter 432 and the power amplifier 431. [ The configuration of the first transmission circuit 430_1 may be applied to the second to n-th receiving circuits 430_2 to 430_n. That is, the modem 450 may provide the digital reference signals D_RS2 'to D_RSn' and the digital baseband signals BB _IN2 to BB _INn to the second to n-th transmitting circuits 430_2 to 430_n, respectively.

Furthermore, as described above, the embodiment in which the wireless communication device 400 includes one frequency divider and the transmitting circuits 430_1 to 430_n share one frequency divider, the transmitting circuits 430_1 to 430_n, An embodiment in which each of them includes a frequency divider or the like can be applied.

14 is a block diagram illustrating an implementation in which the transmit and receive circuits of a wireless communication device share a phase locked loop circuit in accordance with one embodiment of the present disclosure;

14, the wireless communication apparatus 500 may include a plurality of transmission / reception circuits 530_1 to 530_n, a modem 550, and a shared phase locked loop circuit 570. [ The transmitting and receiving circuits 530_1 to 530_n may share one shared phase locked loop circuit 570 and the transmitting and receiving circuits 530_1 to 530_n from the shared phase locked loop circuit 570 receive the frequency signal F_S can do.

Each of the transmission / reception circuits 530_1 to 530_n may include at least one transmission circuit and at least one reception circuit, and the transmission circuit and reception circuit included in each of the transmission / reception circuits 530_1 to 530_n may be a shared phase- (570). Furthermore, as described above, the embodiments in which the radio communication apparatus 500 includes one frequency divider and the transmission / reception circuits 530_1 to 530_n share one frequency divider, the transmission / reception circuits 530_1 to 530_n, An embodiment in which each of them includes a frequency divider, an embodiment including a time interleaving ADC in the transmission / reception circuits 530_1 to 530_n, and the like can be applied.

15 is a block diagram illustrating an electronic device supporting a communication function including a beamforming function according to an embodiment of the present disclosure;

15, an electronic device 1000 includes a memory 1010, a processor unit 1020, an input / output control unit 1040, a display unit 1050, an input device 1060, and a communication processing unit 1090 . Here, a plurality of memories 1010 may exist. The components are as follows.

 The memory 1010 may include a program storage unit 1011 for storing a program for controlling the operation of the electronic device and a data storage unit 1012 for storing data generated during program execution. The data storage unit 1012 can store data necessary for the operations of the application program 1013, the frequency conversion program and data type conversion program 1014, and the like. The program storage unit 1011 may include an application program 1013, a frequency conversion program and data type conversion program 1014, Here, the program included in the program storage unit 1011 may be expressed as a set of instructions and an instruction set.

The application program 1013 includes an application program running on the electronic device. That is, the application program 1013 includes instructions of an application that is driven by the processor 1022. [ The frequency conversion program & data type conversion program 1014 can control the digital frequency up / down conversion operation of the RF signal according to the present disclosure and the change of the sampling rate in ADC operation. That is, the frequency conversion program 1014 includes instructions based on the modem (or baseband processor) of the communication processing unit 1090 for generating a digital reference signal and providing it to the receiving circuit of the communication processing unit 1090 . The data type conversion program 1014 may include instructions that are based on the modem of the communication processing unit 1090 to provide information that can control the sampling rate when the ADC of the receiving circuits performs the ADC operation. Specifically, by executing the frequency conversion program & data type conversion program 1014 by the modem, the operation conforming to the above-described embodiments can be performed.

The peripheral device interface 1023 may control the connection of the processor 1022 and the memory interface 1021 to the input / output peripheral of the base station. The processor 1022 controls the base station to provide the corresponding service using at least one software program. At this time, the processor 1022 may execute at least one program stored in the memory 1010 and provide a service corresponding to the program.

The input / output control unit 1040 may provide an interface between the input / output device such as the display unit 1050 and the input device 1060 and the peripheral device interface 1023. [ The display unit 1050 displays status information, characters to be input, a moving picture, and a still picture. For example, the display unit 1050 can display application program information driven by the processor 1022. [

The input device 1060 may provide the input data generated by the selection of the electronic device to the processor unit 1020 through the input / output control unit 1040. [ At this time, the input device 1060 may include a keypad including at least one hardware button and a touchpad for sensing touch information. For example, the input device 1060 may provide touch information such as a touch, a touch movement, and a touch release sensed through the touch pad to the processor 1022 through the input / output control unit 1040.

The electronic device 1000 includes a communication processing unit 1090 that performs a communication function for voice communication and data communication and the communication processing unit 1090 includes the receiving circuits (or transmitting circuits, The shared phase locked loop circuit 1092 includes a shared phase locked loop circuit 1092 that is shared by the receiving circuits (or transmitting circuits, or transmitting and receiving circuits) Can provide a frequency signal having

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (20)

1. An RF (Radio Frequency) integrated circuit supporting Carrier Aggregation (CA)
A plurality of first receiving circuits; And
And a first shared phase locked loop circuit for providing a first frequency signal having a first frequency to the first receiving circuits,
Wherein the first receiving circuit comprises:
An ADC (Analog to Digital Converter) for converting the received RF signal into a digital signal using the first frequency signal; And
And a digital conversion circuit for performing frequency down conversion on the digital signal to generate a digital baseband signal. The method according to claim 1,
Wherein the first frequency is selected from the group consisting of:
Wherein the first receiving circuits are determined according to a band group corresponding to the RF signal received by the first receiving circuits. The method according to claim 1,
Wherein the first frequency is selected from the group consisting of:
Wherein the first receiving circuits are determined according to a band group corresponding to the RF signal received by the first receiving circuits. The method according to claim 1,
Wherein the first receiving circuit comprises:
Further comprising a frequency divider for receiving the first frequency signal, dividing the first frequency signal, and providing the divided first frequency signal to the ADC. 5. The method of claim 4,
The frequency division ratio of the frequency divider is,
Wherein the first receiving circuit is determined according to a band group corresponding to the RF signal received by the first receiving circuit. The method according to claim 1,
Wherein the sampling rate for the RF signal of the ADC,
Wherein the frequency band is determined according to a band group corresponding to the RF signal. The method according to claim 6,
Wherein the ADC comprises a plurality of ADC circuits each receiving the first frequency signal,
Wherein the sampling operation is performed by providing the RF signal with a time difference to at least one of the ADC circuits based on a band group corresponding to the RF signal. The method according to claim 1,
The RF integrated circuit includes:
A plurality of second receiving circuits; And
And a second shared phase locked loop circuit for providing a second frequency signal having a second frequency to the second receiving circuits. The method according to claim 1,
The RF integrated circuit includes:
A plurality of second receiving circuits; And
Further comprising a frequency divider that receives the first frequency signal from the first shared phase locked loop circuit and divides the first frequency signal and provides the divided first frequency signal to the second receiving circuits Wherein the RF integrated circuit comprises: The method according to claim 1,
The RF integrated circuit includes:
A plurality of transmit circuits; And
And a second shared phase locked loop circuit for providing a second frequency signal having a second frequency to the transmitting circuits,
The transmission circuit comprising:
A digital conversion circuit for performing frequency up conversion on the received digital baseband signal to generate a digital output signal; And
And a DAC (Digital to Analog Converter) for converting the digital output signal into an analog signal using the second frequency signal. The method according to claim 1,
The RF integrated circuit further includes a plurality of transmission circuits,
Wherein the first shared phase locked loop circuit provides the first frequency signal to the transmitting circuits. 1. A wireless communication device supporting carrier aggregation,
An RF integrated circuit having a plurality of receiving circuits for receiving an RF signal and a shared phase locked loop circuit for providing a frequency signal having a predetermined frequency used for analog-to-digital converting operations to the receiving circuits; And
And a modem for providing the RF integrated circuit with a digital reference signal used for frequency down conversion of the RF signal. 13. The method of claim 12,
The receiving circuit includes:
An ADC for converting the received RF signal into a digital signal based on the frequency signal; And
And a digital conversion circuit for generating a digital baseband signal by performing frequency down conversion on the digital signal based on the digital reference signal. 14. The method of claim 13,
The modem includes:
And receives the digital baseband signal from the digital conversion circuit, and processes the digital baseband signal. 14. The method of claim 13,
Wherein the modem provides the ADC with information related to a band group corresponding to the RF signal received by the receiving circuit,
Wherein the ADC determines a sampling rate based on the information and converts the RF signal into the digital signal according to the sampling rate. 13. The method of claim 12,
The RF integrated circuit includes:
Further comprising a frequency divider that receives the frequency signal from the shared phase locked loop circuit, divides the frequency signal, and provides the divided frequency signal to the receiving circuits,
The modem includes:
Wherein the frequency division ratio of the frequency divider is controlled based on a highest frequency band among two or more frequency band groups corresponding to the RF signal received by the receiving circuits. 13. The method of claim 12,
The receiving circuit includes:
Further comprising a frequency divider for receiving the frequency signal and dividing the frequency signal to generate the frequency-divided frequency signal used for the analog-to-digital conversion operation,
The modem includes:
Wherein the dividing ratio of the frequency divider is controlled based on a band group corresponding to the RF signal received by the receiving circuit. 13. The method of claim 12,
Wherein the RF integrated circuit further comprises a plurality of transmission circuits for transmitting the RF signal,
Wherein the shared phase locked loop circuit provides the frequency signals used in the digital-to-analog converting operation to the transmitting circuits. 19. The method of claim 18,
The transmission circuit comprising:
A digital conversion circuit for performing a frequency up conversion on a digital baseband signal received from the modem to generate a digital output signal; And
And a DAC for converting the digital output signal into an analog signal using the frequency signal. 17. A non-transitory processor readable storage medium comprising instructions,
Wherein the instructions are executed by a processor in a wireless communication device having a plurality of receiving circuits sharing one phase locked loop circuit,
Wherein the receiving circuits provide the receiving circuits with a digital reference signal required for frequency down conversion based on a frequency channel corresponding to the RF signal received,
Wherein the receiving circuits provide a signal to the receiving circuits to adjust a sampling rate in an analog-to-digital converting operation of the receiving circuits based on a band group corresponding to the RF signal received by the receiving circuits. Readable storage medium.

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