CN109842480B

CN109842480B - Radio frequency integrated circuit supporting carrier aggregation and wireless communication device including the same

Info

Publication number: CN109842480B
Application number: CN201811423374.9A
Authority: CN
Inventors: 巴罗塞姆·成; 罗启伦; 李在训; 李宗祐; 吴承贤
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2017-11-27
Filing date: 2018-11-27
Publication date: 2023-11-10
Anticipated expiration: 2038-11-27
Also published as: TWI789462B; KR20190062138A; KR102503212B1; CN109842480A; TW201929469A

Abstract

A radio frequency integrated circuit supporting carrier aggregation and a wireless communication device including the same are provided. The radio frequency integrated circuit supports carrier aggregation and includes a plurality of first receiving circuits configured to receive radio frequency signals and a first shared phase-locked loop circuit that provides a first frequency signal at a first frequency to the plurality of first receiving circuits. At least one of the plurality of first receiving circuits includes an analog-to-digital converter and a digital conversion circuit. The analog-to-digital converter converts the received radio frequency signal into a digital signal by using the first frequency signal. The digital conversion circuit generates a digital baseband signal by performing down-conversion on the digital signal.

Description

Radio frequency integrated circuit supporting carrier aggregation and wireless communication device including the same

The present application claims priority to korean patent applications No. 10-2017-0159682 and No. 10-2018-0083140, which are filed on the south of the korean intellectual property office on the respective days of 2017, 11, 27 and 2018, 7, 17, the disclosure of each of which is incorporated herein by reference in its entirety.

Technical Field

Apparatuses, devices and articles consistent with the present disclosure relate to Radio Frequency (RF) integrated circuits supporting carrier aggregation, and more particularly, to RF integrated circuits transmitting and receiving RF signals.

Background

The wireless communication device may modulate data and transmit Radio Frequency (RF) signals to a wireless communication network by loading the RF signals onto a particular carrier. In addition, the wireless communication device may receive RF signals from the wireless communication network, amplify the received RF signals, and demodulate the amplified RF signals. To transmit and receive more data, a wireless communication device may support carrier aggregation, i.e., transception of RF signals modulated into multiple carriers.

Disclosure of Invention

An aspect provides a Radio Frequency (RF) integrated circuit capable of reducing a design area of the RF integrated circuit, supporting carrier aggregation, and consuming power efficiently in a communication operation, and a wireless communication device including the RF integrated circuit.

According to an aspect of an example embodiment, there is provided a Radio Frequency (RF) integrated circuit configured to support carrier aggregation, the RF integrated circuit comprising: a plurality of first receiving circuits; and a first shared phase-locked loop circuit configured to provide a first frequency signal of a first frequency to the plurality of first receiving circuits, wherein one of the plurality of first receiving circuits comprises: an analog-to-digital converter (ADC) configured to convert an RF signal received by the one of the plurality of first receiving circuits into a digital signal by using a first frequency signal; a digital conversion circuit configured to generate a digital baseband signal by performing down-conversion on the digital signal.

The first frequency is determined from a band group corresponding to the RF signal received by the one of the plurality of first receiving circuits.

The band group includes a plurality of band groups corresponding to the RF signal, and the first frequency is determined based on a highest band group among the plurality of band groups.

The one of the plurality of first receiving circuits further includes: and a frequency divider configured to receive the first frequency signal, divide the first frequency signal and provide the divided first frequency signal to the ADC.

The division ratio of the divider is determined from the band group corresponding to the RF signal.

The RF signal sampling rate of the ADC is determined from the set of frequency bands corresponding to the RF signal.

The ADC includes a plurality of ADC circuits, each configured to receive a first frequency signal and configured to perform a sampling operation by providing an RF signal to at least one ADC circuit among the plurality of ADC circuits with a time difference based on a band group corresponding to the RF signal.

The one of the plurality of first receiving circuits further includes: a first path configured to receive RF signals corresponding to a first band group; a second path configured to receive RF signals corresponding to a second band group; a multiplexer configured to selectively connect any one of the first path and the second path to the ADC.

The digital conversion circuit includes: a digital mixer configured to receive the digital reference signal and down-convert the digital signal based on the digital reference signal; a low pass filter configured to filter the down-converted digital signal; a decimation filter configured to downsample the filtered digital signal and generate a digital baseband signal.

The RF integrated circuit further includes: a plurality of second receiving circuits; a second shared phase-locked loop circuit configured to provide a second frequency signal at a second frequency to the plurality of second receiving circuits.

The first band group corresponding to the RF signals received by the plurality of first receiving circuits and the second band group corresponding to the RF signals received by the plurality of second receiving circuits are different from each other.

The RF integrated circuit further includes: a plurality of second receiving circuits; a frequency divider configured to receive the first frequency signal from the first shared phase-locked loop circuit, divide the first frequency signal, and provide the divided first frequency signal to the plurality of second receiving circuits.

The RF integrated circuit further includes: a plurality of transmitting circuits; a second shared phase-locked loop circuit configured to provide a second frequency signal at a second frequency to the plurality of transmit circuits, wherein one of the plurality of transmit circuits comprises: a digital conversion circuit (DAC) configured to up-convert the received digital baseband signal and generate a digital output signal; a digital-to-analog converter configured to convert the digital output signal into an analog signal by using the second frequency signal.

The RF integrated circuit further includes: a plurality of transmit circuits, wherein the first shared phase-locked loop circuit is configured to provide the first frequency signal to the plurality of transmit circuits.

According to another aspect of the example embodiments, there is provided a wireless communication apparatus configured to support carrier aggregation, the wireless communication apparatus comprising: a Radio Frequency (RF) integrated circuit, comprising: a plurality of receiving circuits configured to receive RF signals; and a shared phase-locked loop circuit configured to provide a frequency signal of a specific frequency for analog-to-digital conversion to the plurality of receiving circuits; and a modem configured to provide a digital reference signal for down-conversion of the RF signal to the RF integrated circuit.

One of the plurality of receiving circuits includes: an analog-to-digital converter (ADC) configured to convert the received RF signal into a digital signal based on the frequency signal; and a digital conversion circuit configured to down-convert the digital signal based on the digital reference signal and generate a digital baseband signal.

The modem is configured to receive the digital baseband signal from the digital conversion circuit and process the digital baseband signal.

The modem is configured to provide band group information regarding a band group corresponding to the RF signal to the ADC, and the ADC is configured to determine a sampling rate based on the band group information and to convert the RF signal to a digital signal according to the sampling rate.

The RF integrated circuit further includes: a frequency divider configured to receive the frequency signal from the shared phase-locked loop circuit, divide the frequency signal, and provide the divided frequency signal to the plurality of receiving circuits, the modem configured to control a division ratio of the frequency divider based on a highest band group among two or more band groups corresponding to the radio frequency signal.

One of the plurality of receiving circuits includes: a frequency divider configured to receive the frequency signal, divide the frequency signal, and generate a divided frequency signal for analog-to-digital conversion, the modem configured to control a division ratio of the frequency divider based on a basis set corresponding to the RF signal.

The RF integrated circuit further includes a plurality of transmit circuits that transmit RF signals, the shared phase-locked loop circuit being configured to provide frequency signals for digital-to-analog conversion to the plurality of transmit circuits.

One of the plurality of transmitting circuits includes: a digital conversion circuit configured to up-convert a digital baseband signal received by the modem and generate a digital output signal; a digital-to-analog converter (DAC) configured to convert the digital output signal into an analog signal by using the frequency signal. According to another aspect of the example embodiments, there is provided a non-transitory processor-readable storage medium comprising a command, wherein when the command is executed by a processor internal to a wireless communication device comprising a plurality of receive circuits sharing one phase-locked loop circuit, the non-transitory processor is configured to: a digital reference signal for down-converting a Radio Frequency (RF) signal received by the plurality of receiving circuits is provided to the plurality of receiving circuits based on a channel corresponding to the RF signal, and a signal for adjusting a sampling rate at the time of analog-to-digital conversion performed by the plurality of receiving circuits based on a band group corresponding to the RF signal is provided to the plurality of receiving circuits.

Drawings

Example embodiments will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which:

fig. 1 illustrates a wireless communication apparatus performing a wireless communication operation and a wireless communication system including the same according to an example embodiment;

fig. 2A to 2D and fig. 3A and 3B are diagrams for explaining a technique of Carrier Aggregation (CA) according to an example embodiment;

fig. 4 is a block diagram illustrating a wireless communication device according to an example embodiment;

fig. 5 is a block diagram showing a connection relationship between a plurality of receiving circuits of a wireless communication apparatus according to an example embodiment;

fig. 6A to 6C are diagrams illustrating a connection structure between a receiving circuit and a shared phase-locked loop circuit according to an example embodiment;

fig. 7 is a block diagram of the first receiving circuit in fig. 5 according to an example embodiment;

fig. 8A and 8B are diagrams illustrating an implementation example of a time-interleaved analog-to-digital converter (ADC) capable of time interleaving according to an example embodiment;

fig. 9A and 9B are diagrams for explaining detailed operations of the time interleaving ADC of fig. 8A and 8B according to example embodiments;

fig. 10A and 10B are block diagrams of an implementation example of a wireless communication device including a frequency divider according to an example embodiment;

Fig. 11A and 11B are diagrams for explaining operations of a receiving circuit and a modem when an inter-band CA operation is performed according to an example embodiment, and fig. 11C is a flowchart of an example embodiment of sequentially adjusting a sampling rate in an ADC operation of the receiving circuit;

fig. 12A and 12B are block diagrams showing an implementation example of a wireless communication apparatus in which each of a plurality of receiving circuits includes a frequency divider according to an example embodiment;

fig. 13 is a block diagram illustrating an example of an implementation of a transmit circuit shared phase-locked loop circuit of a wireless communication device according to an example embodiment;

fig. 14 is a block diagram illustrating an example of an implementation of a transceiver circuit shared phase-locked loop circuit of a wireless communication device according to an example embodiment;

fig. 15 is a block diagram illustrating an electronic device supporting communication functions including beamforming functions according to an example embodiment.

Detailed Description

In general, a wireless communication device supporting carrier aggregation may include an RF integrated circuit (or RF front-end module) including a plurality of receiving circuits (or receivers) receiving RF signals and a plurality of transmitting circuits (or transmitters) transmitting RF signals.

Each of the plurality of receiving circuits may individually have a hardware configuration of a local oscillator that generates a frequency signal for down-conversion of the RF signal. Due to such a configuration, it is difficult to reduce the design area of the receiving circuit, and since the wireless communication apparatus requires a large number of local oscillators, the power consumed by the local oscillators is significant, and it is difficult to efficiently utilize the power at the time of communication operation of the wireless communication apparatus.

Hereinafter, example embodiments are described in detail with reference to the accompanying drawings.

Fig. 1 shows a wireless communication apparatus 100 that performs a wireless communication operation and a wireless communication system 10 including the wireless communication apparatus 100.

Referring to fig. 1, a wireless communication system 10 may be any one of the following systems: long Term Evolution (LTE) systems, code Division Multiple Access (CDMA) systems, global system for mobile communications (GSM) systems, wireless Local Area Network (WLAN) systems, and the like. In addition, CDMA systems may also be implemented in various CDMA releases such as Wideband CDMA (WCDMA), time division synchronous CDMA (TD-SCDMA), and CDMA 2000.

The wireless communication system 10 may include at least two base stations 110 and 112 and a system controller 120. However, the example embodiments are not limited thereto and the wireless communication system 10 may include multiple base stations and multiple network entities. The wireless communication device 100 may be referred to as a User Equipment (UE), a Mobile Station (MS), a Mobile Terminal (MT), a User Terminal (UT), a Subscriber Station (SS), a mobile device, etc. Base stations 110 and 112 may be referred to as fixed stations that communicate with wireless communication device 100 and/or other base stations, and base stations 110 and 112 may communicate with wireless communication device 100 and/or other base stations to transceive Radio Frequency (RF) signals including control information. Each of base stations 110 and 112 may be referred to as a node B, an evolved node B (eNB), a Base Transceiver System (BTS), an Access Point (AP), etc.

The wireless communication device 100 may communicate with the wireless communication system 10 and may receive signals from the broadcast station 114. Further, the wireless communication device 100 may receive signals from satellites 130 of a Global Navigation Satellite System (GNSS). The wireless communication device 100 may support radio technologies for wireless communications (e.g., LTE, CDMA200, WCDMA, TD-SCDMA, GSM, 802.11, etc.).

The wireless communication device 100 may support carrier aggregation by performing transceiving operations using a plurality of carriers. The wireless communication device 100 may perform wireless communication with the wireless communication system 10 in a low frequency band, a medium frequency band, and a high frequency band. Each of the low, medium, and high frequency bands may be referred to as a band group, and each band group may include a plurality of bands. The band group may be variably determined according to a communication standard or a communication infrastructure, and may be determined more finely or coarsely than the above-described low, medium, and high frequency bands. That is, the low frequency band, the middle frequency band, and the high frequency band are only examples. Furthermore, the bandwidths of the frequency bands included in each band group may vary according to a communication standard or a communication infrastructure.

For example, in LTE, one frequency band may cover up to about 20MHz. Carrier aggregation (hereinafter, referred to as CA) can be classified into intra-band CA and inter-band CA. The intra-band CA may represent performing a wireless communication operation by using a plurality of carriers within the same frequency band, and the inter-band CA may represent performing a wireless communication operation by using a plurality of carriers within different frequency bands.

The RF integrated circuit of the wireless communication device 100 according to example embodiments may include a plurality of receiving circuits for receiving the RF signal, and at least two receiving circuits among the plurality of receiving circuits may share one phase-locked loop circuit generating a frequency signal for analog-to-digital conversion of the RF signal. In addition, each of the receiving circuits may include a digital conversion circuit that down-converts (i.e., performs down-conversion of) the RF signal, and the digital conversion circuit may receive the RF signal converted into the digital signal and perform down-conversion on the RF signal. The digital conversion circuit may receive a digital reference signal for performing the down-conversion from a modem of the wireless communication device 100.

Further, the RF integrated circuit of the wireless communication apparatus 100 may include a plurality of transmission circuits for transmitting the RF signal, and at least two transmission circuits among the plurality of transmission circuits may share one phase-locked loop circuit generating a frequency signal for digital-to-analog conversion operation of the RF signal. In addition, each transmit circuit may include a digital conversion circuit that up-converts (i.e., performs up-conversion of) the RF signal, and the digital conversion circuit may receive the digital baseband signal from the modem and perform up-conversion on the digital baseband signal. The digital conversion circuit may receive a digital reference signal for performing up-conversion from a modem of the wireless communication device 100.

Further, the receiving circuit and the transmitting circuit of the RF integrated circuit of the wireless communication apparatus 100 may be implemented to share one phase-locked loop circuit, and a specific example embodiment in which the phase-locked loop circuit is shared is described with reference to fig. 6A and the like.

Fig. 2A to 2D and fig. 3A and 3B are diagrams for explaining a technique of CA.

Fig. 2A is an exemplary diagram of a continuous in-band CA. Referring to fig. 2A, the wireless communication device 100 in fig. 1 may transceive signals by using four consecutive carriers within the same frequency band in a low frequency band.

Fig. 2B is an exemplary diagram of a discontinuous in-band CA. Referring to fig. 2B, the wireless communication device 100 may transceive signals by using four non-contiguous carriers within the same frequency band in a low frequency band. The frequency band may include a plurality of frequency channels, and the four non-contiguous carriers may correspond to different frequency channels, respectively. For example, the plurality of carriers may be separated from each other by about 5MHz, about 10MHz, or other amounts.

Fig. 2C is an exemplary diagram of inter-band CA in the same band group. Referring to fig. 2C, the wireless communication apparatus 100 may perform transceiving of signals by using four carriers corresponding to channels included in two bands (i.e., low band 1 and low band 2) in the same band group (i.e., low band).

Fig. 2D is an exemplary diagram of inter-band CA in different band groups. Referring to fig. 2D, the wireless communication apparatus 100 may perform transceiving of signals by using four carriers corresponding to frequency channels in different band groups. Two carriers may correspond to channels included in any one of the low frequency bands, and the other two carriers may correspond to channels included in any one of the medium frequency bands.

The CAs shown in fig. 2A to 2D are not limited to these examples, and the wireless communication apparatus 100 may support various combinations of CAs for a plurality of frequency bands or a plurality of band groups. Further, the CA shown in fig. 2A to 2D shows four carriers, but the specific number of carriers is not limited and may be smaller or larger than the number of carriers shown.

Referring to fig. 3A, a new technique for CA has emerged that combines and operates multiple frequency bands at one or more base stations to meet the need for increased bit rates. LTE, which is one of mobile networks, can achieve a data transmission rate of about 100Mbps, and thus, can smoothly transmit and receive a large-capacity video in a wireless environment. Fig. 3A shows an example in which five frequency bands in the LTE standard are combined by CA technology to increase the data transmission rate by approximately 5 times. Since each carrier in fig. 3A is a carrier defined by LTE and one frequency bandwidth is defined to reach about 20MHz in the LTE standard, the wireless communication apparatus 100 according to the example embodiment may increase the data rate to a maximum bandwidth of about 100 MHz.

Although fig. 3A shows an example in which only carriers defined by LTE are combined, example embodiments are not limited thereto. As shown in fig. 3B, the carriers of different wireless communication networks may also be combined. Referring to fig. 3B, since a plurality of frequency bands are combined through CA technology, not only a plurality of frequency bands in the LTE standard but also a plurality of frequency bands in the 3G and Wi-Fi standards may be combined. In a similar manner, LTE-advanced (LTE-a) can perform faster data transmission by employing CA technology.

Fig. 4 is a block diagram illustrating a wireless communication device 200 according to an example embodiment.

Referring to fig. 4, the wireless communication device 200 may include a first transceiving circuit (or transceiver) 230_1 connected to a primary antenna 210_1, a second transceiving circuit 230_2 connected to a secondary antenna 210_2, and a modem (or baseband processor) 250. The first transceiving circuit 230_1 may include a first antenna interface circuit 232_1, a receive circuit 234_1, and a transmit circuit 236_1. The second transceiver circuit 230_2 may include a second antenna interface circuit 232_2, a receiving circuit 234_2, and a transmitting circuit 236_2. In fig. 4, each of the first transceiving circuit 230_1 and the second transceiving circuit 230_2 is shown to include one of the receiving circuit 234_1 and the receiving circuit 234_2 and one of the transmitting circuit 236_1 and the transmitting circuit 236_2, respectively, but this is merely an example embodiment. The example embodiment is not limited thereto, and the first transceiving circuit 230_1 and the second transceiving circuit 230_2 may further include a plurality of receiving circuits and a plurality of transmitting circuits, respectively.

The first transceiver circuit 230_1 and the second transceiver 230_2 may support multiple frequency bands, multiple radio technologies, CA, receive diversity, multiple-input multiple-output (MIMO) transmission between multiple transmit antennas and multiple receive antennas, and so on.

The receive circuit 234_1 and the receive circuit 234_2 may include a low noise amplifier, an analog-to-digital converter (ADC), and a digital conversion circuit dc_ckt. The configuration of the reception circuit 234_1 and the reception circuit 234_2 can be applied to other reception circuits included in the wireless communication apparatus 200. Hereinafter, the operation of the first transceiving circuit 230_1 is described, and example embodiments of the first transceiving circuit 230_1 may be applied to the second transceiving circuit 230_2.

For receiving data, the primary antenna 210_1 may receive RF signals from the base station 110, the base station 112, and the like. The first antenna interface circuit 232_1 may route RF signals to the selected receive circuit 234_1. The first antenna interface circuit 232_1 may include a duplexer, a filter circuit, an input matching circuit, and the like.

The receiving circuit 234_1 according to example embodiments may filter the received RF signal such that only signal components corresponding to a specific band group (or a specific band) pass, and may perform an operation (or analog-to-digital conversion (ADC)) of converting the filtered RF signal into a digital signal. In addition, the digital conversion circuit cd_ckt may receive a digital reference signal from the modem 250 and may perform down-conversion on the RF signal that has been converted into the digital signal based on the received digital reference signal. Since the receiving circuit 234_1 includes the digital converting circuit dc_ckt, a hardware configuration of a local oscillator for generating a frequency signal having a variable frequency according to a channel corresponding to the RF signal received through the receiving circuit 234_1 may not be required. Accordingly, the size of the receiving circuit 234_1 can be reduced, and as a result, the design efficiency of the RF integrated circuit including the receiving circuit 234_1 can be improved. The reception circuit 234_1 may provide the digital baseband signal generated via the down-conversion to the modem 250, and the modem 250 may process the digital baseband signal to generate a data signal.

Further, in some example embodiments, a plurality of receiving circuits in the first transceiving circuit 230_1 including the receiving circuit 234_1 may share a phase locked loop circuit. In some example embodiments, the phase-locked loop circuit may generate a frequency signal for analog-to-digital conversion and provide the generated frequency signal to multiple receive circuits sharing the phase-locked loop circuit. Since the plurality of receiving circuits sharing the phase-locked loop circuit commonly receive the frequency signal having the same frequency, the frequency dividing operation of the frequency signal can be used so that each of the plurality of receiving circuits acquires the frequency signal having the target frequency. In some example embodiments, the modem 250 may control a frequency dividing operation of the frequency signal of the phase locked loop circuit such that each of the plurality of receiving circuits acquires the frequency signal having the target frequency, and the receiving circuit may perform an analog-to-digital conversion operation by using the frequency signal having the target frequency. Detailed example embodiments of this are described later with reference to fig. 8A to 8B, 10A to 10B, 13, and the like.

In some example embodiments, the plurality of receiving circuits 234_2 in the second transceiving circuit 230_2 may share a different phase-locked loop circuit than the phase-locked loop circuit shared by the plurality of receiving circuits 234_1 in the first transceiving circuit 230_1. In other words, the wireless copper wire device 200 may be implemented to have a structure such that: the first transceiving circuit 230_1 and the second transceiving circuit 230_2 each individually share their own different phase-locked loop circuits. In another example embodiment, the plurality of receiving circuits 234_1 in the first transceiving circuit 230_1 and the plurality of receiving circuits 234_2 in the second transceiving circuit 230_2 may share one phase locked loop circuit. In other words, the wireless communication apparatus 200 may be implemented to have a structure such that: the first transceiving circuit 230_1 and the second transceiving circuit 230_2 share one phase locked loop circuit. Furthermore, it is possible to realize: the plurality of receiving circuits in the first transceiving circuit 230_1 and the second transceiving circuit 230_2 are grouped and the receiving circuits in different groups share phase locked loop circuits different from each other. However, the above example embodiments are merely illustrative, and example embodiments of the receiving circuits 234_1 and 234_2 sharing a phase-locked loop circuit may be implemented differently.

The transmitting circuits 236_1 and 236_2 may include a power amplifier, an analog-to-digital converter (DAC), and a digital conversion circuit (not shown). The configuration of the transmission circuits 236_1 and 236_2 can be applied to other transmission circuits included in the wireless communication device 200.

The digital conversion circuit of the transmission circuit 236_1 may receive the digital reference signal and the digital baseband signal from the modem 250 and perform up-conversion on the digital baseband signal based on the digital reference signal. Thereafter, the DAC of the transmit circuit 236_1 may convert the digital RF signal to an analog RF signal, and the power amplifier of the transmit circuit 236_1 may amplify the analog RF signal to have an appropriate output power level. The transmitting circuit 236_1 may provide the amplified analog RF signal to the primary antenna 210_1 via the first antenna interface circuit 232_1, and the primary antenna 210_1 may transmit the amplified analog RF signal to the base stations 110 and 112, etc.

Example embodiments similar to example embodiments in which the receiving circuits 234_1 and 234_2 share a phase-locked loop circuit may also be applied to the transmitting circuits 236_1 and 236_2, and the phase-locked loop circuit shared by the transmitting circuits 236_1 and 236_2 may be the same as or different from the phase-locked loop circuit shared by the receiving circuits 234_1 and 234_2. Hereinafter, a phase-locked loop circuit shared by a plurality of receiving circuits or a plurality of transmitting circuits may be referred to as a shared phase-locked loop circuit.

The modem 250 may generate a data signal by demodulating the baseband signals received from the transceiving circuits 230_1 and 230_2 and provide the baseband signals generated by modulating the data signal to the transceiving circuits 230_1 and 230_2. In addition, the modem 250 may generate digital reference signals for down-conversion or up-conversion of the transceiving circuits 230_1 and 230_2 and provide the generated digital reference signals to the transceiving circuits 230_1 and 230_2. The modem 250 may control a frequency dividing operation of the frequency signal sharing the phase-locked loop circuit such that each of the receiving circuits 234_1 and 234_2 or each of the transmitting circuits 236_1 and 236_2 acquires the frequency signal having the target frequency. The modem 250 may include a memory 250a, and the memory 250a may store instructions defined to perform the above-described operations of the modem 250. The modem 250 may perform operations of the modem 250 according to example embodiments by executing instructions stored in the memory 250 a.

Fig. 5 is a block diagram showing a connection relationship between a plurality of receiving circuits of the wireless communication apparatus 300 according to an example embodiment.

Referring to fig. 5, the wireless communication apparatus 300 may include first to nth receiving circuits 330_1 to 330—n, a modem 350, and a Shared phase-locked loop circuit (shared_pll) 370. The first receiving circuit 330_1 may include first to mth Low Noise Amplifiers (LNAs) 331_1 to 331_m, first to mth filters 332_1 to 332_m, a Multiplexer (MUX) 333, an ADC334, and a digital conversion circuit 335, and the configuration of the first receiving circuit 330_1 may be applied to the second to nth receiving circuits 330_2 to 330—n. RF signal RF _IN At least one of the first to nth receiving circuits 330_1 to 330—n may be selected to receive the RF signal RF according to a CA type (i.e., intra-band CA or inter-band CA) may be transmitted via a plurality of carriers in at least one band group _IN 。

In some example embodiments, the shared_pll 370 may include a voltage controlled oscillator and a frequency multiplier, and may generate a frequency signal having a specific frequency. The frequency of the frequency signal generated by shared_ppl 370 may be controlled by modem 350 via PPL control signal pll_cs. The shared_ppl 370 may be implemented as a local oscillator according to example embodiments and may have a structure in which the first to nth receiving circuits 330_1 to 330—n share one local oscillator.

The first LNA 331_1 and the first filter 332_1 may constitute a path through which a signal component transmitted through a carrier corresponding to one band group is received among a plurality of signal components of the RF signal. Further, in order to support the inter-band CA described with reference to fig. 2C, the first LNA 331_1 and the first filter 332_1 may constitute a path in which a signal component transmitted through a carrier corresponding to one frequency band is received among a plurality of signal components of the RF signal. In other words, the first to mth filters 331_1 to 331_m and the first to mth filters 332_1 to mth filters may be passed through 332—m configuration capable of receiving RF signals RF corresponding to each band group (or each band) _IN The MUX 333 may receive the multiplexer control signal mux_cs from the modem 350 and perform the CA operation by selecting one of a plurality of paths based on the received multiplexer control signal mux_cs. In other words, the first receiving circuit 330_1 can receive the RF signal RF corresponding to one band group among the plurality of band groups through the configurations of the first LNA 331_1 to the mth LNA 331_m, the first filter 332_1 to the mth filter 332_m, and the MUX 333 _IN . The first to mth filters 332_1 to 332_m may be implemented to make only the RF signal RF _IN The components corresponding to the specific band group pass through. However, the example embodiments are not limited thereto, and the first to mth filters 332_1 to 332_m may be applied to the RF signal RF _IN Selectively filtered to support CA. For example, the filter may have various pass bands.

The ADC 334 may receive a frequency signal f_s having a specific frequency from the shared_pll 370. The shared_pll 370 may provide the same frequency signal f_s to the first to nth receiving circuits 330_1 to 330—n. In other words, the first to nth receiving circuits 330_1 to 330—n may be implemented to share one shared_pll 370.ADC 334 may receive RF signal RF from MUX 333 that has passed through the selected path _IN And analog-to-digital conversion may be performed based on the frequency signal f_s.

The digital conversion circuit 335 may perform down-conversion on the RF signal that has been converted into the digital signal based on the first digital reference signal d_rs1 received from the modem 350. In other words, the digital conversion circuit 335 may perform an operation of converting an RF band signal into a baseband signal. The first digital reference signal D_RS1 can be based on the RF signal RF _IN The corresponding channel changes. For example, with further reference to FIG. 2A, in the RF signal RF _IN The first digital reference signal D_RS1 in the case of a channel corresponding to a high frequency band may be compared with the RF signal RF _IN The first digital reference signal d_rs1 in the case of a channel corresponding to a low frequency band is different.

Digital conversion circuit 335 may provide first digital baseband signal BB generated as a result of performing the down-conversion to modem 350 _OUT1 The modem 350 can convert the first digital baseband signal BB _OUT1 Processes (or demodulates) and generates a data signal. The above configuration of the first receiving circuit 330_1 can be applied to the second receiving circuit 330_2 to the nth receiving circuit 330—n. In other words, the modem 350 can provide the second digital reference signals d_rs2 to n-th digital reference signals d_rsn to the second receiving circuits 330_2 to n-th receiving circuits 330_n, respectively, and can receive the second digital baseband signals BB from the second receiving circuits 330_2 to n-th receiving circuits 330_n, respectively _OUT2 To the nth digital baseband signal BB _OUTn 。

The first to nth receiving circuits 330_1 to 330_n according to example embodiments may include a digital conversion circuit 335 that receives a digital reference signal from the modem 350 and performs down-conversion, thereby eliminating the need to generate a reference signal according to the RF signal RF _IN A local oscillator of the corresponding channel variable frequency signal. Further, since the structures in which the first to nth receiving circuits 330_1 to 330—n share the shared_pll 370 are applicable, the size of the RF integrated circuit including the first to nth receiving circuits 330_1 to 330—n can be reduced and the power consumption of the RF integrated circuit can be reduced.

Fig. 6A to 6C are diagrams illustrating a connection structure between a receiving circuit and a shared phase-locked loop circuit according to an example embodiment.

Referring to fig. 6a, the rf integrated circuit may include a plurality of first receiving circuits (330g1_1 to 330g1_j), a plurality of second receiving circuits (330g2_1 to 330g2_k), a first shared_pll (shared_pll 1) 370G1, and a second shared_pll (shared_pll 2) 370G2. The plurality of first receiving circuits (330g1_1 to 330g1_j) may constitute a first receiving circuit group rckt_g1, and the plurality of second receiving circuits (330g2_1 to 330g2_k) may constitute a second receiving circuit group rckt_g2. The first and second reception circuit groups rckt_g1 and rckt_g2 may be defined as units for grouping reception circuits sharing shared_pll1370G 1 and shared_pll2g2, respectively.

In some example embodiments, the first receiving circuit group rckt_g1 may be connected to shared_pll1 370G1 to receive the first frequency signal f_s1 of the first frequency. The second receiving circuit set rckt_g2 may be connected to the shared_pll2 370G2 to receive the second frequency signal f_s2 of the second frequency. The first frequency of the first frequency signal f_s1 and the second frequency of the second frequency signal f_s2 may be the same or different from each other. Although fig. 6A shows an example embodiment in which two reception circuit groups (rckt_g1 and rckt_g2) are distinguished, the example embodiment is not limited thereto. Further implementation examples may be possible such that multiple receive circuits constitute more receive circuit groups than the one shown in fig. 6A, and each receive circuit group may be individually connected to a shared phase-locked loop circuit. That is, the number of the receiving circuit groups is not particularly limited and may be more than two shown in fig. 6A.

Hereinafter, an exemplary embodiment of a standard in which a plurality of reception circuits constitute one reception circuit group is described with reference to fig. 6B. Referring to fig. 6A to 6B, the plurality of first receiving circuits (330g1_1 to 330g1_j) may have a configuration capable of receiving the first frequency signal f_s1 corresponding to the first band group BG1 between the first frequency F1 and the second frequency F2 and the second band group BG2 between the second frequency F2 and the third frequency F3, and the plurality of second receiving circuits (330g2_1 to 330g2_k) may have a configuration capable of receiving the second frequency signal f_s2 corresponding to the third band group BG3 between the third frequency F3 and the fourth frequency F4 and the fourth band group BG4 between the fourth frequency F4 and the fifth frequency F5. For example, the plurality of first receiving circuits (330g1_1 to 330g1_j) may include a filter for receiving the first frequency signal f_s1 corresponding to the first band group BG1 and the second band group BG2, and the plurality of second receiving circuits (330g2_1 to 330g2_k) may include a filter for receiving the second frequency signal f_s2 corresponding to the third band group BG3 and the fourth band group BG 4. In other words, the first band group BG1 and the second band group BG2 corresponding to the first frequency signal f_s1 receivable by the plurality of first receiving circuits (330g1_1 to 330g1_j) and the third band group BG3 and the fourth band group BG4 corresponding to the second frequency signal f_s2 receivable by the plurality of second receiving circuits (330g2_1 to 330g2_k) may be different from each other. At this time, the plurality of first receiving circuits (330g1_1 to 330g1_j) may constitute the first receiving circuit group rckt_g1, and the plurality of second receiving circuits (330g2_1 to 330g2_k) may constitute the second receiving circuit group rckt_g2. The first frequency signal f_s1 received from the shared_pll1 370G1 by the plurality of first receiving circuits (330g1_1 to 330g1_j) may have a lower frequency than the second frequency signal f_s2 received from the shared_pll 2G 2 by the plurality of second receiving circuits (330g2_1 to 330g2_k).

The first to fourth band groups BG1 to BG4 described with reference to fig. 6B are only example embodiments. Fewer or more band groups may exist and multiple receive circuits may be grouped according to band groups of frequency signals that may be received by the multiple receive circuits. Further, the RF integrated circuit may include a greater number of shared phase-locked loop circuits than the number of shared phase-locked loop circuits shown in fig. 6A according to example embodiments.

Referring to fig. 6c, the rf integrated circuit may include a plurality of first receiving circuits (330g1_1 to 330g1_j), a plurality of second receiving circuits (330g2_1 to 330g2_k), a frequency divider 370G1', and a shared_pll 370G2'. In some example embodiments, the second receiving circuit group rckt_g2 may be connected to the shared_pll 370G2' to receive the second frequency signal f_s2 of a specific frequency. The first receiving circuit group rckt_g1 may be connected to a frequency divider 370G1' to receive a signal f_s1', wherein the signal f_s1' is a signal divided from the second frequency signal f_s2. The division ratio of the frequency divider 370G1' may be determined according to a band group (or a band in the band group, or a channel) of the RF signal receivable by the plurality of first receiving circuits (330g1_1 to 330g1_j). The example embodiment shown in fig. 6C is merely illustrative, and various implementations in which more frequency dividers are respectively connected to more receiving circuit groups may be possible.

Fig. 7 is a block diagram of the first receiving circuit 330_1 in fig. 5 according to an example embodiment.

Referring to fig. 7, the first receiving circuit 330_1 may include first to third LNAs 331_1 to 331_3, a Low Band (LB) filter 332_1', a Middle Band (MB) filter 332_2', a High Band (HB) filter 332_3', a MUX 333, an ADC 334, and a digital conversion circuit 335. The first to third LNAs 331_1 to 331_3, the LB filter 332_1', the MB filter 332_2', the HB filter 332_3', the MUX 333, and the ADC 334 may be referred to as AN analog circuit an_ckt, in which the original RF signal RF _IN Is input to the analog circuit an_ckt. Digital conversionCircuit 335 may include digital mixers DMa and DMb, digital low pass filters FTa and FTb, and digital decimation filters DEa and DEb.

The LB filter 332_1' may be used to make RF signal RF only _IN The MB filter 332_2' may pass only the signal component corresponding to the LB of (b) _IN The signal component corresponding to MB of (B) passes through, and the HB filter 332_3' can pass only the RF signal RF _IN The signal component corresponding to HB passes. However, the example embodiment is only an example, and each of the LB filters 332_1', the MB filters 332_2', and the HB filters 332_3' may be implemented to pass only signal components corresponding to different frequency bands, and the first receiving circuit 330_1 may include more than three filters. Hereinafter, for convenience of description, it is assumed that each of the LB filters 332_1', the MB filters 332_2', and the HB filters 332_3' is implemented to pass only signal components corresponding to different band groups. The modem 350 may provide the MUX 333 with a MUX control signal mux_cs and control the MUX 333 such that the RF signal RF having passed through any one of the LB filters 332_1', MB filters 332_2', and HB filters 332_3 _IN Is output to ADC 334. The ADC 334 may receive the frequency signal F_S from the shared_PLL 370 and pair the analog RF signal RF based on the frequency signal F_S _IN Performing sampling to generate a digital RF signal RF _IN 。

The digital mixer DMa and the digital mixer DMb may receive the digital reference signal d_rs1a and the digital reference signal d_rs1b from the modem 350, respectively, and may divide the digital RF signal into an I channel and a Q channel by using the digital reference signal d_rs1a and the digital reference signal d_rs1b, respectively, and generate down-converted digital signals. The generated down-converted digital signal may be filtered via passing through respective digital low pass filters FTa and FTb to remove noise signals generated during down-conversion. The filtered digital signals may be downsampled via respective decimation filters DEa and Deb, respectively, resulting in an I digital baseband signal i_bb comprising samples of the signal corresponding to the target channel _OUT1 And Q digital baseband signal Q_BB _OUT2 May be generated separately. Modem 350 may receive I digital baseband signal i_bb from digital conversion circuit 335 _OUT1 And Q digital baseband signal Q_BB _OUT2 . The modem 350 can control the degree of downsampling of the digital decimation filters DEa and DEb, and thus can be optimized for the I digital baseband signal i_bb _OUT1 And Q digital baseband signal Q_BB _OUT2 Is a processing operation speed of the above.

The modem 350 can receive the RF signal RF from the first receiving circuit 330_1 _IN The digital reference signals d_rs1a and d_rs1b are changed corresponding to channels. For example, when the path formed by the first LNA 331_1 and the LB filter 332_1' is activated by the MUX 333, the first receiving circuit 330_1 may receive the RF signal RF corresponding to LB _IN And the modem 350 may generate the digital reference signals d_rs1a and d_rs1b having specific values such that the digital conversion circuit 335 is RF to the RF signal _IN Down-conversion from the channel in the LB to baseband is performed. In addition, when the path formed by the second LNA 331_2 and the MB filter 332_2' is activated by the MUX 333, the first receiving circuit 330_1 may receive the RF signal RF corresponding to MB _IN And the modem 350 may generate the digital reference signals d_rs1a and d_rs1b having specific values such that the digital conversion circuit 335 is RF to the RF signal _IN Down-conversion from channels in MB to baseband is performed.

The configuration of the first receiving circuit 330_1 shown in fig. 7 may be applied to the other second receiving circuits 330_2 to n-th receiving circuits 330—n shown in fig. 5.

Fig. 8A and 8B are diagrams illustrating an implementation example of a time-interleaved analog-to-digital converter (ADC) 400 capable of time interleaving according to an example embodiment.

According to an example embodiment, the ADC 334 in fig. 7 may be implemented as the time-interleaved ADC 400 of fig. 8A. The time interleaving ADC 400 may include a splitter 401, a first ADC circuit adc_1 402, a second ADC circuit adc_2 403, a third ADC circuit adc_3 404, a fourth ADC circuit adc_4 405, a combiner 406, and a time interleaving control circuit 407. The time interleaving control circuit 407 can receive the RF signal RF received by the first receiving circuit 330_1 from the modem 350 (refer to fig. 7) _IN Corresponding Band Group Information (BGI), and may be provided to the splitter by providing time interleaving control signals tl_cs and tl_cs', respectively, based on the BGI401 and combiner 406 to control the sampling rate of the time interleaved ADC 400.

The splitter 401 may receive AN analog signal (or RF signal) an_s and provide the analog signal an_s to the first to fourth ADC circuits 402 to 405 with a constant time difference based on the time interleaving control signal tl_cs. As a result, the first to fourth ADC circuits 402 to 405 may receive the analog signals an_s having constant phases different from each other from the splitter 401 and the frequency signal f_s from the shared_pll 370 (refer to fig. 7), and may digitally convert the received analog signals an_s based on the same sampling rate and provide the digital conversion result to the combiner 406. The combiner 406 may combine the digital conversion results from the first to fourth ADC circuits 402 to 405 based on the time interleaving control signal tl_cs', and may generate a digital signal dg_s.

Since the first receiving circuit (330_1 in fig. 7) shares the phase-locked loop circuit (370 in fig. 7) with other receiving circuits, it may be difficult for the first receiving circuit 330_1 to obtain a frequency signal of an appropriate frequency having an appropriate sampling rate every time in an actual ADC operation. Accordingly, the first receiving circuit (330_1 in fig. 7) may be implemented to include the time-interleaved ADC 400 of fig. 8A, thereby selectively controlling the first to fourth ADC circuits 402 to 405 to appropriately change the sampling rate of the entire time-interleaved ADC 400. For example, when the time-interleaved ADC 400 receives a frequency signal f_s having a frequency lower than the threshold frequency, the time-interleaved control circuit 407 may selectively use a greater number of ADC circuits than the number of ADC circuits to be used at the threshold frequency to obtain an appropriate sampling rate. When receiving the frequency signal f_s having a frequency higher than the threshold frequency, the time interleaving control circuit 407 can selectively control a smaller number of ADC circuits than the number of ADC circuits to be used at the threshold frequency to obtain an appropriate sampling rate.

However, the example embodiments are merely examples. The time interleaving control circuit 407 can receive the RF signal RF received by the first receiving circuit 330_1 from the modem (350 in fig. 7) _IN Corresponding band-related information or channel-related information, and the time-interleaved ADC may be controlled based on the band-related information or channel-related informationA sampling rate of 400. When the time interleaving ADC 400 is controlled based on the band-related information or the channel-related information, the sampling rate can be adjusted more finely than in the case when the time interleaving ADC 400 is controlled based on BGI.

Fig. 8A shows an example embodiment in which the time interleaving ADC 400 includes a separate time interleaving control circuit 407, but the example embodiment is not limited thereto, and in some example embodiments, a modem (350 in fig. 7) may be implemented as the direct control time interleaving ADC 400. Further, fig. 8A illustrates an example embodiment in which the time-interleaved ADC 400 includes four ADC circuits (i.e., 402 to 405), but the example embodiment is not limited thereto, and the time-interleaved ADC 400 may be implemented to include fewer or more ADC circuits than the number illustrated in fig. 8A.

Referring to fig. 8B, the time-interleaved ADC 400 may further include an ADC driving voltage supply circuit 408, as compared to fig. 8A. The time interleaving control circuit 407 may provide the ADC driving voltage supply circuit 408 with a voltage supply control signal v_cs including information about at least one ADC circuit used in ADC operation. The ADC driving voltage supply circuit 408 may drive the voltage V based on the voltage supply control signal V_CS _DD Is provided to at least one of the first to fourth ADC circuits 402 to 405 for ADC operation without driving the voltage V _DD To an ADC circuit not used for ADC operation. In other words, the ADC driving voltage supply circuit 408 can supply the driving voltage V _DD Only to the ADC circuit for ADC operation, thereby reducing power consumption.

Fig. 9A and 9B are diagrams for explaining detailed operations of the time interleaving ADC 400 according to example embodiments.

Referring to fig. 9A, the time interleaving control circuit 407 may determine the sampling rate of the time interleaving ADC 400 based on the first BGI1 received from the modem (350 in fig. 7), and may provide the first time interleaving control signals tl_cs1 and tl_cs1' to the splitter 401 and the combiner 406, respectively. The splitter 401 may receive the analog signal an_s1 and may perform a predetermined time interval T based on the first time interleaving control signal tl_cs1 _INV The analog signal an_s1 is supplied to the first to fourth ADC circuits 402 to 405. The first ADC circuit 402 to the fourth ADC circuit 405 may be based on the slave ADC circuitsThe frequency signal f_s received by the shared phase-locked loop circuit (370 in fig. 7) performs a sampling operation every certain period Ts. The plurality of sampling results respectively generated by sampling the analog signal an_s1 at each of the first to eighth times t1 to t8 through the first to fourth ADC circuits 402 to 405 may be provided to the combiner 406, and the combiner 406 may output the digital signal dg_s1 by combining the plurality of sampling results based on the first interleaving control signal tl_cs1'.

Referring to fig. 9B, the time interleaving control circuit 407 may determine the sampling rate of the time interleaving ADC 400 based on the second BGI2 received from the modem (350 in fig. 7), and may provide the second time interleaving control signals tl_cs2 and tl_cs2' to the splitter 401 and the combiner 406, respectively. The splitter 401 may receive the analog signal an_s2 and may perform a predetermined time interval T based on the second time interleaving control signal tl_cs2 _INV ' the analog signal an_s2 is supplied to the first ADC circuit 402 and the third ADC circuit 404. The first ADC circuit 402 and the third ADC circuit 404 may perform sampling operations on the analog signal an_s2 every certain period of time Ts based on the frequency signal f_s received from the shared phase-locked loop circuit (370 in fig. 7). The plurality of sampling results respectively generated by sampling the analog signal an_s2 at the first time t1, the third time t3, the fifth time t5, and the eighth time t8 through the first ADC circuit 402 and the third ADC circuit 404 may be provided to the combiner 406, and the combiner 406 may output the digital signal dg_s2 by combining the plurality of sampling results based on the second time interleaving control signal tl_cs2'. Furthermore, as described above with reference to FIG. 8B, in some example embodiments, the ADC drive voltage supply circuitry (408 in FIG. 8B) may be provided and controlled such that the drive voltage V _DD Are not provided to the second ADC circuit 403 and the fourth ADC circuit 405. For example, the driving voltage V _DD May be provided only to the first ADC circuit 402 and the third ADC circuit 404, and may not be provided to the second ADC circuit 403 and the fourth ADC circuit 405 as indicated by shading in fig. 9B.

By controlling the time interleaving ADC 400 in the manner described with reference to fig. 9A and 9B, the sampling rate can be appropriately adjusted without directly changing the frequency of the frequency signal f_s.

Fig. 10A and 10B are block diagrams of an implementation example of a wireless communication apparatus 300 including a shared_pll 370 for generating a frequency signal having a variable frequency according to an example embodiment.

In contrast to the wireless communication device 300 of fig. 5, the wireless communication device 300 of fig. 10A may receive the frequency control signal f_cs from the modem 350. Hereinafter, the contents overlapping with those given with reference to fig. 5 are omitted, and only the new configuration is described.

Referring to fig. 10A, the modem 350 may be based on the RF signals RF received by the first to nth receiving circuits 330_1 to 330—n _IN Generates the frequency control signal f_cs. For example, when the first receiving circuit 330_1 receives the RF signal RF corresponding to LB _IN The second receiving circuit 330_2 receives the RF signal RF corresponding to MB _IN The third receiving circuit 330_3 receives the RF signal RF corresponding to HB _IN In this case, the modem 350 may generate the frequency control signal f_cs by determining the target frequency based on the band group corresponding to the highest band group among the HB. As another example, when the first receiving circuit 330_1 receives the RF signal RF corresponding to LB _IN And the second receiving circuit 330_2 receives the RF signal RF corresponding to MB _IN In this case, the modem 350 may generate the frequency control signal f_cs by determining the target frequency based on the band group corresponding to the highest band group among the MBs.

The shared_pll 370 may receive the frequency control signal f_cs from the modem 350 and may provide the first to nth receiving circuits 330_1 to 330—n with the frequency signal f_s having the target frequency based on the frequency control signal f_cs. In other words, the shared_pll 370 may provide the frequency signal f_s having a relatively high frequency to the first to nth receiving circuits 330_1 to 330—n such that the RF signal RF having and received from among the first to nth receiving circuits 330_1 to 330—n is provided by using _IN The corresponding receive circuit of the highest band group performs the appropriate ADC operation.

In other example embodiments, the modem 350 may be based on the RF signals RF received by the first through nth receiving circuits 330_1 through 330—n _IN Of frequency bands or channels of (a)Information is used to generate the frequency control signal f_cs so as to more finely adjust the frequency control signal f_cs.

Referring to fig. 10B, each of the first to nth receiving circuits 330_1 to 330—n may include an ADC implemented by the time-interleaved ADC described with reference to fig. 8A or the like. Hereinafter, the first receiving circuit 330_1 is described as an example. The first receiving circuit 330_1 may include a time interleaved ADC (adc_til) 334'. As described with reference to fig. 10A, since the frequency of the frequency control signal f_cs is controlled by using the RF signal RF having the same frequency as that of the received RF signal _IN The receiving circuit of the corresponding highest band group, and thus the frequency signal f_s may not have an appropriate frequency for performing the ADC operation. At this time, the modem 350 may provide the adc_til334' with the RF signal RF related to the reception by the first receiving circuit 330_1 _IN And adc_til334' may adjust the sampling rate based on the BGI. In another embodiment, the modem 350 may provide the RF signal RF received by the first receiving circuit 330_1 to the ADC_TIL 334 _IN And ADC TIL 334' may adjust the sampling rate based on the band-related information or the channel-related information. A detailed description has been given with reference to fig. 8A, and thus a repetitive description thereof is omitted.

Fig. 11A and 11B are diagrams for explaining the operations of the first and second receiving circuits 330_1 and 330_2 and the modem 350 when the inter-band CA operation is performed according to an example embodiment, and fig. 11C is a flowchart of an example embodiment of sequentially adjusting the sampling rate in the ADC operation of the receiving circuits.

Referring to fig. 11A, the wireless communication device 300 may include a first receiving circuit 330_1, a second receiving circuit 330_2, and a shared_pll 370. The first receiving circuit 330_1 may include first to third LNAs 331_11 to 331_31, an LB filter 332_11, an MB filter 332_21, an HB filter 332_31, a MUX 333_1, an ADC 334_1, and a digital conversion circuit 335_1. The second receiving circuit 330_2 may include first to third LNAs 331_12 to 331_32, a first LB filter 332_12, an MB filter 332_22, an HB filter 332_32, a MUX 333_2, an ADC 334_2, and a digital conversion circuit 335_2. Hereinafter, the first receiving circuit 330_1 and the second receiving circuit 330_2 may receive an RF signal RF including a signal component corresponding to the first channel ω1 and a signal component corresponding to the second channel ω2 based on MUX control signals mux_cs1 and mux_cs2 received from the modem 350, respectively _IN . The signal component corresponding to the first frequency channel ω1 may be referred to as a signal component transmitted via a carrier of the first frequency channel ω1, and the signal component corresponding to the second frequency channel ω2 may be referred to as a signal component transmitted via a carrier of the second frequency channel ω2. Hereinafter, it is assumed that the first channel ω1 is included in HB and the second channel ω2 is included in LB.

The first receiving circuit 330_1 may receive the RF signal RF corresponding to HB _IN The second receiving circuit 330_2 may receive the RF signal RF corresponding to LB _IN . As described above, in the case of prioritizing the first receiving circuit 330_1, the modem 350 can be based on the RF signal RF received by the first receiving circuit 330_1 _IN The target frequency is determined and the frequency control signal f_cs may be generated based on the determined target frequency. The shared_pll 370 may receive the frequency control signal f_cs from the modem 350 and may generate a frequency signal f_s having a target frequency based on the frequency control signal f_cs. The shared_pll 370 may provide the frequency signal f_s to the ADC 334_1 of the first receiving circuit 330_1 and the ADC 334_2 of the second receiving circuit 330_2, respectively.

The ADC 334_1 of the first receiving circuit 330_1 may use the frequency signal f_s to apply an analog RF signal RF including only the signal component of the first channel ω1 _IN Converted into a digital signal. The digital conversion circuit 335_1 of the first receiving circuit 330_1 may perform down-conversion on the digital signal by using the first digital reference signal d_rs1 received from the modem 350. The digital conversion circuit 335_1 can convert RF signals RF _IN Extracting signal component of first channel omega 1 to generate first digital baseband signal BB _OUT1 (ω1) and apply the first digital baseband signal BB _OUT1 (ω1) is provided to modem 350.

The ADC 334_2 of the second receiving circuit 330_2 may use the frequency signal f_s to apply an analog RF signal RF including only the signal component of the second channel ω2 _IN Converted into a digital signal. The digital conversion circuit 335_2 of the second receiving circuit 330_2 can pass throughThe digital signal is down-converted using the second digital reference signal d_rs2 received from the modem 350. The digital conversion circuit 335_2 can convert RF signals RF _IN Extracting the signal component of the second channel omega 2 to generate a second digital baseband signal BB _OUT1 (ω2) and apply the second digital baseband signal BB _OUT1 (ω2) is provided to modem 350.

Referring to fig. 11B, the first receiving circuit 330_1 may include an adc_til334_1 ', and the second receiving circuit 330_2 may include an adc_til334_2'. The adc_til334_1 'and the adc_til334_2' may receive the RF signal RF received by the first receiving circuit 330_1 from the modem 350, respectively _IN Corresponding first BGI1 and RF signal RF received by second receiving circuit 330_2 _IN And a corresponding second BGI BGI2, and the sampling rate may be adjusted based on the first BGI BGI1 and the second BGI BGI 2. For example, the modem 350 may provide the adc_til 334-1' with a signal indicating that the first receiving circuit 330_1 receives the RF signal RF corresponding to HB _IN And may provide the adc_til334-2' with a signal indicating that the second receiving circuit 330_2 receives the RF signal RF corresponding to LB _IN Is a second BGI2 of (b). Details of the adc_til 334-1 'and the adc_til 334-2' have been described with reference to fig. 8A and the like, and duplicate descriptions are omitted.

Referring to fig. 11C, a modem according to an example embodiment of the inventive concepts may sequentially adjust a sampling rate during an ADC operation of each of a plurality of receiving circuits. First, the modem may determine a target frequency of the frequency signal by considering a receiving circuit receiving the RF signal corresponding to the highest frequency band group among the plurality of receiving circuits, and may control generation of the frequency signal having the target frequency (S100). Next, the modem may control time interleaving of the ADCs in the receiving circuits by considering a band group corresponding to the RF signal received by each receiving circuit (S110). As a result, the ADC included in each receiving circuit may perform an ADC operation on the analog RF signal based on an appropriate sampling rate (S120).

Fig. 12A and 12B are block diagrams of an implementation example of a wireless communication apparatus 300 in which each receiving circuit includes a frequency divider according to an example embodiment.

The first receiving circuit 330_1 in fig. 12A may further include a frequency divider 380' as compared to the first receiving circuit 330_1 in fig. 5. Similar to the first receiving circuit 330_1, each of the second to nth receiving circuits (330_2 to 330—n in fig. 5) may further include a frequency divider 380'. Each of the receiving circuits in the wireless communication device 300 of fig. 12A including the first receiving circuit 330_1 may individually include a frequency divider 380'. Hereinafter, the first receiving circuit 330_1 shown in fig. 12A is described with reference to, and it can be clearly understood that the example embodiment of the first receiving circuit 330_1 is also applicable to other receiving circuits sharing the shared_pll 370.

The modem 350 may be based on the RF signal RF received by the first receiving circuit 330_1 _IN The corresponding band group determines the division ratio of the frequency divider 380 'and may provide the division ratio control signal div_rt_cs to the frequency divider 380'. For example, when the first receiving circuit 330_1 receives the RF signal RF corresponding to LB _IN When the modem 350 may determine the division ratio as the first division ratio. When the first receiving circuit 330_1 receives the RF signal RF corresponding to MB _IN In this case, the modem 350 may determine the frequency division ratio as the second frequency division ratio. When the first receiving circuit 330_1 receives the RF signal RF corresponding to HB _IN In this case, the modem 350 may determine the frequency division ratio as the third frequency division ratio. The magnitudes of the plurality of division ratios may have the following magnitude relation: third frequency dividing ratio>Second frequency dividing ratio>A first frequency division ratio. The frequency divider 380' may receive the frequency signal f_s from the shared_pll 370 and divide the frequency signal f_s to generate a divided signal div_f_s. The frequency divider 380' may provide the frequency division signal div_f_s to the ADC 334, and the ADC 334 may perform ADC operation according to a sampling rate satisfying the frequency division signal div_f_s.

In this manner, when each of the plurality of receiving circuits is provided with a separate frequency divider, the modem 350 may provide a separate frequency division ratio control signal to each frequency divider to adjust the frequency division ratio of the frequency signal f_s, thereby adjusting the sampling rate of the ADC of each receiving circuit.

In addition, as described above, the modem 350 may be based on the RF signal received by the first receiving circuit 330_1RF _IN The corresponding band related information or channel related information determines the division ratio of the divider 380', and the division ratio control signal div_rt_cs may be provided to the divider 380'.

Referring to fig. 12B, the first receiving circuit 330_1 may include a time interleaving ADC 334_1'. The time interleaving ADC 334_1' may receive the RF signal RF received by the first receiving circuit 330_1 from the modem 350 _IN Corresponding BGIs, and the sampling rate may be adjusted based on the BGIs. A detailed description about the problem has been described with reference to fig. 8A and the like, and duplicate descriptions are omitted for simplicity.

Further, the modem 350 according to an example embodiment may sequentially adjust the sampling rate during the ADC operation of the first receiving circuit 330_1. First, the modem 350 can receive the RF signal RF from the first receiving circuit 330_1 by taking into consideration _IN The frequency division ratio of the frequency divider 380' is determined by the corresponding band group, and the frequency division operation of the frequency signal f_s may be controlled according to the determined frequency division ratio. Next, the RF signal RF received by the first receiving circuit 330_1 may be taken into consideration _IN The corresponding band group controls the time interleaving of the time interleaving ADC 334_1'. As a result, the time-interleaved ADC 334_1' included in the first receiving circuit 330_1 may simulate the RF signal RF based on the appropriate sampling rate _IN An ADC operation is performed.

Fig. 13 is a block diagram showing an implementation example in which a shared_pll 570 is Shared by a plurality of transmission circuits of the wireless communication apparatus 500 according to an example embodiment.

Referring to fig. 13, the wireless communication apparatus 500 may include first to nth transmission circuits 530_1 to 530—n, a modem 550, and a shared_pll 570. The first through nth transmitting circuits 530_1 through 530_n may share one shared_pll 570, and the first through nth transmitting circuits 530_1 through 530_n may receive the frequency signal f_s from the shared_pll 570. The first transmitting circuit 530_1 may include a Power Amplifier (PA) 531, a filter 532, a DAC 533, and a digital conversion circuit 534.

The digital conversion circuit 534 of the first transmitting circuit 530_1 can receive the digital baseband signal BB from the modem 550 _IN1 And a digital reference signal D _ RS1',and can be based on the digital reference signal D_RS1' to the digital baseband signal BB _IN1 Up-conversion is performed. DAC 533 may convert a digital RF signal to an analog RF signal. The first transmitting circuit 530_1 may pass the analog RF signal through the filter 532 and the PA 531 and output the result as an RF output signal RF _OUT . The above configuration of the first transmission circuit 530_1 can be applied to the second transmission circuit 530_2 to the nth transmission circuit 530—n. In other words, the modem 550 can convert the second digital reference signals D_RS2 'to the nth digital reference signal D_RSn' and the second digital baseband signal BB _IN2 To the nth digital baseband signal BB _INn Are supplied to the second to nth transmission circuits 530_2 to 530—n, respectively.

Further, as described above, the wireless communication apparatus 500 includes one frequency divider so that the example embodiment in which the first to nth transmission circuits 530_1 to 530—n share one frequency divider may be applicable, and the example embodiment in which each of the first to nth transmission circuits 530_1 to 530—n includes one separate frequency divider may also be applicable.

Fig. 14 is a block diagram showing an implementation example of a Shared PLL 670 for a plurality of transceiving circuits of a wireless communication device 600 according to an example embodiment.

Referring to fig. 14, the wireless communication apparatus 600 may include first to nth transceiving circuits 630_1 to 630—n, a modem 650, and a shared_pll 670. The first to nth transceiving circuits 630_1 to 630_n may share one shared_pll 670, and the first to nth transceiving circuits 630_1 to 630_n may receive the frequency signal f_s from the shared_pll 670.

Each of the first to nth transceiving circuits 630_1 to 630_n may include at least one transmitting circuit and at least one receiving circuit, and the transmitting circuit and the receiving circuit included in each of the first to nth transceiving circuits 630_1 to 630_n may share the shared_pll 670. Further, as described above, the wireless communication apparatus 600 includes one frequency divider so that the example embodiment in which the first to nth transceiving circuits 630_1 to 630_n share one frequency divider may be applicable, and the example embodiment in which each of the first to nth transceiving circuits 630_1 to 630_n includes one separate frequency divider may also be applicable.

Fig. 15 is a block diagram illustrating an electronic device 1000 supporting communication functions including beamforming functions according to an example embodiment.

Referring to fig. 15, the electronic device 1000 may include a memory 1010, a processor unit 1020, an input/output controller 1040, a display 1050, an input device 1060, and a communication processor 1090. Here, a plurality of memories 1010 may be included.

The memory 1010 may include a program storage device 1011 storing a program for controlling the operation of the electronic apparatus 1000 and a data storage device 1012 storing data generated during program execution. The data storage 1012 may store data for the operation of the application 1013 and the frequency conversion program and data type conversion program 1014. The program storage device 1011 may store an application program 1013 and a frequency conversion program and data type conversion program 1014. Here, the program stored in the program storage device 1011 may be a set of program codes or instructions, and may be represented as an instruction set.

The applications 1013 may include applications operable in the electronic device 1000. In other words, the application 1013 may include application instructions that are executed by the processor 1022. According to the inventive concept, the frequency conversion procedure and the data type conversion procedure 1014 can control the RF signal RF _IN Digital down conversion/digital up conversion operations of (c), and changes in sampling rate in ADC operation. In other words, the frequency conversion program and the data type conversion program 1014 may include instructions that underlie the modem (or baseband processor) of the communication processor 1090 to generate a digital reference signal and provide the generated digital reference signal to the receive circuitry of the communication processor 1090. The frequency conversion program and data type conversion program 1014 may include instructions that serve as a basis for a modem of the communication processor 1090 to provide information for controlling the sampling rate at which an ADC of the receiving circuit performs ADC operations. Operations consistent with the above embodiments may be performed when the modem performs the frequency conversion procedure and the data type conversion procedure 1014.

Peripheral interface 1023 may control the connection of input/output peripheral devices of the base station to processor 1022 and memory interface 1021. Processor 1022 may control the base station to provide applicable services using at least one software program. At this time, the processor 1022 may execute at least one program stored in the memory 1010 to provide a service corresponding to the applicable program.

The input/output controller 1040 may provide an interface between input/output devices, such as a display 1050 and an input device 1060, and the peripheral interface 1023. The display 1050 may display status information, input characters, moving pictures, still pictures, and the like. For example, display 1050 may display information about applications executed by processor 1022.

Input device 1060 may provide input data generated by selection of electronic device 1000 to processor unit 1020 via input/output controller 1040. At this time, the input device 1060 may include a keyboard including at least one hardware key and a touch pad for sensing touch information. For example, input device 1060 may provide touch information (such as touches, touch movements, and touch releases that have been sensed by a touchpad) to processor 1022 via input/output controller 1040.

The electronic device 1000 may include a communication processor 1090 that performs communication functions for voice communications and data communications. The communication processor 1090 may include a shared PLL circuit 1092 shared by multiple receiving circuits (or multiple transmitting circuits, or multiple transceiving circuits) described with reference to fig. 5, etc. The shared PLL circuit 1092 may commonly supply a frequency signal of a specific frequency to a plurality of receiving circuits (or a plurality of transmitting circuits, or a plurality of transceiving circuits).

While the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present inventive concept as defined by the following claims. Therefore, the true scope of the inventive concept should be determined by the technical concept of the appended claims.

Claims

1. A radio frequency integrated circuit configured to support carrier aggregation, the radio frequency integrated circuit comprising:

a plurality of first receiving circuits configured to receive radio frequency signals;

a first shared phase-locked loop circuit configured to provide a first frequency signal of a first frequency to the plurality of first receiving circuits,

Wherein at least one first receiving circuit of the plurality of first receiving circuits includes:

an analog-to-digital converter configured to convert a received radio frequency signal into a digital signal by using a first frequency signal;

a digital conversion circuit configured to generate a digital baseband signal by performing down-conversion on the digital signal,

wherein the analog-to-digital converter comprises a time interleaving control circuit and a plurality of analog-to-digital converter circuits, each configured to receive a first frequency signal,

wherein the time interleaving control circuit selectively uses a greater number of analog-to-digital converter circuits than the number of analog-to-digital converter circuits to be used at the threshold frequency to obtain the radio frequency signal sampling rate of the analog-to-digital converter when the analog-to-digital converter receives a first frequency signal having a frequency lower than the threshold frequency, and/or selectively uses a lesser number of analog-to-digital converter circuits than the number of analog-to-digital converter circuits to be used at the threshold frequency to obtain the radio frequency signal sampling rate of the analog-to-digital converter when the analog-to-digital converter receives a first frequency signal having a frequency higher than the threshold frequency,

wherein the analog-to-digital converter is a time-interleaved analog-to-digital converter.

2. The radio frequency integrated circuit of claim 1, wherein the first frequency is determined from a set of frequency bands corresponding to radio frequency signals received by the at least one of the plurality of first receiving circuits.

3. The radio frequency integrated circuit of claim 2, wherein a band group comprises a plurality of band groups corresponding to radio frequency signals, the first frequency being determined based on a highest band group among the plurality of band groups.

4. The radio frequency integrated circuit of claim 1, wherein the at least one of the plurality of first receive circuits further comprises: and a frequency divider configured to receive the first frequency signal, divide the first frequency signal and provide the divided first frequency signal to the analog-to-digital converter.

5. The radio frequency integrated circuit of claim 4, wherein the division ratio of the divider is determined from a set of frequency bands corresponding to the radio frequency signal.

6. The radio frequency integrated circuit of claim 1, wherein the radio frequency signal sampling rate of the analog-to-digital converter is determined from a set of frequency bands corresponding to the radio frequency signal.

7. The radio frequency integrated circuit of claim 6, wherein the analog-to-digital converter further comprises a splitter configured to provide the radio frequency signal to at least one analog-to-digital converter circuit of the plurality of analog-to-digital converter circuits at a constant time difference based on a band group corresponding to the radio frequency signal, the at least one analog-to-digital converter circuit performing a sampling operation based on the provided radio frequency signal.

8. The radio frequency integrated circuit of claim 1, wherein the at least one of the plurality of first receive circuits further comprises:

a first path configured to receive radio frequency signals corresponding to a first band group;

a second path configured to receive radio frequency signals corresponding to a second band group;

a multiplexer configured to selectively connect either one of the first path and the second path to the analog-to-digital converter.

9. The radio frequency integrated circuit of claim 1, wherein the digital conversion circuit comprises:

a digital mixer configured to receive the digital reference signal and down-convert the digital signal based on the digital reference signal;

a low pass filter configured to filter the down-converted digital signal;

a decimation filter configured to downsample the filtered digital signal and generate a digital baseband signal.

10. The radio frequency integrated circuit of claim 1, further comprising:

a plurality of second receiving circuits;

a second shared phase-locked loop circuit configured to provide a second frequency signal at a second frequency to the plurality of second receiving circuits.

11. The radio frequency integrated circuit of claim 10, wherein a first band group corresponding to radio frequency signals received by the plurality of first receiving circuits and a second band group corresponding to radio frequency signals received by the plurality of second receiving circuits are different from each other.

12. The radio frequency integrated circuit of claim 1, further comprising:

a plurality of second receiving circuits;

a frequency divider configured to receive the first frequency signal from the first shared phase-locked loop circuit, divide the first frequency signal, and provide the divided first frequency signal to the plurality of second receiving circuits.

13. The radio frequency integrated circuit of claim 1, further comprising:

a plurality of transmitting circuits;

a second shared phase-locked loop circuit configured to provide a second frequency signal of a second frequency to the plurality of transmit circuits,

wherein at least one of the plurality of transmitting circuits includes:

a digital conversion circuit configured to up-convert the received digital baseband signal and generate a digital output signal;

a digital-to-analog converter configured to convert the digital output signal into an analog signal by using the second frequency signal.

14. The radio frequency integrated circuit of claim 1, further comprising: a plurality of transmit circuits, wherein the first shared phase-locked loop circuit is configured to provide the first frequency signal to the plurality of transmit circuits.

15. A wireless communications apparatus configured to support carrier aggregation, the wireless communications apparatus comprising:

A radio frequency integrated circuit, comprising:

a plurality of receiving circuits configured to receive radio frequency signals;

a shared phase-locked loop circuit configured to supply a frequency signal of a specific frequency for analog-to-digital conversion to the plurality of receiving circuits;

a modem configured to provide a digital reference signal for down-conversion of the radio frequency signal to the radio frequency integrated circuit,

wherein at least one of the plurality of receiving circuits comprises:

an analog-to-digital converter configured to convert the received radio frequency signal into a digital signal based on the frequency signal,

wherein the analog-to-digital converter comprises a time interleaving control circuit and a plurality of analog-to-digital converter circuits, each configured to receive a frequency signal,

wherein the time interleaving control circuit selectively uses a greater number of analog-to-digital converter circuits than the number of analog-to-digital converter circuits to be used at the threshold frequency to obtain the radio frequency signal sampling rate of the analog-to-digital converter when the analog-to-digital converter receives a frequency signal having a frequency lower than the threshold frequency, and/or selectively uses a lesser number of analog-to-digital converter circuits than the number of analog-to-digital converter circuits to be used at the threshold frequency to obtain the radio frequency signal sampling rate of the analog-to-digital converter when the analog-to-digital converter receives a frequency signal having a frequency higher than the threshold frequency,

16. The wireless communication apparatus of claim 15, wherein at least one of the plurality of receive circuits further comprises:

and a digital conversion circuit configured to down-convert the digital signal based on the digital reference signal and generate a digital baseband signal.

17. The wireless communication device of claim 16, wherein the modem is configured to receive the digital baseband signal from the digital conversion circuit and process the digital baseband signal.

18. The wireless communication device of claim 16, wherein the modem is configured to provide band group information about a band group corresponding to the radio frequency signal to the analog-to-digital converter, the analog-to-digital converter configured to determine a sampling rate based on the band group information and to convert the radio frequency signal to the digital signal according to the sampling rate.

19. The wireless communications apparatus of claim 15, wherein:

the radio frequency integrated circuit further comprises: a frequency divider configured to receive the frequency signal from the shared phase-locked loop circuit, divide the frequency signal, and provide the divided frequency signal to the plurality of receiving circuits,

The modem is further configured to control a division ratio of the divider based on a highest band group among two or more band groups corresponding to the radio frequency signal.

20. The wireless communications apparatus of claim 15, wherein:

at least one of the plurality of receiving circuits includes: a frequency divider configured to receive the frequency signal, divide the frequency signal, and generate a divided frequency signal for analog-to-digital conversion,

the modem is further configured to control a division ratio of the divider based on a band group corresponding to the radio frequency signal.

21. The wireless communication apparatus of claim 15, wherein the radio frequency integrated circuit further comprises a plurality of transmit circuits that transmit radio frequency signals, the shared phase-locked loop circuit further configured to provide frequency signals for digital-to-analog conversion to the plurality of transmit circuits.

22. The wireless communication device of claim 21, wherein at least one of the plurality of transmit circuits comprises:

a digital conversion circuit configured to up-convert a digital baseband signal received from the modem and generate a digital output signal;

a digital-to-analog converter configured to convert a digital output signal into an analog signal by using a frequency signal.

23. A non-transitory computer-readable storage medium comprising commands, wherein when the commands are executed by a processor internal to a wireless communication device comprising a plurality of receive circuits sharing a phase-locked loop circuit, the processor is configured to: providing a digital reference signal for down-converting the radio frequency signal to the plurality of receiving circuits based on a channel corresponding to the radio frequency signal received by the plurality of receiving circuits, and providing a signal for adjusting a sampling rate at the time of analog-to-digital conversion performed by the plurality of receiving circuits based on a band group corresponding to the radio frequency signal to the plurality of receiving circuits,

wherein at least one of the plurality of receiving circuits comprises:

wherein the time interleaving control circuit selectively uses a greater number of analog-to-digital converter circuits than the number of analog-to-digital converter circuits to be used at the threshold frequency to obtain the sampling rate of the analog-to-digital converter when the analog-to-digital converter receives a frequency signal having a frequency lower than the threshold frequency, and/or selectively uses a lesser number of analog-to-digital converter circuits than the number of analog-to-digital converter circuits to be used at the threshold frequency to obtain the sampling rate of the analog-to-digital converter when the analog-to-digital converter receives a frequency signal having a frequency higher than the threshold frequency,