TWI789257B - Semiconductor device, protection circuit, and manufacturing method of semiconductor device - Google Patents

Abstract

Embodiments provide a semiconductor device with high dimensional control, a protection circuit, and a method of manufacturing the semiconductor device. A semiconductor device according to an embodiment includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a gate electrode, a first layer, and an insulating layer. The first semiconductor layer has a first conductivity type. The second semiconductor layer is disposed on the first semiconductor layer and has a second conductivity type. The third semiconductor layer is provided on the first semiconductor layer, arranged side by side with the second semiconductor layer in the first direction, and has the second conductivity type. The gate electrode is disposed on the first semiconductor layer and between the second semiconductor layer and the third semiconductor layer. The first layer has a lower impurity concentration than the second semiconductor layer, is provided on the first semiconductor layer, and has one end in contact with the second semiconductor layer. The insulating layer is provided on the first layer, and one end is in contact with the second semiconductor layer.

Description

Semiconductor device, protection circuit, and manufacturing method of semiconductor device

Embodiments of the present invention relate to a semiconductor device, a protection circuit, and a method for manufacturing the semiconductor device.

In the protection circuit for protecting electronic devices from damage caused by surges such as electrostatic discharge, transistors for switching to prevent surges from being input to electronic devices and protection resistors for protecting the transistors are sometimes installed. As a method of forming such a protective resistor, a method using a silicide block is known. However, if the previous method is adopted, there is a problem that it is difficult to control the size of the protection resistor.

The problem to be solved by the present invention is to provide a protection circuit with high dimensional control and a method of manufacturing the protection circuit.

A semiconductor device according to one embodiment of the present invention includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a gate electrode, a first layer, and an insulating layer. The first semiconductor layer has a first conductivity type. The second semiconductor layer is disposed on the first semiconductor layer and has a second conductivity type. The third semiconductor layer is provided on the first semiconductor layer, arranged side by side with the second semiconductor layer in the first direction, and has the second conductivity type. The gate electrode is disposed on the first semiconductor layer and between the second semiconductor layer and the third semiconductor layer. The first layer has a lower impurity concentration than the second semiconductor layer, is provided on the first semiconductor layer, and has one end in contact with the second semiconductor layer. The insulating layer is provided on the first layer, and one end is in contact with the second semiconductor layer.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, this invention is not limited by embodiment. In addition, the constituent elements of the embodiment include those that can be easily imagined by a person in the business or those that are substantially the same.

FIG. 1 is a diagram showing an example of the utilization form of the protection circuit 1 according to the embodiment. The protection circuit 1 of this embodiment is used to protect specific electronic devices (eg, processors, memories, etc.) from damage caused by surges such as electrostatic discharge (ESD: Electro-Static Discharge). In the configuration illustrated in FIG. 1 , a plurality of (four in this example) protection circuits 1 are connected in parallel between a wire 10 connected to an electronic device to be protected and through which an external current flows, and a ground electrode.

Each protection circuit 1 includes a transistor 11 and a protection resistor 12 . The transistor 11 is a switching element that operates according to the magnitude of the surge voltage or the surge current, and operates in a manner of conducting the surge current to the ground electrode when the surge current or the surge voltage exceeds a threshold value. The protection resistor 12 is a resistor connected between the wire 10 and the transistor 11, and has the effect of preventing the transistor 11 from being damaged by the surge current. Moreover, the protective resistors 12 are respectively provided for a plurality of protective circuits 1, and each protective resistor 12 exerts a buffering effect of attenuating the surge current, thereby preventing the surge current from concentrating on one protective circuit 1 (transistor 11).

FIG. 1 exemplifies the case where the transistor 11 is an N-channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor, Metal-Oxide-Semiconductor Field Effect Transistor), but the configuration of the transistor 11 is not limited thereto. When the transistor 11 is an N-channel MOSFET, the drain of the transistor 11 is connected to the protection resistor 12, the source is connected to the ground electrode, and the gate is input with a ground voltage. Hereinafter, the case where the transistor 11 is an N-channel MOSFET is taken as an example for description.

FIG. 2 is a plan view showing an example of the configuration of the protection circuit 1 according to the embodiment. FIG. 3 is a cross-sectional view of A-A in FIG. 2 of the protection circuit 1 of the embodiment. FIG. 4 is a sectional view taken along line B-B in FIG. 2 of the protection circuit 1 of the embodiment. In the figure, the X direction corresponds to the left-right direction of the paper (the arrangement direction of the transistor 11 and the protection resistor 12), the Y direction corresponds to the direction perpendicular to the paper (the width direction of the transistor 11 or the protection resistor 12), and the Z direction corresponds to In the direction perpendicular to the XY plane (stacking direction). The X direction is an example of the first direction, the Y direction is an example of the second direction, and the Z direction is an example of the third direction.

As shown in FIGS. 2 and 3 , the protection circuit 1 includes a transistor 11 , a protection resistor 12 , a first contact 21 , a second contact 22 , a first insulating portion 25 and a second insulating portion 26 . The first contact point 21 is connected to the lead wire 10, and the second contact point 22 is connected to the ground electrode.

The transistor 11 illustrated here is an N-channel MOSFET, as shown in FIG. One example), P-type semiconductor layer 55 (an example of a first semiconductor layer), N-type diffusion layer 56 (an example of a second semiconductor layer or a diffusion layer), and N-type diffusion layer 57 (an example of a third semiconductor layer).

The P-type semiconductor layer 55 is a region that becomes an inversion layer according to the voltage input to the gate electrode 31, and contains impurities such as B at a specific concentration. The N-type diffusion layer 56 in contact with the drain electrode 41 is in contact with the resistance layer 63 of the protection resistor 12 described below. The N-type diffusion layer 57 in contact with the source electrode 42 is connected to the ground electrode via the second contact 22 .

As shown in FIGS. 2 to 4 , the protection resistor 12 includes a trench portion 61 , an insulating layer 62 , a resistance layer 63 (an example of the first layer), a semiconductor layer 65 (an example of the fourth semiconductor layer), and a silicide layer 66 . The silicide layer 66 (an example of the second region) is in contact with the first contact 21 and the semiconductor layer 65 . The first contact 21 , the silicide layer 66 and the semiconductor layer 65 constitute an input portion 70 that conducts an external current flowing through the wire 10 ( FIG. 1 ) to the inside of the protection circuit 1 . Furthermore, the semiconductor layer 65 may be the same semiconductor layer as the N-type diffusion layer 57 , or may be a semiconductor layer different from the N-type diffusion layer 57 . Also, the semiconductor layer 65 may be a conductive layer having higher electrical conductivity than the N-type diffusion layer 57 .

The trench portion 61 is formed in the N-type diffusion layer 56 to separate the input portion 70 from the transistor 11 . That is, the trench portion 61 has a structure similar to a so-called STI (Shallow Trench Isolation). An insulating layer 62 and a resistive layer 63 are formed inside the trench portion 61 of the present embodiment. As shown in FIG. 4 , the groove portion 61 of this embodiment has an inverted trapezoidal cross-sectional shape along the YZ plane. That is, the width Wt of the opening of the groove portion 61 is greater than the width Wb of the bottom 71 of the groove portion 61 .

The insulating layer 62 is made of an insulating material, and can be made of, for example, SiO ₂ , SiN, etc. as a main component.

The resistance layer 63 is a region having a specific resistance value (electrical conductivity). The resistance value of the resistance layer 63 is set to a value capable of protecting the transistor 11 from the surge current input from the input unit 70 . The resistance value of the resistance layer 63 in this embodiment is higher than that of the N-type diffusion layer 56 and lower than that of the insulating layer 62 .

The resistance layer 63 and the N-type diffusion layer 56 of this embodiment contain impurities (such as B) contained in the P-type semiconductor layer 55 , and the impurity concentration of the resistance layer 63 is lower than that of the N-type diffusion layer 56 . Such an adjustment of the impurity concentration can be performed with relatively high precision using a known ion implantation method or the like. Furthermore, the impurities included in the resistance layer 63 are not limited to the above-mentioned ones, and may vary according to the configuration of the transistor 11 . For example, when the transistor 11 is a P-channel MOSFET, impurities such as As and P contained in the N-type semiconductor layer will be contained in the resistance layer and the diffusion layer.

In addition, the resistance layer 63 of this embodiment is formed on the bottom 71 of the groove portion 61 . By forming the resistance layer 63 in such a position, the manufacturability of the protection resistor 12 (protection circuit 1) improves, but the formation position of the resistance layer 63 is not limited to this. For example, the resistance layer 63 may also be formed on the side surface 72 of the trench portion 61 or the central portion of the insulating layer 62 .

By forming the protective resistor 12 with a structure similar to that of STI as described above, the dimensional controllability of the protective resistor 12 can be improved compared to the method using a silicide block, etc., which need to consider the penetration amount of liquid. In addition, by such improvement of dimensional controllability, design margins can be reduced. Furthermore, since the protection resistor 12 includes the resistance layer 63 having a lower impurity concentration than the N-type diffusion layer 56, the same resistance value as before can be realized with the protection resistor 12 having a smaller capacity (length in the X direction) than before. Thereby, the overall size of the protection circuit 1 can be reduced.

Hereinafter, a method of manufacturing the protection circuit 1 as described above will be described.

FIG. 5 is a cross-sectional view along B-B in FIG. 2 showing an example of a method of manufacturing the protection circuit 1 of the embodiment. FIG. 6 is a cross-sectional view taken along line C-C in FIG. 2 showing an example of a method of manufacturing the protection circuit 1 according to the embodiment. In FIGS. 5(A) to (E), changes in the YZ plane of the portion where the protective resistor 12 is formed are illustrated as the manufacturing method of the present embodiment proceeds. In FIGS. 6(A) to (E), changes in the XZ plane of the portion where the protective resistor 12 is formed are illustrated as the manufacturing method of the present embodiment proceeds.

First, as shown in FIG. 5(A) and FIG. 6(A), an amorphous silicon layer 101 is formed on the upper surface of the P-type semiconductor layer 55, and a specific portion on the amorphous silicon layer 101 (corresponding to the resistance layer 63 part) forming a resist (resist) 102, and then performing RIE (Reactive Ion Etching, reactive ion etching). Thereby, as shown in FIG. 5(B) and FIG. 6(B), a layer having a thickness corresponding to the thickness of the resist 102 shown in FIG. 5(A) and FIG. 6(B) remains on the P-type semiconductor layer 55. Amorphous silicon layer 101. The amorphous silicon layer 101 is, for example, a first mask layer.

Then, as shown in FIG. 5(B) and FIG. 6(B), a SiN layer 105 is formed on the P-type semiconductor layer 55 with the amorphous silicon layer 101 remaining, and a resist 103 is formed on the outer edge of the SiN layer 105, Then perform RIE. The SiN layer 105 is, for example, a second mask layer. At this time, the resist 102 shown in FIG. 5(B) is a part corresponding to the outer region of the groove portion 61 in the Y direction, and the resist 102 shown in FIG. The portion corresponding to the outer region (N-type diffusion layer 56 and semiconductor layer 65 ) in the X direction. Thereby, as shown in FIG. 5(C) and FIG. 6(C), a groove portion 61 having a depth corresponding to the thickness of the resist 102 shown in FIG. 5(B) and FIG. 6(B) is formed. At this time, from the nature of the RIE process, the greater the distance (depth) from the upper surface, the more difficult it is to etch, so the shape of the groove portion 61 naturally becomes an inverted trapezoid. Also, the P-type semiconductor layer 55 of the thickness of the amorphous silicon layer 101 shown in FIG. 5(B) and FIG. 6(B) has not been etched, so the P-type semiconductor layer 55 is formed at the bottom of the trench portion 61 upward. The protruding part 110 formed by swelling. The convex part 110 is a structure formed by the 1st part and the 2nd part located deeper than the 1st part so that the 1st part protrudes.

Next, as shown in FIG. 5(C) and FIG. 6(C), NSG (Non-doped Silicate Glass) or the like is filled inside the trench portion 61 to form an insulating layer 62 .

Then, as shown in FIG. 5(D) and FIG. 6(D), a resist 104 is formed on the outer edge of the insulating layer 62, and ion implantation is performed to ionize an ionized substance formed by ionizing impurities (such as B, etc.). (For example, BF ₃ gas etc.) is injected into the convex portion 110 . At this time, ion implantation is performed so that the impurity concentration of the convex portion 110 is lower than the impurity concentration of the N-type diffusion layer 56 .

Through the above processing, as shown in FIG. 5(E) and FIG. 6(E), a resistance layer 63 having an impurity concentration lower than that of the N-type diffusion layer 56 is formed at the bottom of the trench portion 61 .

After the insulating layer 62 and the resistive layer 63 are formed in the above manner, a semiconductor layer 65 and a silicide layer 66 are formed by using a suitable semiconductor manufacturing process, thereby forming the protective resistor 12 . Then, the transistor 11 is formed by using a suitable semiconductor manufacturing process. The transistor 11 can also be formed simultaneously with the semiconductor layer 65 and the silicide layer 66 .

As mentioned above, the manufacturing method of this embodiment includes the following steps: forming the groove portion 61 separating the input portion 70 from the transistor 11 in the N-type diffusion layer 56; forming the convex portion 110 at the bottom of the groove portion 61; And the resistive layer 63 is formed by implanting ions into the protruding portion 110 . Thereby, the dimension of the protection resistor 12 can be controlled with high precision, and the excess margin in design can be reduced. In addition, the protection resistor 12 can be formed to include a resistance layer 63 having a lower impurity concentration than the N-type diffusion layer 56, so that the same resistance value as before can be realized with the protection resistor 12 having a smaller capacity (length in the X direction) than before. . Thereby, the overall size of the protection circuit 1 can be reduced.

Several embodiments of the present invention have been described, but these embodiments have been presented as examples only, and are not intended to limit the scope of the invention. These novel embodiments can be implemented in other various forms, and various omissions, substitutions, or changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the inventions described in the claims and their equivalent scopes.

[Reference to related applications] This application enjoys the priority of the basic application based on Japanese Patent Application No. 2021-149536 (filing date: September 14, 2021) and Japanese Patent Application No. 2021-201871 (filing date: December 13, 2021). This application incorporates the entire content of the basic application by referring to this basic application.

1: Protection circuit 10: wire 11: Transistor 12: Protection resistor 21: The first contact 22: The second contact 25: The first insulation part 26: The second insulation part 31: Gate electrode 32: oxide insulating film 33,34: insulation part 41: Drain electrode 42: Source electrode 55: P-type semiconductor layer 56,57: N-type diffusion layer 61: groove part 62: Insulation layer 63: Resistance layer 65: Semiconductor layer 66: Silicide layer 70: input part 71: bottom 72: side face 101: Amorphous silicon layer 102: Anticorrosion 105: SiN layer 110: convex part

FIG. 1 is a diagram showing an example of a usage form of a protection circuit according to an embodiment. FIG. 2 is a plan view showing an example of the configuration of the protection circuit of the embodiment. Fig. 3 is a cross-sectional view along A-A in Fig. 2 of the protection circuit of the embodiment. Fig. 4 is a cross-sectional view along B-B in Fig. 2 of the protection circuit of the embodiment. 5(A) to (E) are sectional views taken along line B-B in FIG. 2 showing an example of the method of manufacturing the semiconductor device according to the embodiment. 6(A) to (E) are cross-sectional views taken along line C-C in FIG. 2 showing an example of the manufacturing method of the semiconductor device according to the embodiment.

1: Protection circuit

11: Transistor

12: Protection resistor

21: The first contact

22: The second contact

25: The first insulation part

26: The second insulation part

31: Gate electrode

32: oxide insulating film

33,34: insulation part

41: Drain electrode

42: Source electrode

55: P-type semiconductor layer

56,57: N-type diffusion layer

61: groove part

62: Insulation layer

63: Resistance layer

65: Semiconductor layer

66: Silicide layer

70: input part

Claims (10)

A semiconductor device comprising: a first semiconductor layer of the first conductivity type, which has a first impurity concentration; A second semiconductor layer of a second conductivity type different from the above-mentioned first conductivity type, which is provided on the above-mentioned first semiconductor layer and has a second impurity concentration; The third semiconductor layer of the second conductivity type, which is provided on the first semiconductor layer and arranged side by side with the second semiconductor layer in the first direction; a gate electrode provided between the second semiconductor layer and the third semiconductor layer, and above the first semiconductor layer via a gate insulating film; The first layer of the second conductivity type is provided on the first semiconductor layer, has an end in contact with the second semiconductor layer, and has a third impurity concentration lower than the second impurity concentration of the second semiconductor layer. impurity concentration; and The insulating layer is provided on the first layer and has an end in contact with the second semiconductor layer. The semiconductor device according to claim 1, wherein the gate electrode has a gate length extending in the first direction and a gate width extending in a second direction intersecting the first direction, and The width of the insulating layer in the second direction increases with distance from the side closer to the first layer in a third direction intersecting the first direction and the second direction. The semiconductor device according to claim 1, further comprising a fourth semiconductor layer, the fourth semiconductor layer being in contact with the other end of the first layer and in contact with the other end of the insulating layer. The semiconductor device according to claim 3, which further includes: a first region, which is provided on the above-mentioned third semiconductor layer; a first contact, which is in contact with the above-mentioned first area; a second region disposed on the above-mentioned fourth semiconductor layer; and The second contact is in contact with the second region. The semiconductor device according to claim 4, wherein the other end of the insulating layer is in contact with the second region. The semiconductor device according to claim 1, wherein the gate electrode has a gate length extending in the first direction and a gate width extending in a second direction intersecting the first direction, and The semiconductor device has a first surface including an interface between the first semiconductor layer and the gate insulating film, extending from the first layer to the first layer in a third direction intersecting the first direction and the second direction. The first distance of the surface is greater than the second distance from the interface to the gate electrode in the third direction. The semiconductor device according to claim 1, wherein the gate electrode has a gate length extending in the first direction and a gate width extending in a second direction intersecting the first direction, and The insulating layer has: a first part, which is in contact with the first layer; and a second part, whose position in a third direction intersecting the first direction and the second direction is different from that of the first layer; The width in the second direction of the first portion is smaller than the width in the second direction of the second portion. The semiconductor device according to claim 7, wherein the distance in the third direction from the first part to the first surface including the interface between the first semiconductor layer and the gate insulating layer is shorter than that from the second part to the first The distance in the above-mentioned third direction of the surface is large. A protection circuit comprising: a transistor having a source and a drain; and a protection resistor connected between the input part for external current input and the above-mentioned transistor; and The above protective resistors include: a trench portion formed between the input portion and the transistor; an insulating layer formed inside the trench portion; and The resistance layer is formed inside the trench portion and has a resistance value higher than that of the drain and lower than that of the insulating layer. A method of manufacturing a semiconductor device, which is forming a first mask layer on the first semiconductor layer; forming a first resist on a part of the first mask layer; etching a part of the first mask layer exposed from the first resist; forming a second mask layer on the first semiconductor layer and the first mask layer; Forming a second resist on a part of the above-mentioned second mask layer; Etching the second mask layer exposed from the second resist, and the first semiconductor layer and the first mask layer exposed from the second mask layer by etching the second mask layer, and further Etching the first semiconductor layer exposed from the first mask layer by etching the first mask layer, forming a first part and a second part deeper than the first part on the first semiconductor layer; Forming an insulating layer on the above-mentioned first part and the above-mentioned second part; forming a third resist on a portion of said insulating layer; and Ions are implanted into the first portion from the insulating layer exposed from the third resist to form a second semiconductor layer.

Images