KR20090013888A - Non-volatile memory device and method of manufacturing the same - Google Patents

Abstract

A non-volatile memory device and method of manufacturing the same is provided to overcome single channel effect by applying all memory cells to the depletion mode transistor and maintaining have source and drain of the memory cell with parasitic field. In a non-volatile memory device and method of manufacturing the same, the semiconductor substrate(100) is segmented by a cell region and peripheral area. A depletion channel region(104) is formed in the surface of the cell region. A selecting transistor(112) is formed on the peripheral area, and a dummy transistor(114) is adjacent to the selecting transistor on the cell region. A cell transistor(116) is positioned on the cell region between the dummy transistors. Each selecting transistor, dummy transistor and cell transistor are composed of successively laminated gate oxide pattern, floating gate layer pattern, dielectric layer pattern and control gate film pattern.

Description

NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME}

The present invention relates to a nonvolatile memory device and a method of manufacturing the same. More particularly, the present invention relates to a nonvolatile memory device capable of retaining data even when a power source is removed, and a method of manufacturing the same.

In general, a semiconductor device includes a fabrication (FAB) process for forming an electrical circuit on a silicon wafer used as a semiconductor substrate, a process for inspecting electrical characteristics of the semiconductor devices formed in the fab process, and the semiconductor devices, respectively. It is manufactured through a package assembly process for encapsulation and individualization with epoxy resin.

The fab process includes a deposition process for forming a film on a semiconductor substrate, a chemical mechanical polishing process for planarizing the film, a photolithography process for forming a photoresist pattern on the film, and an electrolysis of the film using the photoresist pattern. An etching process for forming a pattern having a characteristic characteristic, an ion implantation process for implanting specific ions into a predetermined region of the semiconductor substrate, a cleaning process for removing impurities on the semiconductor substrate, and a surface of the semiconductor substrate on which the film or pattern is formed It consists of unit processes such as inspection process for inspection.

The semiconductor device may be roughly divided into a nonvolatile memory device and a volatile memory device, and the nonvolatile memory device may be roughly divided into a NAND type nonvolatile memory device and a NOR type memory device.

In particular, in the NAND type nonvolatile memory device, the size of the cell gate is becoming smaller than the sub-nano to achieve high integration, and according to this trend, many problems related to the short channel effect have been generated.

In order to solve these problems, a structure for omitting a conventionally formed source / drain has been proposed, but there is a problem in that the cell current decreases.

1 is a graph illustrating a change in cell current between a nonvolatile memory device employing a source / drain and a nonvolatile memory device not forming a source / drain.

Referring to FIG. 1, it can be seen that a cell current is significantly reduced in a nonvolatile memory device that does not form a source / drain. That is, the source and drain of each memory cell are not sufficiently inverted only by the parasitic electric field by the voltage applied to the gate, so that the memory cell current decreases due to the increase in the area. Therefore, researches on new memory devices for solving the above problems are actively progressing.

It is a first object of the present invention to provide a nonvolatile memory device capable of reducing a short channel effect and suppressing a decrease in cell current.

It is a second object of the present invention to provide a method of manufacturing the memory device.

According to an embodiment of the present invention for achieving the above-described first object of the present invention, a nonvolatile memory device includes a semiconductor substrate, a depletion channel region, a selection transistor, a dummy transistor, and a cell transistor. The semiconductor substrate may be divided into a cell region and a peripheral region surrounding the cell region. The depletion region is formed on the surface of the cell region and doped with N-type impurities that provide electrons. The selection transistor includes a first gate oxide layer pattern, a first floating gate layer pattern, a first dielectric layer pattern, and a first control gate layer pattern formed on the peripheral area and sequentially stacked. The dummy transistor includes a second gate oxide layer pattern, a second floating gate layer pattern, a second dielectric layer pattern, and a second control gate layer pattern that are formed adjacent to the selection transistor and sequentially stacked on the cell region. The cell transistor includes a third gate oxide layer pattern, a third floating gate layer pattern, a third dielectric layer pattern, and a third control gate layer pattern that are disposed between the dummy transistors and sequentially stacked on the cell region.

The threshold voltage of the cell transistor may be relatively lower than the threshold voltage of the selection transistor. In addition, the N-type impurity may be phosphorus (P), arsenic (As), or antimony (Sb).

According to an embodiment of the present invention for achieving the second object, a method of manufacturing a nonvolatile memory device is provided. Specifically, a gate oxide film is formed on a semiconductor substrate partitioned into a cell region and a peripheral region surrounding the cell region. N-type impurities that provide electrons to the cell region are doped to form a depletion channel region on the surface of the cell region. Thereafter, a floating gate film, a dielectric film, and a control gate film are sequentially formed on the gate oxide film. Subsequently, the gate oxide layer, the floating gate layer, the dielectric layer, and the control gate layer are sequentially etched and formed on the peripheral area, and the first gate oxide layer pattern, the first floating gate layer pattern, the first dielectric layer pattern, and the first control layer are formed on the peripheral region. A select transistor in which a gate film pattern is sequentially stacked; a select transistor formed on the cell region adjacent to the select transistor, and a second gate oxide pattern, a second floating gate pattern, a second dielectric layer pattern, and a second control gate layer pattern are sequentially A dummy transistor stacked on the cell region and a cell transistor disposed between the dummy transistors and sequentially stacked with a third gate oxide layer pattern, a third floating gate layer pattern, a third dielectric layer pattern, and a third control gate layer pattern. do.

Here, the threshold voltage of the cell transistor may be lower than the threshold voltage of the selection transistor. The N-type impurity may be phosphorus (P), arsenic (As), or antimony (Sb).

According to the present invention, all memory cells are applied as depletion transistors to lower the threshold voltage of the cell, while at the same time, the source and drain of the cell are applied by the parasitic electric field of the gate to overcome the short channel effect. At the same time, the cell current can be increased.

Hereinafter, with reference to the accompanying drawings will be described in detail with respect to the substrate transport apparatus according to the preferred embodiments of the present invention, the present invention is not limited to the following embodiments, those of ordinary skill in the art If the present invention can be implemented in various other forms without departing from the spirit of the present invention. In the accompanying drawings, when components are referred to as "first," "second," "third," and / or "fourth," they are not intended to limit these components but merely to distinguish them. It is for. Thus, "first", "second", "third" and / or "fourth" may be used selectively or interchangeably with respect to the components, respectively. When the first component is referred to as being formed "on" of the second component, the first component may be formed between the first component and the second component as well as when the first component is directly formed on the second component. Three components may be interposed.

Hereinafter, a nonvolatile memory device and a method of manufacturing the same according to exemplary embodiments of the present invention will be described.

2 is a cross-sectional view illustrating a nonvolatile memory device in accordance with an embodiment of the present invention.

Referring to FIG. 2, a nonvolatile memory device includes a semiconductor substrate 100, a depletion channel region 104, a selection transistor 112, a dummy transistor 114, and a cell transistor 116.

The semiconductor substrate 100 may be a silicon wafer or a silicon-on-insulator (SOI) substrate. In addition, the semiconductor substrate 100 is divided into a channel region and a peripheral region surrounding the channel region.

The depletion channel region 104 may include N-type impurities that are formed on the surface of the cell region and provide electrons. For example, the N-type impurities may be phosphorus (P), arsenic (As), or antimony (Sb), which may be used alone or in combination.

The select transistor 112 is formed on the peripheral region and sequentially formed with the first gate oxide layer pattern 102a, the first floating gate layer pattern 106a, the first dielectric layer pattern 108a, and the first control gate layer pattern ( 110a).

The dummy transistor 114 is formed on the cell region adjacent to the selection transistor 112 and sequentially stacked on the second gate oxide layer pattern 102a, the second floating gate layer pattern 106a, and the second dielectric layer pattern 108a. ) And the second control gate film pattern 110b.

The number of cell transistors 116 is at least one. The cell transistor 116 is disposed between the dummy transistors 114 on the cell region and sequentially stacked on the third gate oxide layer pattern 102a, the third floating gate layer pattern 106a, and the third dielectric layer pattern 108a. And a third control gate film pattern 108a. Here, the threshold voltage of the cell transistor 116 may be relatively lower than the threshold voltage of the selection transistor 112.

Further, for convenience, the names of the first to third gate oxide layer patterns, the first to third floating gate layer patterns, the first to third dielectric layer patterns, and the first to third control gate layer patterns may be substantially different from each other. It is the same structure.

Hereinafter, a method of manufacturing the nonvolatile memory device illustrated in FIG. 2 will be described. FIGS. 3 to 5 are cross-sectional views illustrating a method of manufacturing the nonvolatile memory device illustrated in FIG. 1.

Referring to FIG. 3, a semiconductor substrate 100 divided into a cell region and a peripheral region is prepared. For example, the semiconductor substrate 100 may be a silicon wafer including single crystal silicon. As another example, the semiconductor substrate 100 may be a silicon-on-insulator (SOI) substrate.

Subsequently, a thermal oxidation process is performed to form the gate oxide layer 102 on the semiconductor substrate 100. In contrast, the gate oxide layer 102 may be formed on the semiconductor substrate 100 by performing a deposition process such as chemical vapor deposition (CVD).

Thereafter, N-type impurities such as phosphorus (P), arsenic (As), and antimony (Sb) are doped into the cell region. Therefore, a depletion channel region 104 is formed on the surface of the cell region. As shown in FIG. 2, the depletion channel region 104 is selectively formed only on the surface of the cell region.

In the above, the depletion channel region 104 is formed by ion implantation of N-type impurities, but according to another embodiment of the present invention, boron (B), gallium (Ga), and indium ( P-type impurities may be injected at a concentration relatively lower than that of P-impurities such as In).

That is, when a P-type impurity of a first concentration is implanted to form a source / drain in a nonvolatile memory device employing a source / drain, in the present invention, the P-type impurity is lower than the first concentration. By injecting the same effect can be obtained.

Here, the gate oxide layer 102 may be damaged in the ion implantation process. Therefore, after the gate oxide film 102 is removed, the gate oxide film 102 may be newly formed through a new thermal oxidation process or a deposition process.

Referring to FIG. 4, the floating gate layer 102, the dielectric layer 108, and the control gate layer 110 may be deposited on the gate oxide layer 102 by a chemical vapor deposition, a physical vapor deposition process, or an atomic layer deposition process. Form sequentially through.

The floating gate layer 102 and the control gate layer 110 may be formed using a conductive material such as doped polysilicon, a metal, or an alloy. The dielectric layer 108 may be a single layer or a composite layer.

When the dielectric film 108 has a single film structure, the dielectric film 108 may be formed using an insulating material such as silicon oxide or silicon nitride. In contrast, when the dielectric film 108 has a composite film structure, the dielectric film 108 may have an oxide-nitride-oxide (ONO) structure of a silicon oxide film-silicon nitride film-silicon oxide film sequentially stacked.

Referring to FIG. 5, after forming a mask layer (not shown) on the control gate layer 110, the control gate layer 110, the dielectric layer 108, and the floating gate layer 106 are formed using the mask layer as an etching mask. And the gate oxide film 102 are sequentially etched. Thereafter, the mask film is removed.

By the etching process, the control gate layer 110, the dielectric layer 108, the floating gate layer 106, and the gate oxide layer 102 may be formed in the control gate layer pattern 110a, the dielectric layer pattern 108a, and the floating gate layer pattern, respectively. 106a) and the gate oxide film pattern 102, the select transistor 112, the dummy transistor 114, and the cell transistor 116 are formed. More specifically, the first gate oxide layer pattern 102a, the first floating gate layer pattern 106a, the first dielectric layer pattern 108a, and the first control gate layer pattern 110a are sequentially disposed on the peripheral region of the semiconductor substrate 100. Stacked select transistors 112 are formed.

The second gate oxide pattern 102a, the second floating gate layer pattern 106a, the second dielectric layer pattern 108a, and the second control gate layer pattern 110a are sequentially stacked on the cell region of the semiconductor substrate 100. The transistor transistor 114, the third gate oxide layer pattern 102a, the third floating gate layer pattern 106a, the third dielectric layer pattern 108a, and the third control gate layer pattern 110a are sequentially stacked. 116 is formed. Here, the threshold voltage of the cell transistor 116 may be relatively lower than the threshold voltage of the selection transistor 112.

The dummy transistor 114 is positioned on the outermost part of the cell region so as to be adjacent to the selection transistor 112 of the cell region. In addition, the number of cell transistors 116 is at least one, and is positioned to be spaced apart from each other between the dummy transistors 114.

Further, for convenience, the names of the first to third gate oxide layer patterns, the first to third floating gate layer patterns, the first to third dielectric layer patterns, and the first to third control gate layer patterns may be substantially different from each other. It is the same structure.

As described above, the source and drain regions are inverted with a voltage applied to the gate without forming a source / drain between the cell transistors 116 formed in the conventional nonvolatile memory device to reduce the short channel effect. A structure that can be presented.

However, the above structure is limited in reducing the length of the selection transistor 114 and the distance between the nearest cell transistor 116. In the conventional memory cell structure, if the distance between the select transistor 114 and the adjacent cell transistor 116 is reduced, the select transistor 114 is capped by a program voltage applied to the gate of the cell during the program inhibit operation. The leakage caused by capacitive coupling lowers the boosting voltage in the channel of the memory cell, causing program disturb. Therefore, the present invention adopts a structure in which the dummy transistor 114 is placed between the selection transistor 114 and the closest cell transistor 116 so that the voltage applied to the dummy transistor 114 is shielded during the program inhibit operation. Therefore, the above problem can be solved.

According to the present invention, all memory cells are applied as depletion transistors to lower the threshold voltage of the cell, while at the same time, the source and drain of the cell are applied by the parasitic electric field of the gate to overcome the short channel effect. At the same time, the cell current can be increased.

Although described with reference to the preferred embodiment of the present invention as described above, those of ordinary skill in the art will be various within the scope of the present invention without departing from the spirit and scope of the present invention described in the claims It will be understood that modifications and changes can be made.

1 is a graph illustrating a change in cell current between a nonvolatile memory device employing a source / drain and a nonvolatile memory device not forming a source / drain.

2 is a cross-sectional view illustrating a nonvolatile memory device in accordance with an embodiment of the present invention.

3 to 5 are cross-sectional views illustrating a method of manufacturing the nonvolatile memory device shown in FIG. 2.

<Description of the symbols for the main parts of the drawings>

100 semiconductor substrate 102 gate oxide film

102a: gate oxide film pattern 104: depletion channel region

106: floating gate film 106a: floating gate film pattern

108: dielectric film 108a: dielectric film pattern

110: control gate film 110a: control gate film pattern

112: select transistor 114: dummy transistor

116: cell transistor

Claims (6)

A semiconductor substrate partitioned into a cell region and a peripheral region surrounding the cell region; A depletion channel region formed on the surface of the cell region and doped with N-type impurities to provide electrons; A selection transistor formed on the peripheral area and sequentially stacked with a first gate oxide layer pattern, a first floating gate layer pattern, a first dielectric layer pattern, and a first control gate layer pattern; A dummy transistor on the cell region adjacent to the selection transistor and sequentially stacked with a second gate oxide layer pattern, a second floating gate layer pattern, a second dielectric layer pattern, and a second control gate layer pattern; And And a cell transistor disposed between the dummy transistors on the cell region and sequentially stacked with a third gate oxide pattern, a third floating gate pattern, a third dielectric layer pattern, and a third control gate layer pattern. Volatile memory device. The nonvolatile memory device of claim 1, wherein the threshold voltage of the cell transistor is lower than the threshold voltage of the selection transistor. The nonvolatile memory device of claim 1, wherein the N-type impurity is phosphorus (P), arsenic (As), or antimony (Sb). Forming a gate oxide film on a semiconductor substrate partitioned into a cell region and a peripheral region surrounding the cell region; Doping N-type impurities providing electrons to the cell region to form a depletion channel region on the surface of the cell region; Sequentially forming a floating gate layer, a dielectric layer, and a control gate layer on the gate oxide layer; The gate oxide layer, the floating gate layer, the dielectric layer, and the control gate layer are sequentially etched and formed on the peripheral area, and the first gate oxide layer pattern, the first floating gate layer pattern, the first dielectric layer pattern, and the first control gate layer are formed. A selection transistor in which a pattern is sequentially stacked, and formed adjacent to the selection transistor on the cell region, and a second gate oxide pattern, a second floating gate pattern, a second dielectric layer pattern, and a second control gate layer pattern are sequentially stacked Forming a cell transistor on the dummy transistor and the cell region, the cell transistor having a third gate oxide layer pattern, a third floating gate layer pattern, a third dielectric layer pattern, and a third control gate layer pattern sequentially stacked between the dummy transistors Nonvolatile memory device comprising a. The nonvolatile memory device of claim 4, wherein the threshold voltage of the cell transistor is lower than the threshold voltage of the selection transistor. The nonvolatile memory device of claim 4, wherein the N-type impurity is phosphorus (P), arsenic (As), or antimony (Sb).

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