TWI788162B - Display driving circuit and display driving method - Google Patents

Abstract

The present disclosure provides a display driving circuit and a display driving method. The display driving circuit includes a first memory, a selection control unit, and an output buffer. The display driving circuit is configured to process image data by rotating or mirroring. In the display driving method, the image data to be processed is sent to the first memory. Use the selection control unit to rotate or mirror the image data and send the processed image data to the output buffer. The output buffer sends the processed image data to the display panel for display.

Description

Display driving circuit and display driving method

This disclosed document relates to a display driving circuit and a display driving method, in particular to a display driving circuit and a display driving method applied to real-time random image rotation.

The image processing of the display panel includes two parts, namely an application processor (application processor, AP) and a display driver IC (DDIC). In order to provide rotated or mirrored images, in the past, the display frame will first be mapped between two random access memories (random access memory, RAM) in the application processor, and the mapped display The frame is sent to the random access memory of the display panel driver IC for processing and display. In this method, since the data needs to be repeatedly read and written between more than three random access memories, it will not only increase the power consumption and increase the delay time, but also increase the process cost, and the partial rotation, The function of the mirror cannot be realized in this way.

The disclosed document provides a display driving circuit, including a first memory, an output buffer, and a selection control unit. The first memory is coupled to the application processor, and is used for receiving the display frame from the application processor and storing the display frame in the first memory. The output buffer is used for coupling the display panel and controlling multiple data lines on the display panel. The selection control unit is coupled between the first memory and the output buffer, and the control unit is used to: in the first selection mode, read a plurality of first memory units in the first axial direction of the first memory The first data voltage is written into the output buffer; in the second selection mode, a plurality of second data voltages in the plurality of second memory cells located in the second axial direction of the first memory are read, and written into the output buffer , the second axis is different from the first axis. The output buffer drives a plurality of data lines of the display panel according to a plurality of first data voltages or a plurality of second data voltages.

This disclosure document provides a display driving method, including the following operations: receiving a display frame from an application processor and storing it in a first memory; Determine the current display mode to control the output buffer, including: When the current display mode is the first selection mode, read a plurality of first data voltages in a plurality of first memory cells located in the first axial direction of the first memory, and write them into an output buffer; When the current display mode is the second selection mode, read the plurality of second data voltages in the plurality of second memory cells located in the first memory on the second axis, and write them into the output buffer, and the second axis is different in the first axis; and The plurality of data lines of the display panel are driven according to the plurality of first data voltages or the plurality of second data voltages in the output buffer.

The following disclosure provides many different embodiments, or examples, for implementing different features of the presented subject matter. Specific examples of components and arrangements are described below to simplify the present case. Of course, these are examples only and are not intended to be limiting. For example, in the following description, the first feature is formed on the second feature or on the second feature may include the embodiment that the first feature and the second feature are formed in direct contact, and may also include the embodiment that the first feature may be formed on the first feature. An embodiment where an additional feature is formed with a second feature such that the first feature and the second feature may not be in direct contact. In addition, in this case, element symbols and/or letters may be repeated in each example. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or configurations discussed.

In addition, for ease of description, spatially relative terms (such as "under", "below", "lower", "above", "upper" and the like may be used herein to describe an element or an element illustrated in the figures. The relationship of a feature to another element (or elements) or feature (or features). Spatially relative terms are intended to encompass different orientations of elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and thus the spatially relative descriptors used herein may be interpreted similarly.

FIG. 1 is a structural diagram of a display device 100 according to some embodiments. The display device 100 includes an application processor 120 , a display driving circuit 140 , a transmission interface 160 , a display panel 180 and a scan driving circuit 190 . The display driving circuit 140 is connected to the application processor 120 through the transmission interface 160 to receive the display frame Pix to be processed, and display the processed display frame Pix on the display panel 180 . In some embodiments, the transmission interface 160 may be implemented using a mobile industry processor interface (MIPI).

The scanning driving circuit 190 is used to control the scanning switching sequence of the pixel transistors of each pixel in the display panel 180 . Generally, the scanning method of the display panel is well known to those skilled in the art, so it will not be repeated here.

As shown in Figure 1, the display panel 180 is illustrated by a display matrix composed of 4*4 pixel units, but this disclosure document is not limited to 4*4 pixel units, and it can also be 1024 pixels in practical applications. *768, 720*480, 1600*900 or other number of pixel units. In some embodiments, the display panel 180 has four data lines D1-D4 parallel to each other, four scan lines S1-S4 parallel to each other and perpendicular to the data lines, and pixels corresponding to intersections of the four data lines and the four scan lines. Units P1~P16. The data lines D1-D4 are coupled to the display driving circuit 140, and the display driving circuit 140 is used to provide the data voltage corresponding to the display frame and transmit it to the corresponding pixel units P1-P16 through the data lines D1-D4.

It should be noted that the numbers of data lines and scan lines in FIG. 1 are examples. Other numbers of data lines and scan lines are within the scope of this disclosure.

Generally speaking, the display content of the display image frame distinguishes up and down directions. For example, when the display content has a face, the direction above the head usually corresponds to the top of the display device 100 .

In some applications, the user may rotate the orientation of the display device 100. For example, when the display device 100 is a rotatable liquid crystal display panel, a smart phone, or a wearable smart watch, the display device 100 does not necessarily The upper part of the screen will be displayed in a fixed direction. It is possible to rotate different sides of the display device 100 above the line of sight following the user's operation.

In some embodiments, the display panel 180 may be a plasma display panel (plasma display panel), a liquid crystal display panel (liquid crystal display panel, LCD), a light emitting diode display panel (LED display panel) or other display images. Functional device.

FIG. 2 is a block diagram of the application processor 120 according to some embodiments. The application processor 120 includes a second memory 122. The second memory 122 is composed of a plurality of memory cells CE for storing the data voltage Pix_V corresponding to the display frame Pix. The memory cells CE are arranged in multiple rows and multiple columns. . In some embodiments, the data voltage Pix_V of the memory cell CE of the second memory 122 can be copied to the display driving circuit 140 through the transmission interface 160 .

Under normal circumstances, the application processor 120 is used to generate display frame Pix content to be displayed, such as still pictures, photos, dynamic pictures, and the like. If the user adjusts the placement direction of the display device 100, in order to match the user's line of sight, in some traditional methods, a plurality of additional memories provided inside the application processor 120 are used to divide the memory between different memories. The display image frame Pix is firstly rotated before being transmitted to the display driving circuit 140. In this case, all display image frames Pix need to be transmitted multiple times in multiple memories inside the application processor 120, except for the need to use In addition to the large number of devices, it also leads to problems such as high device cost, long processing time, and high power consumption.

FIG. 3 is a structural diagram of the display driving circuit 140 and its peripheral devices according to some embodiments. The display driving circuit 140 includes a first memory 142 , a selection control unit 144 and an output buffer 146 . In some embodiments, both the first memory 142 and the second memory 122 in FIG. 2 are random access memory (RAM).

The first memory 142 is composed of a plurality of memory cells CE for storing the data voltage Pix_V corresponding to the display frame Pix. The memory cells CE are arranged in a plurality of rows and a plurality of columns. The first memory 142 receives the data voltage Pix_V from the second memory 122 through the transmission interface 160 .

In one embodiment, the selection control unit 144 can adopt different selection modes to read the data voltage Pix_V of the memory cell CE in the first memory 142, and transmit it to the output buffer 146, and the output buffer then receives the received The data voltage Pix_V is transmitted to the data line 182 for image presentation. These different selection modes can respectively enable the display image frame Pix to realize image processing such as direct output, rotation, flipping, and mirroring during the reading process. Through this method, multiple transmissions of the display frame Pix within the application processor 120 can be avoided, so as to save device cost and reduce processing time.

Please also refer to FIG. 4A , which shows a schematic diagram of the selection control unit 144 reading the first memory 142 according to the first axis AX1 and transmitting to the output buffer 146 in the first selection mode according to some embodiments.

In some embodiments, the plurality of memory cells CE of the first memory 142 are arranged in a 4*4 array, including memory cells CE1, CE2, . . . , CE16, each of which has a corresponding data voltage Pix_V. In the first selection mode, the selection control unit 144 uses the first axis AX1 to select from the first row of memory cells CE, and sequentially transmits the data voltage Pix_V of the row of memory cells CE to the output buffer 146 (for example, in the form of The order of CE1, CE2, CE3, CE4), in the embodiment shown in Figure 4A, the first axis AX1 can be, for example, a horizontal axis and read from left to right, that is In other words, the selection control unit 144 reads the memory cells CE1-CE4 on the same horizontal column of the first memory 142, and sends them to the output buffer 146. For example, the output buffer 146 can be a linear buffer for temporarily storing The data voltage Pix_V read from the cells CE1~CE4 is used to write the data voltage Pix_V read from the memory cells CE1~CE4 into the first memory cell through the data lines D1~D4 during a data update cycle of the display panel 180. The output buffer 146 of the pixel units P1 - P4 in the row transmits the received data voltage Pix_V to the data line 182 of the display panel 180 for image presentation.

Afterwards, the selection control unit 144 selects the memory cells CE5-CE8 of the second row from the second memory 122, and the output buffer 146 is used to write the data voltage Pix_V read from the memory cells CE5-CE8 into the memory cells through the data lines D1-D4. Pixel units P5~P8 in the second column, and so on.

In the embodiment shown in FIG. 4A, in the first selection mode, since the selection control unit 144 reads the first memory 142 according to the first axis AX1 and transmits it to the output buffer 146, the content of the original display frame Pix will be According to the original pattern direction, it is sent to the display panel 180 . Therefore, the picture displayed by the display panel 180 is substantially the same as the content of the display frame Pix originally generated by the application processor 120 to be displayed.

Please also refer to FIG. 4B , which shows a schematic diagram of the selection control unit 144 reading the first memory 142 according to the second axis AX2a and transmitting to the output buffer 146 in the second selection mode according to some embodiments.

In some embodiments, the plurality of memory cells CE of the first memory 142 are arranged in a 4*4 array, including memory cells CE1, CE2, . . . , CE16, each of which has a corresponding data voltage Pix_V. In the second selection mode, the selection control unit 144 uses the second axis AX2a to select from the first row of memory cells CE, and sequentially transmits the data voltage Pix_V of this row of memory cells CE to the output buffer 146 (for example, in the form of The order of CE13, CE9, CE5, CE1), in the embodiment shown in Figure 4B, the second axis AX2a can be, for example, a vertical axis and read from bottom to top, that is to say The selection control unit 144 reads the memory cells CE13, CE9, CE5, and CE1 on the same vertical row of the first memory 142, and sends them to the output buffer 146. For example, the output buffer 146 can be a linear buffer for temporarily Store the data voltage Pix_V read from the memory cells CE13, CE9, CE5, and CE1. During a data update cycle of the display panel 180, the output buffer 146 is used to transfer the data voltage Pix_V read from the memory cells CE13, CE9, CE5, and CE1. The data lines D1 - D4 are written into the pixels P1 - P4 in the first row, and the output buffer 146 transmits the received data voltage Pix_V to the data line 182 of the display panel 180 for displaying images.

Afterwards, the selection control unit 144 selects the memory cells CE14, CE10, CE6, and CE2 in the second row from the second memory 122, and the output buffer 146 is used to pass the data voltage Pix_V read from the memory cells CE14, CE10, CE6, and CE2 through The data lines D1-D4 are written into the pixels P5-P8 in the second row, and so on.

As mentioned above, the second selection mode in the embodiment of FIG. 4B can be used to realize the application of rotating the display frame Pix by 90 degrees. In this embodiment, there is no need to pre-rotate or pre-process the display image frame Pix in the application processor 120, which can reduce the resources of the application processor 120 for setting the graphics rotation circuit and additional memory, and because there is no need for the application processor 120 to Pre-rotation or pre-processing can improve the efficiency of display frame Pix when rotating. In the embodiment shown in FIG. 4B, in the second selection mode, since the selection control unit 144 reads the first memory 142 according to the second axis AX2a and transmits it to the output buffer 146, the content of the original display frame Pix will be is rotated 90 degrees. Therefore, the display panel 180 can present a state in which the display frame Pix is rotated by 90 degrees.

It should be noted that the second selection mode is not limited to the embodiment shown in FIG. 4B , and can also be used to realize mirror flip in other applications. Please also refer to FIG. 4C , which shows a schematic diagram of the selection control unit 144 using another second selection mode to read the first memory 142 and transmit it to the output buffer 146 according to some other embodiments.

In some embodiments, the plurality of memory cells CE of the first memory 142 are arranged in a 4*4 array, including memory cells CE1, CE2, . . . , CE16, each of which has a corresponding data voltage Pix_V. In another second selection mode, the selection control unit 144 uses the second axis AX2b to select from the first row of memory cells CE, and sequentially transmits the data voltage Pix_V of this row of memory cells CE to the output buffer 146 (for example , in the order of CE4, CE3, CE2, CE1), in the embodiment shown in FIG. 4C, the second axis AX2b can be, for example, a horizontal axis and read from right to left, That is to say, the selection control unit 144 reads the memory cells CE4-CE1 on the same horizontal column of the first memory 142, and sends them to the output buffer 146. For example, the output buffer 146 can be a linear buffer for temporary storage. The data voltage Pix_V read from the memory cells CE4~CE1 is used to write the data voltage Pix_V of the memory cells CE4~CE1 through the data lines D1~D4 into the output buffer 146 during a data update cycle of the display panel 180. For the pixels P1 - P4 in the first column, the output buffer 146 transmits the received data voltage Pix_V to the data line 182 of the display panel 180 for image presentation.

Afterwards, the selection control unit 144 selects the memory cells CE8-CE5 of the second row from the second memory 122, and the output buffer 146 is used to write the data voltage Pix_V read from the memory cells CE5-CE8 into the memory cells through the data lines D1-D4. Pixels P5~P8 in the second column, and so on.

As mentioned above, the second selection mode in the embodiment in FIG. 4C can be used to realize the application of flipping the left and right mirror images of the displayed image frame Pix. In this embodiment, there is no need to pre-flip or pre-process the display image frame Pix in the application processor 120, which can reduce the resources of the application processor 120 to set the graphics flip circuit and additional memory, and also because there is no need for the application processor 120 to Pre-flipping or pre-processing can improve the efficiency of the display frame Pix when flipping left and right. In the embodiment shown in FIG. 4C, in the second selection mode, since the selection control unit 144 reads the first memory 142 according to the second axis AX2b and transmits it to the output buffer 146, the content of the original display frame Pix will be Mirrored left and right. Therefore, the display panel 180 can present a state in which the display frame Pix is flipped left and right.

It should be noted that the second selection mode is not limited to the embodiments shown in FIG. 4B and FIG. 4C. Please also refer to FIG. 4D, which shows another selection mode adopted by the selection control unit 144 in other embodiments. A schematic diagram of reading the first memory 142 and sending it to the output buffer 146 in a second selection mode.

In some embodiments, the plurality of memory cells CE of the first memory 142 are arranged in a 4*4 array, including memory cells CE1, CE2, . . . , CE16, each of which has a corresponding data voltage Pix_V. In yet another second selection mode, the selection control unit 144 uses the second axis AX2c to select from the first row of memory cells CE, and sequentially transmits the data voltage Pix_V of this row of memory cells CE to the output buffer 146 ( For example, in the order of CE1, CE5, CE9, CE13), in the embodiment shown in Figure 4D, the second axis AX2c can be, for example, a vertical axis and read from top to bottom That is to say, the selection control unit 144 reads the memory cells CE1, CE5, CE9, and CE13 on the same vertical row of the first memory 142, and transmits them to the output buffer 146. For example, the output buffer 146 can be a linear buffer , used to temporarily store the data voltage Pix_V read from the memory cells CE1, CE5, CE9, and CE13. In a data update cycle of the display panel 180, the output buffer 146 is used to transfer the data voltage Pix_V read from the memory cells CE1, CE5, CE9, and CE13. The data voltage Pix_V is written into the pixels P1 - P4 of the first column through the data lines D1 - D4 , and the output buffer 146 transmits the received data voltage Pix_V to the data line 182 of the display panel 180 for displaying images.

Afterwards, the selection control unit 144 selects the memory cells CE2, CE6, CE10, and CE14 in the second row from the second memory 122, and the output buffer 146 is used to pass the data voltage Pix_V read from the memory cells CE2, CE6, CE10, and CE14 through The data lines D1-D4 are written into the pixels P5-P8 in the second row, and so on.

As mentioned above, the second selection mode in the embodiment of FIG. 4D can be used to realize the application of rotating the displayed image frame Pix by 90 degrees and flipping it left and right. In this embodiment, there is no need to pre-rotate/flip or pre-process the display frame Pix in the application processor 120, which can reduce the resources of the application processor 120 to set the graphics rotation/flip circuit and additional memory, and because there is no need to The application processor 120 pre-rotates/flips or pre-processes, which can improve the efficiency when the display frame Pix is rotated and flipped. In the embodiment shown in FIG. 4D, in the second selection mode, since the selection control unit 144 reads the first memory 142 according to the second axis AX2c and transmits it to the output buffer 146, the content of the original display frame Pix will be is rotated 90 degrees and mirrored left and right. Therefore, the display panel 180 may present a state in which the display frame Pix is rotated by 90 degrees and mirrored left and right.

Please also refer to FIG. 4E , which shows a schematic diagram of the selection control unit 144 using the third selection mode to read the first memory 142 and transmit it to the output buffer 146 according to some embodiments.

In some embodiments, the plurality of memory cells CE of the first memory 142 are arranged in a 4*4 array, including memory cells CE1, CE2, . . . , CE16, each of which has a corresponding data voltage Pix_V. In the third selection mode, the selection control unit 144 uses the third axis AX3 to select from a specific memory cell CE, and sequentially transmits the data voltage Pix_V of the selected memory cell CE to the output buffer 146 (for example, with CE9 , CE6, CE3), in the embodiment shown in Figure 4E, the third axis AX3 can be, for example, an axis with an angle of 45 degrees and a reading sequence from bottom left to top right, that is to say The selection control unit 144 reads the memory cells CE9, CE6, and CE3 on the same slant of the first memory 142, and sends them to the output buffer 146. For example, the output buffer 146 can be a linear buffer for temporarily storing memory cells The data voltage Pix_V read by CE9, CE6, and CE3 is used to write the data voltage Pix_V read from the memory cells CE9, CE6, and CE3 through the data lines D1-D4 in the output buffer 146 during a data update cycle of the display panel 180. To the pixels P1 - P4 in the first column, the output buffer 146 transmits the received data voltage Pix_V to the data line 182 of the display panel 180 for image presentation.

Afterwards, the selection control unit 144 selects the memory cells CE14, CE11, and CE8 in the next oblique column from the second memory 122, and the output buffer 146 is used to pass the data voltage Pix_V read from the memory cells CE14, CE11, and CE8 through the data line D1. ~D4 is written to pixels P5~P8 in the second column, and so on.

As mentioned above, the third selection mode in the embodiment of FIG. 4E can be used to realize the application of rotating the display frame Pix by 45 degrees. In this embodiment, there is no need to pre-rotate or pre-process the display image frame Pix in the application processor 120, which can reduce the resources of the application processor 120 for setting the graphics rotation circuit and additional memory, and because there is no need for the application processor 120 to Pre-rotation or pre-processing can improve the efficiency of display frame Pix when rotating. In the embodiment shown in FIG. 4E, in the third selection mode, since the selection control unit 144 reads the first memory 142 according to the third axis AX3 and transmits it to the output buffer 146, the content of the original display frame Pix will be is rotated 45 degrees. Therefore, the display panel 180 may present a state in which the display frame Pix is rotated by 45 degrees. Furthermore, in the third selection mode, the display frame Pix can be rotated at any angle.

It should be noted that the total number of memory cells CE of the first memory 142 in FIGS. 4A˜4E , the number of rows/rows, and the data voltage are all examples. The total number of other memory cells CE, row/row number, and data voltage are all within the scope of this disclosure.

In some embodiments, when the display driving circuit allows switching between the first selection mode and the second selection mode, the display panel is driven at a first frame rate. When the display driving circuit is fixed in the first selection mode, the display panel is driven by a second frame update rate, wherein the second frame update rate is greater than the first frame update rate. Through this limitation, the update rate of the image frame can be increased when there is no need to operate on the displayed image frame Pix.

FIG. 5 illustrates a timing diagram 500 of the display driver circuit 140 according to some embodiments. From the time when the display frame Pix is updated to the time when the display frame Pix is transmitted to the output buffer 146 , the time in between is the cut-off time T _Blank . The time required to copy the display frame Pix of the second memory 122 to the first memory 142 is the transmission time T _AddrTransmit . The deadline T _Blank must be greater than or equal to the transmission time T _AddrTransmit . Through this restriction, image tearing (Tearing) caused when the deadline T _Blank is less than the transmission time T _AddrTransmit can be avoided.

FIG. 6 shows a flowchart of a display driving method 600 according to some embodiments. It should be noted that the display driving method 600 is provided by way of example only and does not limit the scope of this disclosure. Therefore, it should be understood that additional operations may be provided before, during and after the display driving method 600 of FIG. 6 , while some other operations may only be briefly described here. Display driving method 600 includes operations 602 , 604 and 606 .

In operation 602 , the display frame Pix stored in the second memory 122 is copied to the first memory 142 through the transmission interface 160 , and operation 604 is performed.

In operation 604 , according to the selected first selection mode, second selection mode or third selection mode, the data voltage Pix_V of the memory cell CE is selected and transmitted to the output buffer 146 , and operation 606 is performed.

In operation 606 , the output buffer 146 transmits the received data voltage Pix_V to the plurality of data lines 182 of the display panel 180 to display images.

Through the methods mentioned in this disclosure document, some image rotation or mirroring that cannot be provided by application processors can be supplemented. Since the operation is merged into the display panel driver IC, this process does not generate a rotation delay (rotation delay). In addition, through the adjustment of the cut-off time T _Blank , the frame update rate and rotation function can be switched according to the application requirements.

The foregoing outlines features of several embodiments so that those skilled in the art can better understand aspects of the present case. Those skilled in the art will appreciate that this disclosure can readily be used as a basis for designing or modifying other processes and structures in order to carry out the same purposes and/or achieve the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that various changes, substitutions and modifications can be made herein without departing from the spirit and scope of the disclosure.

100: display device 120: application processor 122: second memory 140: display drive circuit 142: first memory 144: selection control unit 146: output buffer 160: transmission interface 180: display panel 182: data line 190: scanning Driving circuit 500: timing diagram of display driving circuit 600: display driving method 602, 604, 606: operation AX1: first axis AX2a~AX2c: second axis AX3: third axis CE1~CE16: memory unit D1~ D4: data line Pix: display image frame Pix_V: data voltage P1~P16: pixel unit S1~S4: scanning line T _Blank : deadline T _AddrTransmit : transmission time

The aspects of the present case are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with the standard practice in the industry, features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 shows a structural diagram of a display device according to some embodiments; FIG. 2 illustrates a block diagram of an application processor according to some embodiments; FIG. 3 shows a structural diagram of a display driving circuit and its peripheral devices according to some embodiments; FIG. 4A shows a block diagram of a selection control unit processing a display frame in a first selection mode according to some embodiments; FIG. 4B shows a block diagram of a selection control unit processing a display frame in a second selection mode according to some embodiments; FIG. 4C shows a block diagram of a selection control unit processing a display frame in another second selection mode according to some embodiments; FIG. 4D shows a block diagram of a selection control unit processing a display frame in yet another second selection mode according to some embodiments; FIG. 4E shows a block diagram of a selection control unit processing a display frame in a third selection mode according to some embodiments; FIG. 5 illustrates a timing diagram of a display driver circuit processing a display frame according to some embodiments; and FIG. 6 is a flow chart of a display driving method according to some embodiments.

Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

140: Display drive circuit

142: The first memory

144:Select control unit

146: output buffer

180: display panel

182: data line

190: Scanning drive circuit

CE: memory cell

Pix_V: data voltage

Claims (10)

A display driving circuit, comprising: a first memory, coupled to an application processor, for receiving a display frame from the application processor, and storing the display frame in the first memory; an output buffer for coupling a display panel and controlling a plurality of data lines on the display panel; and a selection control unit, coupled between the first memory and the output buffer, the selection control unit is used for: In a first selection mode, read a plurality of first data voltages in a plurality of first memory cells located in a first axial direction of the first memory, and write into the output buffer; and In a second selection mode, read a plurality of second data voltages in a plurality of second memory cells located in a second axial direction of the first memory, and write into the output buffer, and the second axial direction corresponds to different from the first axis, Wherein the output buffer drives the plurality of data lines of the display panel according to the plurality of first data voltages or the plurality of second data voltages. The display driving circuit as described in Claim 1, wherein the application processor includes a second memory, the application processor is used to generate the display frame to be displayed, the display frame is stored in the second memory, the The display driving circuit copies the display frame from the second memory of the application processor to the first memory in the same row and column arrangement. The display driving circuit according to claim 1, wherein the first axis and the second axis are perpendicular to each other, or the first axis and the second axis are parallel to each other but in opposite directions. The display driving circuit as described in claim 3, wherein the selection control unit is further used for: In a third selection mode, read a plurality of third data voltages in a plurality of third memory units of the first memory located on a third axis, and write into the output buffer, wherein the third axis not parallel to and not perpendicular to the first axis and the second axis. The display driving circuit as described in Claim 1, wherein a deadline representing the time required for the display frame to be written to the output buffer from being updated; and a transfer time represents the time required for the display frame to be copied from the second memory to the first memory, Wherein the cut-off time is greater than or equal to the transmission time. The display driving circuit as described in Claim 1, wherein When the display driving circuit allows switching between the first selection mode and the second selection mode, driving the display panel with a first frame update rate; and When the display driving circuit is fixed in the first selection mode, a second frame update rate is used to drive the display panel, and the second frame update rate is greater than the first frame update rate. A display driving method, comprising: receiving a display frame from an application processor and storing it in a first memory; Determine a current display mode to control an output buffer, including: When the current display mode is a first selection mode, read a plurality of first data voltages in a plurality of first memory cells located in a first axial direction of the first memory, and write into the output buffer; When the current display mode is a second selection mode, read a plurality of second data voltages in a plurality of second memory units located in a second axial direction of the first memory, and write into the output buffer, the the second axis is different from the first axis; and Driving a plurality of data lines of a display panel according to the plurality of first data voltages or the plurality of second data voltages in the output buffer. The display driving method as described in claim 7, wherein the application processor includes a second memory, the application processor is used to generate the display frame to be displayed, the display frame is stored in the second memory, the The second memory of the application processor copies the display frame to the first memory in the same row and column arrangement. The display driving method according to claim 7, wherein the first axis and the second axis are perpendicular to each other, or the first axis and the second axis are parallel to each other but in opposite directions. The display driving method as described in Claim 9, further comprising: When the current display mode is a third selection mode, read a plurality of third data voltages in a plurality of third memory cells located in a third axial direction of the first memory, and write into the output buffer, wherein The third axis is neither parallel nor perpendicular to the first axis and the second axis.

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