CN114495792B - Display driving circuit and display driving method - Google Patents
Display driving circuit and display driving method Download PDFInfo
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- CN114495792B CN114495792B CN202210094500.0A CN202210094500A CN114495792B CN 114495792 B CN114495792 B CN 114495792B CN 202210094500 A CN202210094500 A CN 202210094500A CN 114495792 B CN114495792 B CN 114495792B
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- 238000000034 method Methods 0.000 title claims abstract description 28
- 230000015654 memory Effects 0.000 claims abstract description 152
- 230000005540 biological transmission Effects 0.000 claims description 13
- 230000008878 coupling Effects 0.000 claims description 2
- 238000010168 coupling process Methods 0.000 claims description 2
- 238000005859 coupling reaction Methods 0.000 claims description 2
- 238000012545 processing Methods 0.000 abstract description 12
- 238000010586 diagram Methods 0.000 description 17
- 230000008569 process Effects 0.000 description 7
- 230000006870 function Effects 0.000 description 3
- 101000795655 Canis lupus familiaris Thymic stromal cotransporter homolog Proteins 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
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- 238000013459 approach Methods 0.000 description 1
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
Abstract
The disclosure provides a display driving circuit and a display driving method. The display driving circuit is used for processing the display frame in a rotating or mirror image mode. In the display driving method, a display image frame to be processed is transmitted to a first memory. The display frame is rotated or mirrored by the selection control unit and transferred to the output buffer. The output buffer transmits the rotated or mirrored display image frames to the display panel for display.
Description
Technical Field
The present disclosure relates to a display driving circuit and a display driving method, and more particularly, to a display driving circuit and a display driving method for real-time random image rotation.
Background
The image processing of the display panel comprises two parts, namely an application processor (application processor, AP) and a display panel drive integrated circuit (DDIC). In order to provide a rotated or mirrored image, in the prior art, the display frame is mapped between two random access memories (random access memory, RAM) in the application processor, and the mapped display frame is transferred to the RAM of the display panel driver ic for processing and display. In this method, since data needs to be repeatedly read and written between three or more random access memories, power consumption increases, delay time increases, process cost increases, and partial rotation and mirroring functions cannot be realized in this method.
Disclosure of Invention
The disclosure provides a display driving circuit, which comprises a first memory, an output buffer and a selection control unit. The first memory is coupled to the application processor, and is configured to receive the display frame from the application processor and store the display frame in the first memory. The output buffer is used for coupling the display panel and controlling a plurality of data lines on the display panel. The selection control unit is coupled between the first memory and the output buffer, and is configured to: in a first selection mode, reading a plurality of first data voltages in a plurality of first memory cells of a first memory bit in a first axial direction, and writing the first data voltages into an output buffer; in the second selection mode, a plurality of second data voltages in a plurality of second memory cells of the first memory bit in a second axial direction are read and written into the output buffer, and the second axial direction is different from the first axial direction. The output buffer drives a plurality of data lines of the display panel according to the plurality of first data voltages or the plurality of second data voltages.
The present disclosure provides a display driving method including the operations of:
receiving a display frame from an application processor and storing the display frame in a first memory;
judging the current display mode, thereby controlling output buffering, comprising:
when the current display mode is a first selection mode, reading a plurality of first data voltages in a plurality of first memory cells of the first memory bit in a first axial direction, and writing the first data voltages into an output buffer;
when the current display mode is the second selection mode, reading a plurality of second data voltages in a plurality of second storage units of the first storage unit in a second axial direction, and writing the second data voltages into an output buffer, wherein the second axial direction is different from the first axial direction; and
the plurality of data lines of the display panel are driven according to the plurality of first data voltages or the plurality of second data voltages in the output buffer.
Drawings
Embodiments of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the features are not drawn to scale in accordance with standard practices in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
FIG. 1 illustrates a block diagram of a display device, according to some embodiments;
FIG. 2 illustrates a block diagram of an application processor, according to some embodiments;
FIG. 3 is a block diagram illustrating a display driving circuit and its peripheral devices according to some embodiments;
FIG. 4A illustrates a block diagram of a pick control unit processing display frames in a first pick mode, in accordance with some embodiments;
FIG. 4B illustrates a block diagram of a selection control unit processing a display frame in a second selection mode, in accordance with some embodiments;
FIG. 4C illustrates a block diagram of a selection control unit processing a display frame in another second selection mode, in accordance with some embodiments;
FIG. 4D illustrates a block diagram of a selection control unit processing display frames in yet another second selection mode, in accordance with some embodiments;
FIG. 4E illustrates a block diagram of a pick control unit processing display frames in a third pick mode, in accordance with some embodiments;
FIG. 5 illustrates a timing diagram of a display drive circuit processing display frames, according to some embodiments; and
fig. 6 illustrates a flow chart of a display driving method, according to some embodiments.
Reference numerals illustrate:
100: display device
120: application processor
122: second memory
140: display driving circuit
142: first memory
144: selection control unit
146: output buffering
160: transmission interface
180: display panel
182: data line
190: scanning driving circuit
500: timing diagram of display driving circuit
600: display driving method
602,604,606: operation of
AX1: first axial direction
AX2a to AX2c: second axis
AX3: third axial direction
CE1 to CE16: memory cell
D1-D4: data line
Pix: displaying a picture frame
Pix_v: data voltage
P1 to P16: pixel unit
S1-S4: scanning line
T Blank : cut-off time
T AddrTransmit : transmission time
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Moreover, for ease of description, spatially relative terms such as "under," "below," "lower," "above," "upper," and the like may be used herein to describe one element or feature's relationship to another element (or elements) or feature (or features) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Fig. 1 illustrates a block diagram of a display device 100, according to some embodiments. The display device 100 includes an application processor 120, a display driving circuit 140, a transmission interface 160, a display panel 180, and a scan driving circuit 190. The display driving circuit 140 is connected to the application processor 120 through the transmission interface 160 to receive the display frame Pix to be processed, and displays the processed display frame Pix on the display panel 180. In some embodiments, the transmission interface 160 may be implemented using a mobile industry processor interface (mobile industry processor interface, MIPI).
The scan driving circuit 190 is used to control the scan switching sequence of the pixel transistors of each pixel in the display panel 180, and the scan method of the display panel is well known in the art and is not described herein.
As shown in fig. 1, the display panel 180 is exemplified by a display matrix comprising 4*4 pixel units, but the disclosure is not limited to 4*4 pixel units, and 1024×768, 720×480, 1600×900 or other numbers of pixel units can be used in practical applications. In some embodiments, the display panel 180 has four data lines D1 to D4 parallel to each other, four scan lines S1 to S4 parallel to each other and perpendicular to the data lines, and pixel units P1 to P16 corresponding to intersections of the four data lines and the four scan lines. The data lines D1-D4 are coupled to the display driving circuit 140, and the display driving circuit 140 is used for providing data voltages corresponding to the display frames to the corresponding pixel units P1-P16 through the data lines D1-D4.
It should be noted that the numbers of data lines and scan lines in fig. 1 are all examples. Other numbers of data lines and scan lines are within the scope of this disclosure.
Generally, the display contents of the display frames are divided into upper and lower directions, for example, when the display contents have a face, the direction of the top of the head corresponds to the upper direction of the display device 100.
In some applications, the user may rotate the display device 100 in a placement direction, for example, when the display device 100 is a rotatable lcd panel, a smart phone or a wearable smart watch, the display device 100 is not necessarily positioned above the display screen in a fixed direction. It is possible to rotate the different sides of the display device 100 to above the line of sight according to the user's operation.
In some embodiments, the display panel 180 may be a plasma display panel (plasma display panel), a liquid crystal display panel (liquid crystal display panel, LCD), a light emitting diode display panel (LED display panel), or other device having a function of displaying images.
Fig. 2 illustrates a block diagram of an application processor 120, according to some embodiments. The application processor 120 includes a second memory 122, where the second memory 122 is composed of a plurality of memory cells CE for storing the data voltages pix_v corresponding to the display frame Pix, and the memory cells CE are arranged in a plurality of rows and a plurality of columns. In some embodiments, the data voltage pix_v of the memory cell CE of the second memory 122 may be copied to the display driving circuit 140 through the transmission interface 160.
In a typical case, the application processor 120 is used to generate display frame Pix content to be displayed, such as still pictures, photos, dynamic pictures, etc. If the user adjusts the placement direction of the display device 100, in order to match the line of sight of the user, in some conventional methods, a plurality of memories additionally provided inside the application processor 120 are utilized to rotate the display frame Pix between different memories before the display frame Pix is transmitted to the display driving circuit 140, in this case, all the display frames Pix need to be transmitted multiple times in the plurality of memories inside the application processor 120, which results in the problems of higher device cost, longer processing time, and higher power consumption besides the larger number of devices.
Fig. 3 is a block diagram illustrating the display driving circuit 140 and its peripheral devices according to some embodiments. The display driving circuit 140 includes a first memory 142, a selection control unit 144, and an output buffer 146. In some embodiments, the first memory 142 and the second memory 122 in fig. 2 are both Random Access Memories (RAMs).
The first memory 142 is configured by a plurality of memory cells CE for storing the data voltages pix_v corresponding to the display frame Pix, and the memory cells CE are arranged in a plurality of rows and a plurality of columns. The first memory 142 receives the data voltage pix_v from the second memory 122 through the transmission interface 160.
In one embodiment, the selection control unit 144 can employ different selection modes to read the data voltage pix_v of the memory cell CE in the first memory 142, and transmit the data voltage pix_v to the output buffer 146, and the output buffer transmits the received data voltage pix_v to the data line 182 for image presentation. The different selection modes can respectively realize the image processing of direct output, rotation, overturn, mirror image and the like of the display image frame Pix in the reading process. By this method, the display frame Pix can be prevented from being transmitted inside the application processor 120 for multiple times, so as to save the device cost and reduce the processing time.
Referring to fig. 4A, in a first selection mode, the selection control unit 144 reads the first memory 142 according to the first axis AX1 and sends the first memory to the output buffer 146 according to some embodiments.
In some embodiments, the plurality of memory cells CE of the first memory 142 are arranged in an array 4*4, including the memory cells CE1, CE2, …, CE16, each having a corresponding data voltage pix_v. In the first selection mode, the selection control unit 144 selects from the first row of the memory cells CE using the first axis AX1, sequentially transfers the data voltages pix_v of the row of the memory cells CE to the output buffer 146 (e.g., in the order of CE1, CE2, CE3, CE 4), in the embodiment shown in fig. 4A, the first axis AX1 may be, for example, an axis direction of the first axis AX1 and a reading order from left to right is adopted, that is, the selection control unit 144 reads the memory cells CE1 to CE4 on the same horizontal column of the first memory 142, and transfers the data voltages pix_v read by the memory cells CE1 to CE4 to the output buffer 146, for example, the output buffer 146 may be a linear buffer for temporarily storing the data voltages pix_v read by the memory cells CE1 to CE4, and the output buffer 146 is used to write the data voltages pix_v read by the memory cells CE1 to CE4 to the pixel cells P1 to P4 of the first row through the data lines D1 to D4 in a data update period of the display panel 180, and the data lines 182 of the display panel is transferred from the output buffer 146.
The selection control unit 144 then selects the memory cells CE5 to CE8 in the second row from the second memory 122, and the output buffer 146 is used to write the data voltages pix_v read from the memory cells CE5 to CE8 into the pixel cells P5 to P8 in the second row through the data lines D1 to D4, and so on.
In the embodiment shown in fig. 4A, in the first selection mode, since the selection control unit 144 reads the first memory 142 according to the first axial direction AX1 and transmits the read first memory to the output buffer 146, the original display frame Pix content is transmitted to the display panel 180 according to the original pattern direction. Therefore, the display panel 180 displays a screen substantially identical to the content of the display frame Pix that the application processor 120 originally generates to be displayed.
Referring to fig. 4B, in a second selection mode, the selection control unit 144 reads the first memory 142 according to the second axis AX2a and sends the first memory to the output buffer 146 according to some embodiments.
In some embodiments, the plurality of memory cells CE of the first memory 142 are arranged in an array 4*4, including the memory cells CE1, CE2, …, CE16, each having a corresponding data voltage pix_v. In the second selection mode, the selection control unit 144 employs the second axis AX2a to select from the first row of the memory cells CE, sequentially transfers the data voltages pix_v of the row of the memory cells CE to the output buffer 146 (e.g. in the order of CE13, CE9, CE5, CE 1), in the embodiment shown in fig. 4B, the second axis AX2a may be, for example, the axis direction of the vertical direction and the bottom-to-top reading order, that is, the selection control unit 144 reads the memory cells CE13, CE9, CE5, CE1 of the first memory 142 on the same vertical row, and transfers the data voltages pix_v to the output buffer 146, for example, the output buffer 146 may be a linear buffer for temporarily storing the data voltages pix_v read out by the memory cells CE13, CE9, CE5, CE1, and the output buffer 146 is used to write the data voltages pix_v read from the memory cells CE13, CE9, CE5, CE1 to the first row of the memory cells P1 through the data lines D1 to D4 in a data update period of the display panel 180, and then transfers the data voltages pix_v to the output buffer 146.
The selection control unit 144 then selects the memory cells CE14, CE10, CE6, CE2 of the second row from the second memory 122, and the output buffer 146 is used for writing the data voltages pix_v read from the memory cells CE14, CE10, CE6, CE2 to the pixels P5-P8 of the second column through the data lines D1-D4, and so on.
As described above, the second selection mode in the embodiment of fig. 4B may be used to implement an application that rotates the display frame Pix by 90 degrees. In this embodiment, the display frame Pix does not need to be pre-rotated or pre-processed by the application processor 120, so that the resources of the application processor 120 for setting the graphics rotation circuit and the additional memory can be reduced, and the efficiency of the display frame Pix in rotation can be improved because the application processor 120 does not need to pre-rotate or pre-process. In the embodiment shown in fig. 4B, in the second selection mode, since the selection control unit 144 reads the first memory 142 according to the second axis AX2a and transmits it to the output buffer 146, the original display frame Pix content is rotated by 90 degrees. Accordingly, the display panel 180 may present an embodiment in which the display frame Pix is rotated by 90 degrees.
It should be noted that the second selection mode is not limited to the embodiment of fig. 4B, and may be used to implement image flipping in other applications. Referring to fig. 4C, a schematic diagram of the selection control unit 144 reading the first memory 142 and transferring to the output buffer 146 in another second selection mode according to another embodiment is shown.
In some embodiments, the plurality of memory cells CE of the first memory 142 are arranged in an array 4*4, including the memory cells CE1, CE2, …, CE16, each having a corresponding data voltage pix_v. In another second selection mode, the selection control unit 144 employs the second axis AX2b to sequentially select from the first row of the memory cells CE, and transfers the data voltages pix_v of the row of the memory cells CE to the output buffer 146 (e.g. in the order of CE4, CE3, CE2, CE 1), in the embodiment shown in fig. 4C, the second axis AX2b may be, for example, the axis direction of the second axis AX2b and the reading order from right to left is adopted, that is, the selection control unit 144 reads the memory cells CE4 to CE1 on the same horizontal column of the first memory 142, and transfers the data voltages pix_v read by the memory cells CE4 to CE1 to the output buffer 146, for example, the output buffer 146 may be a linear buffer for temporarily storing the data voltages pix_v read by the memory cells CE4 to CE1, and the output buffer 146 is used to write the data voltages pix_v of the memory cells CE4 to CE1 to the pixels P1 to P4 of the first row through the data lines D1 to D4 in a data update period of the display panel 180, and the data is transferred to the display panel 182.
The selection control unit 144 then selects the memory cells CE 8-CE 5 of the second row from the second memory 122, and the output buffer 146 is used to write the data voltages pix_v read from the memory cells CE 5-CE 8 to the pixels P5-P8 of the second row through the data lines D1-D4, and so on.
As described above, the second selection mode in the embodiment of fig. 4C may be used to implement an application that mirror-inverts the display frame Pix from side to side. In this embodiment, the display frame Pix does not need to be pre-flipped or pre-processed by the application processor 120, so that the resources of the application processor 120 for setting the graphics flipping circuit and the additional memory can be reduced, and the efficiency of the display frame Pix in performing left-right flipping can be improved because the application processor 120 does not need to pre-flip or pre-process. In the embodiment shown in fig. 4C, in the second selection mode, since the selection control unit 144 reads the first memory 142 according to the second axis AX2b and transmits it to the output buffer 146, the original display frame Pix content is mirrored left and right. Accordingly, the display panel 180 may present an embodiment in which the display frame Pix is flipped left and right.
It should be noted that the second selection mode is not limited to the embodiment of fig. 4B and fig. 4C, and fig. 4D is also shown, which illustrates a schematic diagram of the selection control unit 144 reading the first memory 142 and transmitting to the output buffer 146 in yet another second selection mode according to other embodiments.
In some embodiments, the plurality of memory cells CE of the first memory 142 are arranged in an array 4*4, including the memory cells CE1, CE2, …, CE16, each having a corresponding data voltage pix_v. In still another second selection mode, the selection control unit 144 employs the second axis AX2c to sequentially select from the first row of the memory cells CE, and transfers the data voltages pix_v of the row of the memory cells CE to the output buffer 146 (e.g., in the order of CE1, CE5, CE9, CE 13), in the embodiment shown in fig. 4D, the second axis AX2c may be, for example, the vertical axis and employ the top-to-bottom reading order, that is, the selection control unit 144 reads the memory cells CE1, CE5, CE9, CE13 on the same vertical row of the first memory 142, and transfers the data voltages pix_v read out by the memory cells CE1, CE5, CE9, CE13 to the output buffer 146, for example, the output buffer 146 may be a linear buffer for temporarily storing the data voltages pix_v read out by the memory cells CE1, CE5, CE9, CE13, and in a data update period of the display panel 180, and the output buffer 146 is used to present the data voltages pix_v read from the memory cells CE1, CE5, CE9, CE13 to the first row of the display panel P1 to the output buffer 146 via the data lines D4 to the output buffer 146.
The selection control unit 144 then selects the memory cells CE2, CE6, CE10, CE14 of the second row from the second memory 122, and the output buffer 146 is used for writing the data voltages pix_v read from the memory cells CE2, CE6, CE10, CE14 to the pixels P5-P8 of the second column through the data lines D1-D4, and so on.
As described above, the second selection mode in the embodiment of fig. 4D may be used to implement an application that rotates the display frame Pix by 90 degrees and mirror-flip around. In this embodiment, the display frame Pix does not need to be pre-rotated/flipped or pre-processed by the application processor 120, so that the resources of the application processor 120 for setting the graphics rotation/flipping circuit and the additional memory can be reduced, and the efficiency of the display frame Pix in rotation and flipping can be improved because the application processor 120 does not need to pre-rotate/flip or pre-process. In the embodiment shown in fig. 4D, in the second selection mode, since the selection control unit 144 reads the first memory 142 according to the second axis AX2c and transmits it to the output buffer 146, the original display frame Pix content is rotated by 90 degrees and mirrored thereabout. Accordingly, the display panel 180 may present an embodiment in which the display frame Pix is rotated by 90 degrees and mirrored left and right.
Referring to fig. 4E, a schematic diagram of the selection control unit 144 reading the first memory 142 and transferring to the output buffer 146 in the third selection mode according to some embodiments is shown.
In some embodiments, the plurality of memory cells CE of the first memory 142 are arranged in an array 4*4, including the memory cells CE1, CE2, …, CE16, each having a corresponding data voltage pix_v. In the third selection mode, the selection control unit 144 starts to select from the specific memory cell CE by using the third axial AX3, and sequentially transfers the data voltages pix_v of the selected memory cell CE to the output buffer 146 (e.g. in the order of CE9, CE6, CE 3), in the embodiment shown in fig. 4E, the third axial AX3 may be, for example, an axial direction with an angle of 45 degrees and a reading order from left to right, that is, the selection control unit 144 reads the memory cells CE9, CE6, CE3 on the same diagonal of the first memory 142, and transfers the data voltages pix_v to the output buffer 146, for example, the output buffer 146 may be a linear buffer for temporarily storing the data voltages pix_v read by the memory cells CE9, CE6, CE3, and in a data update period of the display panel 180, the output buffer 146 is used for writing the data voltages pix_v read from the memory cells CE9, CE6, CE3 to the pixels P1 to P4 of the first column through the data lines D1 to D4, and the output buffer 146 is used for rendering the image display of the image 182.
The selection control unit 144 then selects the next diagonal memory cells CE14, CE11, CE8 from the second memory 122, and the output buffer 146 is used to write the data voltages pix_v read from the memory cells CE14, CE11, CE8 to the pixels P5-P8 of the second row through the data lines D1-D4, and so on.
As described above, the third selection mode in the embodiment of fig. 4E may be used to implement an application that rotates the display frame Pix by 45 degrees. In this embodiment, the display frame Pix does not need to be pre-rotated or pre-processed by the application processor 120, so that the resources of the application processor 120 for setting the graphics rotation circuit and the additional memory can be reduced, and the efficiency of the display frame Pix in rotation can be improved because the application processor 120 does not need to pre-rotate or pre-process. In the embodiment shown in fig. 4E, in the third selection mode, since the selection control unit 144 reads the first memory 142 according to the third axial direction AX3 and transmits it to the output buffer 146, the original display frame Pix content is rotated 45 degrees. Accordingly, the display panel 180 may present an embodiment in which the display frame Pix is rotated by 45 degrees. Further, in the third selection mode, the display frame Pix may be rotated by any angle.
It should be noted that the total number, the row/column number, and the data voltage of the memory cells CE of the first memory 142 in fig. 4A to 4E are all examples. The total number, row/column number, data voltages of other memory cells CE are within the scope of the present disclosure.
In some embodiments, a first frame rate (frame rate) is used to drive the display panel when the display driving circuit allows switching between the first selection mode and the second selection mode. When the display driving circuit is fixed in the first selection mode, the display panel is driven by adopting a second frame updating rate, wherein the second frame updating rate is larger than the first frame updating rate. By this limitation, the frame update rate when the display frame Pix does not need to be operated can be improved.
Fig. 5 illustrates a timing diagram 500 of the display driver circuit 140, according to some embodiments. Starting from the time of display frame Pix update to the time of starting transmission of display frame Pix to output buffer 146, the time of the intermediate interval is the deadline T Blank . The time required for copying the display frame Pix of the second memory 122 to the first memory 142 is the transmission time T AddrTransmit . Cut-off time T Blank Must be greater than or equal to the transmission time T AddrTransmit . With this limitation, the deadline T can be avoided Blank Less than the transmission time T AddrTransmit Image Tearing (Tearing) caused by the time.
Fig. 6 illustrates a flow chart of a display driving method 600, according to some embodiments. It should be noted that the display driving method 600 is provided by way of example only and does not limit the scope of the present disclosure. Accordingly, it should be appreciated that additional operations may be provided before, during, and after the display driving method 600 of FIG. 6, and that some other operations may only be briefly described herein. The display driving method 600 includes operations 602,604, and 606.
In operation 602, the display frame Pix stored in the second memory 122 is copied to the first memory 142 through the transmission interface 160, and operation 604 is performed.
In operation 604, the data voltage pix_v of the memory cell CE is selected and transferred to the output buffer 146 according to the selected first selection mode, second selection mode or third selection mode, and operation 606 is performed.
In operation 606, the output buffer 146 transmits the received data voltage pix_v to the plurality of data lines 182 of the display panel 180 for image presentation.
By the approach mentioned in this disclosure, some image rotations or mirror images that cannot be provided by the application processor can be complemented. This flow does not generate a rotation delay (rotation delay) due to the incorporation of the operation into the display panel driving integrated circuit. Furthermore, by the deadline T Blank The frame update rate and the rotation function can be switched according to the application requirements.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the embodiments of the present disclosure. It should be appreciated by those skilled in the art that the present disclosure may be readily utilized as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the disclosure.
Claims (10)
1. A display driving circuit, comprising:
the first memory is coupled with the application processor and used for receiving a display image frame from the application processor and storing the display image frame in the first memory;
an output buffer for coupling to a display panel and for controlling a plurality of data lines on the display panel; and
a selection control unit coupled between the first memory and the output buffer, the selection control unit being configured to:
in a first selection mode, reading a plurality of first data voltages in a plurality of first memory cells of the first memory bit in a first axial direction, and writing the first data voltages into the output buffer; and
in a second selection mode, a plurality of second data voltages in a plurality of second memory cells of the first memory bit in a second axial direction are read and written into the output buffer, the second axial direction is different from the first axial direction,
the output buffer drives the data lines of the display panel according to the first data voltages or the second data voltages.
2. The display driving circuit as claimed in claim 1, wherein the application processor comprises a second memory, the application processor is used for generating the display frames to be displayed, the display frames are stored in the second memory, and the display driving circuit copies the display frames to the first memory in the same row and column arrangement by the second memory of the application processor.
3. The display driver circuit of claim 1, wherein the first and second axes are perpendicular to each other or the first and second axes are parallel to each other but opposite in direction.
4. The display driving circuit according to claim 3, wherein the selection control unit is further configured to:
in a third selection mode, a plurality of third data voltages in a plurality of third memory cells of the first memory bit in a third axial direction are read and written into the output buffer, wherein the third axial direction is not parallel and perpendicular to the first axial direction and the second axial direction.
5. The display driving circuit according to claim 1, wherein
A deadline represents the time required for the display frame from updating to writing into the output buffer; and
a transmission time represents the time required for the display frame to be copied from the second memory to the first memory,
wherein the deadline is greater than or equal to the transit time.
6. The display driving circuit according to claim 1, wherein
When the display driving circuit allows the switching between the first selection mode and the second selection mode, driving the display panel by adopting a first frame updating rate; and
when the display driving circuit is fixed in the first selection mode, a second frame updating rate is adopted to drive the display panel, and the second frame updating rate is larger than the first frame updating rate.
7. A display driving method, comprising:
receiving a display frame from an application processor and storing the display frame in a first memory;
determining a current display mode thereby controlling an output buffer, comprising:
when the current display mode is a first selection mode, reading a plurality of first data voltages in a plurality of first memory cells of the first memory bit in a first axial direction, and writing the first data voltages into the output buffer;
when the current display mode is a second selection mode, a plurality of second data voltages in a plurality of second memory cells of the first memory in a second axial direction are read and written into the output buffer, and the second axial direction is different from the first axial direction; and
the plurality of data lines of a display panel are driven according to the plurality of first data voltages or the plurality of second data voltages in the output buffer.
8. The display driving method as claimed in claim 7, wherein the application processor comprises a second memory, the application processor is used for generating the display frames to be displayed, the display frames are stored in the second memory, and the second memory of the application processor copies the display frames to the first memory in the same row and column arrangement.
9. The display driving method according to claim 7, wherein the first axial direction and the second axial direction are perpendicular to each other or the first axial direction and the second axial direction are parallel to each other but opposite in direction.
10. The display driving method according to claim 9, further comprising:
when the current display mode is a third selection mode, a plurality of third data voltages in a plurality of third memory cells of the first memory in a third axial direction are read and written into the output buffer, wherein the third axial direction is not parallel and perpendicular to the first axial direction and the second axial direction.
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| TW110148969 | 2021-12-27 | ||
| TW110148969A TWI788162B (en) | 2021-02-02 | 2021-12-27 | Display driving circuit and display driving method |
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| US8797231B2 (en) * | 2009-04-15 | 2014-08-05 | Nlt Technologies, Ltd. | Display controller, display device, image processing method, and image processing program for a multiple viewpoint display |
| CN103425444B (en) * | 2012-05-25 | 2016-12-21 | 华为技术有限公司 | Display control method, system and display device |
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| TW201435854A (en) * | 2013-03-07 | 2014-09-16 | Samsung Electronics Co Ltd | Display drive integrated circuit and image display system |
| CN108109584A (en) * | 2016-11-25 | 2018-06-01 | 瑞鼎科技股份有限公司 | Driving circuit and its operation method |
| CN106710560A (en) * | 2017-02-28 | 2017-05-24 | 昆山龙腾光电有限公司 | Driving circuit for display panel and display device |
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